vf610.dtsi 12 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. */
  9. #include "skeleton.dtsi"
  10. #include "vf610-pinfunc.h"
  11. #include <dt-bindings/clock/vf610-clock.h>
  12. #include <dt-bindings/interrupt-controller/irq.h>
  13. / {
  14. aliases {
  15. can0 = &can0;
  16. can1 = &can1;
  17. serial0 = &uart0;
  18. serial1 = &uart1;
  19. serial2 = &uart2;
  20. serial3 = &uart3;
  21. serial4 = &uart4;
  22. serial5 = &uart5;
  23. gpio0 = &gpio1;
  24. gpio1 = &gpio2;
  25. gpio2 = &gpio3;
  26. gpio3 = &gpio4;
  27. gpio4 = &gpio5;
  28. usbphy0 = &usbphy0;
  29. usbphy1 = &usbphy1;
  30. };
  31. cpus {
  32. #address-cells = <1>;
  33. #size-cells = <0>;
  34. cpu@0 {
  35. compatible = "arm,cortex-a5";
  36. device_type = "cpu";
  37. reg = <0x0>;
  38. next-level-cache = <&L2>;
  39. };
  40. };
  41. clocks {
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. sxosc {
  45. compatible = "fixed-clock";
  46. #clock-cells = <0>;
  47. clock-frequency = <32768>;
  48. };
  49. fxosc {
  50. compatible = "fixed-clock";
  51. #clock-cells = <0>;
  52. clock-frequency = <24000000>;
  53. };
  54. };
  55. soc {
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. compatible = "simple-bus";
  59. interrupt-parent = <&intc>;
  60. ranges;
  61. aips0: aips-bus@40000000 {
  62. compatible = "fsl,aips-bus", "simple-bus";
  63. #address-cells = <1>;
  64. #size-cells = <1>;
  65. interrupt-parent = <&intc>;
  66. reg = <0x40000000 0x70000>;
  67. ranges;
  68. intc: interrupt-controller@40002000 {
  69. compatible = "arm,cortex-a9-gic";
  70. #interrupt-cells = <3>;
  71. interrupt-controller;
  72. reg = <0x40003000 0x1000>,
  73. <0x40002100 0x100>;
  74. };
  75. L2: l2-cache@40006000 {
  76. compatible = "arm,pl310-cache";
  77. reg = <0x40006000 0x1000>;
  78. cache-unified;
  79. cache-level = <2>;
  80. arm,data-latency = <1 1 1>;
  81. arm,tag-latency = <2 2 2>;
  82. };
  83. edma0: dma-controller@40018000 {
  84. #dma-cells = <2>;
  85. compatible = "fsl,vf610-edma";
  86. reg = <0x40018000 0x2000>,
  87. <0x40024000 0x1000>,
  88. <0x40025000 0x1000>;
  89. interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
  90. <0 9 IRQ_TYPE_LEVEL_HIGH>;
  91. interrupt-names = "edma-tx", "edma-err";
  92. dma-channels = <32>;
  93. clock-names = "dmamux0", "dmamux1";
  94. clocks = <&clks VF610_CLK_DMAMUX0>,
  95. <&clks VF610_CLK_DMAMUX1>;
  96. };
  97. can0: flexcan@40020000 {
  98. compatible = "fsl,vf610-flexcan";
  99. reg = <0x40020000 0x4000>;
  100. interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
  101. clocks = <&clks VF610_CLK_FLEXCAN0>,
  102. <&clks VF610_CLK_FLEXCAN0>;
  103. clock-names = "ipg", "per";
  104. status = "disabled";
  105. };
  106. uart0: serial@40027000 {
  107. compatible = "fsl,vf610-lpuart";
  108. reg = <0x40027000 0x1000>;
  109. interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
  110. clocks = <&clks VF610_CLK_UART0>;
  111. clock-names = "ipg";
  112. dmas = <&edma0 0 2>,
  113. <&edma0 0 3>;
  114. dma-names = "rx","tx";
  115. status = "disabled";
  116. };
  117. uart1: serial@40028000 {
  118. compatible = "fsl,vf610-lpuart";
  119. reg = <0x40028000 0x1000>;
  120. interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
  121. clocks = <&clks VF610_CLK_UART1>;
  122. clock-names = "ipg";
  123. dmas = <&edma0 0 4>,
  124. <&edma0 0 5>;
  125. dma-names = "rx","tx";
  126. status = "disabled";
  127. };
  128. uart2: serial@40029000 {
  129. compatible = "fsl,vf610-lpuart";
  130. reg = <0x40029000 0x1000>;
  131. interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
  132. clocks = <&clks VF610_CLK_UART2>;
  133. clock-names = "ipg";
  134. dmas = <&edma0 0 6>,
  135. <&edma0 0 7>;
  136. dma-names = "rx","tx";
  137. status = "disabled";
  138. };
  139. uart3: serial@4002a000 {
  140. compatible = "fsl,vf610-lpuart";
  141. reg = <0x4002a000 0x1000>;
  142. interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
  143. clocks = <&clks VF610_CLK_UART3>;
  144. clock-names = "ipg";
  145. dmas = <&edma0 0 8>,
  146. <&edma0 0 9>;
  147. dma-names = "rx","tx";
  148. status = "disabled";
  149. };
  150. dspi0: dspi0@4002c000 {
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. compatible = "fsl,vf610-dspi";
  154. reg = <0x4002c000 0x1000>;
  155. interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
  156. clocks = <&clks VF610_CLK_DSPI0>;
  157. clock-names = "dspi";
  158. spi-num-chipselects = <5>;
  159. status = "disabled";
  160. };
  161. sai2: sai@40031000 {
  162. compatible = "fsl,vf610-sai";
  163. reg = <0x40031000 0x1000>;
  164. interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
  165. clocks = <&clks VF610_CLK_SAI2>;
  166. clock-names = "sai";
  167. dma-names = "tx", "rx";
  168. dmas = <&edma0 0 21>,
  169. <&edma0 0 20>;
  170. status = "disabled";
  171. };
  172. pit: pit@40037000 {
  173. compatible = "fsl,vf610-pit";
  174. reg = <0x40037000 0x1000>;
  175. interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
  176. clocks = <&clks VF610_CLK_PIT>;
  177. clock-names = "pit";
  178. };
  179. pwm0: pwm@40038000 {
  180. compatible = "fsl,vf610-ftm-pwm";
  181. #pwm-cells = <3>;
  182. reg = <0x40038000 0x1000>;
  183. clock-names = "ftm_sys", "ftm_ext",
  184. "ftm_fix", "ftm_cnt_clk_en";
  185. clocks = <&clks VF610_CLK_FTM0>,
  186. <&clks VF610_CLK_FTM0_EXT_SEL>,
  187. <&clks VF610_CLK_FTM0_FIX_SEL>,
  188. <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
  189. status = "disabled";
  190. };
  191. adc0: adc@4003b000 {
  192. compatible = "fsl,vf610-adc";
  193. reg = <0x4003b000 0x1000>;
  194. interrupts = <0 53 0x04>;
  195. clocks = <&clks VF610_CLK_ADC0>;
  196. clock-names = "adc";
  197. status = "disabled";
  198. };
  199. wdog@4003e000 {
  200. compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
  201. reg = <0x4003e000 0x1000>;
  202. clocks = <&clks VF610_CLK_WDT>;
  203. clock-names = "wdog";
  204. };
  205. qspi0: quadspi@40044000 {
  206. #address-cells = <1>;
  207. #size-cells = <0>;
  208. compatible = "fsl,vf610-qspi";
  209. reg = <0x40044000 0x1000>;
  210. interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
  211. clocks = <&clks VF610_CLK_QSPI0_EN>,
  212. <&clks VF610_CLK_QSPI0>;
  213. clock-names = "qspi_en", "qspi";
  214. status = "disabled";
  215. };
  216. iomuxc: iomuxc@40048000 {
  217. compatible = "fsl,vf610-iomuxc";
  218. reg = <0x40048000 0x1000>;
  219. #gpio-range-cells = <3>;
  220. };
  221. gpio1: gpio@40049000 {
  222. compatible = "fsl,vf610-gpio";
  223. reg = <0x40049000 0x1000 0x400ff000 0x40>;
  224. interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
  225. gpio-controller;
  226. #gpio-cells = <2>;
  227. interrupt-controller;
  228. #interrupt-cells = <2>;
  229. gpio-ranges = <&iomuxc 0 0 32>;
  230. };
  231. gpio2: gpio@4004a000 {
  232. compatible = "fsl,vf610-gpio";
  233. reg = <0x4004a000 0x1000 0x400ff040 0x40>;
  234. interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
  235. gpio-controller;
  236. #gpio-cells = <2>;
  237. interrupt-controller;
  238. #interrupt-cells = <2>;
  239. gpio-ranges = <&iomuxc 0 32 32>;
  240. };
  241. gpio3: gpio@4004b000 {
  242. compatible = "fsl,vf610-gpio";
  243. reg = <0x4004b000 0x1000 0x400ff080 0x40>;
  244. interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
  245. gpio-controller;
  246. #gpio-cells = <2>;
  247. interrupt-controller;
  248. #interrupt-cells = <2>;
  249. gpio-ranges = <&iomuxc 0 64 32>;
  250. };
  251. gpio4: gpio@4004c000 {
  252. compatible = "fsl,vf610-gpio";
  253. reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
  254. interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
  255. gpio-controller;
  256. #gpio-cells = <2>;
  257. interrupt-controller;
  258. #interrupt-cells = <2>;
  259. gpio-ranges = <&iomuxc 0 96 32>;
  260. };
  261. gpio5: gpio@4004d000 {
  262. compatible = "fsl,vf610-gpio";
  263. reg = <0x4004d000 0x1000 0x400ff100 0x40>;
  264. interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
  265. gpio-controller;
  266. #gpio-cells = <2>;
  267. interrupt-controller;
  268. #interrupt-cells = <2>;
  269. gpio-ranges = <&iomuxc 0 128 7>;
  270. };
  271. anatop: anatop@40050000 {
  272. compatible = "fsl,vf610-anatop", "syscon";
  273. reg = <0x40050000 0x400>;
  274. };
  275. usbphy0: usbphy@40050800 {
  276. compatible = "fsl,vf610-usbphy";
  277. reg = <0x40050800 0x400>;
  278. interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
  279. clocks = <&clks VF610_CLK_USBPHY0>;
  280. fsl,anatop = <&anatop>;
  281. };
  282. usbphy1: usbphy@40050c00 {
  283. compatible = "fsl,vf610-usbphy";
  284. reg = <0x40050c00 0x400>;
  285. interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
  286. clocks = <&clks VF610_CLK_USBPHY1>;
  287. fsl,anatop = <&anatop>;
  288. };
  289. i2c0: i2c@40066000 {
  290. #address-cells = <1>;
  291. #size-cells = <0>;
  292. compatible = "fsl,vf610-i2c";
  293. reg = <0x40066000 0x1000>;
  294. interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
  295. clocks = <&clks VF610_CLK_I2C0>;
  296. clock-names = "ipg";
  297. dmas = <&edma0 0 50>,
  298. <&edma0 0 51>;
  299. dma-names = "rx","tx";
  300. status = "disabled";
  301. };
  302. clks: ccm@4006b000 {
  303. compatible = "fsl,vf610-ccm";
  304. reg = <0x4006b000 0x1000>;
  305. #clock-cells = <1>;
  306. };
  307. usbdev0: usb@40034000 {
  308. compatible = "fsl,vf610-usb", "fsl,imx27-usb";
  309. reg = <0x40034000 0x800>;
  310. interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
  311. clocks = <&clks VF610_CLK_USBC0>;
  312. fsl,usbphy = <&usbphy0>;
  313. fsl,usbmisc = <&usbmisc0 0>;
  314. dr_mode = "peripheral";
  315. status = "disabled";
  316. };
  317. usbmisc0: usb@40034800 {
  318. #index-cells = <1>;
  319. compatible = "fsl,vf610-usbmisc";
  320. reg = <0x40034800 0x200>;
  321. clocks = <&clks VF610_CLK_USBC0>;
  322. };
  323. };
  324. aips1: aips-bus@40080000 {
  325. compatible = "fsl,aips-bus", "simple-bus";
  326. #address-cells = <1>;
  327. #size-cells = <1>;
  328. reg = <0x40080000 0x80000>;
  329. ranges;
  330. edma1: dma-controller@40098000 {
  331. #dma-cells = <2>;
  332. compatible = "fsl,vf610-edma";
  333. reg = <0x40098000 0x2000>,
  334. <0x400a1000 0x1000>,
  335. <0x400a2000 0x1000>;
  336. interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
  337. <0 11 IRQ_TYPE_LEVEL_HIGH>;
  338. interrupt-names = "edma-tx", "edma-err";
  339. dma-channels = <32>;
  340. clock-names = "dmamux0", "dmamux1";
  341. clocks = <&clks VF610_CLK_DMAMUX2>,
  342. <&clks VF610_CLK_DMAMUX3>;
  343. };
  344. uart4: serial@400a9000 {
  345. compatible = "fsl,vf610-lpuart";
  346. reg = <0x400a9000 0x1000>;
  347. interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
  348. clocks = <&clks VF610_CLK_UART4>;
  349. clock-names = "ipg";
  350. status = "disabled";
  351. };
  352. uart5: serial@400aa000 {
  353. compatible = "fsl,vf610-lpuart";
  354. reg = <0x400aa000 0x1000>;
  355. interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
  356. clocks = <&clks VF610_CLK_UART5>;
  357. clock-names = "ipg";
  358. status = "disabled";
  359. };
  360. adc1: adc@400bb000 {
  361. compatible = "fsl,vf610-adc";
  362. reg = <0x400bb000 0x1000>;
  363. interrupts = <0 54 0x04>;
  364. clocks = <&clks VF610_CLK_ADC1>;
  365. clock-names = "adc";
  366. status = "disabled";
  367. };
  368. esdhc1: esdhc@400b2000 {
  369. compatible = "fsl,imx53-esdhc";
  370. reg = <0x400b2000 0x1000>;
  371. interrupts = <0 28 0x04>;
  372. clocks = <&clks VF610_CLK_IPG_BUS>,
  373. <&clks VF610_CLK_PLATFORM_BUS>,
  374. <&clks VF610_CLK_ESDHC1>;
  375. clock-names = "ipg", "ahb", "per";
  376. status = "disabled";
  377. };
  378. usbh1: usb@400b4000 {
  379. compatible = "fsl,vf610-usb", "fsl,imx27-usb";
  380. reg = <0x400b4000 0x800>;
  381. interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
  382. clocks = <&clks VF610_CLK_USBC1>;
  383. fsl,usbphy = <&usbphy1>;
  384. fsl,usbmisc = <&usbmisc1 0>;
  385. dr_mode = "host";
  386. status = "disabled";
  387. };
  388. usbmisc1: usb@400b4800 {
  389. #index-cells = <1>;
  390. compatible = "fsl,vf610-usbmisc";
  391. reg = <0x400b4800 0x200>;
  392. clocks = <&clks VF610_CLK_USBC1>;
  393. };
  394. ftm: ftm@400b8000 {
  395. compatible = "fsl,ftm-timer";
  396. reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
  397. interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
  398. clock-names = "ftm-evt", "ftm-src",
  399. "ftm-evt-counter-en", "ftm-src-counter-en";
  400. clocks = <&clks VF610_CLK_FTM2>,
  401. <&clks VF610_CLK_FTM3>,
  402. <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
  403. <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
  404. status = "disabled";
  405. };
  406. fec0: ethernet@400d0000 {
  407. compatible = "fsl,mvf600-fec";
  408. reg = <0x400d0000 0x1000>;
  409. interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
  410. clocks = <&clks VF610_CLK_ENET0>,
  411. <&clks VF610_CLK_ENET0>,
  412. <&clks VF610_CLK_ENET>;
  413. clock-names = "ipg", "ahb", "ptp";
  414. status = "disabled";
  415. };
  416. fec1: ethernet@400d1000 {
  417. compatible = "fsl,mvf600-fec";
  418. reg = <0x400d1000 0x1000>;
  419. interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
  420. clocks = <&clks VF610_CLK_ENET1>,
  421. <&clks VF610_CLK_ENET1>,
  422. <&clks VF610_CLK_ENET>;
  423. clock-names = "ipg", "ahb", "ptp";
  424. status = "disabled";
  425. };
  426. can1: flexcan@400d4000 {
  427. compatible = "fsl,vf610-flexcan";
  428. reg = <0x400d4000 0x4000>;
  429. interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
  430. clocks = <&clks VF610_CLK_FLEXCAN1>,
  431. <&clks VF610_CLK_FLEXCAN1>;
  432. clock-names = "ipg", "per";
  433. status = "disabled";
  434. };
  435. };
  436. };
  437. };