zynq-parallella.dts 1.8 KB

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  1. /*
  2. * Copyright (c) 2014 SUSE LINUX Products GmbH
  3. *
  4. * Derived from zynq-zed.dts:
  5. *
  6. * Copyright (C) 2011 Xilinx
  7. * Copyright (C) 2012 National Instruments Corp.
  8. * Copyright (C) 2013 Xilinx
  9. *
  10. * This software is licensed under the terms of the GNU General Public
  11. * License version 2, as published by the Free Software Foundation, and
  12. * may be copied, distributed, and modified under those terms.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. */
  19. /dts-v1/;
  20. /include/ "zynq-7000.dtsi"
  21. / {
  22. model = "Adapteva Parallella Board";
  23. compatible = "adapteva,parallella", "xlnx,zynq-7000";
  24. memory {
  25. device_type = "memory";
  26. reg = <0x0 0x40000000>;
  27. };
  28. chosen {
  29. bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
  30. linux,stdout-path = "/amba/serial@e0001000";
  31. };
  32. };
  33. &clkc {
  34. fclk-enable = <0xf>;
  35. };
  36. &gem0 {
  37. status = "okay";
  38. phy-mode = "rgmii-id";
  39. phy-handle = <&ethernet_phy>;
  40. ethernet_phy: ethernet-phy@0 {
  41. /* Marvell 88E1318 */
  42. compatible = "ethernet-phy-id0141.0e90",
  43. "ethernet-phy-ieee802.3-c22";
  44. reg = <0>;
  45. marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
  46. <0x3 0x11 0xfff0 0xa>;
  47. };
  48. };
  49. &i2c0 {
  50. status = "okay";
  51. isl9305: isl9305@68 {
  52. compatible = "isl,isl9305";
  53. reg = <0x68>;
  54. regulators {
  55. dcd1 {
  56. regulator-name = "VDD_DSP";
  57. regulator-always-on;
  58. };
  59. dcd2 {
  60. regulator-name = "1P35V";
  61. regulator-always-on;
  62. };
  63. ldo1 {
  64. regulator-name = "VDD_ADJ";
  65. };
  66. ldo2 {
  67. regulator-name = "VDD_GPIO";
  68. regulator-always-on;
  69. };
  70. };
  71. };
  72. };
  73. &sdhci1 {
  74. status = "okay";
  75. };
  76. &uart1 {
  77. status = "okay";
  78. };