g1010.dts 18 KB

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  1. /dts-v1/;
  2. #include "mt6753.dtsi"
  3. #include <dt-bindings/lcm/r63417_fhd_dsi_cmd_truly_nt50358.dtsi>
  4. #include "g1010_bat_setting.dtsi"
  5. / {
  6. memory@00000000 {
  7. device_type = "memory";
  8. reg = <0 0x40000000 0 0x3F000000>;
  9. };
  10. bus {
  11. compatible = "simple-bus";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. ranges = <0 0 0 0xffffffff>;
  15. MTKFB@5e200000 {
  16. compatible = "mediatek,MTKFB";
  17. reg = <0x7F000000 0x1000000>;
  18. };
  19. };
  20. led0:led@0 {
  21. compatible = "mediatek,red";
  22. led_mode = <0>;
  23. data = <1>;
  24. pwm_config = <0 0 0 0 0>;
  25. };
  26. led1:led@1 {
  27. compatible = "mediatek,green";
  28. led_mode = <0>;
  29. data = <1>;
  30. pwm_config = <0 0 0 0 0>;
  31. };
  32. led2:led@2 {
  33. compatible = "mediatek,blue";
  34. led_mode = <0>;
  35. data = <1>;
  36. pwm_config = <0 0 0 0 0>;
  37. };
  38. led3:led@3 {
  39. compatible = "mediatek,jogball-backlight";
  40. led_mode = <0>;
  41. data = <1>;
  42. pwm_config = <0 0 0 0 0>;
  43. };
  44. led4:led@4 {
  45. compatible = "mediatek,keyboard-backlight";
  46. led_mode = <0>;
  47. data = <1>;
  48. pwm_config = <0 0 0 0 0>;
  49. };
  50. led5:led@5 {
  51. compatible = "mediatek,button-backlight";
  52. led_mode = <0>;
  53. data = <1>;
  54. pwm_config = <0 0 0 0 0>;
  55. };
  56. led6:led@6 {
  57. compatible = "mediatek,lcd-backlight";
  58. led_mode = <5>;
  59. data = <1>;
  60. pwm_config = <0 0 0 0 0>;
  61. };
  62. vibrator0:vibrator@0 {
  63. compatible = "mediatek,vibrator";
  64. vib_timer = <25>;
  65. vib_limit = <9>;
  66. vib_vol= <5>;
  67. };
  68. /* sensor standardization */
  69. cust_accel@0 {
  70. compatible = "mediatek,kxtj2_1009_new";
  71. i2c_num = <2>;
  72. i2c_addr = <0x0E 0 0 0>;
  73. direction = <0>;
  74. power_id = <0xffff>;
  75. power_vol = <0>;
  76. firlen = <0>;
  77. is_batch_supported = <0>;
  78. };
  79. cust_alsps@0 {
  80. compatible = "mediatek,apds9930";
  81. i2c_num = <2>;
  82. i2c_addr = <0x72 0x48 0x78 0x00>;
  83. polling_mode_ps = <0>;
  84. polling_mode_als = <1>;
  85. power_id = <0xffff>;
  86. power_vol = <0>;
  87. als_level = <1 2 5 10 20 30 40 80 200 300 400 600 1000 1600 2000>;
  88. als_value = <80 400 800 1200 1800 2000 2300 2300 12000 12000 12000 48000 48000 72000 81920 81920>;
  89. ps_threshold_high = <90>;
  90. ps_threshold_low = <70>;
  91. is_batch_supported_ps = <0>;
  92. is_batch_supported_als = <0>;
  93. };
  94. cust_mag@0 {
  95. compatible = "mediatek,akm09911";
  96. i2c_num = <2>;
  97. i2c_addr = <0x0D 0 0 0>;
  98. direction = <1>;
  99. power_id = <0xffff>;
  100. power_vol = <0>;
  101. is_batch_supported = <0>;
  102. };
  103. cust_gyro@0 {
  104. compatible = "mediatek,mpu6050gy";
  105. i2c_num = <2>;
  106. i2c_addr = <0x69 0 0 0>;
  107. direction = <4>;
  108. power_id = <0xffff>;
  109. power_vol = <0>;
  110. firlen = <0>;
  111. is_batch_supported = <0>;
  112. };
  113. };
  114. /* sensor gpio standization */
  115. &pio {
  116. alsps_intpin_cfg: alspspincfg {
  117. pins_cmd_dat {
  118. pins = <PINMUX_GPIO65__FUNC_GPIO65>;
  119. slew-rate = <0>;
  120. bias-pull-up = <00>;
  121. };
  122. };
  123. alsps_intpin_default: alspsdefaultcfg {
  124. };
  125. gyro_intpin_cfg: gyropincfg {
  126. pins_cmd_dat {
  127. pins = <PINMUX_GPIO67__FUNC_GPIO67>;
  128. slew-rate = <0>;
  129. bias-pull-down = <00>;
  130. };
  131. };
  132. gyro_intpin_default: gyrodefaultcfg {
  133. };
  134. };
  135. &alsps {
  136. pinctrl-names = "pin_default", "pin_cfg";
  137. pinctrl-0 = <&alsps_intpin_default>;
  138. pinctrl-1 = <&alsps_intpin_cfg>;
  139. status = "okay";
  140. };
  141. &gyro {
  142. pinctrl-names = "pin_default", "pin_cfg";
  143. pinctrl-0 = <&gyro_intpin_default>;
  144. pinctrl-1 = <&gyro_intpin_cfg>;
  145. status = "okay";
  146. };
  147. /* sensor end */
  148. /*ACCDET GPIO standardization */
  149. &accdet {
  150. interrupt-parent = <&eintc>;
  151. interrupts = <86 IRQ_TYPE_LEVEL_LOW>;
  152. eint-debounce = <256>;
  153. accdet-gpio = <&pio 86 0>;
  154. accdet-mic-vol = <7>;
  155. headset-mode-setting = <0x500 0x200 1 0x1f0 0x800 0x800 0x20>;
  156. accdet-plugout-debounce = <20>;
  157. /*1:ACC mode, 2:low cost without in bias, 6:low cost with in bias*/
  158. accdet-mic-mode = <1>;
  159. /*0--MD_MAX--UP_MAX--DW_MAX*/
  160. headset-three-key-threshold = <0 80 220 500>;
  161. /*0--MD_MAX--VOICE_MAX--UP_MAX--DW_MAX*/
  162. headset-four-key-threshold = <0 58 121 192 450>;
  163. pinctrl-names = "default", "state_eint_as_int";
  164. pinctrl-0 = <&accdet_pins_default>;
  165. pinctrl-1 = <&accdet_pins_eint_as_int>;
  166. status = "okay";
  167. };
  168. &pio{
  169. accdet_pins_default: eint86default {
  170. };
  171. accdet_pins_eint_as_int: eint86 {
  172. pins_cmd_dat {
  173. pins = <PINMUX_GPIO86__FUNC_GPIO86>;
  174. bias-disable;
  175. };
  176. };
  177. };
  178. /*ACCDET end*/
  179. /*TOUCH GPIO standardization */
  180. &touch {
  181. tpd-resolution = <1200 1920>;
  182. use-tpd-button = <0>;
  183. tpd-key-num = <3>;
  184. tpd-key-local= <139 172 158 0>;
  185. tpd-key-dim-local = <90 883 100 40 230 883 100 40 370 883 100 40 0 0 0 0>;
  186. tpd-max-touch-num = <5>;
  187. tpd-filter-enable = <1>;
  188. tpd-filter-pixel-density = <186>;
  189. tpd-filter-custom-prameters = <0 0 0 0 0 0 0 0 0 0 0 0>;
  190. tpd-filter-custom-speed = <0 0 0>;
  191. pinctrl-names = "default", "state_eint_as_int", "state_eint_output0", "state_eint_output1",
  192. "state_rst_output0", "state_rst_output1";
  193. pinctrl-0 = <&CTP_pins_default>;
  194. pinctrl-1 = <&CTP_pins_eint_as_int>;
  195. pinctrl-2 = <&CTP_pins_eint_output0>;
  196. pinctrl-3 = <&CTP_pins_eint_output1>;
  197. pinctrl-4 = <&CTP_pins_rst_output0>;
  198. pinctrl-5 = <&CTP_pins_rst_output1>;
  199. status = "okay";
  200. };
  201. &pio {
  202. CTP_pins_default: eint0default {
  203. };
  204. CTP_pins_eint_as_int: eint@0 {
  205. pins_cmd_dat {
  206. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  207. slew-rate = <0>;
  208. bias-disable;
  209. };
  210. };
  211. CTP_pins_eint_output0: eintoutput0 {
  212. pins_cmd_dat {
  213. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  214. slew-rate = <1>;
  215. output-low;
  216. };
  217. };
  218. CTP_pins_eint_output1: eintoutput1 {
  219. pins_cmd_dat {
  220. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  221. slew-rate = <1>;
  222. output-high;
  223. };
  224. };
  225. CTP_pins_rst_output0: rstoutput0 {
  226. pins_cmd_dat {
  227. pins = <PINMUX_GPIO62__FUNC_GPIO62>;
  228. slew-rate = <1>;
  229. output-low;
  230. };
  231. };
  232. CTP_pins_rst_output1: rstoutput1 {
  233. pins_cmd_dat {
  234. pins = <PINMUX_GPIO62__FUNC_GPIO62>;
  235. slew-rate = <1>;
  236. output-high;
  237. };
  238. };
  239. };
  240. /* TOUCH end */
  241. /* CAMERA GPIO standardization */
  242. &pio {
  243. camera_pins_cam0_rst0: cam0@0 {
  244. pins_cmd_dat {
  245. pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST_PIN*/
  246. slew-rate = <1>; /*direction 0:in, 1:out*/
  247. output-low;/*direction out used only. output_low or high*/
  248. };
  249. };
  250. camera_pins_cam0_rst1: cam0@1 {
  251. pins_cmd_dat {
  252. pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST_PIN*/
  253. slew-rate = <1>;
  254. output-high;
  255. };
  256. };
  257. camera_pins_cam0_pnd0: cam0@2 {
  258. pins_cmd_dat {
  259. pins = <PINMUX_GPIO82__FUNC_GPIO82>;/*GPIO_CAMERA_CMPDN_PIN*/
  260. slew-rate = <1>;
  261. output-low;
  262. };
  263. };
  264. camera_pins_cam0_pnd1: cam0@3 {
  265. pins_cmd_dat {
  266. pins = <PINMUX_GPIO82__FUNC_GPIO82>;/*GPIO_CAMERA_CMPDN_PIN*/
  267. slew-rate = <1>;
  268. output-high;
  269. };
  270. };
  271. camera_pins_cam1_rst0: cam1@0 {
  272. pins_cmd_dat {
  273. pins = <PINMUX_GPIO11__FUNC_GPIO11>;/*GPIO_CAMERA_CMRST1_PIN*/
  274. slew-rate = <1>; /*direction 0:in, 1:out*/
  275. output-low;/*direction out used only. output_low or high*/
  276. };
  277. };
  278. camera_pins_cam1_rst1: cam1@1 {
  279. pins_cmd_dat {
  280. pins = <PINMUX_GPIO11__FUNC_GPIO11>;/*GPIO_CAMERA_CMRST1_PIN*/
  281. slew-rate = <1>;
  282. output-high;
  283. };
  284. };
  285. camera_pins_cam1_pnd0: cam1@2 {
  286. pins_cmd_dat {
  287. pins = <PINMUX_GPIO12__FUNC_GPIO12>;/*GPIO_CAMERA_CMPDN1_PIN*/
  288. slew-rate = <1>;
  289. output-low;
  290. };
  291. };
  292. camera_pins_cam1_pnd1: cam1@3 {
  293. pins_cmd_dat {
  294. pins = <PINMUX_GPIO12__FUNC_GPIO12>;/*GPIO_CAMERA_CMPDN1_PIN*/
  295. slew-rate = <1>;
  296. output-high;
  297. };
  298. };
  299. camera_pins_cam_ldo0_0: cam@0 {
  300. pins_cmd_dat {
  301. pins = <PINMUX_GPIO63__FUNC_GPIO63>;
  302. slew-rate = <1>;
  303. output-low;
  304. };
  305. };
  306. camera_pins_cam_ldo0_1: cam@1 {
  307. pins_cmd_dat {
  308. pins = <PINMUX_GPIO63__FUNC_GPIO63>;
  309. slew-rate = <1>;
  310. output-high;
  311. };
  312. };
  313. camera_pins_default: camdefault {
  314. };
  315. };
  316. &kd_camera_hw1 {
  317. pinctrl-names = "default", "cam0_rst0", "cam0_rst1", "cam0_pnd0", "cam0_pnd1",
  318. "cam1_rst0", "cam1_rst1", "cam1_pnd0", "cam1_pnd1",
  319. "cam_ldo0_0", "cam_ldo0_1";
  320. pinctrl-0 = <&camera_pins_default>;
  321. pinctrl-1 = <&camera_pins_cam0_rst0>;
  322. pinctrl-2 = <&camera_pins_cam0_rst1>;
  323. pinctrl-3 = <&camera_pins_cam0_pnd0>;
  324. pinctrl-4 = <&camera_pins_cam0_pnd1>;
  325. pinctrl-5 = <&camera_pins_cam1_rst0>;
  326. pinctrl-6 = <&camera_pins_cam1_rst1>;
  327. pinctrl-7 = <&camera_pins_cam1_pnd0>;
  328. pinctrl-8 = <&camera_pins_cam1_pnd1>;
  329. pinctrl-9 = <&camera_pins_cam_ldo0_0>;
  330. pinctrl-10 = <&camera_pins_cam_ldo0_1>;
  331. status = "okay";
  332. };
  333. /* CAMERA GPIO end */
  334. /* CONSYS GPIO standardization */
  335. &pio {
  336. consys_pins_default: default {
  337. };
  338. gpslna_pins_init: gpslna@0 {
  339. pins_cmd_dat {
  340. pins = <PINMUX_GPIO77__FUNC_GPIO77>;
  341. slew-rate = <0>;
  342. bias-disable;
  343. output-low;
  344. };
  345. };
  346. gpslna_pins_oh: gpslna@1 {
  347. pins_cmd_dat {
  348. pins = <PINMUX_GPIO77__FUNC_GPIO77>;
  349. slew-rate = <1>;
  350. bias-pull-up = <00>;
  351. output-high;
  352. };
  353. };
  354. gpslna_pins_ol: gpslna@2 {
  355. pins_cmd_dat {
  356. pins = <PINMUX_GPIO77__FUNC_GPIO77>;
  357. slew-rate = <1>;
  358. bias-pull-up = <00>;
  359. output-low;
  360. };
  361. };
  362. };
  363. &consys {
  364. pinctrl-names = "default", "gps_lna_state_init", "gps_lna_state_oh", "gps_lna_state_ol";
  365. pinctrl-0 = <&consys_pins_default>;
  366. pinctrl-1 = <&gpslna_pins_init>;
  367. pinctrl-2 = <&gpslna_pins_oh>;
  368. pinctrl-3 = <&gpslna_pins_ol>;
  369. status = "okay";
  370. };
  371. /* CONSYS end */
  372. /* mmc start */
  373. &mmc0 {
  374. clk_src = /bits/ 8 <MSDC50_CLKSRC_400MHZ>;
  375. bus-width = <8>;
  376. max-frequency = <200000000>;
  377. cap-mmc-highspeed;
  378. msdc-sys-suspend;
  379. mmc-ddr-1_8v;
  380. mmc-hs200-1_8v;
  381. mmc-hs400-1_8v;
  382. non-removable;
  383. pinctl = <&mmc0_pins_default>;
  384. register_setting = <&mmc0_register_setting_default>;
  385. host_function = /bits/ 8 <MSDC_EMMC>;
  386. bootable;
  387. status = "okay";
  388. };
  389. &mmc1 {
  390. clk_src = /bits/ 8 <MSDC30_CLKSRC_200MHZ>;
  391. bus-width = <4>;
  392. max-frequency = <200000000>;
  393. msdc-sys-suspend;
  394. sd_need_power;
  395. cap-sd-highspeed;
  396. //remove uhs support xmzyw bugid:56318
  397. /*
  398. sd-uhs-sdr12;
  399. sd-uhs-sdr25;
  400. sd-uhs-sdr50;
  401. sd-uhs-sdr104;
  402. sd-uhs-ddr50;
  403. */
  404. pinctl = <&mmc1_pins_default>;
  405. pinctl_sdr104 = <&mmc1_pins_sdr104>;
  406. pinctl_sdr50 = <&mmc1_pins_sdr50>;
  407. pinctl_ddr50 = <&mmc1_pins_ddr50>;
  408. register_setting = <&mmc1_register_setting_default>;
  409. host_function = /bits/ 8 <MSDC_SD>;
  410. cd_level = /bits/ 8 <MSDC_CD_LOW>;
  411. cd-gpios = <&pio 76 0>;
  412. status = "okay";
  413. };
  414. &mmc2 {
  415. clk_src = /bits/ 8 <MSDC30_CLKSRC_200MHZ>;
  416. bus-width = <4>;
  417. max-frequency = <200000000>;
  418. cap-sd-highspeed;
  419. sd-uhs-sdr12;
  420. sd-uhs-sdr25;
  421. sd-uhs-sdr50;
  422. sd-uhs-sdr104;
  423. sd-uhs-ddr50;
  424. non-removable;
  425. host_function = /bits/ 8 <MSDC_SDIO>;
  426. status = "okay";
  427. };
  428. &pio {
  429. mmc0_pins_default: mmc0@default {
  430. pins_cmd {
  431. drive-strength = /bits/ 8 <2>;
  432. };
  433. pins_dat {
  434. drive-strength = /bits/ 8 <2>;
  435. };
  436. pins_clk {
  437. drive-strength = /bits/ 8 <2>;
  438. };
  439. pins_rst {
  440. drive-strength = /bits/ 8 <2>;
  441. };
  442. pins_ds {
  443. drive-strength = /bits/ 8 <2>;
  444. };
  445. };
  446. mmc0_register_setting_default: mmc0@register_default {
  447. dat0rddly = /bits/ 8 <0>;
  448. dat1rddly = /bits/ 8 <0>;
  449. dat2rddly = /bits/ 8 <0>;
  450. dat3rddly = /bits/ 8 <0>;
  451. dat4rddly = /bits/ 8 <0>;
  452. dat5rddly = /bits/ 8 <0>;
  453. dat6rddly = /bits/ 8 <0>;
  454. dat7rddly = /bits/ 8 <0>;
  455. datwrddly = /bits/ 8 <0>;
  456. cmdrrddly = /bits/ 8 <0>;
  457. cmdrddly = /bits/ 8 <0>;
  458. cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  459. rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  460. wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  461. ett-hs200-cells = <12>;
  462. ett-hs200-default = <OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_INT_DAT_LATCH_CK_SEL 0x0
  463. OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_CKGEN_MSDC_DLY_SEL 0x0
  464. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_CMD_RSP_TA_CNTR 0x1
  465. OFFSET_MSDC_IOCON MSDC_IOCON_RSPL 0x1
  466. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRDLY 0xf
  467. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRRDLY 0x0
  468. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_WRDAT_CRCS_TA_CNTR 0x1
  469. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_DATWRDLY 0xf
  470. OFFSET_MSDC_IOCON MSDC_IOCON_W_D0SPL 0x1
  471. OFFSET_MSDC_DAT_RDDLY0 MSDC_DAT_RDDLY0_D0 0xf
  472. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_DATRRDLY 0x16
  473. OFFSET_MSDC_IOCON MSDC_IOCON_R_D_SMPL 0x0>;
  474. ett-hs400-cells = <8>;
  475. ett-hs400-default = <OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_INT_DAT_LATCH_CK_SEL 0x0
  476. OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_CKGEN_MSDC_DLY_SEL 0x0
  477. OFFSET_EMMC50_PAD_DS_TUNE MSDC_EMMC50_PAD_DS_TUNE_DLY1 0x2
  478. OFFSET_EMMC50_PAD_DS_TUNE MSDC_EMMC50_PAD_DS_TUNE_DLY3 0xe
  479. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_CMD_RSP_TA_CNTR 0x1
  480. OFFSET_MSDC_IOCON MSDC_IOCON_RSPL 0x0
  481. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRDLY 0xf
  482. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRRDLY 0xd>;
  483. };
  484. mmc1_pins_default: mmc1@default {
  485. pins_cmd {
  486. drive-strength = /bits/ 8 <3>;
  487. };
  488. pins_dat {
  489. drive-strength = /bits/ 8 <3>;
  490. };
  491. pins_clk {
  492. drive-strength = /bits/ 8 <3>;
  493. };
  494. };
  495. mmc1_pins_sdr104: mmc1@sdr104 {
  496. pins_cmd {
  497. drive-strength = /bits/ 8 <2>;
  498. };
  499. pins_dat {
  500. drive-strength = /bits/ 8 <2>;
  501. };
  502. pins_clk {
  503. drive-strength = /bits/ 8 <3>;
  504. };
  505. };
  506. mmc1_pins_sdr50: mmc1@sdr50 {
  507. pins_cmd {
  508. drive-strength = /bits/ 8 <2>;
  509. };
  510. pins_dat {
  511. drive-strength = /bits/ 8 <2>;
  512. };
  513. pins_clk {
  514. drive-strength = /bits/ 8 <3>;
  515. };
  516. };
  517. mmc1_pins_ddr50: mmc1@ddr50 {
  518. pins_cmd {
  519. drive-strength = /bits/ 8 <2>;
  520. };
  521. pins_dat {
  522. drive-strength = /bits/ 8 <2>;
  523. };
  524. pins_clk {
  525. drive-strength = /bits/ 8 <3>;
  526. };
  527. };
  528. mmc1_register_setting_default: mmc1@register_default {
  529. dat0rddly = /bits/ 8 <0>;
  530. dat1rddly = /bits/ 8 <0>;
  531. dat2rddly = /bits/ 8 <0>;
  532. dat3rddly = /bits/ 8 <0>;
  533. datwrddly = /bits/ 8 <0>;
  534. cmdrrddly = /bits/ 8 <0>;
  535. cmdrddly = /bits/ 8 <0>;
  536. cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  537. rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  538. wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  539. };
  540. };
  541. /* mmc end */
  542. /* USB GPIO Kernal Standardization start */
  543. &pio {
  544. usb_default: usb_default {
  545. };
  546. gpio67_mode5_iddig: iddig_irq_init {
  547. pins_cmd_dat {
  548. pins = <PINMUX_GPIO67__FUNC_IDDIG>;
  549. slew-rate = <0>;
  550. bias-pull-up = <00>;
  551. };
  552. };
  553. gpio83_mode2_drvvbus: drvvbus_init {
  554. pins_cmd_dat {
  555. pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
  556. slew-rate = <1>;
  557. bias-pull-up = <00>;
  558. };
  559. };
  560. gpio83_mode2_drvvbus_low: drvvbus_low {
  561. pins_cmd_dat {
  562. pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
  563. slew-rate = <1>;
  564. output-low;
  565. };
  566. };
  567. gpio83_mode2_drvvbus_high: drvvbus_high {
  568. pins_cmd_dat {
  569. pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
  570. slew-rate = <1>;
  571. output-high;
  572. };
  573. };
  574. };
  575. &usb0 {
  576. iddig_gpio = <67 1>;
  577. pinctrl-names = "usb_default", "iddig_irq_init", "drvvbus_init", "drvvbus_low", "drvvbus_high";
  578. pinctrl-0 = <&usb_default>;
  579. pinctrl-1 = <&gpio67_mode5_iddig>;
  580. pinctrl-2 = <&gpio83_mode2_drvvbus>;
  581. pinctrl-3 = <&gpio83_mode2_drvvbus_low>;
  582. pinctrl-4 = <&gpio83_mode2_drvvbus_high>;
  583. status = "okay";
  584. };
  585. /* USB GPIO Kernal Standardization end */
  586. /* AUDIO GPIO standardization */
  587. &mt_soc_dl1_pcm {
  588. pinctrl-names = "default", "audpmicclk-mode0", "audpmicclk-mode1", "audi2s1-mode0", "audi2s1-mode1", "extamp-pullhigh", "extamp-pulllow", "rcvspk-pullhigh", "rcvspk-pulllow";
  589. pinctrl-0 = <&aud_pins_default>;
  590. pinctrl-1 = <&aud_pins_pmicclk_mode0>;
  591. pinctrl-2 = <&aud_pins_pmicclk_mode1>;
  592. pinctrl-3 = <&aud_pins_i2s1_mode0>;
  593. pinctrl-4 = <&aud_pins_i2s1_mode1>;
  594. pinctrl-5 = <&aud_pins_extamp_high>;
  595. pinctrl-6 = <&aud_pins_extamp_low>;
  596. pinctrl-7 = <&aud_pins_rcvspk_high>;
  597. pinctrl-8 = <&aud_pins_rcvspk_low>;
  598. status = "okay";
  599. };
  600. &pio {
  601. aud_pins_default: audiodefault {
  602. };
  603. aud_pins_pmicclk_mode0: pmicclkmode0 {
  604. pins_cmd0_dat {
  605. pins = <PINMUX_GPIO143__FUNC_GPIO143>;
  606. };
  607. pins_cmd1_dat {
  608. pins = <PINMUX_GPIO144__FUNC_GPIO144>;
  609. };
  610. pins_cmd2_dat {
  611. pins = <PINMUX_GPIO145__FUNC_GPIO145>;
  612. };
  613. };
  614. aud_pins_pmicclk_mode1: pmicclkmode1 {
  615. pins_cmd0_dat {
  616. pins = <PINMUX_GPIO143__FUNC_AUD_CLK_MOSI>;
  617. };
  618. pins_cmd1_dat {
  619. pins = <PINMUX_GPIO144__FUNC_AUD_DAT_MISO>;
  620. };
  621. pins_cmd2_dat {
  622. pins = <PINMUX_GPIO145__FUNC_AUD_DAT_MOSI>;
  623. };
  624. };
  625. aud_pins_i2s1_mode0: audi2s1mode0 {
  626. pins_cmd0_dat {
  627. pins = <PINMUX_GPIO78__FUNC_GPIO78>;
  628. };
  629. pins_cmd1_dat {
  630. pins = <PINMUX_GPIO79__FUNC_GPIO79>;
  631. };
  632. pins_cmd2_dat {
  633. pins = <PINMUX_GPIO80__FUNC_GPIO80>;
  634. };
  635. };
  636. aud_pins_i2s1_mode1: audi2s1mode1 {
  637. pins_cmd0_dat {
  638. pins = <PINMUX_GPIO78__FUNC_I2S0_DI>;
  639. };
  640. pins_cmd1_dat {
  641. pins = <PINMUX_GPIO79__FUNC_I2S0_LRCK>;
  642. };
  643. pins_cmd2_dat {
  644. pins = <PINMUX_GPIO80__FUNC_I2S0_BCK>;
  645. };
  646. };
  647. aud_pins_extamp_high: audexamphigh {
  648. pins_cmd_dat {
  649. pins = <PINMUX_GPIO64__FUNC_GPIO64>;
  650. slew-rate = <1>;
  651. output-high;
  652. };
  653. };
  654. aud_pins_extamp_low: audexamplow {
  655. pins_cmd_dat {
  656. pins = <PINMUX_GPIO64__FUNC_GPIO64>;
  657. slew-rate = <1>;
  658. output-low;
  659. };
  660. };
  661. aud_pins_rcvspk_high: audrcvspkhigh {
  662. pins_cmd_dat {
  663. pins = <PINMUX_GPIO120__FUNC_GPIO120>;
  664. slew-rate = <1>;
  665. output-low; /*set low for receiver out*/
  666. };
  667. };
  668. aud_pins_rcvspk_low: audrcvspklow {
  669. pins_cmd_dat {
  670. pins = <PINMUX_GPIO120__FUNC_GPIO120>;
  671. slew-rate = <1>;
  672. output-high; /*set high for speaker out*/
  673. };
  674. };
  675. };
  676. /* AUDIO end */
  677. /* LCM GPIO Kernal Standardization start */
  678. &pio {
  679. lcm_mode_default: lcm_mode_default {
  680. pins_cmd_dat {
  681. pins = <PINMUX_GPIO80__FUNC_GPIO80>;
  682. };
  683. };
  684. lcm_mode_00: lcm_mode@0 {
  685. pins_cmd_dat {
  686. pins = <PINMUX_GPIO80__FUNC_GPIO80>;
  687. };
  688. };
  689. lcm_mode_01: lcm_mode@1 {
  690. pins_cmd_dat {
  691. pins = <PINMUX_GPIO80__FUNC_I2S0_BCK>;
  692. };
  693. };
  694. lcm_mode_02: lcm_mode@2 {
  695. pins_cmd_dat {
  696. pins = <PINMUX_GPIO80__FUNC_PCM1_CLK_1>;
  697. };
  698. };
  699. lcm_mode_03: lcm_mode@3 {
  700. pins_cmd_dat {
  701. pins = <PINMUX_GPIO80__FUNC_I2S3_BCK>;
  702. };
  703. };
  704. lcm_mode_04: lcm_mode@4 {
  705. pins_cmd_dat {
  706. pins = <PINMUX_GPIO80__FUNC_I2S1_BCK>;
  707. };
  708. };
  709. lcm_mode_05: lcm_mode@5 {
  710. pins_cmd_dat {
  711. pins = <PINMUX_GPIO80__FUNC_PWM4>;
  712. };
  713. };
  714. lcm_mode_06: lcm_mode@6 {
  715. pins_cmd_dat {
  716. pins = <PINMUX_GPIO80__FUNC_I2S2_BCK>;
  717. };
  718. };
  719. lcm_mode_07: lcm_mode@7 {
  720. pins_cmd_dat {
  721. pins = <PINMUX_GPIO80__FUNC_DBG_MON_A28>;
  722. };
  723. };
  724. };
  725. &lcm {
  726. gpio_lcm_pwr_en = <&pio 57 0>;
  727. gpio_lcm_rst_en = <&pio 146 0>;
  728. lcm_bl_gpio = <&pio 3 0>;
  729. lcm_bias_enp_gpio= <&pio 58 0>;
  730. lcm_id_gpio= <&pio 19 0>;
  731. };
  732. &lcm_mode {
  733. pinctrl-names = "default", "lcm_mode_00", "lcm_mode_01", "lcm_mode_02", "lcm_mode_03", "lcm_mode_04",
  734. "lcm_mode_05", "lcm_mode_06", "lcm_mode_07";
  735. pinctrl-0 = <&lcm_mode_default>;
  736. pinctrl-1 = <&lcm_mode_00>;
  737. pinctrl-2 = <&lcm_mode_01>;
  738. pinctrl-3 = <&lcm_mode_02>;
  739. pinctrl-4 = <&lcm_mode_03>;
  740. pinctrl-5 = <&lcm_mode_04>;
  741. pinctrl-6 = <&lcm_mode_05>;
  742. pinctrl-7 = <&lcm_mode_06>;
  743. pinctrl-8 = <&lcm_mode_07>;
  744. lcm_power_gpio = <&pio 80 0>;
  745. lcm_bl_gpio = <&pio 129 0>;
  746. status = "okay";
  747. };
  748. /* LCM GPIO Kernal Standardization end */
  749. /* i2c start */
  750. &i2c3 {
  751. bq24296@6b {
  752. status = "okay";
  753. compatible = "bq24296";
  754. reg = <0x6b>;
  755. };
  756. };
  757. /* i2c end */