b4420si-post.dtsi 4.1 KB

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  1. /*
  2. * B4420 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2012 Freescale Semiconductor, Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * This software is provided by Freescale Semiconductor "as is" and any
  24. * express or implied warranties, including, but not limited to, the implied
  25. * warranties of merchantability and fitness for a particular purpose are
  26. * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27. * direct, indirect, incidental, special, exemplary, or consequential damages
  28. * (including, but not limited to, procurement of substitute goods or services;
  29. * loss of use, data, or profits; or business interruption) however caused and
  30. * on any theory of liability, whether in contract, strict liability, or tort
  31. * (including negligence or otherwise) arising in any way out of the use of
  32. * this software, even if advised of the possibility of such damage.
  33. */
  34. /include/ "b4si-post.dtsi"
  35. /* controller at 0x200000 */
  36. &pci0 {
  37. compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
  38. };
  39. &dcsr {
  40. dcsr-epu@0 {
  41. compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
  42. };
  43. dcsr-npc {
  44. compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
  45. };
  46. dcsr-dpaa@9000 {
  47. compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
  48. };
  49. dcsr-ocn@11000 {
  50. compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
  51. };
  52. dcsr-nal@18000 {
  53. compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
  54. };
  55. dcsr-rcpm@22000 {
  56. compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
  57. };
  58. dcsr-snpc@30000 {
  59. compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
  60. };
  61. dcsr-snpc@31000 {
  62. compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
  63. };
  64. dcsr-cpu-sb-proxy@108000 {
  65. compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  66. cpu-handle = <&cpu1>;
  67. reg = <0x108000 0x1000 0x109000 0x1000>;
  68. };
  69. };
  70. &soc {
  71. cpc: l3-cache-controller@10000 {
  72. compatible = "fsl,b4420-l3-cache-controller", "cache";
  73. };
  74. guts: global-utilities@e0000 {
  75. compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
  76. };
  77. clockgen: global-utilities@e1000 {
  78. compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
  79. ranges = <0x0 0xe1000 0x1000>;
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. sysclk: sysclk {
  83. #clock-cells = <0>;
  84. compatible = "fsl,qoriq-sysclk-2.0";
  85. clock-output-names = "sysclk";
  86. };
  87. pll0: pll0@800 {
  88. #clock-cells = <1>;
  89. reg = <0x800 0x4>;
  90. compatible = "fsl,qoriq-core-pll-2.0";
  91. clocks = <&sysclk>;
  92. clock-output-names = "pll0", "pll0-div2", "pll0-div4";
  93. };
  94. pll1: pll1@820 {
  95. #clock-cells = <1>;
  96. reg = <0x820 0x4>;
  97. compatible = "fsl,qoriq-core-pll-2.0";
  98. clocks = <&sysclk>;
  99. clock-output-names = "pll1", "pll1-div2", "pll1-div4";
  100. };
  101. mux0: mux0@0 {
  102. #clock-cells = <0>;
  103. reg = <0x0 0x4>;
  104. compatible = "fsl,qoriq-core-mux-2.0";
  105. clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
  106. <&pll1 0>, <&pll1 1>, <&pll1 2>;
  107. clock-names = "pll0", "pll0-div2", "pll0-div4",
  108. "pll1", "pll1-div2", "pll1-div4";
  109. clock-output-names = "cmux0";
  110. };
  111. };
  112. rcpm: global-utilities@e2000 {
  113. compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
  114. };
  115. L2: l2-cache-controller@c20000 {
  116. compatible = "fsl,b4420-l2-cache-controller";
  117. };
  118. };