bsc9132si-post.dtsi 4.4 KB

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  1. /*
  2. * BSC9132 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2014 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &ifc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,ifc", "simple-bus";
  38. /* FIXME: Test whether interrupts are split */
  39. interrupts = <16 2 0 0 20 2 0 0>;
  40. };
  41. &soc {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. device_type = "soc";
  45. compatible = "fsl,bsc9132-immr", "simple-bus";
  46. bus-frequency = <0>; // Filled out by uboot.
  47. ecm-law@0 {
  48. compatible = "fsl,ecm-law";
  49. reg = <0x0 0x1000>;
  50. fsl,num-laws = <12>;
  51. };
  52. ecm@1000 {
  53. compatible = "fsl,bsc9132-ecm", "fsl,ecm";
  54. reg = <0x1000 0x1000>;
  55. interrupts = <16 2 0 0>;
  56. };
  57. memory-controller@2000 {
  58. compatible = "fsl,bsc9132-memory-controller";
  59. reg = <0x2000 0x1000>;
  60. interrupts = <16 2 1 8>;
  61. };
  62. /include/ "pq3-i2c-0.dtsi"
  63. i2c@3000 {
  64. interrupts = <17 2 0 0>;
  65. };
  66. /include/ "pq3-i2c-1.dtsi"
  67. i2c@3100 {
  68. interrupts = <17 2 0 0>;
  69. };
  70. /include/ "pq3-duart-0.dtsi"
  71. serial0: serial@4500 {
  72. interrupts = <18 2 0 0>;
  73. };
  74. serial1: serial@4600 {
  75. interrupts = <18 2 0 0 >;
  76. };
  77. /include/ "pq3-espi-0.dtsi"
  78. spi0: spi@7000 {
  79. fsl,espi-num-chipselects = <1>;
  80. interrupts = <22 0x2 0 0>;
  81. };
  82. /include/ "pq3-gpio-0.dtsi"
  83. gpio-controller@f000 {
  84. interrupts = <19 0x2 0 0>;
  85. };
  86. L2: l2-cache-controller@20000 {
  87. compatible = "fsl,bsc9132-l2-cache-controller";
  88. reg = <0x20000 0x1000>;
  89. cache-line-size = <32>; // 32 bytes
  90. cache-size = <0x40000>; // L2,256K
  91. interrupts = <16 2 1 0>;
  92. };
  93. /include/ "pq3-dma-0.dtsi"
  94. dma@21300 {
  95. dma-channel@0 {
  96. interrupts = <62 2 0 0>;
  97. };
  98. dma-channel@80 {
  99. interrupts = <63 2 0 0>;
  100. };
  101. dma-channel@100 {
  102. interrupts = <64 2 0 0>;
  103. };
  104. dma-channel@180 {
  105. interrupts = <65 2 0 0>;
  106. };
  107. };
  108. /include/ "pq3-usb2-dr-0.dtsi"
  109. usb@22000 {
  110. compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
  111. interrupts = <40 0x2 0 0>;
  112. };
  113. /include/ "pq3-esdhc-0.dtsi"
  114. sdhc@2e000 {
  115. fsl,sdhci-auto-cmd12;
  116. interrupts = <41 0x2 0 0>;
  117. };
  118. /include/ "pq3-sec4.4-0.dtsi"
  119. crypto@30000 {
  120. interrupts = <57 2 0 0>;
  121. sec_jr0: jr@1000 {
  122. interrupts = <58 2 0 0>;
  123. };
  124. sec_jr1: jr@2000 {
  125. interrupts = <59 2 0 0>;
  126. };
  127. sec_jr2: jr@3000 {
  128. interrupts = <60 2 0 0>;
  129. };
  130. sec_jr3: jr@4000 {
  131. interrupts = <61 2 0 0>;
  132. };
  133. };
  134. /include/ "pq3-mpic.dtsi"
  135. /include/ "pq3-mpic-timer-B.dtsi"
  136. /include/ "pq3-etsec2-0.dtsi"
  137. enet0: ethernet@b0000 {
  138. queue-group@b0000 {
  139. fsl,rx-bit-map = <0xff>;
  140. fsl,tx-bit-map = <0xff>;
  141. interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
  142. };
  143. };
  144. /include/ "pq3-etsec2-1.dtsi"
  145. enet1: ethernet@b1000 {
  146. queue-group@b1000 {
  147. fsl,rx-bit-map = <0xff>;
  148. fsl,tx-bit-map = <0xff>;
  149. interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
  150. };
  151. };
  152. global-utilities@e0000 {
  153. compatible = "fsl,bsc9132-guts";
  154. reg = <0xe0000 0x1000>;
  155. fsl,has-rstcr;
  156. };
  157. };