t1040si-post.dtsi 11 KB

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  1. /*
  2. * T1040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2013 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &ifc {
  35. #address-cells = <2>;
  36. #size-cells = <1>;
  37. compatible = "fsl,ifc", "simple-bus";
  38. interrupts = <25 2 0 0>;
  39. };
  40. &pci0 {
  41. compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
  42. device_type = "pci";
  43. #size-cells = <2>;
  44. #address-cells = <3>;
  45. bus-range = <0x0 0xff>;
  46. interrupts = <20 2 0 0>;
  47. fsl,iommu-parent = <&pamu0>;
  48. pcie@0 {
  49. reg = <0 0 0 0 0>;
  50. #interrupt-cells = <1>;
  51. #size-cells = <2>;
  52. #address-cells = <3>;
  53. device_type = "pci";
  54. interrupts = <20 2 0 0>;
  55. interrupt-map-mask = <0xf800 0 0 7>;
  56. interrupt-map = <
  57. /* IDSEL 0x0 */
  58. 0000 0 0 1 &mpic 40 1 0 0
  59. 0000 0 0 2 &mpic 1 1 0 0
  60. 0000 0 0 3 &mpic 2 1 0 0
  61. 0000 0 0 4 &mpic 3 1 0 0
  62. >;
  63. };
  64. };
  65. &pci1 {
  66. compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
  67. device_type = "pci";
  68. #size-cells = <2>;
  69. #address-cells = <3>;
  70. bus-range = <0 0xff>;
  71. interrupts = <21 2 0 0>;
  72. fsl,iommu-parent = <&pamu0>;
  73. pcie@0 {
  74. reg = <0 0 0 0 0>;
  75. #interrupt-cells = <1>;
  76. #size-cells = <2>;
  77. #address-cells = <3>;
  78. device_type = "pci";
  79. interrupts = <21 2 0 0>;
  80. interrupt-map-mask = <0xf800 0 0 7>;
  81. interrupt-map = <
  82. /* IDSEL 0x0 */
  83. 0000 0 0 1 &mpic 41 1 0 0
  84. 0000 0 0 2 &mpic 5 1 0 0
  85. 0000 0 0 3 &mpic 6 1 0 0
  86. 0000 0 0 4 &mpic 7 1 0 0
  87. >;
  88. };
  89. };
  90. &pci2 {
  91. compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
  92. device_type = "pci";
  93. #size-cells = <2>;
  94. #address-cells = <3>;
  95. bus-range = <0x0 0xff>;
  96. interrupts = <22 2 0 0>;
  97. fsl,iommu-parent = <&pamu0>;
  98. pcie@0 {
  99. reg = <0 0 0 0 0>;
  100. #interrupt-cells = <1>;
  101. #size-cells = <2>;
  102. #address-cells = <3>;
  103. device_type = "pci";
  104. interrupts = <22 2 0 0>;
  105. interrupt-map-mask = <0xf800 0 0 7>;
  106. interrupt-map = <
  107. /* IDSEL 0x0 */
  108. 0000 0 0 1 &mpic 42 1 0 0
  109. 0000 0 0 2 &mpic 9 1 0 0
  110. 0000 0 0 3 &mpic 10 1 0 0
  111. 0000 0 0 4 &mpic 11 1 0 0
  112. >;
  113. };
  114. };
  115. &pci3 {
  116. compatible = "fsl,t1040-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
  117. device_type = "pci";
  118. #size-cells = <2>;
  119. #address-cells = <3>;
  120. bus-range = <0x0 0xff>;
  121. interrupts = <23 2 0 0>;
  122. fsl,iommu-parent = <&pamu0>;
  123. pcie@0 {
  124. reg = <0 0 0 0 0>;
  125. #interrupt-cells = <1>;
  126. #size-cells = <2>;
  127. #address-cells = <3>;
  128. device_type = "pci";
  129. interrupts = <23 2 0 0>;
  130. interrupt-map-mask = <0xf800 0 0 7>;
  131. interrupt-map = <
  132. /* IDSEL 0x0 */
  133. 0000 0 0 1 &mpic 43 1 0 0
  134. 0000 0 0 2 &mpic 0 1 0 0
  135. 0000 0 0 3 &mpic 4 1 0 0
  136. 0000 0 0 4 &mpic 8 1 0 0
  137. >;
  138. };
  139. };
  140. &dcsr {
  141. #address-cells = <1>;
  142. #size-cells = <1>;
  143. compatible = "fsl,dcsr", "simple-bus";
  144. dcsr-epu@0 {
  145. compatible = "fsl,t1040-dcsr-epu", "fsl,dcsr-epu";
  146. interrupts = <52 2 0 0
  147. 84 2 0 0
  148. 85 2 0 0>;
  149. reg = <0x0 0x1000>;
  150. };
  151. dcsr-npc {
  152. compatible = "fsl,t1040-dcsr-cnpc", "fsl,dcsr-cnpc";
  153. reg = <0x1000 0x1000 0x1002000 0x10000>;
  154. };
  155. dcsr-nxc@2000 {
  156. compatible = "fsl,dcsr-nxc";
  157. reg = <0x2000 0x1000>;
  158. };
  159. dcsr-corenet {
  160. compatible = "fsl,dcsr-corenet";
  161. reg = <0x8000 0x1000 0x1A000 0x1000>;
  162. };
  163. dcsr-dpaa@9000 {
  164. compatible = "fsl,t1040-dcsr-dpaa", "fsl,dcsr-dpaa";
  165. reg = <0x9000 0x1000>;
  166. };
  167. dcsr-ocn@11000 {
  168. compatible = "fsl,t1040-dcsr-ocn", "fsl,dcsr-ocn";
  169. reg = <0x11000 0x1000>;
  170. };
  171. dcsr-ddr@12000 {
  172. compatible = "fsl,dcsr-ddr";
  173. dev-handle = <&ddr1>;
  174. reg = <0x12000 0x1000>;
  175. };
  176. dcsr-nal@18000 {
  177. compatible = "fsl,t1040-dcsr-nal", "fsl,dcsr-nal";
  178. reg = <0x18000 0x1000>;
  179. };
  180. dcsr-rcpm@22000 {
  181. compatible = "fsl,t1040-dcsr-rcpm", "fsl,dcsr-rcpm";
  182. reg = <0x22000 0x1000>;
  183. };
  184. dcsr-snpc@30000 {
  185. compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
  186. reg = <0x30000 0x1000 0x1022000 0x10000>;
  187. };
  188. dcsr-snpc@31000 {
  189. compatible = "fsl,t1040-dcsr-snpc", "fsl,dcsr-snpc";
  190. reg = <0x31000 0x1000 0x1042000 0x10000>;
  191. };
  192. dcsr-cpu-sb-proxy@100000 {
  193. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  194. cpu-handle = <&cpu0>;
  195. reg = <0x100000 0x1000 0x101000 0x1000>;
  196. };
  197. dcsr-cpu-sb-proxy@108000 {
  198. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  199. cpu-handle = <&cpu1>;
  200. reg = <0x108000 0x1000 0x109000 0x1000>;
  201. };
  202. dcsr-cpu-sb-proxy@110000 {
  203. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  204. cpu-handle = <&cpu2>;
  205. reg = <0x110000 0x1000 0x111000 0x1000>;
  206. };
  207. dcsr-cpu-sb-proxy@118000 {
  208. compatible = "fsl,dcsr-e5500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  209. cpu-handle = <&cpu3>;
  210. reg = <0x118000 0x1000 0x119000 0x1000>;
  211. };
  212. };
  213. &soc {
  214. #address-cells = <1>;
  215. #size-cells = <1>;
  216. device_type = "soc";
  217. compatible = "simple-bus";
  218. soc-sram-error {
  219. compatible = "fsl,soc-sram-error";
  220. interrupts = <16 2 1 29>;
  221. };
  222. corenet-law@0 {
  223. compatible = "fsl,corenet-law";
  224. reg = <0x0 0x1000>;
  225. fsl,num-laws = <16>;
  226. };
  227. ddr1: memory-controller@8000 {
  228. compatible = "fsl,qoriq-memory-controller-v5.0",
  229. "fsl,qoriq-memory-controller";
  230. reg = <0x8000 0x1000>;
  231. interrupts = <16 2 1 23>;
  232. };
  233. cpc: l3-cache-controller@10000 {
  234. compatible = "fsl,t1040-l3-cache-controller", "cache";
  235. reg = <0x10000 0x1000>;
  236. interrupts = <16 2 1 27>;
  237. };
  238. corenet-cf@18000 {
  239. compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
  240. reg = <0x18000 0x1000>;
  241. interrupts = <16 2 1 31>;
  242. fsl,ccf-num-csdids = <32>;
  243. fsl,ccf-num-snoopids = <32>;
  244. };
  245. iommu@20000 {
  246. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  247. reg = <0x20000 0x1000>;
  248. ranges = <0 0x20000 0x1000>;
  249. #address-cells = <1>;
  250. #size-cells = <1>;
  251. interrupts = <
  252. 24 2 0 0
  253. 16 2 1 30>;
  254. pamu0: pamu@0 {
  255. reg = <0 0x1000>;
  256. fsl,primary-cache-geometry = <128 1>;
  257. fsl,secondary-cache-geometry = <16 2>;
  258. };
  259. };
  260. /include/ "qoriq-mpic.dtsi"
  261. guts: global-utilities@e0000 {
  262. compatible = "fsl,t1040-device-config", "fsl,qoriq-device-config-2.0";
  263. reg = <0xe0000 0xe00>;
  264. fsl,has-rstcr;
  265. fsl,liodn-bits = <12>;
  266. };
  267. clockgen: global-utilities@e1000 {
  268. compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
  269. ranges = <0x0 0xe1000 0x1000>;
  270. reg = <0xe1000 0x1000>;
  271. #address-cells = <1>;
  272. #size-cells = <1>;
  273. sysclk: sysclk {
  274. #clock-cells = <0>;
  275. compatible = "fsl,qoriq-sysclk-2.0";
  276. clock-output-names = "sysclk", "fixed-clock";
  277. };
  278. pll0: pll0@800 {
  279. #clock-cells = <1>;
  280. reg = <0x800 4>;
  281. compatible = "fsl,qoriq-core-pll-2.0";
  282. clocks = <&sysclk>;
  283. clock-output-names = "pll0", "pll0-div2", "pll0-div4";
  284. };
  285. pll1: pll1@820 {
  286. #clock-cells = <1>;
  287. reg = <0x820 4>;
  288. compatible = "fsl,qoriq-core-pll-2.0";
  289. clocks = <&sysclk>;
  290. clock-output-names = "pll1", "pll1-div2", "pll1-div4";
  291. };
  292. mux0: mux0@0 {
  293. #clock-cells = <0>;
  294. reg = <0x0 4>;
  295. compatible = "fsl,qoriq-core-mux-2.0";
  296. clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
  297. <&pll1 0>, <&pll1 1>, <&pll1 2>;
  298. clock-names = "pll0", "pll0-div2", "pll1-div4",
  299. "pll1", "pll1-div2", "pll1-div4";
  300. clock-output-names = "cmux0";
  301. };
  302. mux1: mux1@20 {
  303. #clock-cells = <0>;
  304. reg = <0x20 4>;
  305. compatible = "fsl,qoriq-core-mux-2.0";
  306. clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
  307. <&pll1 0>, <&pll1 1>, <&pll1 2>;
  308. clock-names = "pll0", "pll0-div2", "pll1-div4",
  309. "pll1", "pll1-div2", "pll1-div4";
  310. clock-output-names = "cmux1";
  311. };
  312. mux2: mux2@40 {
  313. #clock-cells = <0>;
  314. reg = <0x40 4>;
  315. compatible = "fsl,qoriq-core-mux-2.0";
  316. clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
  317. <&pll1 0>, <&pll1 1>, <&pll1 2>;
  318. clock-names = "pll0", "pll0-div2", "pll1-div4",
  319. "pll1", "pll1-div2", "pll1-div4";
  320. clock-output-names = "cmux2";
  321. };
  322. mux3: mux3@60 {
  323. #clock-cells = <0>;
  324. reg = <0x60 4>;
  325. compatible = "fsl,qoriq-core-mux-2.0";
  326. clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
  327. <&pll1 0>, <&pll1 1>, <&pll1 2>;
  328. clock-names = "pll0_0", "pll0_1", "pll0_2",
  329. "pll1_0", "pll1_1", "pll1_2";
  330. clock-output-names = "cmux3";
  331. };
  332. };
  333. rcpm: global-utilities@e2000 {
  334. compatible = "fsl,t1040-rcpm", "fsl,qoriq-rcpm-2.0";
  335. reg = <0xe2000 0x1000>;
  336. };
  337. sfp: sfp@e8000 {
  338. compatible = "fsl,t1040-sfp";
  339. reg = <0xe8000 0x1000>;
  340. };
  341. serdes: serdes@ea000 {
  342. compatible = "fsl,t1040-serdes";
  343. reg = <0xea000 0x4000>;
  344. };
  345. /include/ "elo3-dma-0.dtsi"
  346. /include/ "elo3-dma-1.dtsi"
  347. /include/ "qoriq-espi-0.dtsi"
  348. spi@110000 {
  349. fsl,espi-num-chipselects = <4>;
  350. };
  351. /include/ "qoriq-esdhc-0.dtsi"
  352. sdhc@114000 {
  353. compatible = "fsl,t1040-esdhc", "fsl,esdhc";
  354. fsl,iommu-parent = <&pamu0>;
  355. fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
  356. sdhci,auto-cmd12;
  357. };
  358. /include/ "qoriq-i2c-0.dtsi"
  359. /include/ "qoriq-i2c-1.dtsi"
  360. /include/ "qoriq-duart-0.dtsi"
  361. /include/ "qoriq-duart-1.dtsi"
  362. /include/ "qoriq-gpio-0.dtsi"
  363. /include/ "qoriq-gpio-1.dtsi"
  364. /include/ "qoriq-gpio-2.dtsi"
  365. /include/ "qoriq-gpio-3.dtsi"
  366. /include/ "qoriq-usb2-mph-0.dtsi"
  367. usb0: usb@210000 {
  368. compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
  369. fsl,iommu-parent = <&pamu0>;
  370. fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
  371. phy_type = "utmi";
  372. port0;
  373. };
  374. /include/ "qoriq-usb2-dr-0.dtsi"
  375. usb1: usb@211000 {
  376. compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
  377. fsl,iommu-parent = <&pamu0>;
  378. fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
  379. dr_mode = "host";
  380. phy_type = "utmi";
  381. };
  382. display@180000 {
  383. compatible = "fsl,t1040-diu", "fsl,diu";
  384. reg = <0x180000 1000>;
  385. interrupts = <74 2 0 0>;
  386. };
  387. /include/ "qoriq-sata2-0.dtsi"
  388. sata@220000 {
  389. fsl,iommu-parent = <&pamu0>;
  390. fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
  391. };
  392. /include/ "qoriq-sata2-1.dtsi"
  393. sata@221000 {
  394. fsl,iommu-parent = <&pamu0>;
  395. fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
  396. };
  397. /include/ "qoriq-sec5.0-0.dtsi"
  398. };