kmcoge4.dts 3.1 KB

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  1. /*
  2. * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
  3. *
  4. * (C) Copyright 2014
  5. * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
  6. *
  7. * Copyright 2011 Freescale Semiconductor Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. /include/ "fsl/p2041si-pre.dtsi"
  15. / {
  16. model = "keymile,kmcoge4";
  17. compatible = "keymile,kmcoge4", "keymile,kmp204x";
  18. #address-cells = <2>;
  19. #size-cells = <2>;
  20. interrupt-parent = <&mpic>;
  21. memory {
  22. device_type = "memory";
  23. };
  24. dcsr: dcsr@f00000000 {
  25. ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  26. };
  27. soc: soc@ffe000000 {
  28. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  29. reg = <0xf 0xfe000000 0 0x00001000>;
  30. spi@110000 {
  31. flash@0 {
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. compatible = "spansion,s25fl256s1";
  35. reg = <0>;
  36. spi-max-frequency = <20000000>; /* input clock */
  37. };
  38. network_clock@1 {
  39. compatible = "zarlink,zl30343";
  40. reg = <1>;
  41. spi-max-frequency = <8000000>;
  42. };
  43. flash@2 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. compatible = "micron,m25p32";
  47. reg = <2>;
  48. spi-max-frequency = <15000000>;
  49. };
  50. };
  51. i2c@119000 {
  52. status = "disabled";
  53. };
  54. i2c@119100 {
  55. status = "disabled";
  56. };
  57. usb0: usb@210000 {
  58. status = "disabled";
  59. };
  60. usb1: usb@211000 {
  61. status = "disabled";
  62. };
  63. sata@220000 {
  64. status = "disabled";
  65. };
  66. sata@221000 {
  67. status = "disabled";
  68. };
  69. };
  70. rio: rapidio@ffe0c0000 {
  71. status = "disabled";
  72. };
  73. lbc: localbus@ffe124000 {
  74. reg = <0xf 0xfe124000 0 0x1000>;
  75. ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */
  76. 1 0 0xf 0xfb000000 0x00010000 /* LB 1 */
  77. 2 0 0xf 0xd0000000 0x10000000 /* LB 2 */
  78. 3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */
  79. nand@0,0 {
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. compatible = "fsl,elbc-fcm-nand";
  83. reg = <0 0 0x40000>;
  84. };
  85. board-control@1,0 {
  86. compatible = "keymile,qriox";
  87. reg = <1 0 0x80>;
  88. };
  89. chassis-mgmt@3,0 {
  90. compatible = "keymile,bfticu";
  91. interrupt-controller;
  92. #interrupt-cells = <2>;
  93. reg = <3 0 0x100>;
  94. interrupt-parent = <&mpic>;
  95. interrupts = <6 1 0 0>;
  96. };
  97. };
  98. pci0: pcie@ffe200000 {
  99. reg = <0xf 0xfe200000 0 0x1000>;
  100. ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
  101. 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
  102. pcie@0 {
  103. ranges = <0x02000000 0 0xe0000000
  104. 0x02000000 0 0xe0000000
  105. 0 0x20000000
  106. 0x01000000 0 0x00000000
  107. 0x01000000 0 0x00000000
  108. 0 0x00010000>;
  109. };
  110. };
  111. pci1: pcie@ffe201000 {
  112. status = "disabled";
  113. };
  114. pci2: pcie@ffe202000 {
  115. reg = <0xf 0xfe202000 0 0x1000>;
  116. ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
  117. 0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
  118. pcie@0 {
  119. ranges = <0x02000000 0 0xe0000000
  120. 0x02000000 0 0xe0000000
  121. 0 0x20000000
  122. 0x01000000 0 0x00000000
  123. 0x01000000 0 0x00000000
  124. 0 0x00010000>;
  125. };
  126. };
  127. };
  128. /include/ "fsl/p2041si-post.dtsi"