mpc8572ds_camp_core1.dts 2.3 KB

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  1. /*
  2. * MPC8572 DS Core1 Device Tree Source in CAMP mode.
  3. *
  4. * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
  5. * can be shared, all the other devices must be assigned to one core only.
  6. * This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
  7. *
  8. * Please note to add "-b 1" for core1's dts compiling.
  9. *
  10. * Copyright 2007-2009 Freescale Semiconductor Inc.
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. */
  17. /include/ "mpc8572ds.dts"
  18. / {
  19. model = "fsl,MPC8572DS";
  20. compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
  21. cpus {
  22. PowerPC,8572@0 {
  23. status = "disabled";
  24. };
  25. PowerPC,8572@1 {
  26. };
  27. };
  28. localbus@ffe05000 {
  29. status = "disabled";
  30. };
  31. soc8572@ffe00000 {
  32. ecm-law@0 {
  33. status = "disabled";
  34. };
  35. ecm@1000 {
  36. status = "disabled";
  37. };
  38. memory-controller@2000 {
  39. status = "disabled";
  40. };
  41. memory-controller@6000 {
  42. status = "disabled";
  43. };
  44. i2c@3000 {
  45. status = "disabled";
  46. };
  47. i2c@3100 {
  48. status = "disabled";
  49. };
  50. serial@4500 {
  51. status = "disabled";
  52. };
  53. gpio-controller@f000 {
  54. status = "disabled";
  55. };
  56. l2-cache-controller@20000 {
  57. cache-size = <0x80000>; // L2, 512K
  58. };
  59. dma@21300 {
  60. status = "disabled";
  61. };
  62. ethernet@24000 {
  63. status = "disabled";
  64. };
  65. ptp_clock@24e00 {
  66. status = "disabled";
  67. };
  68. ethernet@25000 {
  69. status = "disabled";
  70. };
  71. mdio@25520 {
  72. status = "disabled";
  73. };
  74. crypto@30000 {
  75. status = "disabled";
  76. };
  77. pic@40000 {
  78. protected-sources = <
  79. 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
  80. 29 30 34 35 36 40 /* enet0 enet1 */
  81. 24 25 20 21 22 23 /* pci0 pci1 dma1 */
  82. 43 /* i2c */
  83. 0x1 0x2 0x3 0x4 /* pci slot */
  84. 0x9 0xa 0xb 0xc /* usb */
  85. 0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
  86. 0xe0 0xe1 0xe2 0xe3 /* msi */
  87. >;
  88. };
  89. timer@41100 {
  90. status = "disabled";
  91. };
  92. msi@41600 {
  93. msi-available-ranges = <0x80 0x80>;
  94. interrupts = <
  95. 0xe4 0 0 0
  96. 0xe5 0 0 0
  97. 0xe6 0 0 0
  98. 0xe7 0 0 0>;
  99. };
  100. global-utilities@e0000 {
  101. status = "disabled";
  102. };
  103. };
  104. pcie@ffe08000 {
  105. status = "disabled";
  106. };
  107. pcie@ffe09000 {
  108. status = "disabled";
  109. };
  110. };