cache.h 2.0 KB

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  1. #ifndef _ASM_POWERPC_CACHE_H
  2. #define _ASM_POWERPC_CACHE_H
  3. #ifdef __KERNEL__
  4. #include <asm/reg.h>
  5. /* bytes per L1 cache line */
  6. #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
  7. #define L1_CACHE_SHIFT 4
  8. #define MAX_COPY_PREFETCH 1
  9. #elif defined(CONFIG_PPC_E500MC)
  10. #define L1_CACHE_SHIFT 6
  11. #define MAX_COPY_PREFETCH 4
  12. #elif defined(CONFIG_PPC32)
  13. #define MAX_COPY_PREFETCH 4
  14. #if defined(CONFIG_PPC_47x)
  15. #define L1_CACHE_SHIFT 7
  16. #else
  17. #define L1_CACHE_SHIFT 5
  18. #endif
  19. #else /* CONFIG_PPC64 */
  20. #define L1_CACHE_SHIFT 7
  21. #endif
  22. #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
  23. #define SMP_CACHE_BYTES L1_CACHE_BYTES
  24. #if defined(__powerpc64__) && !defined(__ASSEMBLY__)
  25. struct ppc64_caches {
  26. u32 dsize; /* L1 d-cache size */
  27. u32 dline_size; /* L1 d-cache line size */
  28. u32 log_dline_size;
  29. u32 dlines_per_page;
  30. u32 isize; /* L1 i-cache size */
  31. u32 iline_size; /* L1 i-cache line size */
  32. u32 log_iline_size;
  33. u32 ilines_per_page;
  34. };
  35. extern struct ppc64_caches ppc64_caches;
  36. static inline void logmpp(u64 x)
  37. {
  38. asm volatile(PPC_LOGMPP(R1) : : "r" (x));
  39. }
  40. #endif /* __powerpc64__ && ! __ASSEMBLY__ */
  41. #if defined(__ASSEMBLY__)
  42. /*
  43. * For a snooping icache, we still need a dummy icbi to purge all the
  44. * prefetched instructions from the ifetch buffers. We also need a sync
  45. * before the icbi to order the the actual stores to memory that might
  46. * have modified instructions with the icbi.
  47. */
  48. #define PURGE_PREFETCHED_INS \
  49. sync; \
  50. icbi 0,r3; \
  51. sync; \
  52. isync
  53. #else
  54. #define __read_mostly __attribute__((__section__(".data..read_mostly")))
  55. #ifdef CONFIG_6xx
  56. extern long _get_L2CR(void);
  57. extern long _get_L3CR(void);
  58. extern void _set_L2CR(unsigned long);
  59. extern void _set_L3CR(unsigned long);
  60. #else
  61. #define _get_L2CR() 0L
  62. #define _get_L3CR() 0L
  63. #define _set_L2CR(val) do { } while(0)
  64. #define _set_L3CR(val) do { } while(0)
  65. #endif
  66. extern void cacheable_memzero(void *p, unsigned int nb);
  67. extern void *cacheable_memcpy(void *, const void *, unsigned int);
  68. #endif /* !__ASSEMBLY__ */
  69. #endif /* __KERNEL__ */
  70. #endif /* _ASM_POWERPC_CACHE_H */