nvme-scsi.c 87 KB

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  1. /*
  2. * NVM Express device driver
  3. * Copyright (c) 2011-2014, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. */
  14. /*
  15. * Refer to the SCSI-NVMe Translation spec for details on how
  16. * each command is translated.
  17. */
  18. #include <linux/nvme.h>
  19. #include <linux/bio.h>
  20. #include <linux/bitops.h>
  21. #include <linux/blkdev.h>
  22. #include <linux/compat.h>
  23. #include <linux/delay.h>
  24. #include <linux/errno.h>
  25. #include <linux/fs.h>
  26. #include <linux/genhd.h>
  27. #include <linux/idr.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/io.h>
  31. #include <linux/kdev_t.h>
  32. #include <linux/kthread.h>
  33. #include <linux/kernel.h>
  34. #include <linux/mm.h>
  35. #include <linux/module.h>
  36. #include <linux/moduleparam.h>
  37. #include <linux/pci.h>
  38. #include <linux/poison.h>
  39. #include <linux/sched.h>
  40. #include <linux/slab.h>
  41. #include <linux/types.h>
  42. #include <scsi/sg.h>
  43. #include <scsi/scsi.h>
  44. static int sg_version_num = 30534; /* 2 digits for each component */
  45. #define SNTI_TRANSLATION_SUCCESS 0
  46. #define SNTI_INTERNAL_ERROR 1
  47. /* VPD Page Codes */
  48. #define VPD_SUPPORTED_PAGES 0x00
  49. #define VPD_SERIAL_NUMBER 0x80
  50. #define VPD_DEVICE_IDENTIFIERS 0x83
  51. #define VPD_EXTENDED_INQUIRY 0x86
  52. #define VPD_BLOCK_DEV_CHARACTERISTICS 0xB1
  53. /* CDB offsets */
  54. #define REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET 6
  55. #define REPORT_LUNS_SR_OFFSET 2
  56. #define READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET 10
  57. #define REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET 4
  58. #define REQUEST_SENSE_DESC_OFFSET 1
  59. #define REQUEST_SENSE_DESC_MASK 0x01
  60. #define DESCRIPTOR_FORMAT_SENSE_DATA_TYPE 1
  61. #define INQUIRY_EVPD_BYTE_OFFSET 1
  62. #define INQUIRY_PAGE_CODE_BYTE_OFFSET 2
  63. #define INQUIRY_EVPD_BIT_MASK 1
  64. #define INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET 3
  65. #define START_STOP_UNIT_CDB_IMMED_OFFSET 1
  66. #define START_STOP_UNIT_CDB_IMMED_MASK 0x1
  67. #define START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET 3
  68. #define START_STOP_UNIT_CDB_POWER_COND_MOD_MASK 0xF
  69. #define START_STOP_UNIT_CDB_POWER_COND_OFFSET 4
  70. #define START_STOP_UNIT_CDB_POWER_COND_MASK 0xF0
  71. #define START_STOP_UNIT_CDB_NO_FLUSH_OFFSET 4
  72. #define START_STOP_UNIT_CDB_NO_FLUSH_MASK 0x4
  73. #define START_STOP_UNIT_CDB_START_OFFSET 4
  74. #define START_STOP_UNIT_CDB_START_MASK 0x1
  75. #define WRITE_BUFFER_CDB_MODE_OFFSET 1
  76. #define WRITE_BUFFER_CDB_MODE_MASK 0x1F
  77. #define WRITE_BUFFER_CDB_BUFFER_ID_OFFSET 2
  78. #define WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET 3
  79. #define WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET 6
  80. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET 1
  81. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK 0xC0
  82. #define FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT 6
  83. #define FORMAT_UNIT_CDB_LONG_LIST_OFFSET 1
  84. #define FORMAT_UNIT_CDB_LONG_LIST_MASK 0x20
  85. #define FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET 1
  86. #define FORMAT_UNIT_CDB_FORMAT_DATA_MASK 0x10
  87. #define FORMAT_UNIT_SHORT_PARM_LIST_LEN 4
  88. #define FORMAT_UNIT_LONG_PARM_LIST_LEN 8
  89. #define FORMAT_UNIT_PROT_INT_OFFSET 3
  90. #define FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET 0
  91. #define FORMAT_UNIT_PROT_FIELD_USAGE_MASK 0x07
  92. #define UNMAP_CDB_PARAM_LIST_LENGTH_OFFSET 7
  93. /* Misc. defines */
  94. #define NIBBLE_SHIFT 4
  95. #define FIXED_SENSE_DATA 0x70
  96. #define DESC_FORMAT_SENSE_DATA 0x72
  97. #define FIXED_SENSE_DATA_ADD_LENGTH 10
  98. #define LUN_ENTRY_SIZE 8
  99. #define LUN_DATA_HEADER_SIZE 8
  100. #define ALL_LUNS_RETURNED 0x02
  101. #define ALL_WELL_KNOWN_LUNS_RETURNED 0x01
  102. #define RESTRICTED_LUNS_RETURNED 0x00
  103. #define NVME_POWER_STATE_START_VALID 0x00
  104. #define NVME_POWER_STATE_ACTIVE 0x01
  105. #define NVME_POWER_STATE_IDLE 0x02
  106. #define NVME_POWER_STATE_STANDBY 0x03
  107. #define NVME_POWER_STATE_LU_CONTROL 0x07
  108. #define POWER_STATE_0 0
  109. #define POWER_STATE_1 1
  110. #define POWER_STATE_2 2
  111. #define POWER_STATE_3 3
  112. #define DOWNLOAD_SAVE_ACTIVATE 0x05
  113. #define DOWNLOAD_SAVE_DEFER_ACTIVATE 0x0E
  114. #define ACTIVATE_DEFERRED_MICROCODE 0x0F
  115. #define FORMAT_UNIT_IMMED_MASK 0x2
  116. #define FORMAT_UNIT_IMMED_OFFSET 1
  117. #define KELVIN_TEMP_FACTOR 273
  118. #define FIXED_FMT_SENSE_DATA_SIZE 18
  119. #define DESC_FMT_SENSE_DATA_SIZE 8
  120. /* SCSI/NVMe defines and bit masks */
  121. #define INQ_STANDARD_INQUIRY_PAGE 0x00
  122. #define INQ_SUPPORTED_VPD_PAGES_PAGE 0x00
  123. #define INQ_UNIT_SERIAL_NUMBER_PAGE 0x80
  124. #define INQ_DEVICE_IDENTIFICATION_PAGE 0x83
  125. #define INQ_EXTENDED_INQUIRY_DATA_PAGE 0x86
  126. #define INQ_BDEV_CHARACTERISTICS_PAGE 0xB1
  127. #define INQ_SERIAL_NUMBER_LENGTH 0x14
  128. #define INQ_NUM_SUPPORTED_VPD_PAGES 5
  129. #define VERSION_SPC_4 0x06
  130. #define ACA_UNSUPPORTED 0
  131. #define STANDARD_INQUIRY_LENGTH 36
  132. #define ADDITIONAL_STD_INQ_LENGTH 31
  133. #define EXTENDED_INQUIRY_DATA_PAGE_LENGTH 0x3C
  134. #define RESERVED_FIELD 0
  135. /* SCSI READ/WRITE Defines */
  136. #define IO_CDB_WP_MASK 0xE0
  137. #define IO_CDB_WP_SHIFT 5
  138. #define IO_CDB_FUA_MASK 0x8
  139. #define IO_6_CDB_LBA_OFFSET 0
  140. #define IO_6_CDB_LBA_MASK 0x001FFFFF
  141. #define IO_6_CDB_TX_LEN_OFFSET 4
  142. #define IO_6_DEFAULT_TX_LEN 256
  143. #define IO_10_CDB_LBA_OFFSET 2
  144. #define IO_10_CDB_TX_LEN_OFFSET 7
  145. #define IO_10_CDB_WP_OFFSET 1
  146. #define IO_10_CDB_FUA_OFFSET 1
  147. #define IO_12_CDB_LBA_OFFSET 2
  148. #define IO_12_CDB_TX_LEN_OFFSET 6
  149. #define IO_12_CDB_WP_OFFSET 1
  150. #define IO_12_CDB_FUA_OFFSET 1
  151. #define IO_16_CDB_FUA_OFFSET 1
  152. #define IO_16_CDB_WP_OFFSET 1
  153. #define IO_16_CDB_LBA_OFFSET 2
  154. #define IO_16_CDB_TX_LEN_OFFSET 10
  155. /* Mode Sense/Select defines */
  156. #define MODE_PAGE_INFO_EXCEP 0x1C
  157. #define MODE_PAGE_CACHING 0x08
  158. #define MODE_PAGE_CONTROL 0x0A
  159. #define MODE_PAGE_POWER_CONDITION 0x1A
  160. #define MODE_PAGE_RETURN_ALL 0x3F
  161. #define MODE_PAGE_BLK_DES_LEN 0x08
  162. #define MODE_PAGE_LLBAA_BLK_DES_LEN 0x10
  163. #define MODE_PAGE_CACHING_LEN 0x14
  164. #define MODE_PAGE_CONTROL_LEN 0x0C
  165. #define MODE_PAGE_POW_CND_LEN 0x28
  166. #define MODE_PAGE_INF_EXC_LEN 0x0C
  167. #define MODE_PAGE_ALL_LEN 0x54
  168. #define MODE_SENSE6_MPH_SIZE 4
  169. #define MODE_SENSE6_ALLOC_LEN_OFFSET 4
  170. #define MODE_SENSE_PAGE_CONTROL_OFFSET 2
  171. #define MODE_SENSE_PAGE_CONTROL_MASK 0xC0
  172. #define MODE_SENSE_PAGE_CODE_OFFSET 2
  173. #define MODE_SENSE_PAGE_CODE_MASK 0x3F
  174. #define MODE_SENSE_LLBAA_OFFSET 1
  175. #define MODE_SENSE_LLBAA_MASK 0x10
  176. #define MODE_SENSE_LLBAA_SHIFT 4
  177. #define MODE_SENSE_DBD_OFFSET 1
  178. #define MODE_SENSE_DBD_MASK 8
  179. #define MODE_SENSE_DBD_SHIFT 3
  180. #define MODE_SENSE10_MPH_SIZE 8
  181. #define MODE_SENSE10_ALLOC_LEN_OFFSET 7
  182. #define MODE_SELECT_CDB_PAGE_FORMAT_OFFSET 1
  183. #define MODE_SELECT_CDB_SAVE_PAGES_OFFSET 1
  184. #define MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET 4
  185. #define MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET 7
  186. #define MODE_SELECT_CDB_PAGE_FORMAT_MASK 0x10
  187. #define MODE_SELECT_CDB_SAVE_PAGES_MASK 0x1
  188. #define MODE_SELECT_6_BD_OFFSET 3
  189. #define MODE_SELECT_10_BD_OFFSET 6
  190. #define MODE_SELECT_10_LLBAA_OFFSET 4
  191. #define MODE_SELECT_10_LLBAA_MASK 1
  192. #define MODE_SELECT_6_MPH_SIZE 4
  193. #define MODE_SELECT_10_MPH_SIZE 8
  194. #define CACHING_MODE_PAGE_WCE_MASK 0x04
  195. #define MODE_SENSE_BLK_DESC_ENABLED 0
  196. #define MODE_SENSE_BLK_DESC_COUNT 1
  197. #define MODE_SELECT_PAGE_CODE_MASK 0x3F
  198. #define SHORT_DESC_BLOCK 8
  199. #define LONG_DESC_BLOCK 16
  200. #define MODE_PAGE_POW_CND_LEN_FIELD 0x26
  201. #define MODE_PAGE_INF_EXC_LEN_FIELD 0x0A
  202. #define MODE_PAGE_CACHING_LEN_FIELD 0x12
  203. #define MODE_PAGE_CONTROL_LEN_FIELD 0x0A
  204. #define MODE_SENSE_PC_CURRENT_VALUES 0
  205. /* Log Sense defines */
  206. #define LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE 0x00
  207. #define LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH 0x07
  208. #define LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE 0x2F
  209. #define LOG_PAGE_TEMPERATURE_PAGE 0x0D
  210. #define LOG_SENSE_CDB_SP_OFFSET 1
  211. #define LOG_SENSE_CDB_SP_NOT_ENABLED 0
  212. #define LOG_SENSE_CDB_PC_OFFSET 2
  213. #define LOG_SENSE_CDB_PC_MASK 0xC0
  214. #define LOG_SENSE_CDB_PC_SHIFT 6
  215. #define LOG_SENSE_CDB_PC_CUMULATIVE_VALUES 1
  216. #define LOG_SENSE_CDB_PAGE_CODE_MASK 0x3F
  217. #define LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET 7
  218. #define REMAINING_INFO_EXCP_PAGE_LENGTH 0x8
  219. #define LOG_INFO_EXCP_PAGE_LENGTH 0xC
  220. #define REMAINING_TEMP_PAGE_LENGTH 0xC
  221. #define LOG_TEMP_PAGE_LENGTH 0x10
  222. #define LOG_TEMP_UNKNOWN 0xFF
  223. #define SUPPORTED_LOG_PAGES_PAGE_LENGTH 0x3
  224. /* Read Capacity defines */
  225. #define READ_CAP_10_RESP_SIZE 8
  226. #define READ_CAP_16_RESP_SIZE 32
  227. /* NVMe Namespace and Command Defines */
  228. #define BYTES_TO_DWORDS 4
  229. #define NVME_MAX_FIRMWARE_SLOT 7
  230. /* Report LUNs defines */
  231. #define REPORT_LUNS_FIRST_LUN_OFFSET 8
  232. /* SCSI ADDITIONAL SENSE Codes */
  233. #define SCSI_ASC_NO_SENSE 0x00
  234. #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03
  235. #define SCSI_ASC_LUN_NOT_READY 0x04
  236. #define SCSI_ASC_WARNING 0x0B
  237. #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10
  238. #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10
  239. #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10
  240. #define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11
  241. #define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D
  242. #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20
  243. #define SCSI_ASC_ILLEGAL_COMMAND 0x20
  244. #define SCSI_ASC_ILLEGAL_BLOCK 0x21
  245. #define SCSI_ASC_INVALID_CDB 0x24
  246. #define SCSI_ASC_INVALID_LUN 0x25
  247. #define SCSI_ASC_INVALID_PARAMETER 0x26
  248. #define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31
  249. #define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44
  250. /* SCSI ADDITIONAL SENSE Code Qualifiers */
  251. #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00
  252. #define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01
  253. #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01
  254. #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02
  255. #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03
  256. #define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04
  257. #define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08
  258. #define SCSI_ASCQ_INVALID_LUN_ID 0x09
  259. /**
  260. * DEVICE_SPECIFIC_PARAMETER in mode parameter header (see sbc2r16) to
  261. * enable DPOFUA support type 0x10 value.
  262. */
  263. #define DEVICE_SPECIFIC_PARAMETER 0
  264. #define VPD_ID_DESCRIPTOR_LENGTH sizeof(VPD_IDENTIFICATION_DESCRIPTOR)
  265. /* MACROs to extract information from CDBs */
  266. #define GET_OPCODE(cdb) cdb[0]
  267. #define GET_U8_FROM_CDB(cdb, index) (cdb[index] << 0)
  268. #define GET_U16_FROM_CDB(cdb, index) ((cdb[index] << 8) | (cdb[index + 1] << 0))
  269. #define GET_U24_FROM_CDB(cdb, index) ((cdb[index] << 16) | \
  270. (cdb[index + 1] << 8) | \
  271. (cdb[index + 2] << 0))
  272. #define GET_U32_FROM_CDB(cdb, index) ((cdb[index] << 24) | \
  273. (cdb[index + 1] << 16) | \
  274. (cdb[index + 2] << 8) | \
  275. (cdb[index + 3] << 0))
  276. #define GET_U64_FROM_CDB(cdb, index) ((((u64)cdb[index]) << 56) | \
  277. (((u64)cdb[index + 1]) << 48) | \
  278. (((u64)cdb[index + 2]) << 40) | \
  279. (((u64)cdb[index + 3]) << 32) | \
  280. (((u64)cdb[index + 4]) << 24) | \
  281. (((u64)cdb[index + 5]) << 16) | \
  282. (((u64)cdb[index + 6]) << 8) | \
  283. (((u64)cdb[index + 7]) << 0))
  284. /* Inquiry Helper Macros */
  285. #define GET_INQ_EVPD_BIT(cdb) \
  286. ((GET_U8_FROM_CDB(cdb, INQUIRY_EVPD_BYTE_OFFSET) & \
  287. INQUIRY_EVPD_BIT_MASK) ? 1 : 0)
  288. #define GET_INQ_PAGE_CODE(cdb) \
  289. (GET_U8_FROM_CDB(cdb, INQUIRY_PAGE_CODE_BYTE_OFFSET))
  290. #define GET_INQ_ALLOC_LENGTH(cdb) \
  291. (GET_U16_FROM_CDB(cdb, INQUIRY_CDB_ALLOCATION_LENGTH_OFFSET))
  292. /* Report LUNs Helper Macros */
  293. #define GET_REPORT_LUNS_ALLOC_LENGTH(cdb) \
  294. (GET_U32_FROM_CDB(cdb, REPORT_LUNS_CDB_ALLOC_LENGTH_OFFSET))
  295. /* Read Capacity Helper Macros */
  296. #define GET_READ_CAP_16_ALLOC_LENGTH(cdb) \
  297. (GET_U32_FROM_CDB(cdb, READ_CAP_16_CDB_ALLOC_LENGTH_OFFSET))
  298. #define IS_READ_CAP_16(cdb) \
  299. ((cdb[0] == SERVICE_ACTION_IN && cdb[1] == SAI_READ_CAPACITY_16) ? 1 : 0)
  300. /* Request Sense Helper Macros */
  301. #define GET_REQUEST_SENSE_ALLOC_LENGTH(cdb) \
  302. (GET_U8_FROM_CDB(cdb, REQUEST_SENSE_CDB_ALLOC_LENGTH_OFFSET))
  303. /* Mode Sense Helper Macros */
  304. #define GET_MODE_SENSE_DBD(cdb) \
  305. ((GET_U8_FROM_CDB(cdb, MODE_SENSE_DBD_OFFSET) & MODE_SENSE_DBD_MASK) >> \
  306. MODE_SENSE_DBD_SHIFT)
  307. #define GET_MODE_SENSE_LLBAA(cdb) \
  308. ((GET_U8_FROM_CDB(cdb, MODE_SENSE_LLBAA_OFFSET) & \
  309. MODE_SENSE_LLBAA_MASK) >> MODE_SENSE_LLBAA_SHIFT)
  310. #define GET_MODE_SENSE_MPH_SIZE(cdb10) \
  311. (cdb10 ? MODE_SENSE10_MPH_SIZE : MODE_SENSE6_MPH_SIZE)
  312. /* Struct to gather data that needs to be extracted from a SCSI CDB.
  313. Not conforming to any particular CDB variant, but compatible with all. */
  314. struct nvme_trans_io_cdb {
  315. u8 fua;
  316. u8 prot_info;
  317. u64 lba;
  318. u32 xfer_len;
  319. };
  320. /* Internal Helper Functions */
  321. /* Copy data to userspace memory */
  322. static int nvme_trans_copy_to_user(struct sg_io_hdr *hdr, void *from,
  323. unsigned long n)
  324. {
  325. int res = SNTI_TRANSLATION_SUCCESS;
  326. unsigned long not_copied;
  327. int i;
  328. void *index = from;
  329. size_t remaining = n;
  330. size_t xfer_len;
  331. if (hdr->iovec_count > 0) {
  332. struct sg_iovec sgl;
  333. for (i = 0; i < hdr->iovec_count; i++) {
  334. not_copied = copy_from_user(&sgl, hdr->dxferp +
  335. i * sizeof(struct sg_iovec),
  336. sizeof(struct sg_iovec));
  337. if (not_copied)
  338. return -EFAULT;
  339. xfer_len = min(remaining, sgl.iov_len);
  340. not_copied = copy_to_user(sgl.iov_base, index,
  341. xfer_len);
  342. if (not_copied) {
  343. res = -EFAULT;
  344. break;
  345. }
  346. index += xfer_len;
  347. remaining -= xfer_len;
  348. if (remaining == 0)
  349. break;
  350. }
  351. return res;
  352. }
  353. not_copied = copy_to_user(hdr->dxferp, from, n);
  354. if (not_copied)
  355. res = -EFAULT;
  356. return res;
  357. }
  358. /* Copy data from userspace memory */
  359. static int nvme_trans_copy_from_user(struct sg_io_hdr *hdr, void *to,
  360. unsigned long n)
  361. {
  362. int res = SNTI_TRANSLATION_SUCCESS;
  363. unsigned long not_copied;
  364. int i;
  365. void *index = to;
  366. size_t remaining = n;
  367. size_t xfer_len;
  368. if (hdr->iovec_count > 0) {
  369. struct sg_iovec sgl;
  370. for (i = 0; i < hdr->iovec_count; i++) {
  371. not_copied = copy_from_user(&sgl, hdr->dxferp +
  372. i * sizeof(struct sg_iovec),
  373. sizeof(struct sg_iovec));
  374. if (not_copied)
  375. return -EFAULT;
  376. xfer_len = min(remaining, sgl.iov_len);
  377. not_copied = copy_from_user(index, sgl.iov_base,
  378. xfer_len);
  379. if (not_copied) {
  380. res = -EFAULT;
  381. break;
  382. }
  383. index += xfer_len;
  384. remaining -= xfer_len;
  385. if (remaining == 0)
  386. break;
  387. }
  388. return res;
  389. }
  390. not_copied = copy_from_user(to, hdr->dxferp, n);
  391. if (not_copied)
  392. res = -EFAULT;
  393. return res;
  394. }
  395. /* Status/Sense Buffer Writeback */
  396. static int nvme_trans_completion(struct sg_io_hdr *hdr, u8 status, u8 sense_key,
  397. u8 asc, u8 ascq)
  398. {
  399. int res = SNTI_TRANSLATION_SUCCESS;
  400. u8 xfer_len;
  401. u8 resp[DESC_FMT_SENSE_DATA_SIZE];
  402. if (scsi_status_is_good(status)) {
  403. hdr->status = SAM_STAT_GOOD;
  404. hdr->masked_status = GOOD;
  405. hdr->host_status = DID_OK;
  406. hdr->driver_status = DRIVER_OK;
  407. hdr->sb_len_wr = 0;
  408. } else {
  409. hdr->status = status;
  410. hdr->masked_status = status >> 1;
  411. hdr->host_status = DID_OK;
  412. hdr->driver_status = DRIVER_OK;
  413. memset(resp, 0, DESC_FMT_SENSE_DATA_SIZE);
  414. resp[0] = DESC_FORMAT_SENSE_DATA;
  415. resp[1] = sense_key;
  416. resp[2] = asc;
  417. resp[3] = ascq;
  418. xfer_len = min_t(u8, hdr->mx_sb_len, DESC_FMT_SENSE_DATA_SIZE);
  419. hdr->sb_len_wr = xfer_len;
  420. if (copy_to_user(hdr->sbp, resp, xfer_len) > 0)
  421. res = -EFAULT;
  422. }
  423. return res;
  424. }
  425. static int nvme_trans_status_code(struct sg_io_hdr *hdr, int nvme_sc)
  426. {
  427. u8 status, sense_key, asc, ascq;
  428. int res = SNTI_TRANSLATION_SUCCESS;
  429. /* For non-nvme (Linux) errors, simply return the error code */
  430. if (nvme_sc < 0)
  431. return nvme_sc;
  432. /* Mask DNR, More, and reserved fields */
  433. nvme_sc &= 0x7FF;
  434. switch (nvme_sc) {
  435. /* Generic Command Status */
  436. case NVME_SC_SUCCESS:
  437. status = SAM_STAT_GOOD;
  438. sense_key = NO_SENSE;
  439. asc = SCSI_ASC_NO_SENSE;
  440. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  441. break;
  442. case NVME_SC_INVALID_OPCODE:
  443. status = SAM_STAT_CHECK_CONDITION;
  444. sense_key = ILLEGAL_REQUEST;
  445. asc = SCSI_ASC_ILLEGAL_COMMAND;
  446. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  447. break;
  448. case NVME_SC_INVALID_FIELD:
  449. status = SAM_STAT_CHECK_CONDITION;
  450. sense_key = ILLEGAL_REQUEST;
  451. asc = SCSI_ASC_INVALID_CDB;
  452. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  453. break;
  454. case NVME_SC_DATA_XFER_ERROR:
  455. status = SAM_STAT_CHECK_CONDITION;
  456. sense_key = MEDIUM_ERROR;
  457. asc = SCSI_ASC_NO_SENSE;
  458. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  459. break;
  460. case NVME_SC_POWER_LOSS:
  461. status = SAM_STAT_TASK_ABORTED;
  462. sense_key = ABORTED_COMMAND;
  463. asc = SCSI_ASC_WARNING;
  464. ascq = SCSI_ASCQ_POWER_LOSS_EXPECTED;
  465. break;
  466. case NVME_SC_INTERNAL:
  467. status = SAM_STAT_CHECK_CONDITION;
  468. sense_key = HARDWARE_ERROR;
  469. asc = SCSI_ASC_INTERNAL_TARGET_FAILURE;
  470. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  471. break;
  472. case NVME_SC_ABORT_REQ:
  473. status = SAM_STAT_TASK_ABORTED;
  474. sense_key = ABORTED_COMMAND;
  475. asc = SCSI_ASC_NO_SENSE;
  476. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  477. break;
  478. case NVME_SC_ABORT_QUEUE:
  479. status = SAM_STAT_TASK_ABORTED;
  480. sense_key = ABORTED_COMMAND;
  481. asc = SCSI_ASC_NO_SENSE;
  482. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  483. break;
  484. case NVME_SC_FUSED_FAIL:
  485. status = SAM_STAT_TASK_ABORTED;
  486. sense_key = ABORTED_COMMAND;
  487. asc = SCSI_ASC_NO_SENSE;
  488. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  489. break;
  490. case NVME_SC_FUSED_MISSING:
  491. status = SAM_STAT_TASK_ABORTED;
  492. sense_key = ABORTED_COMMAND;
  493. asc = SCSI_ASC_NO_SENSE;
  494. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  495. break;
  496. case NVME_SC_INVALID_NS:
  497. status = SAM_STAT_CHECK_CONDITION;
  498. sense_key = ILLEGAL_REQUEST;
  499. asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID;
  500. ascq = SCSI_ASCQ_INVALID_LUN_ID;
  501. break;
  502. case NVME_SC_LBA_RANGE:
  503. status = SAM_STAT_CHECK_CONDITION;
  504. sense_key = ILLEGAL_REQUEST;
  505. asc = SCSI_ASC_ILLEGAL_BLOCK;
  506. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  507. break;
  508. case NVME_SC_CAP_EXCEEDED:
  509. status = SAM_STAT_CHECK_CONDITION;
  510. sense_key = MEDIUM_ERROR;
  511. asc = SCSI_ASC_NO_SENSE;
  512. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  513. break;
  514. case NVME_SC_NS_NOT_READY:
  515. status = SAM_STAT_CHECK_CONDITION;
  516. sense_key = NOT_READY;
  517. asc = SCSI_ASC_LUN_NOT_READY;
  518. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  519. break;
  520. /* Command Specific Status */
  521. case NVME_SC_INVALID_FORMAT:
  522. status = SAM_STAT_CHECK_CONDITION;
  523. sense_key = ILLEGAL_REQUEST;
  524. asc = SCSI_ASC_FORMAT_COMMAND_FAILED;
  525. ascq = SCSI_ASCQ_FORMAT_COMMAND_FAILED;
  526. break;
  527. case NVME_SC_BAD_ATTRIBUTES:
  528. status = SAM_STAT_CHECK_CONDITION;
  529. sense_key = ILLEGAL_REQUEST;
  530. asc = SCSI_ASC_INVALID_CDB;
  531. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  532. break;
  533. /* Media Errors */
  534. case NVME_SC_WRITE_FAULT:
  535. status = SAM_STAT_CHECK_CONDITION;
  536. sense_key = MEDIUM_ERROR;
  537. asc = SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT;
  538. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  539. break;
  540. case NVME_SC_READ_ERROR:
  541. status = SAM_STAT_CHECK_CONDITION;
  542. sense_key = MEDIUM_ERROR;
  543. asc = SCSI_ASC_UNRECOVERED_READ_ERROR;
  544. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  545. break;
  546. case NVME_SC_GUARD_CHECK:
  547. status = SAM_STAT_CHECK_CONDITION;
  548. sense_key = MEDIUM_ERROR;
  549. asc = SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED;
  550. ascq = SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED;
  551. break;
  552. case NVME_SC_APPTAG_CHECK:
  553. status = SAM_STAT_CHECK_CONDITION;
  554. sense_key = MEDIUM_ERROR;
  555. asc = SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED;
  556. ascq = SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED;
  557. break;
  558. case NVME_SC_REFTAG_CHECK:
  559. status = SAM_STAT_CHECK_CONDITION;
  560. sense_key = MEDIUM_ERROR;
  561. asc = SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED;
  562. ascq = SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED;
  563. break;
  564. case NVME_SC_COMPARE_FAILED:
  565. status = SAM_STAT_CHECK_CONDITION;
  566. sense_key = MISCOMPARE;
  567. asc = SCSI_ASC_MISCOMPARE_DURING_VERIFY;
  568. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  569. break;
  570. case NVME_SC_ACCESS_DENIED:
  571. status = SAM_STAT_CHECK_CONDITION;
  572. sense_key = ILLEGAL_REQUEST;
  573. asc = SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID;
  574. ascq = SCSI_ASCQ_INVALID_LUN_ID;
  575. break;
  576. /* Unspecified/Default */
  577. case NVME_SC_CMDID_CONFLICT:
  578. case NVME_SC_CMD_SEQ_ERROR:
  579. case NVME_SC_CQ_INVALID:
  580. case NVME_SC_QID_INVALID:
  581. case NVME_SC_QUEUE_SIZE:
  582. case NVME_SC_ABORT_LIMIT:
  583. case NVME_SC_ABORT_MISSING:
  584. case NVME_SC_ASYNC_LIMIT:
  585. case NVME_SC_FIRMWARE_SLOT:
  586. case NVME_SC_FIRMWARE_IMAGE:
  587. case NVME_SC_INVALID_VECTOR:
  588. case NVME_SC_INVALID_LOG_PAGE:
  589. default:
  590. status = SAM_STAT_CHECK_CONDITION;
  591. sense_key = ILLEGAL_REQUEST;
  592. asc = SCSI_ASC_NO_SENSE;
  593. ascq = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  594. break;
  595. }
  596. res = nvme_trans_completion(hdr, status, sense_key, asc, ascq);
  597. return res;
  598. }
  599. /* INQUIRY Helper Functions */
  600. static int nvme_trans_standard_inquiry_page(struct nvme_ns *ns,
  601. struct sg_io_hdr *hdr, u8 *inq_response,
  602. int alloc_len)
  603. {
  604. struct nvme_dev *dev = ns->dev;
  605. dma_addr_t dma_addr;
  606. void *mem;
  607. struct nvme_id_ns *id_ns;
  608. int res = SNTI_TRANSLATION_SUCCESS;
  609. int nvme_sc;
  610. int xfer_len;
  611. u8 resp_data_format = 0x02;
  612. u8 protect;
  613. u8 cmdque = 0x01 << 1;
  614. u8 fw_offset = sizeof(dev->firmware_rev);
  615. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  616. &dma_addr, GFP_KERNEL);
  617. if (mem == NULL) {
  618. res = -ENOMEM;
  619. goto out_dma;
  620. }
  621. /* nvme ns identify - use DPS value for PROTECT field */
  622. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  623. res = nvme_trans_status_code(hdr, nvme_sc);
  624. /*
  625. * If nvme_sc was -ve, res will be -ve here.
  626. * If nvme_sc was +ve, the status would bace been translated, and res
  627. * can only be 0 or -ve.
  628. * - If 0 && nvme_sc > 0, then go into next if where res gets nvme_sc
  629. * - If -ve, return because its a Linux error.
  630. */
  631. if (res)
  632. goto out_free;
  633. if (nvme_sc) {
  634. res = nvme_sc;
  635. goto out_free;
  636. }
  637. id_ns = mem;
  638. (id_ns->dps) ? (protect = 0x01) : (protect = 0);
  639. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  640. inq_response[2] = VERSION_SPC_4;
  641. inq_response[3] = resp_data_format; /*normaca=0 | hisup=0 */
  642. inq_response[4] = ADDITIONAL_STD_INQ_LENGTH;
  643. inq_response[5] = protect; /* sccs=0 | acc=0 | tpgs=0 | pc3=0 */
  644. inq_response[7] = cmdque; /* wbus16=0 | sync=0 | vs=0 */
  645. strncpy(&inq_response[8], "NVMe ", 8);
  646. strncpy(&inq_response[16], dev->model, 16);
  647. while (dev->firmware_rev[fw_offset - 1] == ' ' && fw_offset > 4)
  648. fw_offset--;
  649. fw_offset -= 4;
  650. strncpy(&inq_response[32], dev->firmware_rev + fw_offset, 4);
  651. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  652. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  653. out_free:
  654. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  655. dma_addr);
  656. out_dma:
  657. return res;
  658. }
  659. static int nvme_trans_supported_vpd_pages(struct nvme_ns *ns,
  660. struct sg_io_hdr *hdr, u8 *inq_response,
  661. int alloc_len)
  662. {
  663. int res = SNTI_TRANSLATION_SUCCESS;
  664. int xfer_len;
  665. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  666. inq_response[1] = INQ_SUPPORTED_VPD_PAGES_PAGE; /* Page Code */
  667. inq_response[3] = INQ_NUM_SUPPORTED_VPD_PAGES; /* Page Length */
  668. inq_response[4] = INQ_SUPPORTED_VPD_PAGES_PAGE;
  669. inq_response[5] = INQ_UNIT_SERIAL_NUMBER_PAGE;
  670. inq_response[6] = INQ_DEVICE_IDENTIFICATION_PAGE;
  671. inq_response[7] = INQ_EXTENDED_INQUIRY_DATA_PAGE;
  672. inq_response[8] = INQ_BDEV_CHARACTERISTICS_PAGE;
  673. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  674. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  675. return res;
  676. }
  677. static int nvme_trans_unit_serial_page(struct nvme_ns *ns,
  678. struct sg_io_hdr *hdr, u8 *inq_response,
  679. int alloc_len)
  680. {
  681. struct nvme_dev *dev = ns->dev;
  682. int res = SNTI_TRANSLATION_SUCCESS;
  683. int xfer_len;
  684. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  685. inq_response[1] = INQ_UNIT_SERIAL_NUMBER_PAGE; /* Page Code */
  686. inq_response[3] = INQ_SERIAL_NUMBER_LENGTH; /* Page Length */
  687. strncpy(&inq_response[4], dev->serial, INQ_SERIAL_NUMBER_LENGTH);
  688. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  689. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  690. return res;
  691. }
  692. static int nvme_trans_device_id_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  693. u8 *inq_response, int alloc_len)
  694. {
  695. struct nvme_dev *dev = ns->dev;
  696. dma_addr_t dma_addr;
  697. void *mem;
  698. struct nvme_id_ctrl *id_ctrl;
  699. int res = SNTI_TRANSLATION_SUCCESS;
  700. int nvme_sc;
  701. u8 ieee[4];
  702. int xfer_len;
  703. __be32 tmp_id = cpu_to_be32(ns->ns_id);
  704. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  705. &dma_addr, GFP_KERNEL);
  706. if (mem == NULL) {
  707. res = -ENOMEM;
  708. goto out_dma;
  709. }
  710. /* nvme controller identify */
  711. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  712. res = nvme_trans_status_code(hdr, nvme_sc);
  713. if (res)
  714. goto out_free;
  715. if (nvme_sc) {
  716. res = nvme_sc;
  717. goto out_free;
  718. }
  719. id_ctrl = mem;
  720. /* Since SCSI tried to save 4 bits... [SPC-4(r34) Table 591] */
  721. ieee[0] = id_ctrl->ieee[0] << 4;
  722. ieee[1] = id_ctrl->ieee[0] >> 4 | id_ctrl->ieee[1] << 4;
  723. ieee[2] = id_ctrl->ieee[1] >> 4 | id_ctrl->ieee[2] << 4;
  724. ieee[3] = id_ctrl->ieee[2] >> 4;
  725. memset(inq_response, 0, STANDARD_INQUIRY_LENGTH);
  726. inq_response[1] = INQ_DEVICE_IDENTIFICATION_PAGE; /* Page Code */
  727. inq_response[3] = 20; /* Page Length */
  728. /* Designation Descriptor start */
  729. inq_response[4] = 0x01; /* Proto ID=0h | Code set=1h */
  730. inq_response[5] = 0x03; /* PIV=0b | Asso=00b | Designator Type=3h */
  731. inq_response[6] = 0x00; /* Rsvd */
  732. inq_response[7] = 16; /* Designator Length */
  733. /* Designator start */
  734. inq_response[8] = 0x60 | ieee[3]; /* NAA=6h | IEEE ID MSB, High nibble*/
  735. inq_response[9] = ieee[2]; /* IEEE ID */
  736. inq_response[10] = ieee[1]; /* IEEE ID */
  737. inq_response[11] = ieee[0]; /* IEEE ID| Vendor Specific ID... */
  738. inq_response[12] = (dev->pci_dev->vendor & 0xFF00) >> 8;
  739. inq_response[13] = (dev->pci_dev->vendor & 0x00FF);
  740. inq_response[14] = dev->serial[0];
  741. inq_response[15] = dev->serial[1];
  742. inq_response[16] = dev->model[0];
  743. inq_response[17] = dev->model[1];
  744. memcpy(&inq_response[18], &tmp_id, sizeof(u32));
  745. /* Last 2 bytes are zero */
  746. xfer_len = min(alloc_len, STANDARD_INQUIRY_LENGTH);
  747. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  748. out_free:
  749. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  750. dma_addr);
  751. out_dma:
  752. return res;
  753. }
  754. static int nvme_trans_ext_inq_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  755. int alloc_len)
  756. {
  757. u8 *inq_response;
  758. int res = SNTI_TRANSLATION_SUCCESS;
  759. int nvme_sc;
  760. struct nvme_dev *dev = ns->dev;
  761. dma_addr_t dma_addr;
  762. void *mem;
  763. struct nvme_id_ctrl *id_ctrl;
  764. struct nvme_id_ns *id_ns;
  765. int xfer_len;
  766. u8 microcode = 0x80;
  767. u8 spt;
  768. u8 spt_lut[8] = {0, 0, 2, 1, 4, 6, 5, 7};
  769. u8 grd_chk, app_chk, ref_chk, protect;
  770. u8 uask_sup = 0x20;
  771. u8 v_sup;
  772. u8 luiclr = 0x01;
  773. inq_response = kmalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL);
  774. if (inq_response == NULL) {
  775. res = -ENOMEM;
  776. goto out_mem;
  777. }
  778. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  779. &dma_addr, GFP_KERNEL);
  780. if (mem == NULL) {
  781. res = -ENOMEM;
  782. goto out_dma;
  783. }
  784. /* nvme ns identify */
  785. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  786. res = nvme_trans_status_code(hdr, nvme_sc);
  787. if (res)
  788. goto out_free;
  789. if (nvme_sc) {
  790. res = nvme_sc;
  791. goto out_free;
  792. }
  793. id_ns = mem;
  794. spt = spt_lut[(id_ns->dpc) & 0x07] << 3;
  795. (id_ns->dps) ? (protect = 0x01) : (protect = 0);
  796. grd_chk = protect << 2;
  797. app_chk = protect << 1;
  798. ref_chk = protect;
  799. /* nvme controller identify */
  800. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  801. res = nvme_trans_status_code(hdr, nvme_sc);
  802. if (res)
  803. goto out_free;
  804. if (nvme_sc) {
  805. res = nvme_sc;
  806. goto out_free;
  807. }
  808. id_ctrl = mem;
  809. v_sup = id_ctrl->vwc;
  810. memset(inq_response, 0, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  811. inq_response[1] = INQ_EXTENDED_INQUIRY_DATA_PAGE; /* Page Code */
  812. inq_response[2] = 0x00; /* Page Length MSB */
  813. inq_response[3] = 0x3C; /* Page Length LSB */
  814. inq_response[4] = microcode | spt | grd_chk | app_chk | ref_chk;
  815. inq_response[5] = uask_sup;
  816. inq_response[6] = v_sup;
  817. inq_response[7] = luiclr;
  818. inq_response[8] = 0;
  819. inq_response[9] = 0;
  820. xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  821. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  822. out_free:
  823. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  824. dma_addr);
  825. out_dma:
  826. kfree(inq_response);
  827. out_mem:
  828. return res;
  829. }
  830. static int nvme_trans_bdev_char_page(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  831. int alloc_len)
  832. {
  833. u8 *inq_response;
  834. int res = SNTI_TRANSLATION_SUCCESS;
  835. int xfer_len;
  836. inq_response = kzalloc(EXTENDED_INQUIRY_DATA_PAGE_LENGTH, GFP_KERNEL);
  837. if (inq_response == NULL) {
  838. res = -ENOMEM;
  839. goto out_mem;
  840. }
  841. inq_response[1] = INQ_BDEV_CHARACTERISTICS_PAGE; /* Page Code */
  842. inq_response[2] = 0x00; /* Page Length MSB */
  843. inq_response[3] = 0x3C; /* Page Length LSB */
  844. inq_response[4] = 0x00; /* Medium Rotation Rate MSB */
  845. inq_response[5] = 0x01; /* Medium Rotation Rate LSB */
  846. inq_response[6] = 0x00; /* Form Factor */
  847. xfer_len = min(alloc_len, EXTENDED_INQUIRY_DATA_PAGE_LENGTH);
  848. res = nvme_trans_copy_to_user(hdr, inq_response, xfer_len);
  849. kfree(inq_response);
  850. out_mem:
  851. return res;
  852. }
  853. /* LOG SENSE Helper Functions */
  854. static int nvme_trans_log_supp_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  855. int alloc_len)
  856. {
  857. int res = SNTI_TRANSLATION_SUCCESS;
  858. int xfer_len;
  859. u8 *log_response;
  860. log_response = kzalloc(LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH, GFP_KERNEL);
  861. if (log_response == NULL) {
  862. res = -ENOMEM;
  863. goto out_mem;
  864. }
  865. log_response[0] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE;
  866. /* Subpage=0x00, Page Length MSB=0 */
  867. log_response[3] = SUPPORTED_LOG_PAGES_PAGE_LENGTH;
  868. log_response[4] = LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE;
  869. log_response[5] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE;
  870. log_response[6] = LOG_PAGE_TEMPERATURE_PAGE;
  871. xfer_len = min(alloc_len, LOG_PAGE_SUPPORTED_LOG_PAGES_LENGTH);
  872. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  873. kfree(log_response);
  874. out_mem:
  875. return res;
  876. }
  877. static int nvme_trans_log_info_exceptions(struct nvme_ns *ns,
  878. struct sg_io_hdr *hdr, int alloc_len)
  879. {
  880. int res = SNTI_TRANSLATION_SUCCESS;
  881. int xfer_len;
  882. u8 *log_response;
  883. struct nvme_command c;
  884. struct nvme_dev *dev = ns->dev;
  885. struct nvme_smart_log *smart_log;
  886. dma_addr_t dma_addr;
  887. void *mem;
  888. u8 temp_c;
  889. u16 temp_k;
  890. log_response = kzalloc(LOG_INFO_EXCP_PAGE_LENGTH, GFP_KERNEL);
  891. if (log_response == NULL) {
  892. res = -ENOMEM;
  893. goto out_mem;
  894. }
  895. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  896. sizeof(struct nvme_smart_log),
  897. &dma_addr, GFP_KERNEL);
  898. if (mem == NULL) {
  899. res = -ENOMEM;
  900. goto out_dma;
  901. }
  902. /* Get SMART Log Page */
  903. memset(&c, 0, sizeof(c));
  904. c.common.opcode = nvme_admin_get_log_page;
  905. c.common.nsid = cpu_to_le32(0xFFFFFFFF);
  906. c.common.prp1 = cpu_to_le64(dma_addr);
  907. c.common.cdw10[0] = cpu_to_le32((((sizeof(struct nvme_smart_log) /
  908. BYTES_TO_DWORDS) - 1) << 16) | NVME_LOG_SMART);
  909. res = nvme_submit_admin_cmd(dev, &c, NULL);
  910. if (res != NVME_SC_SUCCESS) {
  911. temp_c = LOG_TEMP_UNKNOWN;
  912. } else {
  913. smart_log = mem;
  914. temp_k = (smart_log->temperature[1] << 8) +
  915. (smart_log->temperature[0]);
  916. temp_c = temp_k - KELVIN_TEMP_FACTOR;
  917. }
  918. log_response[0] = LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE;
  919. /* Subpage=0x00, Page Length MSB=0 */
  920. log_response[3] = REMAINING_INFO_EXCP_PAGE_LENGTH;
  921. /* Informational Exceptions Log Parameter 1 Start */
  922. /* Parameter Code=0x0000 bytes 4,5 */
  923. log_response[6] = 0x23; /* DU=0, TSD=1, ETC=0, TMC=0, FMT_AND_LNK=11b */
  924. log_response[7] = 0x04; /* PARAMETER LENGTH */
  925. /* Add sense Code and qualifier = 0x00 each */
  926. /* Use Temperature from NVMe Get Log Page, convert to C from K */
  927. log_response[10] = temp_c;
  928. xfer_len = min(alloc_len, LOG_INFO_EXCP_PAGE_LENGTH);
  929. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  930. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_smart_log),
  931. mem, dma_addr);
  932. out_dma:
  933. kfree(log_response);
  934. out_mem:
  935. return res;
  936. }
  937. static int nvme_trans_log_temperature(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  938. int alloc_len)
  939. {
  940. int res = SNTI_TRANSLATION_SUCCESS;
  941. int xfer_len;
  942. u8 *log_response;
  943. struct nvme_command c;
  944. struct nvme_dev *dev = ns->dev;
  945. struct nvme_smart_log *smart_log;
  946. dma_addr_t dma_addr;
  947. void *mem;
  948. u32 feature_resp;
  949. u8 temp_c_cur, temp_c_thresh;
  950. u16 temp_k;
  951. log_response = kzalloc(LOG_TEMP_PAGE_LENGTH, GFP_KERNEL);
  952. if (log_response == NULL) {
  953. res = -ENOMEM;
  954. goto out_mem;
  955. }
  956. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  957. sizeof(struct nvme_smart_log),
  958. &dma_addr, GFP_KERNEL);
  959. if (mem == NULL) {
  960. res = -ENOMEM;
  961. goto out_dma;
  962. }
  963. /* Get SMART Log Page */
  964. memset(&c, 0, sizeof(c));
  965. c.common.opcode = nvme_admin_get_log_page;
  966. c.common.nsid = cpu_to_le32(0xFFFFFFFF);
  967. c.common.prp1 = cpu_to_le64(dma_addr);
  968. c.common.cdw10[0] = cpu_to_le32((((sizeof(struct nvme_smart_log) /
  969. BYTES_TO_DWORDS) - 1) << 16) | NVME_LOG_SMART);
  970. res = nvme_submit_admin_cmd(dev, &c, NULL);
  971. if (res != NVME_SC_SUCCESS) {
  972. temp_c_cur = LOG_TEMP_UNKNOWN;
  973. } else {
  974. smart_log = mem;
  975. temp_k = (smart_log->temperature[1] << 8) +
  976. (smart_log->temperature[0]);
  977. temp_c_cur = temp_k - KELVIN_TEMP_FACTOR;
  978. }
  979. /* Get Features for Temp Threshold */
  980. res = nvme_get_features(dev, NVME_FEAT_TEMP_THRESH, 0, 0,
  981. &feature_resp);
  982. if (res != NVME_SC_SUCCESS)
  983. temp_c_thresh = LOG_TEMP_UNKNOWN;
  984. else
  985. temp_c_thresh = (feature_resp & 0xFFFF) - KELVIN_TEMP_FACTOR;
  986. log_response[0] = LOG_PAGE_TEMPERATURE_PAGE;
  987. /* Subpage=0x00, Page Length MSB=0 */
  988. log_response[3] = REMAINING_TEMP_PAGE_LENGTH;
  989. /* Temperature Log Parameter 1 (Temperature) Start */
  990. /* Parameter Code = 0x0000 */
  991. log_response[6] = 0x01; /* Format and Linking = 01b */
  992. log_response[7] = 0x02; /* Parameter Length */
  993. /* Use Temperature from NVMe Get Log Page, convert to C from K */
  994. log_response[9] = temp_c_cur;
  995. /* Temperature Log Parameter 2 (Reference Temperature) Start */
  996. log_response[11] = 0x01; /* Parameter Code = 0x0001 */
  997. log_response[12] = 0x01; /* Format and Linking = 01b */
  998. log_response[13] = 0x02; /* Parameter Length */
  999. /* Use Temperature Thresh from NVMe Get Log Page, convert to C from K */
  1000. log_response[15] = temp_c_thresh;
  1001. xfer_len = min(alloc_len, LOG_TEMP_PAGE_LENGTH);
  1002. res = nvme_trans_copy_to_user(hdr, log_response, xfer_len);
  1003. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_smart_log),
  1004. mem, dma_addr);
  1005. out_dma:
  1006. kfree(log_response);
  1007. out_mem:
  1008. return res;
  1009. }
  1010. /* MODE SENSE Helper Functions */
  1011. static int nvme_trans_fill_mode_parm_hdr(u8 *resp, int len, u8 cdb10, u8 llbaa,
  1012. u16 mode_data_length, u16 blk_desc_len)
  1013. {
  1014. /* Quick check to make sure I don't stomp on my own memory... */
  1015. if ((cdb10 && len < 8) || (!cdb10 && len < 4))
  1016. return SNTI_INTERNAL_ERROR;
  1017. if (cdb10) {
  1018. resp[0] = (mode_data_length & 0xFF00) >> 8;
  1019. resp[1] = (mode_data_length & 0x00FF);
  1020. /* resp[2] and [3] are zero */
  1021. resp[4] = llbaa;
  1022. resp[5] = RESERVED_FIELD;
  1023. resp[6] = (blk_desc_len & 0xFF00) >> 8;
  1024. resp[7] = (blk_desc_len & 0x00FF);
  1025. } else {
  1026. resp[0] = (mode_data_length & 0x00FF);
  1027. /* resp[1] and [2] are zero */
  1028. resp[3] = (blk_desc_len & 0x00FF);
  1029. }
  1030. return SNTI_TRANSLATION_SUCCESS;
  1031. }
  1032. static int nvme_trans_fill_blk_desc(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1033. u8 *resp, int len, u8 llbaa)
  1034. {
  1035. int res = SNTI_TRANSLATION_SUCCESS;
  1036. int nvme_sc;
  1037. struct nvme_dev *dev = ns->dev;
  1038. dma_addr_t dma_addr;
  1039. void *mem;
  1040. struct nvme_id_ns *id_ns;
  1041. u8 flbas;
  1042. u32 lba_length;
  1043. if (llbaa == 0 && len < MODE_PAGE_BLK_DES_LEN)
  1044. return SNTI_INTERNAL_ERROR;
  1045. else if (llbaa > 0 && len < MODE_PAGE_LLBAA_BLK_DES_LEN)
  1046. return SNTI_INTERNAL_ERROR;
  1047. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1048. &dma_addr, GFP_KERNEL);
  1049. if (mem == NULL) {
  1050. res = -ENOMEM;
  1051. goto out;
  1052. }
  1053. /* nvme ns identify */
  1054. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1055. res = nvme_trans_status_code(hdr, nvme_sc);
  1056. if (res)
  1057. goto out_dma;
  1058. if (nvme_sc) {
  1059. res = nvme_sc;
  1060. goto out_dma;
  1061. }
  1062. id_ns = mem;
  1063. flbas = (id_ns->flbas) & 0x0F;
  1064. lba_length = (1 << (id_ns->lbaf[flbas].ds));
  1065. if (llbaa == 0) {
  1066. __be32 tmp_cap = cpu_to_be32(le64_to_cpu(id_ns->ncap));
  1067. /* Byte 4 is reserved */
  1068. __be32 tmp_len = cpu_to_be32(lba_length & 0x00FFFFFF);
  1069. memcpy(resp, &tmp_cap, sizeof(u32));
  1070. memcpy(&resp[4], &tmp_len, sizeof(u32));
  1071. } else {
  1072. __be64 tmp_cap = cpu_to_be64(le64_to_cpu(id_ns->ncap));
  1073. __be32 tmp_len = cpu_to_be32(lba_length);
  1074. memcpy(resp, &tmp_cap, sizeof(u64));
  1075. /* Bytes 8, 9, 10, 11 are reserved */
  1076. memcpy(&resp[12], &tmp_len, sizeof(u32));
  1077. }
  1078. out_dma:
  1079. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  1080. dma_addr);
  1081. out:
  1082. return res;
  1083. }
  1084. static int nvme_trans_fill_control_page(struct nvme_ns *ns,
  1085. struct sg_io_hdr *hdr, u8 *resp,
  1086. int len)
  1087. {
  1088. if (len < MODE_PAGE_CONTROL_LEN)
  1089. return SNTI_INTERNAL_ERROR;
  1090. resp[0] = MODE_PAGE_CONTROL;
  1091. resp[1] = MODE_PAGE_CONTROL_LEN_FIELD;
  1092. resp[2] = 0x0E; /* TST=000b, TMF_ONLY=0, DPICZ=1,
  1093. * D_SENSE=1, GLTSD=1, RLEC=0 */
  1094. resp[3] = 0x12; /* Q_ALGO_MODIFIER=1h, NUAR=0, QERR=01b */
  1095. /* Byte 4: VS=0, RAC=0, UA_INT=0, SWP=0 */
  1096. resp[5] = 0x40; /* ATO=0, TAS=1, ATMPE=0, RWWP=0, AUTOLOAD=0 */
  1097. /* resp[6] and [7] are obsolete, thus zero */
  1098. resp[8] = 0xFF; /* Busy timeout period = 0xffff */
  1099. resp[9] = 0xFF;
  1100. /* Bytes 10,11: Extended selftest completion time = 0x0000 */
  1101. return SNTI_TRANSLATION_SUCCESS;
  1102. }
  1103. static int nvme_trans_fill_caching_page(struct nvme_ns *ns,
  1104. struct sg_io_hdr *hdr,
  1105. u8 *resp, int len)
  1106. {
  1107. int res = SNTI_TRANSLATION_SUCCESS;
  1108. int nvme_sc;
  1109. struct nvme_dev *dev = ns->dev;
  1110. u32 feature_resp;
  1111. u8 vwc;
  1112. if (len < MODE_PAGE_CACHING_LEN)
  1113. return SNTI_INTERNAL_ERROR;
  1114. nvme_sc = nvme_get_features(dev, NVME_FEAT_VOLATILE_WC, 0, 0,
  1115. &feature_resp);
  1116. res = nvme_trans_status_code(hdr, nvme_sc);
  1117. if (res)
  1118. goto out;
  1119. if (nvme_sc) {
  1120. res = nvme_sc;
  1121. goto out;
  1122. }
  1123. vwc = feature_resp & 0x00000001;
  1124. resp[0] = MODE_PAGE_CACHING;
  1125. resp[1] = MODE_PAGE_CACHING_LEN_FIELD;
  1126. resp[2] = vwc << 2;
  1127. out:
  1128. return res;
  1129. }
  1130. static int nvme_trans_fill_pow_cnd_page(struct nvme_ns *ns,
  1131. struct sg_io_hdr *hdr, u8 *resp,
  1132. int len)
  1133. {
  1134. int res = SNTI_TRANSLATION_SUCCESS;
  1135. if (len < MODE_PAGE_POW_CND_LEN)
  1136. return SNTI_INTERNAL_ERROR;
  1137. resp[0] = MODE_PAGE_POWER_CONDITION;
  1138. resp[1] = MODE_PAGE_POW_CND_LEN_FIELD;
  1139. /* All other bytes are zero */
  1140. return res;
  1141. }
  1142. static int nvme_trans_fill_inf_exc_page(struct nvme_ns *ns,
  1143. struct sg_io_hdr *hdr, u8 *resp,
  1144. int len)
  1145. {
  1146. int res = SNTI_TRANSLATION_SUCCESS;
  1147. if (len < MODE_PAGE_INF_EXC_LEN)
  1148. return SNTI_INTERNAL_ERROR;
  1149. resp[0] = MODE_PAGE_INFO_EXCEP;
  1150. resp[1] = MODE_PAGE_INF_EXC_LEN_FIELD;
  1151. resp[2] = 0x88;
  1152. /* All other bytes are zero */
  1153. return res;
  1154. }
  1155. static int nvme_trans_fill_all_pages(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1156. u8 *resp, int len)
  1157. {
  1158. int res = SNTI_TRANSLATION_SUCCESS;
  1159. u16 mode_pages_offset_1 = 0;
  1160. u16 mode_pages_offset_2, mode_pages_offset_3, mode_pages_offset_4;
  1161. mode_pages_offset_2 = mode_pages_offset_1 + MODE_PAGE_CACHING_LEN;
  1162. mode_pages_offset_3 = mode_pages_offset_2 + MODE_PAGE_CONTROL_LEN;
  1163. mode_pages_offset_4 = mode_pages_offset_3 + MODE_PAGE_POW_CND_LEN;
  1164. res = nvme_trans_fill_caching_page(ns, hdr, &resp[mode_pages_offset_1],
  1165. MODE_PAGE_CACHING_LEN);
  1166. if (res != SNTI_TRANSLATION_SUCCESS)
  1167. goto out;
  1168. res = nvme_trans_fill_control_page(ns, hdr, &resp[mode_pages_offset_2],
  1169. MODE_PAGE_CONTROL_LEN);
  1170. if (res != SNTI_TRANSLATION_SUCCESS)
  1171. goto out;
  1172. res = nvme_trans_fill_pow_cnd_page(ns, hdr, &resp[mode_pages_offset_3],
  1173. MODE_PAGE_POW_CND_LEN);
  1174. if (res != SNTI_TRANSLATION_SUCCESS)
  1175. goto out;
  1176. res = nvme_trans_fill_inf_exc_page(ns, hdr, &resp[mode_pages_offset_4],
  1177. MODE_PAGE_INF_EXC_LEN);
  1178. if (res != SNTI_TRANSLATION_SUCCESS)
  1179. goto out;
  1180. out:
  1181. return res;
  1182. }
  1183. static inline int nvme_trans_get_blk_desc_len(u8 dbd, u8 llbaa)
  1184. {
  1185. if (dbd == MODE_SENSE_BLK_DESC_ENABLED) {
  1186. /* SPC-4: len = 8 x Num_of_descriptors if llbaa = 0, 16x if 1 */
  1187. return 8 * (llbaa + 1) * MODE_SENSE_BLK_DESC_COUNT;
  1188. } else {
  1189. return 0;
  1190. }
  1191. }
  1192. static int nvme_trans_mode_page_create(struct nvme_ns *ns,
  1193. struct sg_io_hdr *hdr, u8 *cmd,
  1194. u16 alloc_len, u8 cdb10,
  1195. int (*mode_page_fill_func)
  1196. (struct nvme_ns *,
  1197. struct sg_io_hdr *hdr, u8 *, int),
  1198. u16 mode_pages_tot_len)
  1199. {
  1200. int res = SNTI_TRANSLATION_SUCCESS;
  1201. int xfer_len;
  1202. u8 *response;
  1203. u8 dbd, llbaa;
  1204. u16 resp_size;
  1205. int mph_size;
  1206. u16 mode_pages_offset_1;
  1207. u16 blk_desc_len, blk_desc_offset, mode_data_length;
  1208. dbd = GET_MODE_SENSE_DBD(cmd);
  1209. llbaa = GET_MODE_SENSE_LLBAA(cmd);
  1210. mph_size = GET_MODE_SENSE_MPH_SIZE(cdb10);
  1211. blk_desc_len = nvme_trans_get_blk_desc_len(dbd, llbaa);
  1212. resp_size = mph_size + blk_desc_len + mode_pages_tot_len;
  1213. /* Refer spc4r34 Table 440 for calculation of Mode data Length field */
  1214. mode_data_length = 3 + (3 * cdb10) + blk_desc_len + mode_pages_tot_len;
  1215. blk_desc_offset = mph_size;
  1216. mode_pages_offset_1 = blk_desc_offset + blk_desc_len;
  1217. response = kzalloc(resp_size, GFP_KERNEL);
  1218. if (response == NULL) {
  1219. res = -ENOMEM;
  1220. goto out_mem;
  1221. }
  1222. res = nvme_trans_fill_mode_parm_hdr(&response[0], mph_size, cdb10,
  1223. llbaa, mode_data_length, blk_desc_len);
  1224. if (res != SNTI_TRANSLATION_SUCCESS)
  1225. goto out_free;
  1226. if (blk_desc_len > 0) {
  1227. res = nvme_trans_fill_blk_desc(ns, hdr,
  1228. &response[blk_desc_offset],
  1229. blk_desc_len, llbaa);
  1230. if (res != SNTI_TRANSLATION_SUCCESS)
  1231. goto out_free;
  1232. }
  1233. res = mode_page_fill_func(ns, hdr, &response[mode_pages_offset_1],
  1234. mode_pages_tot_len);
  1235. if (res != SNTI_TRANSLATION_SUCCESS)
  1236. goto out_free;
  1237. xfer_len = min(alloc_len, resp_size);
  1238. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  1239. out_free:
  1240. kfree(response);
  1241. out_mem:
  1242. return res;
  1243. }
  1244. /* Read Capacity Helper Functions */
  1245. static void nvme_trans_fill_read_cap(u8 *response, struct nvme_id_ns *id_ns,
  1246. u8 cdb16)
  1247. {
  1248. u8 flbas;
  1249. u32 lba_length;
  1250. u64 rlba;
  1251. u8 prot_en;
  1252. u8 p_type_lut[4] = {0, 0, 1, 2};
  1253. __be64 tmp_rlba;
  1254. __be32 tmp_rlba_32;
  1255. __be32 tmp_len;
  1256. flbas = (id_ns->flbas) & 0x0F;
  1257. lba_length = (1 << (id_ns->lbaf[flbas].ds));
  1258. rlba = le64_to_cpup(&id_ns->nsze) - 1;
  1259. (id_ns->dps) ? (prot_en = 0x01) : (prot_en = 0);
  1260. if (!cdb16) {
  1261. if (rlba > 0xFFFFFFFF)
  1262. rlba = 0xFFFFFFFF;
  1263. tmp_rlba_32 = cpu_to_be32(rlba);
  1264. tmp_len = cpu_to_be32(lba_length);
  1265. memcpy(response, &tmp_rlba_32, sizeof(u32));
  1266. memcpy(&response[4], &tmp_len, sizeof(u32));
  1267. } else {
  1268. tmp_rlba = cpu_to_be64(rlba);
  1269. tmp_len = cpu_to_be32(lba_length);
  1270. memcpy(response, &tmp_rlba, sizeof(u64));
  1271. memcpy(&response[8], &tmp_len, sizeof(u32));
  1272. response[12] = (p_type_lut[id_ns->dps & 0x3] << 1) | prot_en;
  1273. /* P_I_Exponent = 0x0 | LBPPBE = 0x0 */
  1274. /* LBPME = 0 | LBPRZ = 0 | LALBA = 0x00 */
  1275. /* Bytes 16-31 - Reserved */
  1276. }
  1277. }
  1278. /* Start Stop Unit Helper Functions */
  1279. static int nvme_trans_power_state(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1280. u8 pc, u8 pcmod, u8 start)
  1281. {
  1282. int res = SNTI_TRANSLATION_SUCCESS;
  1283. int nvme_sc;
  1284. struct nvme_dev *dev = ns->dev;
  1285. dma_addr_t dma_addr;
  1286. void *mem;
  1287. struct nvme_id_ctrl *id_ctrl;
  1288. int lowest_pow_st; /* max npss = lowest power consumption */
  1289. unsigned ps_desired = 0;
  1290. /* NVMe Controller Identify */
  1291. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  1292. sizeof(struct nvme_id_ctrl),
  1293. &dma_addr, GFP_KERNEL);
  1294. if (mem == NULL) {
  1295. res = -ENOMEM;
  1296. goto out;
  1297. }
  1298. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  1299. res = nvme_trans_status_code(hdr, nvme_sc);
  1300. if (res)
  1301. goto out_dma;
  1302. if (nvme_sc) {
  1303. res = nvme_sc;
  1304. goto out_dma;
  1305. }
  1306. id_ctrl = mem;
  1307. lowest_pow_st = max(POWER_STATE_0, (int)(id_ctrl->npss - 1));
  1308. switch (pc) {
  1309. case NVME_POWER_STATE_START_VALID:
  1310. /* Action unspecified if POWER CONDITION MODIFIER != 0 */
  1311. if (pcmod == 0 && start == 0x1)
  1312. ps_desired = POWER_STATE_0;
  1313. if (pcmod == 0 && start == 0x0)
  1314. ps_desired = lowest_pow_st;
  1315. break;
  1316. case NVME_POWER_STATE_ACTIVE:
  1317. /* Action unspecified if POWER CONDITION MODIFIER != 0 */
  1318. if (pcmod == 0)
  1319. ps_desired = POWER_STATE_0;
  1320. break;
  1321. case NVME_POWER_STATE_IDLE:
  1322. /* Action unspecified if POWER CONDITION MODIFIER != [0,1,2] */
  1323. if (pcmod == 0x0)
  1324. ps_desired = POWER_STATE_1;
  1325. else if (pcmod == 0x1)
  1326. ps_desired = POWER_STATE_2;
  1327. else if (pcmod == 0x2)
  1328. ps_desired = POWER_STATE_3;
  1329. break;
  1330. case NVME_POWER_STATE_STANDBY:
  1331. /* Action unspecified if POWER CONDITION MODIFIER != [0,1] */
  1332. if (pcmod == 0x0)
  1333. ps_desired = max(POWER_STATE_0, (lowest_pow_st - 2));
  1334. else if (pcmod == 0x1)
  1335. ps_desired = max(POWER_STATE_0, (lowest_pow_st - 1));
  1336. break;
  1337. case NVME_POWER_STATE_LU_CONTROL:
  1338. default:
  1339. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1340. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1341. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1342. break;
  1343. }
  1344. nvme_sc = nvme_set_features(dev, NVME_FEAT_POWER_MGMT, ps_desired, 0,
  1345. NULL);
  1346. res = nvme_trans_status_code(hdr, nvme_sc);
  1347. if (res)
  1348. goto out_dma;
  1349. if (nvme_sc)
  1350. res = nvme_sc;
  1351. out_dma:
  1352. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ctrl), mem,
  1353. dma_addr);
  1354. out:
  1355. return res;
  1356. }
  1357. /* Write Buffer Helper Functions */
  1358. /* Also using this for Format Unit with hdr passed as NULL, and buffer_id, 0 */
  1359. static int nvme_trans_send_fw_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1360. u8 opcode, u32 tot_len, u32 offset,
  1361. u8 buffer_id)
  1362. {
  1363. int res = SNTI_TRANSLATION_SUCCESS;
  1364. int nvme_sc;
  1365. struct nvme_dev *dev = ns->dev;
  1366. struct nvme_command c;
  1367. struct nvme_iod *iod = NULL;
  1368. unsigned length;
  1369. memset(&c, 0, sizeof(c));
  1370. c.common.opcode = opcode;
  1371. if (opcode == nvme_admin_download_fw) {
  1372. if (hdr->iovec_count > 0) {
  1373. /* Assuming SGL is not allowed for this command */
  1374. res = nvme_trans_completion(hdr,
  1375. SAM_STAT_CHECK_CONDITION,
  1376. ILLEGAL_REQUEST,
  1377. SCSI_ASC_INVALID_CDB,
  1378. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1379. goto out;
  1380. }
  1381. iod = nvme_map_user_pages(dev, DMA_TO_DEVICE,
  1382. (unsigned long)hdr->dxferp, tot_len);
  1383. if (IS_ERR(iod)) {
  1384. res = PTR_ERR(iod);
  1385. goto out;
  1386. }
  1387. length = nvme_setup_prps(dev, iod, tot_len, GFP_KERNEL);
  1388. if (length != tot_len) {
  1389. res = -ENOMEM;
  1390. goto out_unmap;
  1391. }
  1392. c.dlfw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
  1393. c.dlfw.prp2 = cpu_to_le64(iod->first_dma);
  1394. c.dlfw.numd = cpu_to_le32((tot_len/BYTES_TO_DWORDS) - 1);
  1395. c.dlfw.offset = cpu_to_le32(offset/BYTES_TO_DWORDS);
  1396. } else if (opcode == nvme_admin_activate_fw) {
  1397. u32 cdw10 = buffer_id | NVME_FWACT_REPL_ACTV;
  1398. c.common.cdw10[0] = cpu_to_le32(cdw10);
  1399. }
  1400. nvme_sc = nvme_submit_admin_cmd(dev, &c, NULL);
  1401. res = nvme_trans_status_code(hdr, nvme_sc);
  1402. if (res)
  1403. goto out_unmap;
  1404. if (nvme_sc)
  1405. res = nvme_sc;
  1406. out_unmap:
  1407. if (opcode == nvme_admin_download_fw) {
  1408. nvme_unmap_user_pages(dev, DMA_TO_DEVICE, iod);
  1409. nvme_free_iod(dev, iod);
  1410. }
  1411. out:
  1412. return res;
  1413. }
  1414. /* Mode Select Helper Functions */
  1415. static inline void nvme_trans_modesel_get_bd_len(u8 *parm_list, u8 cdb10,
  1416. u16 *bd_len, u8 *llbaa)
  1417. {
  1418. if (cdb10) {
  1419. /* 10 Byte CDB */
  1420. *bd_len = (parm_list[MODE_SELECT_10_BD_OFFSET] << 8) +
  1421. parm_list[MODE_SELECT_10_BD_OFFSET + 1];
  1422. *llbaa = parm_list[MODE_SELECT_10_LLBAA_OFFSET] &&
  1423. MODE_SELECT_10_LLBAA_MASK;
  1424. } else {
  1425. /* 6 Byte CDB */
  1426. *bd_len = parm_list[MODE_SELECT_6_BD_OFFSET];
  1427. }
  1428. }
  1429. static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list,
  1430. u16 idx, u16 bd_len, u8 llbaa)
  1431. {
  1432. u16 bd_num;
  1433. bd_num = bd_len / ((llbaa == 0) ?
  1434. SHORT_DESC_BLOCK : LONG_DESC_BLOCK);
  1435. /* Store block descriptor info if a FORMAT UNIT comes later */
  1436. /* TODO Saving 1st BD info; what to do if multiple BD received? */
  1437. if (llbaa == 0) {
  1438. /* Standard Block Descriptor - spc4r34 7.5.5.1 */
  1439. ns->mode_select_num_blocks =
  1440. (parm_list[idx + 1] << 16) +
  1441. (parm_list[idx + 2] << 8) +
  1442. (parm_list[idx + 3]);
  1443. ns->mode_select_block_len =
  1444. (parm_list[idx + 5] << 16) +
  1445. (parm_list[idx + 6] << 8) +
  1446. (parm_list[idx + 7]);
  1447. } else {
  1448. /* Long LBA Block Descriptor - sbc3r27 6.4.2.3 */
  1449. ns->mode_select_num_blocks =
  1450. (((u64)parm_list[idx + 0]) << 56) +
  1451. (((u64)parm_list[idx + 1]) << 48) +
  1452. (((u64)parm_list[idx + 2]) << 40) +
  1453. (((u64)parm_list[idx + 3]) << 32) +
  1454. (((u64)parm_list[idx + 4]) << 24) +
  1455. (((u64)parm_list[idx + 5]) << 16) +
  1456. (((u64)parm_list[idx + 6]) << 8) +
  1457. ((u64)parm_list[idx + 7]);
  1458. ns->mode_select_block_len =
  1459. (parm_list[idx + 12] << 24) +
  1460. (parm_list[idx + 13] << 16) +
  1461. (parm_list[idx + 14] << 8) +
  1462. (parm_list[idx + 15]);
  1463. }
  1464. }
  1465. static int nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1466. u8 *mode_page, u8 page_code)
  1467. {
  1468. int res = SNTI_TRANSLATION_SUCCESS;
  1469. int nvme_sc;
  1470. struct nvme_dev *dev = ns->dev;
  1471. unsigned dword11;
  1472. switch (page_code) {
  1473. case MODE_PAGE_CACHING:
  1474. dword11 = ((mode_page[2] & CACHING_MODE_PAGE_WCE_MASK) ? 1 : 0);
  1475. nvme_sc = nvme_set_features(dev, NVME_FEAT_VOLATILE_WC, dword11,
  1476. 0, NULL);
  1477. res = nvme_trans_status_code(hdr, nvme_sc);
  1478. if (res)
  1479. break;
  1480. if (nvme_sc) {
  1481. res = nvme_sc;
  1482. break;
  1483. }
  1484. break;
  1485. case MODE_PAGE_CONTROL:
  1486. break;
  1487. case MODE_PAGE_POWER_CONDITION:
  1488. /* Verify the OS is not trying to set timers */
  1489. if ((mode_page[2] & 0x01) != 0 || (mode_page[3] & 0x0F) != 0) {
  1490. res = nvme_trans_completion(hdr,
  1491. SAM_STAT_CHECK_CONDITION,
  1492. ILLEGAL_REQUEST,
  1493. SCSI_ASC_INVALID_PARAMETER,
  1494. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1495. if (!res)
  1496. res = SNTI_INTERNAL_ERROR;
  1497. break;
  1498. }
  1499. break;
  1500. default:
  1501. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1502. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1503. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1504. if (!res)
  1505. res = SNTI_INTERNAL_ERROR;
  1506. break;
  1507. }
  1508. return res;
  1509. }
  1510. static int nvme_trans_modesel_data(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1511. u8 *cmd, u16 parm_list_len, u8 pf,
  1512. u8 sp, u8 cdb10)
  1513. {
  1514. int res = SNTI_TRANSLATION_SUCCESS;
  1515. u8 *parm_list;
  1516. u16 bd_len;
  1517. u8 llbaa = 0;
  1518. u16 index, saved_index;
  1519. u8 page_code;
  1520. u16 mp_size;
  1521. /* Get parm list from data-in/out buffer */
  1522. parm_list = kmalloc(parm_list_len, GFP_KERNEL);
  1523. if (parm_list == NULL) {
  1524. res = -ENOMEM;
  1525. goto out;
  1526. }
  1527. res = nvme_trans_copy_from_user(hdr, parm_list, parm_list_len);
  1528. if (res != SNTI_TRANSLATION_SUCCESS)
  1529. goto out_mem;
  1530. nvme_trans_modesel_get_bd_len(parm_list, cdb10, &bd_len, &llbaa);
  1531. index = (cdb10) ? (MODE_SELECT_10_MPH_SIZE) : (MODE_SELECT_6_MPH_SIZE);
  1532. if (bd_len != 0) {
  1533. /* Block Descriptors present, parse */
  1534. nvme_trans_modesel_save_bd(ns, parm_list, index, bd_len, llbaa);
  1535. index += bd_len;
  1536. }
  1537. saved_index = index;
  1538. /* Multiple mode pages may be present; iterate through all */
  1539. /* In 1st Iteration, don't do NVME Command, only check for CDB errors */
  1540. do {
  1541. page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK;
  1542. mp_size = parm_list[index + 1] + 2;
  1543. if ((page_code != MODE_PAGE_CACHING) &&
  1544. (page_code != MODE_PAGE_CONTROL) &&
  1545. (page_code != MODE_PAGE_POWER_CONDITION)) {
  1546. res = nvme_trans_completion(hdr,
  1547. SAM_STAT_CHECK_CONDITION,
  1548. ILLEGAL_REQUEST,
  1549. SCSI_ASC_INVALID_CDB,
  1550. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1551. goto out_mem;
  1552. }
  1553. index += mp_size;
  1554. } while (index < parm_list_len);
  1555. /* In 2nd Iteration, do the NVME Commands */
  1556. index = saved_index;
  1557. do {
  1558. page_code = parm_list[index] & MODE_SELECT_PAGE_CODE_MASK;
  1559. mp_size = parm_list[index + 1] + 2;
  1560. res = nvme_trans_modesel_get_mp(ns, hdr, &parm_list[index],
  1561. page_code);
  1562. if (res != SNTI_TRANSLATION_SUCCESS)
  1563. break;
  1564. index += mp_size;
  1565. } while (index < parm_list_len);
  1566. out_mem:
  1567. kfree(parm_list);
  1568. out:
  1569. return res;
  1570. }
  1571. /* Format Unit Helper Functions */
  1572. static int nvme_trans_fmt_set_blk_size_count(struct nvme_ns *ns,
  1573. struct sg_io_hdr *hdr)
  1574. {
  1575. int res = SNTI_TRANSLATION_SUCCESS;
  1576. int nvme_sc;
  1577. struct nvme_dev *dev = ns->dev;
  1578. dma_addr_t dma_addr;
  1579. void *mem;
  1580. struct nvme_id_ns *id_ns;
  1581. u8 flbas;
  1582. /*
  1583. * SCSI Expects a MODE SELECT would have been issued prior to
  1584. * a FORMAT UNIT, and the block size and number would be used
  1585. * from the block descriptor in it. If a MODE SELECT had not
  1586. * been issued, FORMAT shall use the current values for both.
  1587. */
  1588. if (ns->mode_select_num_blocks == 0 || ns->mode_select_block_len == 0) {
  1589. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  1590. sizeof(struct nvme_id_ns), &dma_addr, GFP_KERNEL);
  1591. if (mem == NULL) {
  1592. res = -ENOMEM;
  1593. goto out;
  1594. }
  1595. /* nvme ns identify */
  1596. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1597. res = nvme_trans_status_code(hdr, nvme_sc);
  1598. if (res)
  1599. goto out_dma;
  1600. if (nvme_sc) {
  1601. res = nvme_sc;
  1602. goto out_dma;
  1603. }
  1604. id_ns = mem;
  1605. if (ns->mode_select_num_blocks == 0)
  1606. ns->mode_select_num_blocks = le64_to_cpu(id_ns->ncap);
  1607. if (ns->mode_select_block_len == 0) {
  1608. flbas = (id_ns->flbas) & 0x0F;
  1609. ns->mode_select_block_len =
  1610. (1 << (id_ns->lbaf[flbas].ds));
  1611. }
  1612. out_dma:
  1613. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1614. mem, dma_addr);
  1615. }
  1616. out:
  1617. return res;
  1618. }
  1619. static int nvme_trans_fmt_get_parm_header(struct sg_io_hdr *hdr, u8 len,
  1620. u8 format_prot_info, u8 *nvme_pf_code)
  1621. {
  1622. int res = SNTI_TRANSLATION_SUCCESS;
  1623. u8 *parm_list;
  1624. u8 pf_usage, pf_code;
  1625. parm_list = kmalloc(len, GFP_KERNEL);
  1626. if (parm_list == NULL) {
  1627. res = -ENOMEM;
  1628. goto out;
  1629. }
  1630. res = nvme_trans_copy_from_user(hdr, parm_list, len);
  1631. if (res != SNTI_TRANSLATION_SUCCESS)
  1632. goto out_mem;
  1633. if ((parm_list[FORMAT_UNIT_IMMED_OFFSET] &
  1634. FORMAT_UNIT_IMMED_MASK) != 0) {
  1635. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1636. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1637. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1638. goto out_mem;
  1639. }
  1640. if (len == FORMAT_UNIT_LONG_PARM_LIST_LEN &&
  1641. (parm_list[FORMAT_UNIT_PROT_INT_OFFSET] & 0x0F) != 0) {
  1642. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1643. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1644. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1645. goto out_mem;
  1646. }
  1647. pf_usage = parm_list[FORMAT_UNIT_PROT_FIELD_USAGE_OFFSET] &
  1648. FORMAT_UNIT_PROT_FIELD_USAGE_MASK;
  1649. pf_code = (pf_usage << 2) | format_prot_info;
  1650. switch (pf_code) {
  1651. case 0:
  1652. *nvme_pf_code = 0;
  1653. break;
  1654. case 2:
  1655. *nvme_pf_code = 1;
  1656. break;
  1657. case 3:
  1658. *nvme_pf_code = 2;
  1659. break;
  1660. case 7:
  1661. *nvme_pf_code = 3;
  1662. break;
  1663. default:
  1664. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1665. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  1666. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1667. break;
  1668. }
  1669. out_mem:
  1670. kfree(parm_list);
  1671. out:
  1672. return res;
  1673. }
  1674. static int nvme_trans_fmt_send_cmd(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1675. u8 prot_info)
  1676. {
  1677. int res = SNTI_TRANSLATION_SUCCESS;
  1678. int nvme_sc;
  1679. struct nvme_dev *dev = ns->dev;
  1680. dma_addr_t dma_addr;
  1681. void *mem;
  1682. struct nvme_id_ns *id_ns;
  1683. u8 i;
  1684. u8 flbas, nlbaf;
  1685. u8 selected_lbaf = 0xFF;
  1686. u32 cdw10 = 0;
  1687. struct nvme_command c;
  1688. /* Loop thru LBAF's in id_ns to match reqd lbaf, put in cdw10 */
  1689. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  1690. &dma_addr, GFP_KERNEL);
  1691. if (mem == NULL) {
  1692. res = -ENOMEM;
  1693. goto out;
  1694. }
  1695. /* nvme ns identify */
  1696. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  1697. res = nvme_trans_status_code(hdr, nvme_sc);
  1698. if (res)
  1699. goto out_dma;
  1700. if (nvme_sc) {
  1701. res = nvme_sc;
  1702. goto out_dma;
  1703. }
  1704. id_ns = mem;
  1705. flbas = (id_ns->flbas) & 0x0F;
  1706. nlbaf = id_ns->nlbaf;
  1707. for (i = 0; i < nlbaf; i++) {
  1708. if (ns->mode_select_block_len == (1 << (id_ns->lbaf[i].ds))) {
  1709. selected_lbaf = i;
  1710. break;
  1711. }
  1712. }
  1713. if (selected_lbaf > 0x0F) {
  1714. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1715. ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER,
  1716. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1717. }
  1718. if (ns->mode_select_num_blocks != le64_to_cpu(id_ns->ncap)) {
  1719. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  1720. ILLEGAL_REQUEST, SCSI_ASC_INVALID_PARAMETER,
  1721. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1722. }
  1723. cdw10 |= prot_info << 5;
  1724. cdw10 |= selected_lbaf & 0x0F;
  1725. memset(&c, 0, sizeof(c));
  1726. c.format.opcode = nvme_admin_format_nvm;
  1727. c.format.nsid = cpu_to_le32(ns->ns_id);
  1728. c.format.cdw10 = cpu_to_le32(cdw10);
  1729. nvme_sc = nvme_submit_admin_cmd(dev, &c, NULL);
  1730. res = nvme_trans_status_code(hdr, nvme_sc);
  1731. if (res)
  1732. goto out_dma;
  1733. if (nvme_sc)
  1734. res = nvme_sc;
  1735. out_dma:
  1736. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  1737. dma_addr);
  1738. out:
  1739. return res;
  1740. }
  1741. /* Read/Write Helper Functions */
  1742. static inline void nvme_trans_get_io_cdb6(u8 *cmd,
  1743. struct nvme_trans_io_cdb *cdb_info)
  1744. {
  1745. cdb_info->fua = 0;
  1746. cdb_info->prot_info = 0;
  1747. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_6_CDB_LBA_OFFSET) &
  1748. IO_6_CDB_LBA_MASK;
  1749. cdb_info->xfer_len = GET_U8_FROM_CDB(cmd, IO_6_CDB_TX_LEN_OFFSET);
  1750. /* sbc3r27 sec 5.32 - TRANSFER LEN of 0 implies a 256 Block transfer */
  1751. if (cdb_info->xfer_len == 0)
  1752. cdb_info->xfer_len = IO_6_DEFAULT_TX_LEN;
  1753. }
  1754. static inline void nvme_trans_get_io_cdb10(u8 *cmd,
  1755. struct nvme_trans_io_cdb *cdb_info)
  1756. {
  1757. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_10_CDB_FUA_OFFSET) &
  1758. IO_CDB_FUA_MASK;
  1759. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_10_CDB_WP_OFFSET) &
  1760. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1761. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_10_CDB_LBA_OFFSET);
  1762. cdb_info->xfer_len = GET_U16_FROM_CDB(cmd, IO_10_CDB_TX_LEN_OFFSET);
  1763. }
  1764. static inline void nvme_trans_get_io_cdb12(u8 *cmd,
  1765. struct nvme_trans_io_cdb *cdb_info)
  1766. {
  1767. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_12_CDB_FUA_OFFSET) &
  1768. IO_CDB_FUA_MASK;
  1769. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_12_CDB_WP_OFFSET) &
  1770. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1771. cdb_info->lba = GET_U32_FROM_CDB(cmd, IO_12_CDB_LBA_OFFSET);
  1772. cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_12_CDB_TX_LEN_OFFSET);
  1773. }
  1774. static inline void nvme_trans_get_io_cdb16(u8 *cmd,
  1775. struct nvme_trans_io_cdb *cdb_info)
  1776. {
  1777. cdb_info->fua = GET_U8_FROM_CDB(cmd, IO_16_CDB_FUA_OFFSET) &
  1778. IO_CDB_FUA_MASK;
  1779. cdb_info->prot_info = GET_U8_FROM_CDB(cmd, IO_16_CDB_WP_OFFSET) &
  1780. IO_CDB_WP_MASK >> IO_CDB_WP_SHIFT;
  1781. cdb_info->lba = GET_U64_FROM_CDB(cmd, IO_16_CDB_LBA_OFFSET);
  1782. cdb_info->xfer_len = GET_U32_FROM_CDB(cmd, IO_16_CDB_TX_LEN_OFFSET);
  1783. }
  1784. static inline u32 nvme_trans_io_get_num_cmds(struct sg_io_hdr *hdr,
  1785. struct nvme_trans_io_cdb *cdb_info,
  1786. u32 max_blocks)
  1787. {
  1788. /* If using iovecs, send one nvme command per vector */
  1789. if (hdr->iovec_count > 0)
  1790. return hdr->iovec_count;
  1791. else if (cdb_info->xfer_len > max_blocks)
  1792. return ((cdb_info->xfer_len - 1) / max_blocks) + 1;
  1793. else
  1794. return 1;
  1795. }
  1796. static u16 nvme_trans_io_get_control(struct nvme_ns *ns,
  1797. struct nvme_trans_io_cdb *cdb_info)
  1798. {
  1799. u16 control = 0;
  1800. /* When Protection information support is added, implement here */
  1801. if (cdb_info->fua > 0)
  1802. control |= NVME_RW_FUA;
  1803. return control;
  1804. }
  1805. static int nvme_trans_do_nvme_io(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1806. struct nvme_trans_io_cdb *cdb_info, u8 is_write)
  1807. {
  1808. int res = SNTI_TRANSLATION_SUCCESS;
  1809. int nvme_sc;
  1810. struct nvme_dev *dev = ns->dev;
  1811. u32 num_cmds;
  1812. struct nvme_iod *iod;
  1813. u64 unit_len;
  1814. u64 unit_num_blocks; /* Number of blocks to xfer in each nvme cmd */
  1815. u32 retcode;
  1816. u32 i = 0;
  1817. u64 nvme_offset = 0;
  1818. void __user *next_mapping_addr;
  1819. struct nvme_command c;
  1820. u8 opcode = (is_write ? nvme_cmd_write : nvme_cmd_read);
  1821. u16 control;
  1822. u32 max_blocks = queue_max_hw_sectors(ns->queue);
  1823. num_cmds = nvme_trans_io_get_num_cmds(hdr, cdb_info, max_blocks);
  1824. /*
  1825. * This loop handles two cases.
  1826. * First, when an SGL is used in the form of an iovec list:
  1827. * - Use iov_base as the next mapping address for the nvme command_id
  1828. * - Use iov_len as the data transfer length for the command.
  1829. * Second, when we have a single buffer
  1830. * - If larger than max_blocks, split into chunks, offset
  1831. * each nvme command accordingly.
  1832. */
  1833. for (i = 0; i < num_cmds; i++) {
  1834. memset(&c, 0, sizeof(c));
  1835. if (hdr->iovec_count > 0) {
  1836. struct sg_iovec sgl;
  1837. retcode = copy_from_user(&sgl, hdr->dxferp +
  1838. i * sizeof(struct sg_iovec),
  1839. sizeof(struct sg_iovec));
  1840. if (retcode)
  1841. return -EFAULT;
  1842. unit_len = sgl.iov_len;
  1843. unit_num_blocks = unit_len >> ns->lba_shift;
  1844. next_mapping_addr = sgl.iov_base;
  1845. } else {
  1846. unit_num_blocks = min((u64)max_blocks,
  1847. (cdb_info->xfer_len - nvme_offset));
  1848. unit_len = unit_num_blocks << ns->lba_shift;
  1849. next_mapping_addr = hdr->dxferp +
  1850. ((1 << ns->lba_shift) * nvme_offset);
  1851. }
  1852. c.rw.opcode = opcode;
  1853. c.rw.nsid = cpu_to_le32(ns->ns_id);
  1854. c.rw.slba = cpu_to_le64(cdb_info->lba + nvme_offset);
  1855. c.rw.length = cpu_to_le16(unit_num_blocks - 1);
  1856. control = nvme_trans_io_get_control(ns, cdb_info);
  1857. c.rw.control = cpu_to_le16(control);
  1858. iod = nvme_map_user_pages(dev,
  1859. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1860. (unsigned long)next_mapping_addr, unit_len);
  1861. if (IS_ERR(iod)) {
  1862. res = PTR_ERR(iod);
  1863. goto out;
  1864. }
  1865. retcode = nvme_setup_prps(dev, iod, unit_len, GFP_KERNEL);
  1866. if (retcode != unit_len) {
  1867. nvme_unmap_user_pages(dev,
  1868. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1869. iod);
  1870. nvme_free_iod(dev, iod);
  1871. res = -ENOMEM;
  1872. goto out;
  1873. }
  1874. c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
  1875. c.rw.prp2 = cpu_to_le64(iod->first_dma);
  1876. nvme_offset += unit_num_blocks;
  1877. nvme_sc = nvme_submit_io_cmd(dev, &c, NULL);
  1878. if (nvme_sc != NVME_SC_SUCCESS) {
  1879. nvme_unmap_user_pages(dev,
  1880. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1881. iod);
  1882. nvme_free_iod(dev, iod);
  1883. res = nvme_trans_status_code(hdr, nvme_sc);
  1884. goto out;
  1885. }
  1886. nvme_unmap_user_pages(dev,
  1887. (is_write) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
  1888. iod);
  1889. nvme_free_iod(dev, iod);
  1890. }
  1891. res = nvme_trans_status_code(hdr, NVME_SC_SUCCESS);
  1892. out:
  1893. return res;
  1894. }
  1895. /* SCSI Command Translation Functions */
  1896. static int nvme_trans_io(struct nvme_ns *ns, struct sg_io_hdr *hdr, u8 is_write,
  1897. u8 *cmd)
  1898. {
  1899. int res = SNTI_TRANSLATION_SUCCESS;
  1900. struct nvme_trans_io_cdb cdb_info;
  1901. u8 opcode = cmd[0];
  1902. u64 xfer_bytes;
  1903. u64 sum_iov_len = 0;
  1904. struct sg_iovec sgl;
  1905. int i;
  1906. size_t not_copied;
  1907. /* Extract Fields from CDB */
  1908. switch (opcode) {
  1909. case WRITE_6:
  1910. case READ_6:
  1911. nvme_trans_get_io_cdb6(cmd, &cdb_info);
  1912. break;
  1913. case WRITE_10:
  1914. case READ_10:
  1915. nvme_trans_get_io_cdb10(cmd, &cdb_info);
  1916. break;
  1917. case WRITE_12:
  1918. case READ_12:
  1919. nvme_trans_get_io_cdb12(cmd, &cdb_info);
  1920. break;
  1921. case WRITE_16:
  1922. case READ_16:
  1923. nvme_trans_get_io_cdb16(cmd, &cdb_info);
  1924. break;
  1925. default:
  1926. /* Will never really reach here */
  1927. res = SNTI_INTERNAL_ERROR;
  1928. goto out;
  1929. }
  1930. /* Calculate total length of transfer (in bytes) */
  1931. if (hdr->iovec_count > 0) {
  1932. for (i = 0; i < hdr->iovec_count; i++) {
  1933. not_copied = copy_from_user(&sgl, hdr->dxferp +
  1934. i * sizeof(struct sg_iovec),
  1935. sizeof(struct sg_iovec));
  1936. if (not_copied)
  1937. return -EFAULT;
  1938. sum_iov_len += sgl.iov_len;
  1939. /* IO vector sizes should be multiples of block size */
  1940. if (sgl.iov_len % (1 << ns->lba_shift) != 0) {
  1941. res = nvme_trans_completion(hdr,
  1942. SAM_STAT_CHECK_CONDITION,
  1943. ILLEGAL_REQUEST,
  1944. SCSI_ASC_INVALID_PARAMETER,
  1945. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1946. goto out;
  1947. }
  1948. }
  1949. } else {
  1950. sum_iov_len = hdr->dxfer_len;
  1951. }
  1952. /* As Per sg ioctl howto, if the lengths differ, use the lower one */
  1953. xfer_bytes = min(((u64)hdr->dxfer_len), sum_iov_len);
  1954. /* If block count and actual data buffer size dont match, error out */
  1955. if (xfer_bytes != (cdb_info.xfer_len << ns->lba_shift)) {
  1956. res = -EINVAL;
  1957. goto out;
  1958. }
  1959. /* Check for 0 length transfer - it is not illegal */
  1960. if (cdb_info.xfer_len == 0)
  1961. goto out;
  1962. /* Send NVMe IO Command(s) */
  1963. res = nvme_trans_do_nvme_io(ns, hdr, &cdb_info, is_write);
  1964. if (res != SNTI_TRANSLATION_SUCCESS)
  1965. goto out;
  1966. out:
  1967. return res;
  1968. }
  1969. static int nvme_trans_inquiry(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  1970. u8 *cmd)
  1971. {
  1972. int res = SNTI_TRANSLATION_SUCCESS;
  1973. u8 evpd;
  1974. u8 page_code;
  1975. int alloc_len;
  1976. u8 *inq_response;
  1977. evpd = GET_INQ_EVPD_BIT(cmd);
  1978. page_code = GET_INQ_PAGE_CODE(cmd);
  1979. alloc_len = GET_INQ_ALLOC_LENGTH(cmd);
  1980. inq_response = kmalloc(STANDARD_INQUIRY_LENGTH, GFP_KERNEL);
  1981. if (inq_response == NULL) {
  1982. res = -ENOMEM;
  1983. goto out_mem;
  1984. }
  1985. if (evpd == 0) {
  1986. if (page_code == INQ_STANDARD_INQUIRY_PAGE) {
  1987. res = nvme_trans_standard_inquiry_page(ns, hdr,
  1988. inq_response, alloc_len);
  1989. } else {
  1990. res = nvme_trans_completion(hdr,
  1991. SAM_STAT_CHECK_CONDITION,
  1992. ILLEGAL_REQUEST,
  1993. SCSI_ASC_INVALID_CDB,
  1994. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  1995. }
  1996. } else {
  1997. switch (page_code) {
  1998. case VPD_SUPPORTED_PAGES:
  1999. res = nvme_trans_supported_vpd_pages(ns, hdr,
  2000. inq_response, alloc_len);
  2001. break;
  2002. case VPD_SERIAL_NUMBER:
  2003. res = nvme_trans_unit_serial_page(ns, hdr, inq_response,
  2004. alloc_len);
  2005. break;
  2006. case VPD_DEVICE_IDENTIFIERS:
  2007. res = nvme_trans_device_id_page(ns, hdr, inq_response,
  2008. alloc_len);
  2009. break;
  2010. case VPD_EXTENDED_INQUIRY:
  2011. res = nvme_trans_ext_inq_page(ns, hdr, alloc_len);
  2012. break;
  2013. case VPD_BLOCK_DEV_CHARACTERISTICS:
  2014. res = nvme_trans_bdev_char_page(ns, hdr, alloc_len);
  2015. break;
  2016. default:
  2017. res = nvme_trans_completion(hdr,
  2018. SAM_STAT_CHECK_CONDITION,
  2019. ILLEGAL_REQUEST,
  2020. SCSI_ASC_INVALID_CDB,
  2021. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2022. break;
  2023. }
  2024. }
  2025. kfree(inq_response);
  2026. out_mem:
  2027. return res;
  2028. }
  2029. static int nvme_trans_log_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2030. u8 *cmd)
  2031. {
  2032. int res = SNTI_TRANSLATION_SUCCESS;
  2033. u16 alloc_len;
  2034. u8 sp;
  2035. u8 pc;
  2036. u8 page_code;
  2037. sp = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_SP_OFFSET);
  2038. if (sp != LOG_SENSE_CDB_SP_NOT_ENABLED) {
  2039. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2040. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2041. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2042. goto out;
  2043. }
  2044. pc = GET_U8_FROM_CDB(cmd, LOG_SENSE_CDB_PC_OFFSET);
  2045. page_code = pc & LOG_SENSE_CDB_PAGE_CODE_MASK;
  2046. pc = (pc & LOG_SENSE_CDB_PC_MASK) >> LOG_SENSE_CDB_PC_SHIFT;
  2047. if (pc != LOG_SENSE_CDB_PC_CUMULATIVE_VALUES) {
  2048. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2049. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2050. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2051. goto out;
  2052. }
  2053. alloc_len = GET_U16_FROM_CDB(cmd, LOG_SENSE_CDB_ALLOC_LENGTH_OFFSET);
  2054. switch (page_code) {
  2055. case LOG_PAGE_SUPPORTED_LOG_PAGES_PAGE:
  2056. res = nvme_trans_log_supp_pages(ns, hdr, alloc_len);
  2057. break;
  2058. case LOG_PAGE_INFORMATIONAL_EXCEPTIONS_PAGE:
  2059. res = nvme_trans_log_info_exceptions(ns, hdr, alloc_len);
  2060. break;
  2061. case LOG_PAGE_TEMPERATURE_PAGE:
  2062. res = nvme_trans_log_temperature(ns, hdr, alloc_len);
  2063. break;
  2064. default:
  2065. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2066. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2067. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2068. break;
  2069. }
  2070. out:
  2071. return res;
  2072. }
  2073. static int nvme_trans_mode_select(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2074. u8 *cmd)
  2075. {
  2076. int res = SNTI_TRANSLATION_SUCCESS;
  2077. u8 cdb10 = 0;
  2078. u16 parm_list_len;
  2079. u8 page_format;
  2080. u8 save_pages;
  2081. page_format = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_PAGE_FORMAT_OFFSET);
  2082. page_format &= MODE_SELECT_CDB_PAGE_FORMAT_MASK;
  2083. save_pages = GET_U8_FROM_CDB(cmd, MODE_SELECT_CDB_SAVE_PAGES_OFFSET);
  2084. save_pages &= MODE_SELECT_CDB_SAVE_PAGES_MASK;
  2085. if (GET_OPCODE(cmd) == MODE_SELECT) {
  2086. parm_list_len = GET_U8_FROM_CDB(cmd,
  2087. MODE_SELECT_6_CDB_PARAM_LIST_LENGTH_OFFSET);
  2088. } else {
  2089. parm_list_len = GET_U16_FROM_CDB(cmd,
  2090. MODE_SELECT_10_CDB_PARAM_LIST_LENGTH_OFFSET);
  2091. cdb10 = 1;
  2092. }
  2093. if (parm_list_len != 0) {
  2094. /*
  2095. * According to SPC-4 r24, a paramter list length field of 0
  2096. * shall not be considered an error
  2097. */
  2098. res = nvme_trans_modesel_data(ns, hdr, cmd, parm_list_len,
  2099. page_format, save_pages, cdb10);
  2100. }
  2101. return res;
  2102. }
  2103. static int nvme_trans_mode_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2104. u8 *cmd)
  2105. {
  2106. int res = SNTI_TRANSLATION_SUCCESS;
  2107. u16 alloc_len;
  2108. u8 cdb10 = 0;
  2109. u8 page_code;
  2110. u8 pc;
  2111. if (GET_OPCODE(cmd) == MODE_SENSE) {
  2112. alloc_len = GET_U8_FROM_CDB(cmd, MODE_SENSE6_ALLOC_LEN_OFFSET);
  2113. } else {
  2114. alloc_len = GET_U16_FROM_CDB(cmd,
  2115. MODE_SENSE10_ALLOC_LEN_OFFSET);
  2116. cdb10 = 1;
  2117. }
  2118. pc = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CONTROL_OFFSET) &
  2119. MODE_SENSE_PAGE_CONTROL_MASK;
  2120. if (pc != MODE_SENSE_PC_CURRENT_VALUES) {
  2121. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2122. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2123. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2124. goto out;
  2125. }
  2126. page_code = GET_U8_FROM_CDB(cmd, MODE_SENSE_PAGE_CODE_OFFSET) &
  2127. MODE_SENSE_PAGE_CODE_MASK;
  2128. switch (page_code) {
  2129. case MODE_PAGE_CACHING:
  2130. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2131. cdb10,
  2132. &nvme_trans_fill_caching_page,
  2133. MODE_PAGE_CACHING_LEN);
  2134. break;
  2135. case MODE_PAGE_CONTROL:
  2136. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2137. cdb10,
  2138. &nvme_trans_fill_control_page,
  2139. MODE_PAGE_CONTROL_LEN);
  2140. break;
  2141. case MODE_PAGE_POWER_CONDITION:
  2142. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2143. cdb10,
  2144. &nvme_trans_fill_pow_cnd_page,
  2145. MODE_PAGE_POW_CND_LEN);
  2146. break;
  2147. case MODE_PAGE_INFO_EXCEP:
  2148. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2149. cdb10,
  2150. &nvme_trans_fill_inf_exc_page,
  2151. MODE_PAGE_INF_EXC_LEN);
  2152. break;
  2153. case MODE_PAGE_RETURN_ALL:
  2154. res = nvme_trans_mode_page_create(ns, hdr, cmd, alloc_len,
  2155. cdb10,
  2156. &nvme_trans_fill_all_pages,
  2157. MODE_PAGE_ALL_LEN);
  2158. break;
  2159. default:
  2160. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2161. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2162. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2163. break;
  2164. }
  2165. out:
  2166. return res;
  2167. }
  2168. static int nvme_trans_read_capacity(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2169. u8 *cmd)
  2170. {
  2171. int res = SNTI_TRANSLATION_SUCCESS;
  2172. int nvme_sc;
  2173. u32 alloc_len = READ_CAP_10_RESP_SIZE;
  2174. u32 resp_size = READ_CAP_10_RESP_SIZE;
  2175. u32 xfer_len;
  2176. u8 cdb16;
  2177. struct nvme_dev *dev = ns->dev;
  2178. dma_addr_t dma_addr;
  2179. void *mem;
  2180. struct nvme_id_ns *id_ns;
  2181. u8 *response;
  2182. cdb16 = IS_READ_CAP_16(cmd);
  2183. if (cdb16) {
  2184. alloc_len = GET_READ_CAP_16_ALLOC_LENGTH(cmd);
  2185. resp_size = READ_CAP_16_RESP_SIZE;
  2186. }
  2187. mem = dma_alloc_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns),
  2188. &dma_addr, GFP_KERNEL);
  2189. if (mem == NULL) {
  2190. res = -ENOMEM;
  2191. goto out;
  2192. }
  2193. /* nvme ns identify */
  2194. nvme_sc = nvme_identify(dev, ns->ns_id, 0, dma_addr);
  2195. res = nvme_trans_status_code(hdr, nvme_sc);
  2196. if (res)
  2197. goto out_dma;
  2198. if (nvme_sc) {
  2199. res = nvme_sc;
  2200. goto out_dma;
  2201. }
  2202. id_ns = mem;
  2203. response = kzalloc(resp_size, GFP_KERNEL);
  2204. if (response == NULL) {
  2205. res = -ENOMEM;
  2206. goto out_dma;
  2207. }
  2208. nvme_trans_fill_read_cap(response, id_ns, cdb16);
  2209. xfer_len = min(alloc_len, resp_size);
  2210. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2211. kfree(response);
  2212. out_dma:
  2213. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ns), mem,
  2214. dma_addr);
  2215. out:
  2216. return res;
  2217. }
  2218. static int nvme_trans_report_luns(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2219. u8 *cmd)
  2220. {
  2221. int res = SNTI_TRANSLATION_SUCCESS;
  2222. int nvme_sc;
  2223. u32 alloc_len, xfer_len, resp_size;
  2224. u8 select_report;
  2225. u8 *response;
  2226. struct nvme_dev *dev = ns->dev;
  2227. dma_addr_t dma_addr;
  2228. void *mem;
  2229. struct nvme_id_ctrl *id_ctrl;
  2230. u32 ll_length, lun_id;
  2231. u8 lun_id_offset = REPORT_LUNS_FIRST_LUN_OFFSET;
  2232. __be32 tmp_len;
  2233. alloc_len = GET_REPORT_LUNS_ALLOC_LENGTH(cmd);
  2234. select_report = GET_U8_FROM_CDB(cmd, REPORT_LUNS_SR_OFFSET);
  2235. if ((select_report != ALL_LUNS_RETURNED) &&
  2236. (select_report != ALL_WELL_KNOWN_LUNS_RETURNED) &&
  2237. (select_report != RESTRICTED_LUNS_RETURNED)) {
  2238. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2239. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2240. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2241. goto out;
  2242. } else {
  2243. /* NVMe Controller Identify */
  2244. mem = dma_alloc_coherent(&dev->pci_dev->dev,
  2245. sizeof(struct nvme_id_ctrl),
  2246. &dma_addr, GFP_KERNEL);
  2247. if (mem == NULL) {
  2248. res = -ENOMEM;
  2249. goto out;
  2250. }
  2251. nvme_sc = nvme_identify(dev, 0, 1, dma_addr);
  2252. res = nvme_trans_status_code(hdr, nvme_sc);
  2253. if (res)
  2254. goto out_dma;
  2255. if (nvme_sc) {
  2256. res = nvme_sc;
  2257. goto out_dma;
  2258. }
  2259. id_ctrl = mem;
  2260. ll_length = le32_to_cpu(id_ctrl->nn) * LUN_ENTRY_SIZE;
  2261. resp_size = ll_length + LUN_DATA_HEADER_SIZE;
  2262. if (alloc_len < resp_size) {
  2263. res = nvme_trans_completion(hdr,
  2264. SAM_STAT_CHECK_CONDITION,
  2265. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2266. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2267. goto out_dma;
  2268. }
  2269. response = kzalloc(resp_size, GFP_KERNEL);
  2270. if (response == NULL) {
  2271. res = -ENOMEM;
  2272. goto out_dma;
  2273. }
  2274. /* The first LUN ID will always be 0 per the SAM spec */
  2275. for (lun_id = 0; lun_id < le32_to_cpu(id_ctrl->nn); lun_id++) {
  2276. /*
  2277. * Set the LUN Id and then increment to the next LUN
  2278. * location in the parameter data.
  2279. */
  2280. __be64 tmp_id = cpu_to_be64(lun_id);
  2281. memcpy(&response[lun_id_offset], &tmp_id, sizeof(u64));
  2282. lun_id_offset += LUN_ENTRY_SIZE;
  2283. }
  2284. tmp_len = cpu_to_be32(ll_length);
  2285. memcpy(response, &tmp_len, sizeof(u32));
  2286. }
  2287. xfer_len = min(alloc_len, resp_size);
  2288. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2289. kfree(response);
  2290. out_dma:
  2291. dma_free_coherent(&dev->pci_dev->dev, sizeof(struct nvme_id_ctrl), mem,
  2292. dma_addr);
  2293. out:
  2294. return res;
  2295. }
  2296. static int nvme_trans_request_sense(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2297. u8 *cmd)
  2298. {
  2299. int res = SNTI_TRANSLATION_SUCCESS;
  2300. u8 alloc_len, xfer_len, resp_size;
  2301. u8 desc_format;
  2302. u8 *response;
  2303. alloc_len = GET_REQUEST_SENSE_ALLOC_LENGTH(cmd);
  2304. desc_format = GET_U8_FROM_CDB(cmd, REQUEST_SENSE_DESC_OFFSET);
  2305. desc_format &= REQUEST_SENSE_DESC_MASK;
  2306. resp_size = ((desc_format) ? (DESC_FMT_SENSE_DATA_SIZE) :
  2307. (FIXED_FMT_SENSE_DATA_SIZE));
  2308. response = kzalloc(resp_size, GFP_KERNEL);
  2309. if (response == NULL) {
  2310. res = -ENOMEM;
  2311. goto out;
  2312. }
  2313. if (desc_format == DESCRIPTOR_FORMAT_SENSE_DATA_TYPE) {
  2314. /* Descriptor Format Sense Data */
  2315. response[0] = DESC_FORMAT_SENSE_DATA;
  2316. response[1] = NO_SENSE;
  2317. /* TODO How is LOW POWER CONDITION ON handled? (byte 2) */
  2318. response[2] = SCSI_ASC_NO_SENSE;
  2319. response[3] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  2320. /* SDAT_OVFL = 0 | Additional Sense Length = 0 */
  2321. } else {
  2322. /* Fixed Format Sense Data */
  2323. response[0] = FIXED_SENSE_DATA;
  2324. /* Byte 1 = Obsolete */
  2325. response[2] = NO_SENSE; /* FM, EOM, ILI, SDAT_OVFL = 0 */
  2326. /* Bytes 3-6 - Information - set to zero */
  2327. response[7] = FIXED_SENSE_DATA_ADD_LENGTH;
  2328. /* Bytes 8-11 - Cmd Specific Information - set to zero */
  2329. response[12] = SCSI_ASC_NO_SENSE;
  2330. response[13] = SCSI_ASCQ_CAUSE_NOT_REPORTABLE;
  2331. /* Byte 14 = Field Replaceable Unit Code = 0 */
  2332. /* Bytes 15-17 - SKSV=0; Sense Key Specific = 0 */
  2333. }
  2334. xfer_len = min(alloc_len, resp_size);
  2335. res = nvme_trans_copy_to_user(hdr, response, xfer_len);
  2336. kfree(response);
  2337. out:
  2338. return res;
  2339. }
  2340. static int nvme_trans_security_protocol(struct nvme_ns *ns,
  2341. struct sg_io_hdr *hdr,
  2342. u8 *cmd)
  2343. {
  2344. return nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2345. ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND,
  2346. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2347. }
  2348. static int nvme_trans_start_stop(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2349. u8 *cmd)
  2350. {
  2351. int res = SNTI_TRANSLATION_SUCCESS;
  2352. int nvme_sc;
  2353. struct nvme_command c;
  2354. u8 immed, pcmod, pc, no_flush, start;
  2355. immed = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_IMMED_OFFSET);
  2356. pcmod = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_MOD_OFFSET);
  2357. pc = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_POWER_COND_OFFSET);
  2358. no_flush = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_NO_FLUSH_OFFSET);
  2359. start = GET_U8_FROM_CDB(cmd, START_STOP_UNIT_CDB_START_OFFSET);
  2360. immed &= START_STOP_UNIT_CDB_IMMED_MASK;
  2361. pcmod &= START_STOP_UNIT_CDB_POWER_COND_MOD_MASK;
  2362. pc = (pc & START_STOP_UNIT_CDB_POWER_COND_MASK) >> NIBBLE_SHIFT;
  2363. no_flush &= START_STOP_UNIT_CDB_NO_FLUSH_MASK;
  2364. start &= START_STOP_UNIT_CDB_START_MASK;
  2365. if (immed != 0) {
  2366. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2367. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2368. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2369. } else {
  2370. if (no_flush == 0) {
  2371. /* Issue NVME FLUSH command prior to START STOP UNIT */
  2372. memset(&c, 0, sizeof(c));
  2373. c.common.opcode = nvme_cmd_flush;
  2374. c.common.nsid = cpu_to_le32(ns->ns_id);
  2375. nvme_sc = nvme_submit_io_cmd(ns->dev, &c, NULL);
  2376. res = nvme_trans_status_code(hdr, nvme_sc);
  2377. if (res)
  2378. goto out;
  2379. if (nvme_sc) {
  2380. res = nvme_sc;
  2381. goto out;
  2382. }
  2383. }
  2384. /* Setup the expected power state transition */
  2385. res = nvme_trans_power_state(ns, hdr, pc, pcmod, start);
  2386. }
  2387. out:
  2388. return res;
  2389. }
  2390. static int nvme_trans_synchronize_cache(struct nvme_ns *ns,
  2391. struct sg_io_hdr *hdr, u8 *cmd)
  2392. {
  2393. int res = SNTI_TRANSLATION_SUCCESS;
  2394. int nvme_sc;
  2395. struct nvme_command c;
  2396. memset(&c, 0, sizeof(c));
  2397. c.common.opcode = nvme_cmd_flush;
  2398. c.common.nsid = cpu_to_le32(ns->ns_id);
  2399. nvme_sc = nvme_submit_io_cmd(ns->dev, &c, NULL);
  2400. res = nvme_trans_status_code(hdr, nvme_sc);
  2401. if (res)
  2402. goto out;
  2403. if (nvme_sc)
  2404. res = nvme_sc;
  2405. out:
  2406. return res;
  2407. }
  2408. static int nvme_trans_format_unit(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2409. u8 *cmd)
  2410. {
  2411. int res = SNTI_TRANSLATION_SUCCESS;
  2412. u8 parm_hdr_len = 0;
  2413. u8 nvme_pf_code = 0;
  2414. u8 format_prot_info, long_list, format_data;
  2415. format_prot_info = GET_U8_FROM_CDB(cmd,
  2416. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_OFFSET);
  2417. long_list = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_LONG_LIST_OFFSET);
  2418. format_data = GET_U8_FROM_CDB(cmd, FORMAT_UNIT_CDB_FORMAT_DATA_OFFSET);
  2419. format_prot_info = (format_prot_info &
  2420. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_MASK) >>
  2421. FORMAT_UNIT_CDB_FORMAT_PROT_INFO_SHIFT;
  2422. long_list &= FORMAT_UNIT_CDB_LONG_LIST_MASK;
  2423. format_data &= FORMAT_UNIT_CDB_FORMAT_DATA_MASK;
  2424. if (format_data != 0) {
  2425. if (format_prot_info != 0) {
  2426. if (long_list == 0)
  2427. parm_hdr_len = FORMAT_UNIT_SHORT_PARM_LIST_LEN;
  2428. else
  2429. parm_hdr_len = FORMAT_UNIT_LONG_PARM_LIST_LEN;
  2430. }
  2431. } else if (format_data == 0 && format_prot_info != 0) {
  2432. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2433. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2434. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2435. goto out;
  2436. }
  2437. /* Get parm header from data-in/out buffer */
  2438. /*
  2439. * According to the translation spec, the only fields in the parameter
  2440. * list we are concerned with are in the header. So allocate only that.
  2441. */
  2442. if (parm_hdr_len > 0) {
  2443. res = nvme_trans_fmt_get_parm_header(hdr, parm_hdr_len,
  2444. format_prot_info, &nvme_pf_code);
  2445. if (res != SNTI_TRANSLATION_SUCCESS)
  2446. goto out;
  2447. }
  2448. /* Attempt to activate any previously downloaded firmware image */
  2449. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw, 0, 0, 0);
  2450. /* Determine Block size and count and send format command */
  2451. res = nvme_trans_fmt_set_blk_size_count(ns, hdr);
  2452. if (res != SNTI_TRANSLATION_SUCCESS)
  2453. goto out;
  2454. res = nvme_trans_fmt_send_cmd(ns, hdr, nvme_pf_code);
  2455. out:
  2456. return res;
  2457. }
  2458. static int nvme_trans_test_unit_ready(struct nvme_ns *ns,
  2459. struct sg_io_hdr *hdr,
  2460. u8 *cmd)
  2461. {
  2462. int res = SNTI_TRANSLATION_SUCCESS;
  2463. struct nvme_dev *dev = ns->dev;
  2464. if (!(readl(&dev->bar->csts) & NVME_CSTS_RDY))
  2465. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2466. NOT_READY, SCSI_ASC_LUN_NOT_READY,
  2467. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2468. else
  2469. res = nvme_trans_completion(hdr, SAM_STAT_GOOD, NO_SENSE, 0, 0);
  2470. return res;
  2471. }
  2472. static int nvme_trans_write_buffer(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2473. u8 *cmd)
  2474. {
  2475. int res = SNTI_TRANSLATION_SUCCESS;
  2476. u32 buffer_offset, parm_list_length;
  2477. u8 buffer_id, mode;
  2478. parm_list_length =
  2479. GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_PARM_LIST_LENGTH_OFFSET);
  2480. if (parm_list_length % BYTES_TO_DWORDS != 0) {
  2481. /* NVMe expects Firmware file to be a whole number of DWORDS */
  2482. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2483. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2484. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2485. goto out;
  2486. }
  2487. buffer_id = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_ID_OFFSET);
  2488. if (buffer_id > NVME_MAX_FIRMWARE_SLOT) {
  2489. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2490. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2491. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2492. goto out;
  2493. }
  2494. mode = GET_U8_FROM_CDB(cmd, WRITE_BUFFER_CDB_MODE_OFFSET) &
  2495. WRITE_BUFFER_CDB_MODE_MASK;
  2496. buffer_offset =
  2497. GET_U24_FROM_CDB(cmd, WRITE_BUFFER_CDB_BUFFER_OFFSET_OFFSET);
  2498. switch (mode) {
  2499. case DOWNLOAD_SAVE_ACTIVATE:
  2500. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_download_fw,
  2501. parm_list_length, buffer_offset,
  2502. buffer_id);
  2503. if (res != SNTI_TRANSLATION_SUCCESS)
  2504. goto out;
  2505. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw,
  2506. parm_list_length, buffer_offset,
  2507. buffer_id);
  2508. break;
  2509. case DOWNLOAD_SAVE_DEFER_ACTIVATE:
  2510. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_download_fw,
  2511. parm_list_length, buffer_offset,
  2512. buffer_id);
  2513. break;
  2514. case ACTIVATE_DEFERRED_MICROCODE:
  2515. res = nvme_trans_send_fw_cmd(ns, hdr, nvme_admin_activate_fw,
  2516. parm_list_length, buffer_offset,
  2517. buffer_id);
  2518. break;
  2519. default:
  2520. res = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2521. ILLEGAL_REQUEST, SCSI_ASC_INVALID_CDB,
  2522. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2523. break;
  2524. }
  2525. out:
  2526. return res;
  2527. }
  2528. struct scsi_unmap_blk_desc {
  2529. __be64 slba;
  2530. __be32 nlb;
  2531. u32 resv;
  2532. };
  2533. struct scsi_unmap_parm_list {
  2534. __be16 unmap_data_len;
  2535. __be16 unmap_blk_desc_data_len;
  2536. u32 resv;
  2537. struct scsi_unmap_blk_desc desc[0];
  2538. };
  2539. static int nvme_trans_unmap(struct nvme_ns *ns, struct sg_io_hdr *hdr,
  2540. u8 *cmd)
  2541. {
  2542. struct nvme_dev *dev = ns->dev;
  2543. struct scsi_unmap_parm_list *plist;
  2544. struct nvme_dsm_range *range;
  2545. struct nvme_command c;
  2546. int i, nvme_sc, res = -ENOMEM;
  2547. u16 ndesc, list_len;
  2548. dma_addr_t dma_addr;
  2549. list_len = GET_U16_FROM_CDB(cmd, UNMAP_CDB_PARAM_LIST_LENGTH_OFFSET);
  2550. if (!list_len)
  2551. return -EINVAL;
  2552. plist = kmalloc(list_len, GFP_KERNEL);
  2553. if (!plist)
  2554. return -ENOMEM;
  2555. res = nvme_trans_copy_from_user(hdr, plist, list_len);
  2556. if (res != SNTI_TRANSLATION_SUCCESS)
  2557. goto out;
  2558. ndesc = be16_to_cpu(plist->unmap_blk_desc_data_len) >> 4;
  2559. if (!ndesc || ndesc > 256) {
  2560. res = -EINVAL;
  2561. goto out;
  2562. }
  2563. range = dma_alloc_coherent(&dev->pci_dev->dev, ndesc * sizeof(*range),
  2564. &dma_addr, GFP_KERNEL);
  2565. if (!range)
  2566. goto out;
  2567. for (i = 0; i < ndesc; i++) {
  2568. range[i].nlb = cpu_to_le32(be32_to_cpu(plist->desc[i].nlb));
  2569. range[i].slba = cpu_to_le64(be64_to_cpu(plist->desc[i].slba));
  2570. range[i].cattr = 0;
  2571. }
  2572. memset(&c, 0, sizeof(c));
  2573. c.dsm.opcode = nvme_cmd_dsm;
  2574. c.dsm.nsid = cpu_to_le32(ns->ns_id);
  2575. c.dsm.prp1 = cpu_to_le64(dma_addr);
  2576. c.dsm.nr = cpu_to_le32(ndesc - 1);
  2577. c.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
  2578. nvme_sc = nvme_submit_io_cmd(dev, &c, NULL);
  2579. res = nvme_trans_status_code(hdr, nvme_sc);
  2580. dma_free_coherent(&dev->pci_dev->dev, ndesc * sizeof(*range),
  2581. range, dma_addr);
  2582. out:
  2583. kfree(plist);
  2584. return res;
  2585. }
  2586. static int nvme_scsi_translate(struct nvme_ns *ns, struct sg_io_hdr *hdr)
  2587. {
  2588. u8 cmd[BLK_MAX_CDB];
  2589. int retcode;
  2590. unsigned int opcode;
  2591. if (hdr->cmdp == NULL)
  2592. return -EMSGSIZE;
  2593. if (copy_from_user(cmd, hdr->cmdp, hdr->cmd_len))
  2594. return -EFAULT;
  2595. opcode = cmd[0];
  2596. switch (opcode) {
  2597. case READ_6:
  2598. case READ_10:
  2599. case READ_12:
  2600. case READ_16:
  2601. retcode = nvme_trans_io(ns, hdr, 0, cmd);
  2602. break;
  2603. case WRITE_6:
  2604. case WRITE_10:
  2605. case WRITE_12:
  2606. case WRITE_16:
  2607. retcode = nvme_trans_io(ns, hdr, 1, cmd);
  2608. break;
  2609. case INQUIRY:
  2610. retcode = nvme_trans_inquiry(ns, hdr, cmd);
  2611. break;
  2612. case LOG_SENSE:
  2613. retcode = nvme_trans_log_sense(ns, hdr, cmd);
  2614. break;
  2615. case MODE_SELECT:
  2616. case MODE_SELECT_10:
  2617. retcode = nvme_trans_mode_select(ns, hdr, cmd);
  2618. break;
  2619. case MODE_SENSE:
  2620. case MODE_SENSE_10:
  2621. retcode = nvme_trans_mode_sense(ns, hdr, cmd);
  2622. break;
  2623. case READ_CAPACITY:
  2624. retcode = nvme_trans_read_capacity(ns, hdr, cmd);
  2625. break;
  2626. case SERVICE_ACTION_IN:
  2627. if (IS_READ_CAP_16(cmd))
  2628. retcode = nvme_trans_read_capacity(ns, hdr, cmd);
  2629. else
  2630. goto out;
  2631. break;
  2632. case REPORT_LUNS:
  2633. retcode = nvme_trans_report_luns(ns, hdr, cmd);
  2634. break;
  2635. case REQUEST_SENSE:
  2636. retcode = nvme_trans_request_sense(ns, hdr, cmd);
  2637. break;
  2638. case SECURITY_PROTOCOL_IN:
  2639. case SECURITY_PROTOCOL_OUT:
  2640. retcode = nvme_trans_security_protocol(ns, hdr, cmd);
  2641. break;
  2642. case START_STOP:
  2643. retcode = nvme_trans_start_stop(ns, hdr, cmd);
  2644. break;
  2645. case SYNCHRONIZE_CACHE:
  2646. retcode = nvme_trans_synchronize_cache(ns, hdr, cmd);
  2647. break;
  2648. case FORMAT_UNIT:
  2649. retcode = nvme_trans_format_unit(ns, hdr, cmd);
  2650. break;
  2651. case TEST_UNIT_READY:
  2652. retcode = nvme_trans_test_unit_ready(ns, hdr, cmd);
  2653. break;
  2654. case WRITE_BUFFER:
  2655. retcode = nvme_trans_write_buffer(ns, hdr, cmd);
  2656. break;
  2657. case UNMAP:
  2658. retcode = nvme_trans_unmap(ns, hdr, cmd);
  2659. break;
  2660. default:
  2661. out:
  2662. retcode = nvme_trans_completion(hdr, SAM_STAT_CHECK_CONDITION,
  2663. ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_COMMAND,
  2664. SCSI_ASCQ_CAUSE_NOT_REPORTABLE);
  2665. break;
  2666. }
  2667. return retcode;
  2668. }
  2669. int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr)
  2670. {
  2671. struct sg_io_hdr hdr;
  2672. int retcode;
  2673. if (!capable(CAP_SYS_ADMIN))
  2674. return -EACCES;
  2675. if (copy_from_user(&hdr, u_hdr, sizeof(hdr)))
  2676. return -EFAULT;
  2677. if (hdr.interface_id != 'S')
  2678. return -EINVAL;
  2679. if (hdr.cmd_len > BLK_MAX_CDB)
  2680. return -EINVAL;
  2681. retcode = nvme_scsi_translate(ns, &hdr);
  2682. if (retcode < 0)
  2683. return retcode;
  2684. if (retcode > 0)
  2685. retcode = SNTI_TRANSLATION_SUCCESS;
  2686. if (copy_to_user(u_hdr, &hdr, sizeof(sg_io_hdr_t)) > 0)
  2687. return -EFAULT;
  2688. return retcode;
  2689. }
  2690. #ifdef CONFIG_COMPAT
  2691. typedef struct sg_io_hdr32 {
  2692. compat_int_t interface_id; /* [i] 'S' for SCSI generic (required) */
  2693. compat_int_t dxfer_direction; /* [i] data transfer direction */
  2694. unsigned char cmd_len; /* [i] SCSI command length ( <= 16 bytes) */
  2695. unsigned char mx_sb_len; /* [i] max length to write to sbp */
  2696. unsigned short iovec_count; /* [i] 0 implies no scatter gather */
  2697. compat_uint_t dxfer_len; /* [i] byte count of data transfer */
  2698. compat_uint_t dxferp; /* [i], [*io] points to data transfer memory
  2699. or scatter gather list */
  2700. compat_uptr_t cmdp; /* [i], [*i] points to command to perform */
  2701. compat_uptr_t sbp; /* [i], [*o] points to sense_buffer memory */
  2702. compat_uint_t timeout; /* [i] MAX_UINT->no timeout (unit: millisec) */
  2703. compat_uint_t flags; /* [i] 0 -> default, see SG_FLAG... */
  2704. compat_int_t pack_id; /* [i->o] unused internally (normally) */
  2705. compat_uptr_t usr_ptr; /* [i->o] unused internally */
  2706. unsigned char status; /* [o] scsi status */
  2707. unsigned char masked_status; /* [o] shifted, masked scsi status */
  2708. unsigned char msg_status; /* [o] messaging level data (optional) */
  2709. unsigned char sb_len_wr; /* [o] byte count actually written to sbp */
  2710. unsigned short host_status; /* [o] errors from host adapter */
  2711. unsigned short driver_status; /* [o] errors from software driver */
  2712. compat_int_t resid; /* [o] dxfer_len - actual_transferred */
  2713. compat_uint_t duration; /* [o] time taken by cmd (unit: millisec) */
  2714. compat_uint_t info; /* [o] auxiliary information */
  2715. } sg_io_hdr32_t; /* 64 bytes long (on sparc32) */
  2716. typedef struct sg_iovec32 {
  2717. compat_uint_t iov_base;
  2718. compat_uint_t iov_len;
  2719. } sg_iovec32_t;
  2720. static int sg_build_iovec(sg_io_hdr_t __user *sgio, void __user *dxferp, u16 iovec_count)
  2721. {
  2722. sg_iovec_t __user *iov = (sg_iovec_t __user *) (sgio + 1);
  2723. sg_iovec32_t __user *iov32 = dxferp;
  2724. int i;
  2725. for (i = 0; i < iovec_count; i++) {
  2726. u32 base, len;
  2727. if (get_user(base, &iov32[i].iov_base) ||
  2728. get_user(len, &iov32[i].iov_len) ||
  2729. put_user(compat_ptr(base), &iov[i].iov_base) ||
  2730. put_user(len, &iov[i].iov_len))
  2731. return -EFAULT;
  2732. }
  2733. if (put_user(iov, &sgio->dxferp))
  2734. return -EFAULT;
  2735. return 0;
  2736. }
  2737. int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg)
  2738. {
  2739. sg_io_hdr32_t __user *sgio32 = (sg_io_hdr32_t __user *)arg;
  2740. sg_io_hdr_t __user *sgio;
  2741. u16 iovec_count;
  2742. u32 data;
  2743. void __user *dxferp;
  2744. int err;
  2745. int interface_id;
  2746. if (get_user(interface_id, &sgio32->interface_id))
  2747. return -EFAULT;
  2748. if (interface_id != 'S')
  2749. return -EINVAL;
  2750. if (get_user(iovec_count, &sgio32->iovec_count))
  2751. return -EFAULT;
  2752. {
  2753. void __user *top = compat_alloc_user_space(0);
  2754. void __user *new = compat_alloc_user_space(sizeof(sg_io_hdr_t) +
  2755. (iovec_count * sizeof(sg_iovec_t)));
  2756. if (new > top)
  2757. return -EINVAL;
  2758. sgio = new;
  2759. }
  2760. /* Ok, now construct. */
  2761. if (copy_in_user(&sgio->interface_id, &sgio32->interface_id,
  2762. (2 * sizeof(int)) +
  2763. (2 * sizeof(unsigned char)) +
  2764. (1 * sizeof(unsigned short)) +
  2765. (1 * sizeof(unsigned int))))
  2766. return -EFAULT;
  2767. if (get_user(data, &sgio32->dxferp))
  2768. return -EFAULT;
  2769. dxferp = compat_ptr(data);
  2770. if (iovec_count) {
  2771. if (sg_build_iovec(sgio, dxferp, iovec_count))
  2772. return -EFAULT;
  2773. } else {
  2774. if (put_user(dxferp, &sgio->dxferp))
  2775. return -EFAULT;
  2776. }
  2777. {
  2778. unsigned char __user *cmdp;
  2779. unsigned char __user *sbp;
  2780. if (get_user(data, &sgio32->cmdp))
  2781. return -EFAULT;
  2782. cmdp = compat_ptr(data);
  2783. if (get_user(data, &sgio32->sbp))
  2784. return -EFAULT;
  2785. sbp = compat_ptr(data);
  2786. if (put_user(cmdp, &sgio->cmdp) ||
  2787. put_user(sbp, &sgio->sbp))
  2788. return -EFAULT;
  2789. }
  2790. if (copy_in_user(&sgio->timeout, &sgio32->timeout,
  2791. 3 * sizeof(int)))
  2792. return -EFAULT;
  2793. if (get_user(data, &sgio32->usr_ptr))
  2794. return -EFAULT;
  2795. if (put_user(compat_ptr(data), &sgio->usr_ptr))
  2796. return -EFAULT;
  2797. err = nvme_sg_io(ns, sgio);
  2798. if (err >= 0) {
  2799. void __user *datap;
  2800. if (copy_in_user(&sgio32->pack_id, &sgio->pack_id,
  2801. sizeof(int)) ||
  2802. get_user(datap, &sgio->usr_ptr) ||
  2803. put_user((u32)(unsigned long)datap,
  2804. &sgio32->usr_ptr) ||
  2805. copy_in_user(&sgio32->status, &sgio->status,
  2806. (4 * sizeof(unsigned char)) +
  2807. (2 * sizeof(unsigned short)) +
  2808. (3 * sizeof(int))))
  2809. err = -EFAULT;
  2810. }
  2811. return err;
  2812. }
  2813. #endif
  2814. int nvme_sg_get_version_num(int __user *ip)
  2815. {
  2816. return put_user(sg_version_num, ip);
  2817. }