cx23885-dvb.c 51 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/device.h>
  20. #include <linux/fs.h>
  21. #include <linux/kthread.h>
  22. #include <linux/file.h>
  23. #include <linux/suspend.h>
  24. #include "cx23885.h"
  25. #include <media/v4l2-common.h>
  26. #include "dvb_ca_en50221.h"
  27. #include "s5h1409.h"
  28. #include "s5h1411.h"
  29. #include "mt2131.h"
  30. #include "tda8290.h"
  31. #include "tda18271.h"
  32. #include "lgdt330x.h"
  33. #include "xc4000.h"
  34. #include "xc5000.h"
  35. #include "max2165.h"
  36. #include "tda10048.h"
  37. #include "tuner-xc2028.h"
  38. #include "tuner-simple.h"
  39. #include "dib7000p.h"
  40. #include "dib0070.h"
  41. #include "dibx000_common.h"
  42. #include "zl10353.h"
  43. #include "stv0900.h"
  44. #include "stv0900_reg.h"
  45. #include "stv6110.h"
  46. #include "lnbh24.h"
  47. #include "cx24116.h"
  48. #include "cx24117.h"
  49. #include "cimax2.h"
  50. #include "lgs8gxx.h"
  51. #include "netup-eeprom.h"
  52. #include "netup-init.h"
  53. #include "lgdt3305.h"
  54. #include "atbm8830.h"
  55. #include "ts2020.h"
  56. #include "ds3000.h"
  57. #include "cx23885-f300.h"
  58. #include "altera-ci.h"
  59. #include "stv0367.h"
  60. #include "drxk.h"
  61. #include "mt2063.h"
  62. #include "stv090x.h"
  63. #include "stb6100.h"
  64. #include "stb6100_cfg.h"
  65. #include "tda10071.h"
  66. #include "a8293.h"
  67. #include "mb86a20s.h"
  68. #include "si2165.h"
  69. #include "si2168.h"
  70. #include "si2157.h"
  71. #include "m88ds3103.h"
  72. #include "m88ts2022.h"
  73. static unsigned int debug;
  74. #define dprintk(level, fmt, arg...)\
  75. do { if (debug >= level)\
  76. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  77. } while (0)
  78. /* ------------------------------------------------------------------ */
  79. static unsigned int alt_tuner;
  80. module_param(alt_tuner, int, 0644);
  81. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  82. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  83. /* ------------------------------------------------------------------ */
  84. static int queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
  85. unsigned int *num_buffers, unsigned int *num_planes,
  86. unsigned int sizes[], void *alloc_ctxs[])
  87. {
  88. struct cx23885_tsport *port = q->drv_priv;
  89. port->ts_packet_size = 188 * 4;
  90. port->ts_packet_count = 32;
  91. *num_planes = 1;
  92. sizes[0] = port->ts_packet_size * port->ts_packet_count;
  93. *num_buffers = 32;
  94. return 0;
  95. }
  96. static int buffer_prepare(struct vb2_buffer *vb)
  97. {
  98. struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
  99. struct cx23885_buffer *buf =
  100. container_of(vb, struct cx23885_buffer, vb);
  101. return cx23885_buf_prepare(buf, port);
  102. }
  103. static void buffer_finish(struct vb2_buffer *vb)
  104. {
  105. struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
  106. struct cx23885_dev *dev = port->dev;
  107. struct cx23885_buffer *buf = container_of(vb,
  108. struct cx23885_buffer, vb);
  109. struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
  110. cx23885_free_buffer(dev, buf);
  111. dma_unmap_sg(&dev->pci->dev, sgt->sgl, sgt->nents, DMA_FROM_DEVICE);
  112. }
  113. static void buffer_queue(struct vb2_buffer *vb)
  114. {
  115. struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
  116. struct cx23885_buffer *buf = container_of(vb,
  117. struct cx23885_buffer, vb);
  118. cx23885_buf_queue(port, buf);
  119. }
  120. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  121. {
  122. struct vb2_dvb_frontends *f;
  123. struct vb2_dvb_frontend *fe;
  124. f = &port->frontends;
  125. if (f->gate <= 1) /* undefined or fe0 */
  126. fe = vb2_dvb_get_frontend(f, 1);
  127. else
  128. fe = vb2_dvb_get_frontend(f, f->gate);
  129. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  130. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  131. }
  132. static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
  133. {
  134. struct cx23885_tsport *port = q->drv_priv;
  135. struct cx23885_dmaqueue *dmaq = &port->mpegq;
  136. struct cx23885_buffer *buf = list_entry(dmaq->active.next,
  137. struct cx23885_buffer, queue);
  138. cx23885_start_dma(port, dmaq, buf);
  139. return 0;
  140. }
  141. static void cx23885_stop_streaming(struct vb2_queue *q)
  142. {
  143. struct cx23885_tsport *port = q->drv_priv;
  144. cx23885_cancel_buffers(port);
  145. }
  146. static struct vb2_ops dvb_qops = {
  147. .queue_setup = queue_setup,
  148. .buf_prepare = buffer_prepare,
  149. .buf_finish = buffer_finish,
  150. .buf_queue = buffer_queue,
  151. .wait_prepare = vb2_ops_wait_prepare,
  152. .wait_finish = vb2_ops_wait_finish,
  153. .start_streaming = cx23885_start_streaming,
  154. .stop_streaming = cx23885_stop_streaming,
  155. };
  156. static struct s5h1409_config hauppauge_generic_config = {
  157. .demod_address = 0x32 >> 1,
  158. .output_mode = S5H1409_SERIAL_OUTPUT,
  159. .gpio = S5H1409_GPIO_ON,
  160. .qam_if = 44000,
  161. .inversion = S5H1409_INVERSION_OFF,
  162. .status_mode = S5H1409_DEMODLOCKING,
  163. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  164. };
  165. static struct tda10048_config hauppauge_hvr1200_config = {
  166. .demod_address = 0x10 >> 1,
  167. .output_mode = TDA10048_SERIAL_OUTPUT,
  168. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  169. .inversion = TDA10048_INVERSION_ON,
  170. .dtv6_if_freq_khz = TDA10048_IF_3300,
  171. .dtv7_if_freq_khz = TDA10048_IF_3800,
  172. .dtv8_if_freq_khz = TDA10048_IF_4300,
  173. .clk_freq_khz = TDA10048_CLK_16000,
  174. };
  175. static struct tda10048_config hauppauge_hvr1210_config = {
  176. .demod_address = 0x10 >> 1,
  177. .output_mode = TDA10048_SERIAL_OUTPUT,
  178. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  179. .inversion = TDA10048_INVERSION_ON,
  180. .dtv6_if_freq_khz = TDA10048_IF_3300,
  181. .dtv7_if_freq_khz = TDA10048_IF_3500,
  182. .dtv8_if_freq_khz = TDA10048_IF_4000,
  183. .clk_freq_khz = TDA10048_CLK_16000,
  184. };
  185. static struct s5h1409_config hauppauge_ezqam_config = {
  186. .demod_address = 0x32 >> 1,
  187. .output_mode = S5H1409_SERIAL_OUTPUT,
  188. .gpio = S5H1409_GPIO_OFF,
  189. .qam_if = 4000,
  190. .inversion = S5H1409_INVERSION_ON,
  191. .status_mode = S5H1409_DEMODLOCKING,
  192. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  193. };
  194. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  195. .demod_address = 0x32 >> 1,
  196. .output_mode = S5H1409_SERIAL_OUTPUT,
  197. .gpio = S5H1409_GPIO_OFF,
  198. .qam_if = 44000,
  199. .inversion = S5H1409_INVERSION_OFF,
  200. .status_mode = S5H1409_DEMODLOCKING,
  201. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  202. };
  203. static struct s5h1409_config hauppauge_hvr1500_config = {
  204. .demod_address = 0x32 >> 1,
  205. .output_mode = S5H1409_SERIAL_OUTPUT,
  206. .gpio = S5H1409_GPIO_OFF,
  207. .inversion = S5H1409_INVERSION_OFF,
  208. .status_mode = S5H1409_DEMODLOCKING,
  209. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  210. };
  211. static struct mt2131_config hauppauge_generic_tunerconfig = {
  212. 0x61
  213. };
  214. static struct lgdt330x_config fusionhdtv_5_express = {
  215. .demod_address = 0x0e,
  216. .demod_chip = LGDT3303,
  217. .serial_mpeg = 0x40,
  218. };
  219. static struct s5h1409_config hauppauge_hvr1500q_config = {
  220. .demod_address = 0x32 >> 1,
  221. .output_mode = S5H1409_SERIAL_OUTPUT,
  222. .gpio = S5H1409_GPIO_ON,
  223. .qam_if = 44000,
  224. .inversion = S5H1409_INVERSION_OFF,
  225. .status_mode = S5H1409_DEMODLOCKING,
  226. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  227. };
  228. static struct s5h1409_config dvico_s5h1409_config = {
  229. .demod_address = 0x32 >> 1,
  230. .output_mode = S5H1409_SERIAL_OUTPUT,
  231. .gpio = S5H1409_GPIO_ON,
  232. .qam_if = 44000,
  233. .inversion = S5H1409_INVERSION_OFF,
  234. .status_mode = S5H1409_DEMODLOCKING,
  235. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  236. };
  237. static struct s5h1411_config dvico_s5h1411_config = {
  238. .output_mode = S5H1411_SERIAL_OUTPUT,
  239. .gpio = S5H1411_GPIO_ON,
  240. .qam_if = S5H1411_IF_44000,
  241. .vsb_if = S5H1411_IF_44000,
  242. .inversion = S5H1411_INVERSION_OFF,
  243. .status_mode = S5H1411_DEMODLOCKING,
  244. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  245. };
  246. static struct s5h1411_config hcw_s5h1411_config = {
  247. .output_mode = S5H1411_SERIAL_OUTPUT,
  248. .gpio = S5H1411_GPIO_OFF,
  249. .vsb_if = S5H1411_IF_44000,
  250. .qam_if = S5H1411_IF_4000,
  251. .inversion = S5H1411_INVERSION_ON,
  252. .status_mode = S5H1411_DEMODLOCKING,
  253. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  254. };
  255. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  256. .i2c_address = 0x61,
  257. .if_khz = 5380,
  258. };
  259. static struct xc5000_config dvico_xc5000_tunerconfig = {
  260. .i2c_address = 0x64,
  261. .if_khz = 5380,
  262. };
  263. static struct tda829x_config tda829x_no_probe = {
  264. .probe_tuner = TDA829X_DONT_PROBE,
  265. };
  266. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  267. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  268. .if_lvl = 6, .rfagc_top = 0x37 },
  269. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  270. .if_lvl = 6, .rfagc_top = 0x37 },
  271. };
  272. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  273. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  274. .if_lvl = 1, .rfagc_top = 0x37, },
  275. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  276. .if_lvl = 1, .rfagc_top = 0x37, },
  277. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  278. .if_lvl = 1, .rfagc_top = 0x37, },
  279. };
  280. static struct tda18271_config hauppauge_tda18271_config = {
  281. .std_map = &hauppauge_tda18271_std_map,
  282. .gate = TDA18271_GATE_ANALOG,
  283. .output_opt = TDA18271_OUTPUT_LT_OFF,
  284. };
  285. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  286. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  287. .gate = TDA18271_GATE_ANALOG,
  288. .output_opt = TDA18271_OUTPUT_LT_OFF,
  289. };
  290. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  291. .gate = TDA18271_GATE_DIGITAL,
  292. .output_opt = TDA18271_OUTPUT_LT_OFF,
  293. };
  294. static struct tda18271_config hauppauge_hvr4400_tuner_config = {
  295. .gate = TDA18271_GATE_DIGITAL,
  296. .output_opt = TDA18271_OUTPUT_LT_OFF,
  297. };
  298. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  299. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  300. .if_lvl = 1, .rfagc_top = 0x58 },
  301. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  302. .if_lvl = 1, .rfagc_top = 0x58 },
  303. };
  304. static struct tda18271_config hauppauge_hvr127x_config = {
  305. .std_map = &hauppauge_hvr127x_std_map,
  306. .output_opt = TDA18271_OUTPUT_LT_OFF,
  307. };
  308. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  309. .i2c_addr = 0x0e,
  310. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  311. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  312. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  313. .deny_i2c_rptr = 1,
  314. .spectral_inversion = 1,
  315. .qam_if_khz = 4000,
  316. .vsb_if_khz = 3250,
  317. };
  318. static struct dibx000_agc_config xc3028_agc_config = {
  319. BAND_VHF | BAND_UHF, /* band_caps */
  320. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  321. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  322. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  323. * P_agc_nb_est=2, P_agc_write=0
  324. */
  325. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  326. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  327. 712, /* inv_gain */
  328. 21, /* time_stabiliz */
  329. 0, /* alpha_level */
  330. 118, /* thlock */
  331. 0, /* wbd_inv */
  332. 2867, /* wbd_ref */
  333. 0, /* wbd_sel */
  334. 2, /* wbd_alpha */
  335. 0, /* agc1_max */
  336. 0, /* agc1_min */
  337. 39718, /* agc2_max */
  338. 9930, /* agc2_min */
  339. 0, /* agc1_pt1 */
  340. 0, /* agc1_pt2 */
  341. 0, /* agc1_pt3 */
  342. 0, /* agc1_slope1 */
  343. 0, /* agc1_slope2 */
  344. 0, /* agc2_pt1 */
  345. 128, /* agc2_pt2 */
  346. 29, /* agc2_slope1 */
  347. 29, /* agc2_slope2 */
  348. 17, /* alpha_mant */
  349. 27, /* alpha_exp */
  350. 23, /* beta_mant */
  351. 51, /* beta_exp */
  352. 1, /* perform_agc_softsplit */
  353. };
  354. /* PLL Configuration for COFDM BW_MHz = 8.000000
  355. * With external clock = 30.000000 */
  356. static struct dibx000_bandwidth_config xc3028_bw_config = {
  357. 60000, /* internal */
  358. 30000, /* sampling */
  359. 1, /* pll_cfg: prediv */
  360. 8, /* pll_cfg: ratio */
  361. 3, /* pll_cfg: range */
  362. 1, /* pll_cfg: reset */
  363. 0, /* pll_cfg: bypass */
  364. 0, /* misc: refdiv */
  365. 0, /* misc: bypclk_div */
  366. 1, /* misc: IO_CLK_en_core */
  367. 1, /* misc: ADClkSrc */
  368. 0, /* misc: modulo */
  369. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  370. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  371. 20452225, /* timf */
  372. 30000000 /* xtal_hz */
  373. };
  374. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  375. .output_mpeg2_in_188_bytes = 1,
  376. .hostbus_diversity = 1,
  377. .tuner_is_baseband = 0,
  378. .update_lna = NULL,
  379. .agc_config_count = 1,
  380. .agc = &xc3028_agc_config,
  381. .bw = &xc3028_bw_config,
  382. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  383. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  384. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  385. .pwm_freq_div = 0,
  386. .agc_control = NULL,
  387. .spur_protect = 0,
  388. .output_mode = OUTMODE_MPEG2_SERIAL,
  389. };
  390. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  391. .demod_address = 0x0f,
  392. .if2 = 45600,
  393. .no_tuner = 1,
  394. .disable_i2c_gate_ctrl = 1,
  395. };
  396. static struct stv0900_reg stv0900_ts_regs[] = {
  397. { R0900_TSGENERAL, 0x00 },
  398. { R0900_P1_TSSPEED, 0x40 },
  399. { R0900_P2_TSSPEED, 0x40 },
  400. { R0900_P1_TSCFGM, 0xc0 },
  401. { R0900_P2_TSCFGM, 0xc0 },
  402. { R0900_P1_TSCFGH, 0xe0 },
  403. { R0900_P2_TSCFGH, 0xe0 },
  404. { R0900_P1_TSCFGL, 0x20 },
  405. { R0900_P2_TSCFGL, 0x20 },
  406. { 0xffff, 0xff }, /* terminate */
  407. };
  408. static struct stv0900_config netup_stv0900_config = {
  409. .demod_address = 0x68,
  410. .demod_mode = 1, /* dual */
  411. .xtal = 8000000,
  412. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  413. .diseqc_mode = 2,/* 2/3 PWM */
  414. .ts_config_regs = stv0900_ts_regs,
  415. .tun1_maddress = 0,/* 0x60 */
  416. .tun2_maddress = 3,/* 0x63 */
  417. .tun1_adc = 1,/* 1 Vpp */
  418. .tun2_adc = 1,/* 1 Vpp */
  419. };
  420. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  421. .i2c_address = 0x60,
  422. .mclk = 16000000,
  423. .clk_div = 1,
  424. .gain = 8, /* +16 dB - maximum gain */
  425. };
  426. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  427. .i2c_address = 0x63,
  428. .mclk = 16000000,
  429. .clk_div = 1,
  430. .gain = 8, /* +16 dB - maximum gain */
  431. };
  432. static struct cx24116_config tbs_cx24116_config = {
  433. .demod_address = 0x55,
  434. };
  435. static struct cx24117_config tbs_cx24117_config = {
  436. .demod_address = 0x55,
  437. };
  438. static struct ds3000_config tevii_ds3000_config = {
  439. .demod_address = 0x68,
  440. };
  441. static struct ts2020_config tevii_ts2020_config = {
  442. .tuner_address = 0x60,
  443. .clk_out_div = 1,
  444. .frequency_div = 1146000,
  445. };
  446. static struct cx24116_config dvbworld_cx24116_config = {
  447. .demod_address = 0x05,
  448. };
  449. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  450. .prod = LGS8GXX_PROD_LGS8GL5,
  451. .demod_address = 0x19,
  452. .serial_ts = 0,
  453. .ts_clk_pol = 1,
  454. .ts_clk_gated = 1,
  455. .if_clk_freq = 30400, /* 30.4 MHz */
  456. .if_freq = 5380, /* 5.38 MHz */
  457. .if_neg_center = 1,
  458. .ext_adc = 0,
  459. .adc_signed = 0,
  460. .if_neg_edge = 0,
  461. };
  462. static struct xc5000_config mygica_x8506_xc5000_config = {
  463. .i2c_address = 0x61,
  464. .if_khz = 5380,
  465. };
  466. static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
  467. .demod_address = 0x10,
  468. };
  469. static struct xc5000_config mygica_x8507_xc5000_config = {
  470. .i2c_address = 0x61,
  471. .if_khz = 4000,
  472. };
  473. static struct stv090x_config prof_8000_stv090x_config = {
  474. .device = STV0903,
  475. .demod_mode = STV090x_SINGLE,
  476. .clk_mode = STV090x_CLK_EXT,
  477. .xtal = 27000000,
  478. .address = 0x6A,
  479. .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
  480. .repeater_level = STV090x_RPTLEVEL_64,
  481. .adc1_range = STV090x_ADC_2Vpp,
  482. .diseqc_envelope_mode = false,
  483. .tuner_get_frequency = stb6100_get_frequency,
  484. .tuner_set_frequency = stb6100_set_frequency,
  485. .tuner_set_bandwidth = stb6100_set_bandwidth,
  486. .tuner_get_bandwidth = stb6100_get_bandwidth,
  487. };
  488. static struct stb6100_config prof_8000_stb6100_config = {
  489. .tuner_address = 0x60,
  490. .refclock = 27000000,
  491. };
  492. static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  493. {
  494. struct cx23885_tsport *port = fe->dvb->priv;
  495. struct cx23885_dev *dev = port->dev;
  496. if (voltage == SEC_VOLTAGE_18)
  497. cx_write(MC417_RWD, 0x00001e00);
  498. else if (voltage == SEC_VOLTAGE_13)
  499. cx_write(MC417_RWD, 0x00001a00);
  500. else
  501. cx_write(MC417_RWD, 0x00001800);
  502. return 0;
  503. }
  504. static int dvbsky_t9580_set_voltage(struct dvb_frontend *fe,
  505. fe_sec_voltage_t voltage)
  506. {
  507. struct cx23885_tsport *port = fe->dvb->priv;
  508. struct cx23885_dev *dev = port->dev;
  509. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  510. switch (voltage) {
  511. case SEC_VOLTAGE_13:
  512. cx23885_gpio_set(dev, GPIO_1);
  513. cx23885_gpio_clear(dev, GPIO_0);
  514. break;
  515. case SEC_VOLTAGE_18:
  516. cx23885_gpio_set(dev, GPIO_1);
  517. cx23885_gpio_set(dev, GPIO_0);
  518. break;
  519. case SEC_VOLTAGE_OFF:
  520. cx23885_gpio_clear(dev, GPIO_1);
  521. cx23885_gpio_clear(dev, GPIO_0);
  522. break;
  523. }
  524. /* call the frontend set_voltage function */
  525. port->fe_set_voltage(fe, voltage);
  526. return 0;
  527. }
  528. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
  529. {
  530. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  531. struct cx23885_tsport *port = fe->dvb->priv;
  532. struct cx23885_dev *dev = port->dev;
  533. switch (dev->board) {
  534. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  535. switch (p->modulation) {
  536. case VSB_8:
  537. cx23885_gpio_clear(dev, GPIO_5);
  538. break;
  539. case QAM_64:
  540. case QAM_256:
  541. default:
  542. cx23885_gpio_set(dev, GPIO_5);
  543. break;
  544. }
  545. break;
  546. case CX23885_BOARD_MYGICA_X8506:
  547. case CX23885_BOARD_MYGICA_X8507:
  548. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  549. /* Select Digital TV */
  550. cx23885_gpio_set(dev, GPIO_0);
  551. break;
  552. }
  553. /* Call the real set_frontend */
  554. if (port->set_frontend)
  555. return port->set_frontend(fe);
  556. return 0;
  557. }
  558. static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
  559. struct dvb_frontend *fe)
  560. {
  561. port->set_frontend = fe->ops.set_frontend;
  562. fe->ops.set_frontend = cx23885_dvb_set_frontend;
  563. }
  564. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  565. .prod = LGS8GXX_PROD_LGS8G75,
  566. .demod_address = 0x19,
  567. .serial_ts = 0,
  568. .ts_clk_pol = 1,
  569. .ts_clk_gated = 1,
  570. .if_clk_freq = 30400, /* 30.4 MHz */
  571. .if_freq = 6500, /* 6.50 MHz */
  572. .if_neg_center = 1,
  573. .ext_adc = 0,
  574. .adc_signed = 1,
  575. .adc_vpp = 2, /* 1.6 Vpp */
  576. .if_neg_edge = 1,
  577. };
  578. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  579. .i2c_address = 0x61,
  580. .if_khz = 6500,
  581. };
  582. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  583. .prod = ATBM8830_PROD_8830,
  584. .demod_address = 0x44,
  585. .serial_ts = 0,
  586. .ts_sampling_edge = 1,
  587. .ts_clk_gated = 0,
  588. .osc_clk_freq = 30400, /* in kHz */
  589. .if_freq = 0, /* zero IF */
  590. .zif_swap_iq = 1,
  591. .agc_min = 0x2E,
  592. .agc_max = 0xFF,
  593. .agc_hold_loop = 0,
  594. };
  595. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  596. .i2c_address = 0x60,
  597. .osc_clk = 20
  598. };
  599. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  600. .prod = ATBM8830_PROD_8830,
  601. .demod_address = 0x44,
  602. .serial_ts = 1,
  603. .ts_sampling_edge = 1,
  604. .ts_clk_gated = 0,
  605. .osc_clk_freq = 30400, /* in kHz */
  606. .if_freq = 0, /* zero IF */
  607. .zif_swap_iq = 1,
  608. .agc_min = 0x2E,
  609. .agc_max = 0xFF,
  610. .agc_hold_loop = 0,
  611. };
  612. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  613. .i2c_address = 0x60,
  614. .osc_clk = 20
  615. };
  616. static struct stv0367_config netup_stv0367_config[] = {
  617. {
  618. .demod_address = 0x1c,
  619. .xtal = 27000000,
  620. .if_khz = 4500,
  621. .if_iq_mode = 0,
  622. .ts_mode = 1,
  623. .clk_pol = 0,
  624. }, {
  625. .demod_address = 0x1d,
  626. .xtal = 27000000,
  627. .if_khz = 4500,
  628. .if_iq_mode = 0,
  629. .ts_mode = 1,
  630. .clk_pol = 0,
  631. },
  632. };
  633. static struct xc5000_config netup_xc5000_config[] = {
  634. {
  635. .i2c_address = 0x61,
  636. .if_khz = 4500,
  637. }, {
  638. .i2c_address = 0x64,
  639. .if_khz = 4500,
  640. },
  641. };
  642. static struct drxk_config terratec_drxk_config[] = {
  643. {
  644. .adr = 0x29,
  645. .no_i2c_bridge = 1,
  646. }, {
  647. .adr = 0x2a,
  648. .no_i2c_bridge = 1,
  649. },
  650. };
  651. static struct mt2063_config terratec_mt2063_config[] = {
  652. {
  653. .tuner_address = 0x60,
  654. }, {
  655. .tuner_address = 0x67,
  656. },
  657. };
  658. static const struct tda10071_config hauppauge_tda10071_config = {
  659. .demod_i2c_addr = 0x05,
  660. .tuner_i2c_addr = 0x54,
  661. .i2c_wr_max = 64,
  662. .ts_mode = TDA10071_TS_SERIAL,
  663. .spec_inv = 0,
  664. .xtal = 40444000, /* 40.444 MHz */
  665. .pll_multiplier = 20,
  666. };
  667. static const struct a8293_config hauppauge_a8293_config = {
  668. .i2c_addr = 0x0b,
  669. };
  670. static const struct si2165_config hauppauge_hvr4400_si2165_config = {
  671. .i2c_addr = 0x64,
  672. .chip_mode = SI2165_MODE_PLL_XTAL,
  673. .ref_freq_Hz = 16000000,
  674. };
  675. static const struct m88ds3103_config dvbsky_t9580_m88ds3103_config = {
  676. .i2c_addr = 0x68,
  677. .clock = 27000000,
  678. .i2c_wr_max = 33,
  679. .clock_out = 0,
  680. .ts_mode = M88DS3103_TS_PARALLEL,
  681. .ts_clk = 16000,
  682. .ts_clk_pol = 1,
  683. .lnb_en_pol = 1,
  684. .lnb_hv_pol = 0,
  685. .agc = 0x99,
  686. };
  687. static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  688. {
  689. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  690. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  691. uint32_t mem = 0;
  692. mem = cx_read(MC417_RWD);
  693. if (read)
  694. cx_set(MC417_OEN, ALT_DATA);
  695. else {
  696. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  697. mem &= ~ALT_DATA;
  698. mem |= (data & ALT_DATA);
  699. }
  700. if (flag)
  701. mem |= ALT_AD_RG;
  702. else
  703. mem &= ~ALT_AD_RG;
  704. mem &= ~ALT_CS;
  705. if (read)
  706. mem = (mem & ~ALT_RD) | ALT_WR;
  707. else
  708. mem = (mem & ~ALT_WR) | ALT_RD;
  709. cx_write(MC417_RWD, mem); /* start RW cycle */
  710. for (;;) {
  711. mem = cx_read(MC417_RWD);
  712. if ((mem & ALT_RDY) == 0)
  713. break;
  714. if (time_after(jiffies, timeout))
  715. break;
  716. udelay(1);
  717. }
  718. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  719. if (read)
  720. return mem & ALT_DATA;
  721. return 0;
  722. };
  723. static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
  724. {
  725. struct dib7000p_ops *dib7000p_ops = fe->sec_priv;
  726. return dib7000p_ops->set_gpio(fe, 8, 0, !onoff);
  727. }
  728. static int dib7070_tuner_sleep(struct dvb_frontend *fe, int onoff)
  729. {
  730. return 0;
  731. }
  732. static struct dib0070_config dib7070p_dib0070_config = {
  733. .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
  734. .reset = dib7070_tuner_reset,
  735. .sleep = dib7070_tuner_sleep,
  736. .clock_khz = 12000,
  737. .freq_offset_khz_vhf = 550,
  738. /* .flip_chip = 1, */
  739. };
  740. /* DIB7070 generic */
  741. static struct dibx000_agc_config dib7070_agc_config = {
  742. .band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
  743. /*
  744. * P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5,
  745. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
  746. * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0
  747. */
  748. .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) |
  749. (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
  750. .inv_gain = 600,
  751. .time_stabiliz = 10,
  752. .alpha_level = 0,
  753. .thlock = 118,
  754. .wbd_inv = 0,
  755. .wbd_ref = 3530,
  756. .wbd_sel = 1,
  757. .wbd_alpha = 5,
  758. .agc1_max = 65535,
  759. .agc1_min = 0,
  760. .agc2_max = 65535,
  761. .agc2_min = 0,
  762. .agc1_pt1 = 0,
  763. .agc1_pt2 = 40,
  764. .agc1_pt3 = 183,
  765. .agc1_slope1 = 206,
  766. .agc1_slope2 = 255,
  767. .agc2_pt1 = 72,
  768. .agc2_pt2 = 152,
  769. .agc2_slope1 = 88,
  770. .agc2_slope2 = 90,
  771. .alpha_mant = 17,
  772. .alpha_exp = 27,
  773. .beta_mant = 23,
  774. .beta_exp = 51,
  775. .perform_agc_softsplit = 0,
  776. };
  777. static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
  778. .internal = 60000,
  779. .sampling = 15000,
  780. .pll_prediv = 1,
  781. .pll_ratio = 20,
  782. .pll_range = 3,
  783. .pll_reset = 1,
  784. .pll_bypass = 0,
  785. .enable_refdiv = 0,
  786. .bypclk_div = 0,
  787. .IO_CLK_en_core = 1,
  788. .ADClkSrc = 1,
  789. .modulo = 2,
  790. /* refsel, sel, freq_15k */
  791. .sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
  792. .ifreq = (0 << 25) | 0,
  793. .timf = 20452225,
  794. .xtal_hz = 12000000,
  795. };
  796. static struct dib7000p_config dib7070p_dib7000p_config = {
  797. /* .output_mode = OUTMODE_MPEG2_FIFO, */
  798. .output_mode = OUTMODE_MPEG2_SERIAL,
  799. /* .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK, */
  800. .output_mpeg2_in_188_bytes = 1,
  801. .agc_config_count = 1,
  802. .agc = &dib7070_agc_config,
  803. .bw = &dib7070_bw_config_12_mhz,
  804. .tuner_is_baseband = 1,
  805. .spur_protect = 1,
  806. .gpio_dir = 0xfcef, /* DIB7000P_GPIO_DEFAULT_DIRECTIONS, */
  807. .gpio_val = 0x0110, /* DIB7000P_GPIO_DEFAULT_VALUES, */
  808. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  809. .hostbus_diversity = 1,
  810. };
  811. static int dvb_register(struct cx23885_tsport *port)
  812. {
  813. struct dib7000p_ops dib7000p_ops;
  814. struct cx23885_dev *dev = port->dev;
  815. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  816. struct vb2_dvb_frontend *fe0, *fe1 = NULL;
  817. struct si2168_config si2168_config;
  818. struct si2157_config si2157_config;
  819. struct m88ts2022_config m88ts2022_config;
  820. struct i2c_board_info info;
  821. struct i2c_adapter *adapter;
  822. struct i2c_client *client_demod;
  823. struct i2c_client *client_tuner;
  824. int mfe_shared = 0; /* bus not shared by default */
  825. int ret;
  826. /* Get the first frontend */
  827. fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
  828. if (!fe0)
  829. return -EINVAL;
  830. /* init struct vb2_dvb */
  831. fe0->dvb.name = dev->name;
  832. /* multi-frontend gate control is undefined or defaults to fe0 */
  833. port->frontends.gate = 0;
  834. /* Sets the gate control callback to be used by i2c command calls */
  835. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  836. /* init frontend */
  837. switch (dev->board) {
  838. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  839. i2c_bus = &dev->i2c_bus[0];
  840. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  841. &hauppauge_generic_config,
  842. &i2c_bus->i2c_adap);
  843. if (fe0->dvb.frontend != NULL) {
  844. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  845. &i2c_bus->i2c_adap,
  846. &hauppauge_generic_tunerconfig, 0);
  847. }
  848. break;
  849. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  850. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  851. i2c_bus = &dev->i2c_bus[0];
  852. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  853. &hauppauge_lgdt3305_config,
  854. &i2c_bus->i2c_adap);
  855. if (fe0->dvb.frontend != NULL) {
  856. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  857. 0x60, &dev->i2c_bus[1].i2c_adap,
  858. &hauppauge_hvr127x_config);
  859. }
  860. if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
  861. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  862. break;
  863. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  864. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  865. i2c_bus = &dev->i2c_bus[0];
  866. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  867. &hcw_s5h1411_config,
  868. &i2c_bus->i2c_adap);
  869. if (fe0->dvb.frontend != NULL) {
  870. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  871. 0x60, &dev->i2c_bus[1].i2c_adap,
  872. &hauppauge_tda18271_config);
  873. }
  874. tda18271_attach(&dev->ts1.analog_fe,
  875. 0x60, &dev->i2c_bus[1].i2c_adap,
  876. &hauppauge_tda18271_config);
  877. break;
  878. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  879. i2c_bus = &dev->i2c_bus[0];
  880. switch (alt_tuner) {
  881. case 1:
  882. fe0->dvb.frontend =
  883. dvb_attach(s5h1409_attach,
  884. &hauppauge_ezqam_config,
  885. &i2c_bus->i2c_adap);
  886. if (fe0->dvb.frontend != NULL) {
  887. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  888. &dev->i2c_bus[1].i2c_adap, 0x42,
  889. &tda829x_no_probe);
  890. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  891. 0x60, &dev->i2c_bus[1].i2c_adap,
  892. &hauppauge_tda18271_config);
  893. }
  894. break;
  895. case 0:
  896. default:
  897. fe0->dvb.frontend =
  898. dvb_attach(s5h1409_attach,
  899. &hauppauge_generic_config,
  900. &i2c_bus->i2c_adap);
  901. if (fe0->dvb.frontend != NULL)
  902. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  903. &i2c_bus->i2c_adap,
  904. &hauppauge_generic_tunerconfig, 0);
  905. break;
  906. }
  907. break;
  908. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  909. i2c_bus = &dev->i2c_bus[0];
  910. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  911. &hauppauge_hvr1800lp_config,
  912. &i2c_bus->i2c_adap);
  913. if (fe0->dvb.frontend != NULL) {
  914. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  915. &i2c_bus->i2c_adap,
  916. &hauppauge_generic_tunerconfig, 0);
  917. }
  918. break;
  919. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  920. i2c_bus = &dev->i2c_bus[0];
  921. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  922. &fusionhdtv_5_express,
  923. &i2c_bus->i2c_adap);
  924. if (fe0->dvb.frontend != NULL) {
  925. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  926. &i2c_bus->i2c_adap, 0x61,
  927. TUNER_LG_TDVS_H06XF);
  928. }
  929. break;
  930. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  931. i2c_bus = &dev->i2c_bus[1];
  932. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  933. &hauppauge_hvr1500q_config,
  934. &dev->i2c_bus[0].i2c_adap);
  935. if (fe0->dvb.frontend != NULL)
  936. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  937. &i2c_bus->i2c_adap,
  938. &hauppauge_hvr1500q_tunerconfig);
  939. break;
  940. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  941. i2c_bus = &dev->i2c_bus[1];
  942. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  943. &hauppauge_hvr1500_config,
  944. &dev->i2c_bus[0].i2c_adap);
  945. if (fe0->dvb.frontend != NULL) {
  946. struct dvb_frontend *fe;
  947. struct xc2028_config cfg = {
  948. .i2c_adap = &i2c_bus->i2c_adap,
  949. .i2c_addr = 0x61,
  950. };
  951. static struct xc2028_ctrl ctl = {
  952. .fname = XC2028_DEFAULT_FIRMWARE,
  953. .max_len = 64,
  954. .demod = XC3028_FE_OREN538,
  955. };
  956. fe = dvb_attach(xc2028_attach,
  957. fe0->dvb.frontend, &cfg);
  958. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  959. fe->ops.tuner_ops.set_config(fe, &ctl);
  960. }
  961. break;
  962. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  963. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  964. i2c_bus = &dev->i2c_bus[0];
  965. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  966. &hauppauge_hvr1200_config,
  967. &i2c_bus->i2c_adap);
  968. if (fe0->dvb.frontend != NULL) {
  969. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  970. &dev->i2c_bus[1].i2c_adap, 0x42,
  971. &tda829x_no_probe);
  972. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  973. 0x60, &dev->i2c_bus[1].i2c_adap,
  974. &hauppauge_hvr1200_tuner_config);
  975. }
  976. break;
  977. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  978. i2c_bus = &dev->i2c_bus[0];
  979. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  980. &hauppauge_hvr1210_config,
  981. &i2c_bus->i2c_adap);
  982. if (fe0->dvb.frontend != NULL) {
  983. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  984. 0x60, &dev->i2c_bus[1].i2c_adap,
  985. &hauppauge_hvr1210_tuner_config);
  986. }
  987. break;
  988. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  989. i2c_bus = &dev->i2c_bus[0];
  990. if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
  991. return -ENODEV;
  992. fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap,
  993. 0x12, &hauppauge_hvr1400_dib7000_config);
  994. if (fe0->dvb.frontend != NULL) {
  995. struct dvb_frontend *fe;
  996. struct xc2028_config cfg = {
  997. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  998. .i2c_addr = 0x64,
  999. };
  1000. static struct xc2028_ctrl ctl = {
  1001. .fname = XC3028L_DEFAULT_FIRMWARE,
  1002. .max_len = 64,
  1003. .demod = XC3028_FE_DIBCOM52,
  1004. /* This is true for all demods with
  1005. v36 firmware? */
  1006. .type = XC2028_D2633,
  1007. };
  1008. fe = dvb_attach(xc2028_attach,
  1009. fe0->dvb.frontend, &cfg);
  1010. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  1011. fe->ops.tuner_ops.set_config(fe, &ctl);
  1012. }
  1013. break;
  1014. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1015. i2c_bus = &dev->i2c_bus[port->nr - 1];
  1016. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  1017. &dvico_s5h1409_config,
  1018. &i2c_bus->i2c_adap);
  1019. if (fe0->dvb.frontend == NULL)
  1020. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1021. &dvico_s5h1411_config,
  1022. &i2c_bus->i2c_adap);
  1023. if (fe0->dvb.frontend != NULL)
  1024. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  1025. &i2c_bus->i2c_adap,
  1026. &dvico_xc5000_tunerconfig);
  1027. break;
  1028. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  1029. i2c_bus = &dev->i2c_bus[port->nr - 1];
  1030. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1031. &dvico_fusionhdtv_xc3028,
  1032. &i2c_bus->i2c_adap);
  1033. if (fe0->dvb.frontend != NULL) {
  1034. struct dvb_frontend *fe;
  1035. struct xc2028_config cfg = {
  1036. .i2c_adap = &i2c_bus->i2c_adap,
  1037. .i2c_addr = 0x61,
  1038. };
  1039. static struct xc2028_ctrl ctl = {
  1040. .fname = XC2028_DEFAULT_FIRMWARE,
  1041. .max_len = 64,
  1042. .demod = XC3028_FE_ZARLINK456,
  1043. };
  1044. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  1045. &cfg);
  1046. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  1047. fe->ops.tuner_ops.set_config(fe, &ctl);
  1048. }
  1049. break;
  1050. }
  1051. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: {
  1052. i2c_bus = &dev->i2c_bus[port->nr - 1];
  1053. /* cxusb_ctrl_msg(adap->dev, CMD_DIGITAL, NULL, 0, NULL, 0); */
  1054. /* cxusb_bluebird_gpio_pulse(adap->dev, 0x02, 1); */
  1055. if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
  1056. return -ENODEV;
  1057. if (dib7000p_ops.i2c_enumeration(&i2c_bus->i2c_adap, 1, 0x12, &dib7070p_dib7000p_config) < 0) {
  1058. printk(KERN_WARNING "Unable to enumerate dib7000p\n");
  1059. return -ENODEV;
  1060. }
  1061. fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap, 0x80, &dib7070p_dib7000p_config);
  1062. if (fe0->dvb.frontend != NULL) {
  1063. struct i2c_adapter *tun_i2c;
  1064. fe0->dvb.frontend->sec_priv = kmalloc(sizeof(dib7000p_ops), GFP_KERNEL);
  1065. memcpy(fe0->dvb.frontend->sec_priv, &dib7000p_ops, sizeof(dib7000p_ops));
  1066. tun_i2c = dib7000p_ops.get_i2c_master(fe0->dvb.frontend, DIBX000_I2C_INTERFACE_TUNER, 1);
  1067. if (!dvb_attach(dib0070_attach, fe0->dvb.frontend, tun_i2c, &dib7070p_dib0070_config))
  1068. return -ENODEV;
  1069. }
  1070. break;
  1071. }
  1072. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1073. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1074. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1075. i2c_bus = &dev->i2c_bus[0];
  1076. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1077. &dvico_fusionhdtv_xc3028,
  1078. &i2c_bus->i2c_adap);
  1079. if (fe0->dvb.frontend != NULL) {
  1080. struct dvb_frontend *fe;
  1081. struct xc2028_config cfg = {
  1082. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  1083. .i2c_addr = 0x61,
  1084. };
  1085. static struct xc2028_ctrl ctl = {
  1086. .fname = XC2028_DEFAULT_FIRMWARE,
  1087. .max_len = 64,
  1088. .demod = XC3028_FE_ZARLINK456,
  1089. };
  1090. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  1091. &cfg);
  1092. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  1093. fe->ops.tuner_ops.set_config(fe, &ctl);
  1094. }
  1095. break;
  1096. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  1097. i2c_bus = &dev->i2c_bus[0];
  1098. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  1099. &dvico_fusionhdtv_xc3028,
  1100. &i2c_bus->i2c_adap);
  1101. if (fe0->dvb.frontend != NULL) {
  1102. struct dvb_frontend *fe;
  1103. struct xc4000_config cfg = {
  1104. .i2c_address = 0x61,
  1105. .default_pm = 0,
  1106. .dvb_amplitude = 134,
  1107. .set_smoothedcvbs = 1,
  1108. .if_khz = 4560
  1109. };
  1110. fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
  1111. &dev->i2c_bus[1].i2c_adap, &cfg);
  1112. if (!fe) {
  1113. printk(KERN_ERR "%s/2: xc4000 attach failed\n",
  1114. dev->name);
  1115. goto frontend_detach;
  1116. }
  1117. }
  1118. break;
  1119. case CX23885_BOARD_TBS_6920:
  1120. i2c_bus = &dev->i2c_bus[1];
  1121. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1122. &tbs_cx24116_config,
  1123. &i2c_bus->i2c_adap);
  1124. if (fe0->dvb.frontend != NULL)
  1125. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  1126. break;
  1127. case CX23885_BOARD_TBS_6980:
  1128. case CX23885_BOARD_TBS_6981:
  1129. i2c_bus = &dev->i2c_bus[1];
  1130. switch (port->nr) {
  1131. /* PORT B */
  1132. case 1:
  1133. fe0->dvb.frontend = dvb_attach(cx24117_attach,
  1134. &tbs_cx24117_config,
  1135. &i2c_bus->i2c_adap);
  1136. break;
  1137. /* PORT C */
  1138. case 2:
  1139. fe0->dvb.frontend = dvb_attach(cx24117_attach,
  1140. &tbs_cx24117_config,
  1141. &i2c_bus->i2c_adap);
  1142. break;
  1143. }
  1144. break;
  1145. case CX23885_BOARD_TEVII_S470:
  1146. i2c_bus = &dev->i2c_bus[1];
  1147. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  1148. &tevii_ds3000_config,
  1149. &i2c_bus->i2c_adap);
  1150. if (fe0->dvb.frontend != NULL) {
  1151. dvb_attach(ts2020_attach, fe0->dvb.frontend,
  1152. &tevii_ts2020_config, &i2c_bus->i2c_adap);
  1153. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  1154. }
  1155. break;
  1156. case CX23885_BOARD_DVBWORLD_2005:
  1157. i2c_bus = &dev->i2c_bus[1];
  1158. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  1159. &dvbworld_cx24116_config,
  1160. &i2c_bus->i2c_adap);
  1161. break;
  1162. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1163. i2c_bus = &dev->i2c_bus[0];
  1164. switch (port->nr) {
  1165. /* port B */
  1166. case 1:
  1167. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  1168. &netup_stv0900_config,
  1169. &i2c_bus->i2c_adap, 0);
  1170. if (fe0->dvb.frontend != NULL) {
  1171. if (dvb_attach(stv6110_attach,
  1172. fe0->dvb.frontend,
  1173. &netup_stv6110_tunerconfig_a,
  1174. &i2c_bus->i2c_adap)) {
  1175. if (!dvb_attach(lnbh24_attach,
  1176. fe0->dvb.frontend,
  1177. &i2c_bus->i2c_adap,
  1178. LNBH24_PCL | LNBH24_TTX,
  1179. LNBH24_TEN, 0x09))
  1180. printk(KERN_ERR
  1181. "No LNBH24 found!\n");
  1182. }
  1183. }
  1184. break;
  1185. /* port C */
  1186. case 2:
  1187. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  1188. &netup_stv0900_config,
  1189. &i2c_bus->i2c_adap, 1);
  1190. if (fe0->dvb.frontend != NULL) {
  1191. if (dvb_attach(stv6110_attach,
  1192. fe0->dvb.frontend,
  1193. &netup_stv6110_tunerconfig_b,
  1194. &i2c_bus->i2c_adap)) {
  1195. if (!dvb_attach(lnbh24_attach,
  1196. fe0->dvb.frontend,
  1197. &i2c_bus->i2c_adap,
  1198. LNBH24_PCL | LNBH24_TTX,
  1199. LNBH24_TEN, 0x0a))
  1200. printk(KERN_ERR
  1201. "No LNBH24 found!\n");
  1202. }
  1203. }
  1204. break;
  1205. }
  1206. break;
  1207. case CX23885_BOARD_MYGICA_X8506:
  1208. i2c_bus = &dev->i2c_bus[0];
  1209. i2c_bus2 = &dev->i2c_bus[1];
  1210. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  1211. &mygica_x8506_lgs8gl5_config,
  1212. &i2c_bus->i2c_adap);
  1213. if (fe0->dvb.frontend != NULL) {
  1214. dvb_attach(xc5000_attach,
  1215. fe0->dvb.frontend,
  1216. &i2c_bus2->i2c_adap,
  1217. &mygica_x8506_xc5000_config);
  1218. }
  1219. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  1220. break;
  1221. case CX23885_BOARD_MYGICA_X8507:
  1222. i2c_bus = &dev->i2c_bus[0];
  1223. i2c_bus2 = &dev->i2c_bus[1];
  1224. fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
  1225. &mygica_x8507_mb86a20s_config,
  1226. &i2c_bus->i2c_adap);
  1227. if (fe0->dvb.frontend != NULL) {
  1228. dvb_attach(xc5000_attach,
  1229. fe0->dvb.frontend,
  1230. &i2c_bus2->i2c_adap,
  1231. &mygica_x8507_xc5000_config);
  1232. }
  1233. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  1234. break;
  1235. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1236. i2c_bus = &dev->i2c_bus[0];
  1237. i2c_bus2 = &dev->i2c_bus[1];
  1238. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  1239. &magicpro_prohdtve2_lgs8g75_config,
  1240. &i2c_bus->i2c_adap);
  1241. if (fe0->dvb.frontend != NULL) {
  1242. dvb_attach(xc5000_attach,
  1243. fe0->dvb.frontend,
  1244. &i2c_bus2->i2c_adap,
  1245. &magicpro_prohdtve2_xc5000_config);
  1246. }
  1247. cx23885_set_frontend_hook(port, fe0->dvb.frontend);
  1248. break;
  1249. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1250. i2c_bus = &dev->i2c_bus[0];
  1251. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1252. &hcw_s5h1411_config,
  1253. &i2c_bus->i2c_adap);
  1254. if (fe0->dvb.frontend != NULL)
  1255. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1256. 0x60, &dev->i2c_bus[0].i2c_adap,
  1257. &hauppauge_tda18271_config);
  1258. tda18271_attach(&dev->ts1.analog_fe,
  1259. 0x60, &dev->i2c_bus[1].i2c_adap,
  1260. &hauppauge_tda18271_config);
  1261. break;
  1262. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1263. i2c_bus = &dev->i2c_bus[0];
  1264. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  1265. &hcw_s5h1411_config,
  1266. &i2c_bus->i2c_adap);
  1267. if (fe0->dvb.frontend != NULL)
  1268. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1269. 0x60, &dev->i2c_bus[0].i2c_adap,
  1270. &hauppauge_tda18271_config);
  1271. break;
  1272. case CX23885_BOARD_MYGICA_X8558PRO:
  1273. switch (port->nr) {
  1274. /* port B */
  1275. case 1:
  1276. i2c_bus = &dev->i2c_bus[0];
  1277. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1278. &mygica_x8558pro_atbm8830_cfg1,
  1279. &i2c_bus->i2c_adap);
  1280. if (fe0->dvb.frontend != NULL) {
  1281. dvb_attach(max2165_attach,
  1282. fe0->dvb.frontend,
  1283. &i2c_bus->i2c_adap,
  1284. &mygic_x8558pro_max2165_cfg1);
  1285. }
  1286. break;
  1287. /* port C */
  1288. case 2:
  1289. i2c_bus = &dev->i2c_bus[1];
  1290. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1291. &mygica_x8558pro_atbm8830_cfg2,
  1292. &i2c_bus->i2c_adap);
  1293. if (fe0->dvb.frontend != NULL) {
  1294. dvb_attach(max2165_attach,
  1295. fe0->dvb.frontend,
  1296. &i2c_bus->i2c_adap,
  1297. &mygic_x8558pro_max2165_cfg2);
  1298. }
  1299. break;
  1300. }
  1301. break;
  1302. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1303. i2c_bus = &dev->i2c_bus[0];
  1304. mfe_shared = 1;/* MFE */
  1305. port->frontends.gate = 0;/* not clear for me yet */
  1306. /* ports B, C */
  1307. /* MFE frontend 1 DVB-T */
  1308. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  1309. &netup_stv0367_config[port->nr - 1],
  1310. &i2c_bus->i2c_adap);
  1311. if (fe0->dvb.frontend != NULL) {
  1312. if (NULL == dvb_attach(xc5000_attach,
  1313. fe0->dvb.frontend,
  1314. &i2c_bus->i2c_adap,
  1315. &netup_xc5000_config[port->nr - 1]))
  1316. goto frontend_detach;
  1317. /* load xc5000 firmware */
  1318. fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
  1319. }
  1320. /* MFE frontend 2 */
  1321. fe1 = vb2_dvb_get_frontend(&port->frontends, 2);
  1322. if (fe1 == NULL)
  1323. goto frontend_detach;
  1324. /* DVB-C init */
  1325. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  1326. &netup_stv0367_config[port->nr - 1],
  1327. &i2c_bus->i2c_adap);
  1328. if (fe1->dvb.frontend != NULL) {
  1329. fe1->dvb.frontend->id = 1;
  1330. if (NULL == dvb_attach(xc5000_attach,
  1331. fe1->dvb.frontend,
  1332. &i2c_bus->i2c_adap,
  1333. &netup_xc5000_config[port->nr - 1]))
  1334. goto frontend_detach;
  1335. }
  1336. break;
  1337. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1338. i2c_bus = &dev->i2c_bus[0];
  1339. i2c_bus2 = &dev->i2c_bus[1];
  1340. switch (port->nr) {
  1341. /* port b */
  1342. case 1:
  1343. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1344. &terratec_drxk_config[0],
  1345. &i2c_bus->i2c_adap);
  1346. if (fe0->dvb.frontend != NULL) {
  1347. if (!dvb_attach(mt2063_attach,
  1348. fe0->dvb.frontend,
  1349. &terratec_mt2063_config[0],
  1350. &i2c_bus2->i2c_adap))
  1351. goto frontend_detach;
  1352. }
  1353. break;
  1354. /* port c */
  1355. case 2:
  1356. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1357. &terratec_drxk_config[1],
  1358. &i2c_bus->i2c_adap);
  1359. if (fe0->dvb.frontend != NULL) {
  1360. if (!dvb_attach(mt2063_attach,
  1361. fe0->dvb.frontend,
  1362. &terratec_mt2063_config[1],
  1363. &i2c_bus2->i2c_adap))
  1364. goto frontend_detach;
  1365. }
  1366. break;
  1367. }
  1368. break;
  1369. case CX23885_BOARD_TEVII_S471:
  1370. i2c_bus = &dev->i2c_bus[1];
  1371. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  1372. &tevii_ds3000_config,
  1373. &i2c_bus->i2c_adap);
  1374. if (fe0->dvb.frontend != NULL) {
  1375. dvb_attach(ts2020_attach, fe0->dvb.frontend,
  1376. &tevii_ts2020_config, &i2c_bus->i2c_adap);
  1377. }
  1378. break;
  1379. case CX23885_BOARD_PROF_8000:
  1380. i2c_bus = &dev->i2c_bus[0];
  1381. fe0->dvb.frontend = dvb_attach(stv090x_attach,
  1382. &prof_8000_stv090x_config,
  1383. &i2c_bus->i2c_adap,
  1384. STV090x_DEMODULATOR_0);
  1385. if (fe0->dvb.frontend != NULL) {
  1386. if (!dvb_attach(stb6100_attach,
  1387. fe0->dvb.frontend,
  1388. &prof_8000_stb6100_config,
  1389. &i2c_bus->i2c_adap))
  1390. goto frontend_detach;
  1391. fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
  1392. }
  1393. break;
  1394. case CX23885_BOARD_HAUPPAUGE_HVR4400:
  1395. i2c_bus = &dev->i2c_bus[0];
  1396. i2c_bus2 = &dev->i2c_bus[1];
  1397. switch (port->nr) {
  1398. /* port b */
  1399. case 1:
  1400. fe0->dvb.frontend = dvb_attach(tda10071_attach,
  1401. &hauppauge_tda10071_config,
  1402. &i2c_bus->i2c_adap);
  1403. if (fe0->dvb.frontend != NULL) {
  1404. if (!dvb_attach(a8293_attach, fe0->dvb.frontend,
  1405. &i2c_bus->i2c_adap,
  1406. &hauppauge_a8293_config))
  1407. goto frontend_detach;
  1408. }
  1409. break;
  1410. /* port c */
  1411. case 2:
  1412. fe0->dvb.frontend = dvb_attach(si2165_attach,
  1413. &hauppauge_hvr4400_si2165_config,
  1414. &i2c_bus->i2c_adap);
  1415. if (fe0->dvb.frontend != NULL) {
  1416. fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
  1417. if (!dvb_attach(tda18271_attach,
  1418. fe0->dvb.frontend,
  1419. 0x60, &i2c_bus2->i2c_adap,
  1420. &hauppauge_hvr4400_tuner_config))
  1421. goto frontend_detach;
  1422. }
  1423. break;
  1424. }
  1425. break;
  1426. case CX23885_BOARD_HAUPPAUGE_STARBURST:
  1427. i2c_bus = &dev->i2c_bus[0];
  1428. fe0->dvb.frontend = dvb_attach(tda10071_attach,
  1429. &hauppauge_tda10071_config,
  1430. &i2c_bus->i2c_adap);
  1431. if (fe0->dvb.frontend != NULL) {
  1432. dvb_attach(a8293_attach, fe0->dvb.frontend,
  1433. &i2c_bus->i2c_adap,
  1434. &hauppauge_a8293_config);
  1435. }
  1436. break;
  1437. case CX23885_BOARD_DVBSKY_T9580:
  1438. i2c_bus = &dev->i2c_bus[0];
  1439. i2c_bus2 = &dev->i2c_bus[1];
  1440. switch (port->nr) {
  1441. /* port b - satellite */
  1442. case 1:
  1443. /* attach frontend */
  1444. fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
  1445. &dvbsky_t9580_m88ds3103_config,
  1446. &i2c_bus2->i2c_adap, &adapter);
  1447. if (fe0->dvb.frontend == NULL)
  1448. break;
  1449. /* attach tuner */
  1450. memset(&m88ts2022_config, 0, sizeof(m88ts2022_config));
  1451. m88ts2022_config.fe = fe0->dvb.frontend;
  1452. m88ts2022_config.clock = 27000000;
  1453. memset(&info, 0, sizeof(struct i2c_board_info));
  1454. strlcpy(info.type, "m88ts2022", I2C_NAME_SIZE);
  1455. info.addr = 0x60;
  1456. info.platform_data = &m88ts2022_config;
  1457. request_module(info.type);
  1458. client_tuner = i2c_new_device(adapter, &info);
  1459. if (client_tuner == NULL ||
  1460. client_tuner->dev.driver == NULL)
  1461. goto frontend_detach;
  1462. if (!try_module_get(client_tuner->dev.driver->owner)) {
  1463. i2c_unregister_device(client_tuner);
  1464. goto frontend_detach;
  1465. }
  1466. /* delegate signal strength measurement to tuner */
  1467. fe0->dvb.frontend->ops.read_signal_strength =
  1468. fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
  1469. /*
  1470. * for setting the voltage we need to set GPIOs on
  1471. * the card.
  1472. */
  1473. port->fe_set_voltage =
  1474. fe0->dvb.frontend->ops.set_voltage;
  1475. fe0->dvb.frontend->ops.set_voltage =
  1476. dvbsky_t9580_set_voltage;
  1477. port->i2c_client_tuner = client_tuner;
  1478. break;
  1479. /* port c - terrestrial/cable */
  1480. case 2:
  1481. /* attach frontend */
  1482. memset(&si2168_config, 0, sizeof(si2168_config));
  1483. si2168_config.i2c_adapter = &adapter;
  1484. si2168_config.fe = &fe0->dvb.frontend;
  1485. si2168_config.ts_mode = SI2168_TS_SERIAL;
  1486. memset(&info, 0, sizeof(struct i2c_board_info));
  1487. strlcpy(info.type, "si2168", I2C_NAME_SIZE);
  1488. info.addr = 0x64;
  1489. info.platform_data = &si2168_config;
  1490. request_module(info.type);
  1491. client_demod = i2c_new_device(&i2c_bus->i2c_adap, &info);
  1492. if (client_demod == NULL ||
  1493. client_demod->dev.driver == NULL)
  1494. goto frontend_detach;
  1495. if (!try_module_get(client_demod->dev.driver->owner)) {
  1496. i2c_unregister_device(client_demod);
  1497. goto frontend_detach;
  1498. }
  1499. port->i2c_client_demod = client_demod;
  1500. /* attach tuner */
  1501. memset(&si2157_config, 0, sizeof(si2157_config));
  1502. si2157_config.fe = fe0->dvb.frontend;
  1503. memset(&info, 0, sizeof(struct i2c_board_info));
  1504. strlcpy(info.type, "si2157", I2C_NAME_SIZE);
  1505. info.addr = 0x60;
  1506. info.platform_data = &si2157_config;
  1507. request_module(info.type);
  1508. client_tuner = i2c_new_device(adapter, &info);
  1509. if (client_tuner == NULL ||
  1510. client_tuner->dev.driver == NULL) {
  1511. module_put(client_demod->dev.driver->owner);
  1512. i2c_unregister_device(client_demod);
  1513. goto frontend_detach;
  1514. }
  1515. if (!try_module_get(client_tuner->dev.driver->owner)) {
  1516. i2c_unregister_device(client_tuner);
  1517. module_put(client_demod->dev.driver->owner);
  1518. i2c_unregister_device(client_demod);
  1519. goto frontend_detach;
  1520. }
  1521. port->i2c_client_tuner = client_tuner;
  1522. break;
  1523. }
  1524. break;
  1525. default:
  1526. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  1527. " isn't supported yet\n",
  1528. dev->name);
  1529. break;
  1530. }
  1531. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  1532. printk(KERN_ERR "%s: frontend initialization failed\n",
  1533. dev->name);
  1534. goto frontend_detach;
  1535. }
  1536. /* define general-purpose callback pointer */
  1537. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1538. if (fe1)
  1539. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1540. #if 0
  1541. /* Ensure all frontends negotiate bus access */
  1542. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1543. if (fe1)
  1544. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1545. #endif
  1546. /* Put the analog decoder in standby to keep it quiet */
  1547. call_all(dev, core, s_power, 0);
  1548. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1549. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1550. /* register everything */
  1551. ret = vb2_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1552. &dev->pci->dev, adapter_nr, mfe_shared);
  1553. if (ret)
  1554. goto frontend_detach;
  1555. /* init CI & MAC */
  1556. switch (dev->board) {
  1557. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1558. static struct netup_card_info cinfo;
  1559. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1560. memcpy(port->frontends.adapter.proposed_mac,
  1561. cinfo.port[port->nr - 1].mac, 6);
  1562. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1563. port->nr, port->frontends.adapter.proposed_mac);
  1564. netup_ci_init(port);
  1565. break;
  1566. }
  1567. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1568. struct altera_ci_config netup_ci_cfg = {
  1569. .dev = dev,/* magic number to identify*/
  1570. .adapter = &port->frontends.adapter,/* for CI */
  1571. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1572. .fpga_rw = netup_altera_fpga_rw,
  1573. };
  1574. altera_ci_init(&netup_ci_cfg, port->nr);
  1575. break;
  1576. }
  1577. case CX23885_BOARD_TEVII_S470: {
  1578. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1579. if (port->nr != 1)
  1580. break;
  1581. /* Read entire EEPROM */
  1582. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1583. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1584. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1585. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1586. break;
  1587. }
  1588. case CX23885_BOARD_DVBSKY_T9580: {
  1589. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1590. if (port->nr > 2)
  1591. break;
  1592. /* Read entire EEPROM */
  1593. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1594. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
  1595. sizeof(eeprom));
  1596. printk(KERN_INFO "DVBSky T9580 port %d MAC address: %pM\n",
  1597. port->nr, eeprom + 0xc0 + (port->nr-1) * 8);
  1598. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0 +
  1599. (port->nr-1) * 8, 6);
  1600. break;
  1601. }
  1602. }
  1603. return ret;
  1604. frontend_detach:
  1605. port->gate_ctrl = NULL;
  1606. vb2_dvb_dealloc_frontends(&port->frontends);
  1607. return -EINVAL;
  1608. }
  1609. int cx23885_dvb_register(struct cx23885_tsport *port)
  1610. {
  1611. struct vb2_dvb_frontend *fe0;
  1612. struct cx23885_dev *dev = port->dev;
  1613. int err, i;
  1614. /* Here we need to allocate the correct number of frontends,
  1615. * as reflected in the cards struct. The reality is that currently
  1616. * no cx23885 boards support this - yet. But, if we don't modify this
  1617. * code then the second frontend would never be allocated (later)
  1618. * and fail with error before the attach in dvb_register().
  1619. * Without these changes we risk an OOPS later. The changes here
  1620. * are for safety, and should provide a good foundation for the
  1621. * future addition of any multi-frontend cx23885 based boards.
  1622. */
  1623. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1624. port->num_frontends);
  1625. for (i = 1; i <= port->num_frontends; i++) {
  1626. struct vb2_queue *q;
  1627. if (vb2_dvb_alloc_frontend(
  1628. &port->frontends, i) == NULL) {
  1629. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1630. return -ENOMEM;
  1631. }
  1632. fe0 = vb2_dvb_get_frontend(&port->frontends, i);
  1633. if (!fe0)
  1634. err = -EINVAL;
  1635. dprintk(1, "%s\n", __func__);
  1636. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1637. dev->board,
  1638. dev->name,
  1639. dev->pci_bus,
  1640. dev->pci_slot);
  1641. err = -ENODEV;
  1642. /* dvb stuff */
  1643. /* We have to init the queue for each frontend on a port. */
  1644. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1645. q = &fe0->dvb.dvbq;
  1646. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1647. q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
  1648. q->gfp_flags = GFP_DMA32;
  1649. q->min_buffers_needed = 2;
  1650. q->drv_priv = port;
  1651. q->buf_struct_size = sizeof(struct cx23885_buffer);
  1652. q->ops = &dvb_qops;
  1653. q->mem_ops = &vb2_dma_sg_memops;
  1654. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1655. q->lock = &dev->lock;
  1656. err = vb2_queue_init(q);
  1657. if (err < 0)
  1658. return err;
  1659. }
  1660. err = dvb_register(port);
  1661. if (err != 0)
  1662. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1663. __func__, err);
  1664. return err;
  1665. }
  1666. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1667. {
  1668. struct vb2_dvb_frontend *fe0;
  1669. struct i2c_client *client;
  1670. /* remove I2C client for tuner */
  1671. client = port->i2c_client_tuner;
  1672. if (client) {
  1673. module_put(client->dev.driver->owner);
  1674. i2c_unregister_device(client);
  1675. }
  1676. /* remove I2C client for demodulator */
  1677. client = port->i2c_client_demod;
  1678. if (client) {
  1679. module_put(client->dev.driver->owner);
  1680. i2c_unregister_device(client);
  1681. }
  1682. fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
  1683. if (fe0 && fe0->dvb.frontend)
  1684. vb2_dvb_unregister_bus(&port->frontends);
  1685. switch (port->dev->board) {
  1686. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1687. netup_ci_exit(port);
  1688. break;
  1689. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1690. altera_ci_release(port->dev, port->nr);
  1691. break;
  1692. }
  1693. port->gate_ctrl = NULL;
  1694. return 0;
  1695. }