ccif_c2k_platform.h 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687
  1. #ifndef __CCIF_PLATFORM_H__
  2. #define __CCIF_PLATFORM_H__
  3. #include "ccci_core.h"
  4. #include <mach/sync_write.h>
  5. #define ccif_write32(b, a, v) mt_reg_sync_writel(v, (b)+(a))
  6. #define ccif_write16(b, a, v) mt_reg_sync_writew(v, (b)+(a))
  7. #define ccif_write8(b, a, v) mt_reg_sync_writeb(v, (b)+(a))
  8. #define ccif_read32(b, a) ioread32((void __iomem *)((b)+(a)))
  9. #define ccif_read16(b, a) ioread16((void __iomem *)((b)+(a)))
  10. #define ccif_read8(b, a) ioread8((void __iomem *)((b)+(a)))
  11. /*MD peripheral register: MD bank8; AP bank2*/
  12. /*Modem WDT */
  13. #define WDT_MD_MODE (0x00)
  14. #define WDT_MD_LENGTH (0x04)
  15. #define WDT_MD_RESTART (0x08)
  16. #define WDT_MD_STA (0x0C)
  17. #define WDT_MD_SWRST (0x1C)
  18. #define WDT_MD_MODE_KEY (0x0000220E)
  19. /*CCIF */
  20. #define APCCIF_CON (0x00)
  21. #define APCCIF_BUSY (0x04)
  22. #define APCCIF_START (0x08)
  23. #define APCCIF_TCHNUM (0x0C)
  24. #define APCCIF_RCHNUM (0x10)
  25. #define APCCIF_ACK (0x14)
  26. #define APCCIF_CHDATA (0x100)
  27. /*C2K */
  28. #define INFRA_AO_C2K_CONFIG (0x330)
  29. #define INFRA_AO_C2K_STATUS (0x334)
  30. #define INFRA_AO_C2K_SPM_CTRL (0x338)
  31. #define SLEEP_CLK_CON (0x400)
  32. #define TOP_RGU_WDT_MODE (0x0)
  33. #define TOP_RGU_WDT_SWRST (0x14)
  34. #define TOP_RGU_WDT_SWSYSRST (0x18)
  35. #define TOP_RGU_WDT_NONRST_REG (0x20)
  36. #define ETS_SEL_BIT (0x1 << 13)
  37. struct md_hw_info {
  38. /*HW info - Register Address */
  39. unsigned long md_rgu_base;
  40. unsigned long md_boot_slave_Vector;
  41. unsigned long md_boot_slave_Key;
  42. unsigned long md_boot_slave_En;
  43. unsigned long ap_ccif_base;
  44. unsigned long md_ccif_base;
  45. unsigned int sram_size;
  46. /* #ifdef CONFIG_MTK_ECCCI_C2K */
  47. unsigned long sleep_base;
  48. unsigned long infra_ao_base;
  49. unsigned long toprgu_base;
  50. unsigned long c2k_chip_id_base;
  51. unsigned long md1_pccif_base;
  52. unsigned long md3_pccif_base;
  53. /* #endif */
  54. /*HW info - Interrutpt ID */
  55. unsigned int ap_ccif_irq_id;
  56. unsigned int md_wdt_irq_id;
  57. /*HW info - Interrupt flags */
  58. unsigned long ap_ccif_irq_flags;
  59. unsigned long md_wdt_irq_flags;
  60. };
  61. extern unsigned long ccci_modem_boot_count[];
  62. extern int md_ccif_power_off(struct ccci_modem *md, unsigned int timeout);
  63. extern int md_ccif_power_on(struct ccci_modem *md);
  64. extern int md_ccif_let_md_go(struct ccci_modem *md);
  65. int md_ccif_get_modem_hw_info(struct platform_device *dev_ptr,
  66. struct ccci_dev_cfg *dev_cfg,
  67. struct md_hw_info *hw_info);
  68. int md_ccif_io_remap_md_side_register(struct ccci_modem *md);
  69. void reset_md1_md3_pccif(struct ccci_modem *md);
  70. extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
  71. extern void mt_irq_set_polarity(unsigned int irq, unsigned int polarity);
  72. extern void mtk_wdt_set_c2k_sysrst(unsigned int flag);
  73. extern void ccci_mem_dump(int md_id, void *start_addr, int len);
  74. #endif /*__CLDMA_PLATFORM_H__*/