si_mhl2_edid_3d.c 115 KB

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  1. /*
  2. SiI8348 Linux Driver
  3. Copyright (C) 2013 Silicon Image, Inc.
  4. This program is free software; you can redistribute it and/or
  5. modify it under the terms of the GNU General Public License as
  6. published by the Free Software Foundation version 2.
  7. This program is distributed AS-IS WITHOUT ANY WARRANTY of any
  8. kind, whether express or implied; INCLUDING without the implied warranty
  9. of MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE or NON-INFRINGEMENT. See
  10. the GNU General Public License for more details at http://www.gnu.org/licenses/gpl-2.0.html.
  11. */
  12. #include <linux/slab.h>
  13. #include <linux/hrtimer.h>
  14. #include <linux/semaphore.h>
  15. #include <linux/cdev.h>
  16. #include <linux/device.h>
  17. #include "sii_hal.h"
  18. #include "si_fw_macros.h"
  19. #include "si_mhl_defs.h"
  20. #include "si_infoframe.h"
  21. #include "si_edid.h"
  22. #include "si_mhl2_edid_3d_api.h"
  23. #include "si_8348_internal_api.h"
  24. #include "si_mhl_tx_hw_drv_api.h"
  25. #ifdef MEDIA_DATA_TUNNEL_SUPPORT
  26. #include "si_mdt_inputdev.h"
  27. #endif
  28. #include "mhl_linux_tx.h"
  29. #include "platform.h"
  30. #include "hdmi_drv.h"
  31. #include "si_timing_defs.h"
  32. #define SET_3D_FLAG(context,x) \
  33. { \
  34. context->parse_data.flags.x = 1; \
  35. MHL_TX_EDID_INFO(context->dev_context, \
  36. "set %s\n",#x); \
  37. }
  38. #define CLR_3D_FLAG(context,x) \
  39. { \
  40. context->parse_data.flags.x = 0; \
  41. MHL_TX_EDID_INFO(context->dev_context, \
  42. "clr %s\n",#x); \
  43. }
  44. #define TEST_3D_FLAG(context,x) (context->parse_data.flags.x)
  45. typedef struct _timing_mode_from_data_sheet_t
  46. {
  47. uint16_t h_total;
  48. uint16_t v_total;
  49. uint32_t pixel_clock;
  50. struct
  51. {
  52. uint8_t interlaced:1;
  53. uint8_t reserved:7;
  54. }flags;
  55. char *description;
  56. }timing_mode_from_data_sheet_t,*Ptiming_mode_from_data_sheet_t;
  57. timing_mode_from_data_sheet_t timing_modes_from_data_sheet[]=
  58. {
  59. { 800, 525, 25175000,{0,0},"VGA"}
  60. ,{1088, 517, 33750000,{0,0},"WVGA"}
  61. ,{1056, 628, 40000000,{0,0},"SVGA"}
  62. ,{1344, 806, 65000000,{0,0},"XGA"}
  63. ,{1716, 262, 27000000,{1,0},"480i"}/* DS has VTOTAL for progressive */
  64. ,{1728, 312, 27000000,{1,0},"576i"}/* DS has VTOTAL for progressive */
  65. ,{ 858, 525, 27000000,{0,0},"480p"}
  66. ,{ 864, 625, 27000000,{0,0},"576p"}
  67. ,{1650, 750, 74250000,{0,0},"720p"}
  68. ,{2200, 562, 74250000,{1,0},"1080i"}/* DS has VTOTAL for progressive */
  69. ,{2750,1125, 74250000,{0,0},"1080p,24/30"}
  70. ,{2640,1125,148500000,{0,0},"1080p50"}
  71. ,{2200,1125,148500000,{0,0},"1080p60"}
  72. };
  73. void display_timing_enumeration_begin(edid_3d_data_p mhl_edid_3d_data)
  74. {
  75. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  76. "Begin MHL display timing enumeration\n");
  77. }
  78. void display_timing_enumeration_callback(edid_3d_data_p mhl_edid_3d_data,
  79. uint16_t columns, uint16_t rows,
  80. uint8_t bits_per_pixel,
  81. uint32_t vertical_refresh_rate_in_milliHz,
  82. MHL2_video_descriptor_t mhl2_video_descriptor)
  83. {
  84. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  85. "%4d x %4d, %2d bpp at %u Hz 3D - %16s %16s %16s\n\n"
  86. ,columns
  87. ,rows
  88. ,(uint16_t)bits_per_pixel
  89. ,vertical_refresh_rate_in_milliHz
  90. ,mhl2_video_descriptor.left_right ?"Left/Right" :""
  91. ,mhl2_video_descriptor.top_bottom ?"Top/Bottom" :""
  92. ,mhl2_video_descriptor.frame_sequential?"Frame Sequential":""
  93. );
  94. }
  95. void display_timing_enumeration_end(edid_3d_data_p mhl_edid_3d_data)
  96. {
  97. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  98. "End MHL display timing enumeration\n");
  99. }
  100. uint32_t si_mhl_tx_find_timings_from_totals( edid_3d_data_p mhl_edid_3d_data)
  101. {
  102. uint32_t ret_val=0;
  103. uint8_t i;
  104. uint16_t h_total, v_total;
  105. /* Measure the HTOTAL and VTOTAL and look them up in a table */
  106. h_total = si_mhl_tx_drv_get_incoming_horizontal_total(mhl_edid_3d_data->drv_context);
  107. v_total = si_mhl_tx_drv_get_incoming_vertical_total(mhl_edid_3d_data->drv_context);
  108. for (i = 0 ; i < sizeof(timing_modes_from_data_sheet)/sizeof(timing_modes_from_data_sheet[0]); ++i) {
  109. if (timing_modes_from_data_sheet[i].h_total == h_total) {
  110. if (timing_modes_from_data_sheet[i].v_total == v_total) {
  111. ret_val = timing_modes_from_data_sheet[i].pixel_clock;
  112. MHL_TX_DBG_ERR(,"vic was 0, %s\n"
  113. ,timing_modes_from_data_sheet[i].description);
  114. return ret_val;
  115. }
  116. }
  117. }
  118. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  119. "VIC was zero!!! h_total: 0x%04x v_total:0x%04x\n",
  120. h_total,v_total);
  121. return ret_val;
  122. }
  123. PLACE_IN_CODE_SEG char *psz_space ="n/a";
  124. PLACE_IN_CODE_SEG char *psz_frame_sequential ="FS ";
  125. PLACE_IN_CODE_SEG char *psz_top_bottom ="TB ";
  126. PLACE_IN_CODE_SEG char *psz_left_right ="LR ";
  127. /* VIC is a place holder, and not actually stored */
  128. #define CEA_861_D_VIC_info_entry(VIC,columns,rows,HBlank,VBLank,FieldRate,image_aspect_ratio,scanmode,PixelAspectRatio,flags,clocksPerPelShift,AdditionalVBlank) \
  129. {columns,rows,HBlank,VBLank,FieldRate,{image_aspect_ratio,scanmode,PixelAspectRatio,flags,clocksPerPelShift,AdditionalVBlank}}
  130. VIC_info_t VIC_info[]=
  131. {
  132. CEA_861_D_VIC_info_entry( 0, 0, 0, 0, 0, 0000 ,iar_16_to_10 ,vsm_progressive,par_1_to_1 ,vif_single_frame_rate,0,0)
  133. ,CEA_861_D_VIC_info_entry( 1, 640, 480,160,45, 60000 ,iar_4_to_3 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  134. ,CEA_861_D_VIC_info_entry( 2, 720, 480,138,45, 60000 ,iar_4_to_3 ,vsm_progressive,par_8_to_9 ,vif_dual_frame_rate ,0,0)
  135. ,CEA_861_D_VIC_info_entry( 3, 720, 480,138,45, 60000 ,iar_16_to_9 ,vsm_progressive,par_32_to_27 ,vif_dual_frame_rate ,0,0)
  136. ,CEA_861_D_VIC_info_entry( 4,1280, 720,370,30, 60000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  137. ,CEA_861_D_VIC_info_entry( 5,1920,1080,280,22, 60000 ,iar_16_to_9 ,vsm_interlaced ,par_1_to_1 ,vif_dual_frame_rate ,0,1)
  138. ,CEA_861_D_VIC_info_entry( 6, 720, 480,276,22, 60000 ,iar_4_to_3 ,vsm_interlaced ,par_8_to_9 ,vif_dual_frame_rate ,1,1)
  139. ,CEA_861_D_VIC_info_entry( 7, 720, 480,276,22, 60000 ,iar_16_to_9 ,vsm_interlaced ,par_32_to_27 ,vif_dual_frame_rate ,1,1)
  140. ,CEA_861_D_VIC_info_entry( 8, 720, 240,276,22, 60000 ,iar_4_to_3 ,vsm_progressive,par_4_to_9 ,vif_dual_frame_rate ,1,1)
  141. ,CEA_861_D_VIC_info_entry( 9, 720, 428,276,22, 60000 ,iar_16_to_9 ,vsm_progressive,par_16_to_27 ,vif_dual_frame_rate ,1,1)
  142. ,CEA_861_D_VIC_info_entry(10,2880, 480,552,22, 60000 ,iar_4_to_3 ,vsm_interlaced ,par_2_to_9_20_to_9 ,vif_dual_frame_rate ,0,1)
  143. ,CEA_861_D_VIC_info_entry(11,2880, 480,552,22, 60000 ,iar_16_to_9 ,vsm_interlaced ,par_8_to_27_80_to_27 ,vif_dual_frame_rate ,0,1)
  144. ,CEA_861_D_VIC_info_entry(12,2880, 240,552,22, 60000 ,iar_4_to_3 ,vsm_progressive,par_1_to_9_10_to_9 ,vif_dual_frame_rate ,0,1)
  145. ,CEA_861_D_VIC_info_entry(13,2880, 240,552,22, 60000 ,iar_16_to_9 ,vsm_progressive,par_4_to_27_40_to_27 ,vif_dual_frame_rate ,0,1)
  146. ,CEA_861_D_VIC_info_entry(14,1440, 480,276,45, 60000 ,iar_4_to_3 ,vsm_progressive,par_4_to_9 ,vif_dual_frame_rate ,0,0)
  147. ,CEA_861_D_VIC_info_entry(15,1440, 480,276,45, 60000 ,iar_16_to_9 ,vsm_progressive,par_16_to_27 ,vif_dual_frame_rate ,0,0)
  148. ,CEA_861_D_VIC_info_entry(16,1920,1080,280,45, 60000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  149. ,CEA_861_D_VIC_info_entry(17, 720, 576,144,49, 50000 ,iar_4_to_3 ,vsm_progressive,par_16_to_15 ,vif_single_frame_rate,0,0)
  150. ,CEA_861_D_VIC_info_entry(18, 720, 576,144,49, 50000 ,iar_16_to_9 ,vsm_progressive,par_64_to_45 ,vif_single_frame_rate,0,0)
  151. ,CEA_861_D_VIC_info_entry(19,1280, 720,700,30, 50000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_single_frame_rate,0,0)
  152. ,CEA_861_D_VIC_info_entry(20,1920,1080,720,22, 50000 ,iar_16_to_9 ,vsm_interlaced ,par_1_to_1 ,vif_single_frame_rate,0,1)
  153. ,CEA_861_D_VIC_info_entry(21, 720, 576,288,24, 50000 ,iar_4_to_3 ,vsm_interlaced ,par_16_to_15 ,vif_single_frame_rate,1,1) /* (1440) */
  154. ,CEA_861_D_VIC_info_entry(22, 720, 576,288,24, 50000 ,iar_16_to_9 ,vsm_interlaced ,par_64_to_45 ,vif_single_frame_rate,1,1) /* (1440) */
  155. ,CEA_861_D_VIC_info_entry(23, 720, 288,288,24, 50000 ,iar_4_to_3 ,vsm_progressive,par_8_to_15 ,vif_single_frame_rate,1,2) /* (1440) */
  156. ,CEA_861_D_VIC_info_entry(24, 720, 288,288,24, 50000 ,iar_16_to_9 ,vsm_progressive,par_32_to_45 ,vif_single_frame_rate,1,2) /* (1440) */
  157. ,CEA_861_D_VIC_info_entry(25,2880, 576,576,24, 50000 ,iar_4_to_3 ,vsm_interlaced ,par_2_to_15_20_to_15 ,vif_single_frame_rate,0,1)
  158. ,CEA_861_D_VIC_info_entry(26,2880, 576,576,24, 50000 ,iar_16_to_9 ,vsm_interlaced ,par_16_to_45_160_to_45 ,vif_single_frame_rate,0,1)
  159. ,CEA_861_D_VIC_info_entry(27,2880, 288,576,24, 50000 ,iar_4_to_3 ,vsm_progressive,par_1_to_15_10_to_15 ,vif_single_frame_rate,0,2)
  160. ,CEA_861_D_VIC_info_entry(28,2880, 288,576,24, 50000 ,iar_16_to_9 ,vsm_progressive,par_8_to_45_80_to_45 ,vif_single_frame_rate,0,2)
  161. ,CEA_861_D_VIC_info_entry(29,1440, 576,288,49, 50000 ,iar_4_to_3 ,vsm_progressive,par_8_to_15 ,vif_single_frame_rate,0,0)
  162. ,CEA_861_D_VIC_info_entry(30,1440, 576,288,49, 50000 ,iar_16_to_9 ,vsm_progressive,par_32_to_45 ,vif_single_frame_rate,0,0)
  163. ,CEA_861_D_VIC_info_entry(31,1920,1080,720,45, 50000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_single_frame_rate,0,0)
  164. ,CEA_861_D_VIC_info_entry(32,1920,1080,830,45, 24000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  165. ,CEA_861_D_VIC_info_entry(33,1920,1080,720,45, 25000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_single_frame_rate,0,0)
  166. ,CEA_861_D_VIC_info_entry(34,1920,1080,280,45, 30000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  167. ,CEA_861_D_VIC_info_entry(35,2880, 480,552,45, 60000 ,iar_4_to_3 ,vsm_progressive,par_2_to_9 ,vif_dual_frame_rate ,0,0)
  168. ,CEA_861_D_VIC_info_entry(36,2880, 480,552,45, 60000 ,iar_16_to_9 ,vsm_progressive,par_8_to_27 ,vif_dual_frame_rate ,0,0)
  169. ,CEA_861_D_VIC_info_entry(37,2880, 576,576,49, 50000 ,iar_4_to_3 ,vsm_progressive,par_4_to_15 ,vif_single_frame_rate,0,0)
  170. ,CEA_861_D_VIC_info_entry(38,2880, 576,576,49, 50000 ,iar_16_to_9 ,vsm_progressive,par_16_to_45 ,vif_single_frame_rate,0,0)
  171. ,CEA_861_D_VIC_info_entry(39,1920,1080,384,85, 50000 ,iar_16_to_9 ,vsm_interlaced ,par_1_to_1 ,vif_single_frame_rate,0,0) /*1250,total*/
  172. ,CEA_861_D_VIC_info_entry(40,1920,1080,720,22,100000 ,iar_16_to_9 ,vsm_interlaced ,par_1_to_1 ,vif_single_frame_rate,0,1)
  173. ,CEA_861_D_VIC_info_entry(41,1280, 720,700,30,100000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_single_frame_rate,0,0)
  174. ,CEA_861_D_VIC_info_entry(42, 720, 576,144,49,100000 ,iar_4_to_3 ,vsm_progressive,par_16_to_15 ,vif_single_frame_rate,0,0)
  175. ,CEA_861_D_VIC_info_entry(43, 720, 576,144,49,100000 ,iar_16_to_9 ,vsm_progressive,par_64_to_45 ,vif_single_frame_rate,0,0)
  176. ,CEA_861_D_VIC_info_entry(44, 720, 576,288,24,100000 ,iar_4_to_3 ,vsm_interlaced ,par_16_to_15 ,vif_single_frame_rate,1,1) /* (1440) */
  177. ,CEA_861_D_VIC_info_entry(45, 720, 576,288,24,100000 ,iar_16_to_9 ,vsm_interlaced ,par_64_to_45 ,vif_single_frame_rate,1,1) /* (1440) */
  178. ,CEA_861_D_VIC_info_entry(46,1920,1080,280,22,120000 ,iar_16_to_9 ,vsm_interlaced ,par_1_to_1 ,vif_dual_frame_rate ,0,1)
  179. ,CEA_861_D_VIC_info_entry(47,1280, 720,370,30,120000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  180. ,CEA_861_D_VIC_info_entry(48, 720, 480,138,45,120000 ,iar_4_to_3 ,vsm_progressive,par_8_to_9 ,vif_dual_frame_rate ,0,0)
  181. ,CEA_861_D_VIC_info_entry(49, 720, 480,138,45,120000 ,iar_16_to_9 ,vsm_progressive,par_32_to_27 ,vif_dual_frame_rate ,0,0)
  182. ,CEA_861_D_VIC_info_entry(50, 720, 480,276,22,120000 ,iar_4_to_3 ,vsm_interlaced ,par_8_to_9 ,vif_dual_frame_rate ,1,1) /* (1440) */
  183. ,CEA_861_D_VIC_info_entry(51, 720, 480,276,22,120000 ,iar_16_to_9 ,vsm_interlaced ,par_32_to_27 ,vif_dual_frame_rate ,1,1) /* (1440) */
  184. ,CEA_861_D_VIC_info_entry(52, 720, 576,144,49,200000 ,iar_4_to_3 ,vsm_progressive,par_16_to_15 ,vif_single_frame_rate,0,0)
  185. ,CEA_861_D_VIC_info_entry(53, 720, 576,144,49,200000 ,iar_16_to_9 ,vsm_progressive,par_64_to_45 ,vif_single_frame_rate,0,0)
  186. ,CEA_861_D_VIC_info_entry(54, 720, 576,288,24,200000 ,iar_4_to_3 ,vsm_interlaced ,par_16_to_15 ,vif_single_frame_rate,1,1) /* (1440) */
  187. ,CEA_861_D_VIC_info_entry(55, 720, 576,288,24,200000 ,iar_16_to_9 ,vsm_interlaced ,par_64_to_45 ,vif_single_frame_rate,1,1) /* (1440) */
  188. ,CEA_861_D_VIC_info_entry(56, 720, 480,138,45,240000 ,iar_4_to_3 ,vsm_progressive,par_8_to_9 ,vif_dual_frame_rate ,0,0)
  189. ,CEA_861_D_VIC_info_entry(57, 720, 480,138,45,240000 ,iar_16_to_9 ,vsm_progressive,par_32_to_27 ,vif_dual_frame_rate ,0,0)
  190. ,CEA_861_D_VIC_info_entry(58, 720, 480,276,22,240000 ,iar_4_to_3 ,vsm_interlaced ,par_8_to_9 ,vif_dual_frame_rate ,1,1) /* (1440) */
  191. ,CEA_861_D_VIC_info_entry(59, 720, 480,276,22,240000 ,iar_16_to_9 ,vsm_interlaced ,par_32_to_27 ,vif_dual_frame_rate ,1,1) /* (1440) */
  192. ,CEA_861_D_VIC_info_entry(60,1280, 720,370,30, 24000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  193. ,CEA_861_D_VIC_info_entry(61,1280, 720,370,30, 25000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_single_frame_rate,0,0)
  194. ,CEA_861_D_VIC_info_entry(62,1280, 720,370,30, 30000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  195. ,CEA_861_D_VIC_info_entry(63,1920,1080,280,45,120000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_dual_frame_rate ,0,0)
  196. ,CEA_861_D_VIC_info_entry(64,1920,1080,280,45,100000 ,iar_16_to_9 ,vsm_progressive,par_1_to_1 ,vif_single_frame_rate,0,0)
  197. };
  198. uint32_t calculate_pixel_clock(edid_3d_data_p mhl_edid_3d_data,
  199. uint16_t columns, uint16_t rows,
  200. uint32_t vertical_sync_frequency_in_milliHz,
  201. uint8_t VIC)
  202. {
  203. uint32_t pixel_clock_frequency;
  204. uint32_t vertical_sync_period_in_microseconds;
  205. uint32_t vertical_active_period_in_microseconds;
  206. uint32_t vertical_blank_period_in_microseconds;
  207. uint32_t horizontal_sync_frequency_in_hundredths_of_KHz;
  208. uint32_t horizontal_sync_period_in_nanoseconds;
  209. uint32_t horizontal_active_period_in_nanoseconds;
  210. uint32_t horizontal_blank_period_in_nanoseconds;
  211. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  212. "vertical_sync_frequency_in_milliHz: %u\n",vertical_sync_frequency_in_milliHz );
  213. vertical_sync_period_in_microseconds = 1000000000/vertical_sync_frequency_in_milliHz;
  214. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  215. "vertical_sync_frequency_in_milliHz:%u vertical_sync_period_in_microseconds: %u\n",vertical_sync_frequency_in_milliHz,vertical_sync_period_in_microseconds);
  216. if (0 == VIC) {
  217. /* rule of thumb: */
  218. vertical_active_period_in_microseconds = (vertical_sync_period_in_microseconds * 8) / 10;
  219. } else {
  220. uint16_t v_total_in_lines;
  221. uint16_t v_blank_in_lines;
  222. if (vsm_interlaced == VIC_info[VIC].fields.interlaced) {
  223. /* fix up these two values */
  224. vertical_sync_frequency_in_milliHz /= 2;
  225. vertical_sync_period_in_microseconds *= 2;
  226. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  227. "interlaced vertical_sync_frequency_in_milliHz:%u"
  228. " vertical_sync_period_in_microseconds: %u\n"
  229. ,vertical_sync_frequency_in_milliHz
  230. ,vertical_sync_period_in_microseconds);
  231. /* proceed with calculations */
  232. v_blank_in_lines = 2 * VIC_info[VIC].v_blank_in_pixels + VIC_info[VIC].fields.field2_v_blank;
  233. } else {
  234. /* when multiple vertical blanking values present,
  235. allow for higher clocks by calculating maximum possible
  236. */
  237. v_blank_in_lines = VIC_info[VIC].v_blank_in_pixels + VIC_info[VIC].fields.field2_v_blank;
  238. }
  239. v_total_in_lines = VIC_info[VIC].rows +v_blank_in_lines ;
  240. vertical_active_period_in_microseconds = (vertical_sync_period_in_microseconds * VIC_info[VIC].rows) / v_total_in_lines;
  241. }
  242. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  243. "vertical_active_period_in_microseconds: %u\n",vertical_active_period_in_microseconds);
  244. /* rigorous calculation: */
  245. vertical_blank_period_in_microseconds = vertical_sync_period_in_microseconds - vertical_active_period_in_microseconds;
  246. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  247. "vertical_blank_period_in_microseconds: %u\n",vertical_blank_period_in_microseconds);
  248. horizontal_sync_frequency_in_hundredths_of_KHz = rows * 100000;
  249. horizontal_sync_frequency_in_hundredths_of_KHz /= vertical_active_period_in_microseconds;
  250. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  251. "horizontal_sync_frequency_in_hundredths_of_KHz: %u\n",horizontal_sync_frequency_in_hundredths_of_KHz);
  252. horizontal_sync_period_in_nanoseconds = 100000000 / horizontal_sync_frequency_in_hundredths_of_KHz;
  253. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  254. "horizontal_sync_period_in_nanoseconds: %u\n",horizontal_sync_period_in_nanoseconds);
  255. if (0 == VIC) {
  256. /* rule of thumb: */
  257. horizontal_active_period_in_nanoseconds = (horizontal_sync_period_in_nanoseconds * 8) / 10;
  258. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  259. "horizontal_active_period_in_nanoseconds: %u\n",horizontal_active_period_in_nanoseconds);
  260. } else {
  261. uint16_t h_total_in_pixels;
  262. uint16_t h_clocks;
  263. h_clocks = VIC_info[VIC].columns << VIC_info[VIC].fields.clocks_per_pixel_shift_count;
  264. h_total_in_pixels = h_clocks + VIC_info[VIC].h_blank_in_pixels;
  265. horizontal_active_period_in_nanoseconds = (horizontal_sync_period_in_nanoseconds * h_clocks) / h_total_in_pixels;
  266. }
  267. /* rigorous calculation: */
  268. horizontal_blank_period_in_nanoseconds = horizontal_sync_period_in_nanoseconds - horizontal_active_period_in_nanoseconds;
  269. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  270. "horizontal_blank_period_in_nanoseconds: %u\n",horizontal_blank_period_in_nanoseconds);
  271. pixel_clock_frequency = columns * (1000000000/ horizontal_active_period_in_nanoseconds);
  272. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  273. "pixel_clock_frequency: %u\n",pixel_clock_frequency);
  274. return pixel_clock_frequency;
  275. }
  276. uint8_t qualify_pixel_clock_for_mhl(edid_3d_data_p mhl_edid_3d_data, uint32_t pixel_clock_frequency, uint8_t bits_per_pixel)
  277. {
  278. uint32_t pixel_clock_frequency_div_8;
  279. uint32_t link_clock_frequency;
  280. uint32_t max_link_clock_frequency;
  281. uint8_t ret_val;
  282. pixel_clock_frequency_div_8 = pixel_clock_frequency / 8;
  283. link_clock_frequency = pixel_clock_frequency_div_8 * (uint32_t)bits_per_pixel;
  284. if ( si_peer_supports_packed_pixel(mhl_edid_3d_data->dev_context) ) {
  285. max_link_clock_frequency = 300000000;
  286. } else {
  287. max_link_clock_frequency = 225000000;
  288. }
  289. if (link_clock_frequency < max_link_clock_frequency) {
  290. ret_val = 1;
  291. } else {
  292. ret_val = 0;
  293. }
  294. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  295. "Link clock:%u Hz %12s for MHL at %d bpp (max: %u Hz)\n"
  296. ,link_clock_frequency
  297. ,ret_val?"valid":"unattainable"
  298. ,(uint16_t)bits_per_pixel
  299. ,max_link_clock_frequency);
  300. return ret_val;
  301. }
  302. /*
  303. is_MHL_timing_mode
  304. MHL has a maximum link clock of 75Mhz.
  305. For now, we use a rule of thumb regarding
  306. blanking intervals to calculate a pixel clock,
  307. then we convert it to a link clock and compare to 75MHz
  308. */
  309. static uint8_t is_MHL_timing_mode(edid_3d_data_p mhl_edid_3d_data,
  310. uint16_t columns, uint16_t rows,
  311. uint32_t vertical_sync_frequency_in_milliHz,
  312. PMHL2_video_descriptor_t p_MHL2_video_descriptor_parm,
  313. uint8_t VIC)
  314. {
  315. uint32_t pixel_clock_frequency;
  316. uint8_t ret_val = 0;
  317. MHL2_video_descriptor_t dummy;
  318. PMHL2_video_descriptor_t pMHL2_video_descriptor = p_MHL2_video_descriptor_parm;
  319. if (NULL == p_MHL2_video_descriptor_parm) {
  320. dummy.frame_sequential=0;
  321. dummy.left_right=0;
  322. dummy.top_bottom=0;
  323. dummy.reserved_high=0;
  324. dummy.reserved_low=0;
  325. pMHL2_video_descriptor=&dummy;
  326. }
  327. pixel_clock_frequency = calculate_pixel_clock(mhl_edid_3d_data, columns, rows,
  328. vertical_sync_frequency_in_milliHz, VIC);
  329. if (qualify_pixel_clock_for_mhl(mhl_edid_3d_data,pixel_clock_frequency, 24)) {
  330. display_timing_enumeration_callback(mhl_edid_3d_data, columns, rows,
  331. 24, vertical_sync_frequency_in_milliHz,*pMHL2_video_descriptor);
  332. ret_val = 1;
  333. }
  334. if (qualify_pixel_clock_for_mhl(mhl_edid_3d_data,pixel_clock_frequency, 16)) {
  335. display_timing_enumeration_callback(mhl_edid_3d_data, columns, rows,
  336. 16, vertical_sync_frequency_in_milliHz,*pMHL2_video_descriptor);
  337. ret_val = 1;
  338. }
  339. return ret_val;
  340. }
  341. #ifdef CONFIG_MTK_HDMI_3D_SUPPORT
  342. void si_mhl_tx_prune_dtd_list(edid_3d_data_p mhl_edid_3d_data,
  343. P_18_byte_descriptor_u p_desc,uint8_t limit)
  344. {
  345. uint8_t i;
  346. uint8_t number_that_we_pruned = 0;
  347. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"limit: %d\n",(uint16_t)limit);
  348. if (limit) {
  349. for (i = 0 ; i < limit -1 ; ++i) {
  350. if ((0 != p_desc->dtd.pixel_clock_low) || (0 != p_desc->dtd.pixel_clock_high)) {
  351. if ((0 == p_desc->dtd.horz_active_7_0)&&(0 == p_desc->dtd.horz_active_blanking_high.horz_active_11_8)) {
  352. P_18_byte_descriptor_u p_holder=p_desc,p_next_desc = p_desc+1;
  353. uint8_t j;
  354. number_that_we_pruned++;
  355. for (j = i+1; j < limit ; ++j) {
  356. /* move the rest of the entries one by one */
  357. *p_desc++ = *p_next_desc++;
  358. }
  359. /* re-consider the new occupant of the i'th entry on the next iteration */
  360. i--;
  361. p_desc=p_holder;
  362. }
  363. }
  364. }
  365. /* at this point "i" holds the value of mhl_edid_3d_data->svddata_block_length-1
  366. and p_desc points to the last entry in the list
  367. */
  368. for (;number_that_we_pruned >0;--number_that_we_pruned,--p_desc) {
  369. uint8_t *pu8_temp = (uint8_t *)p_desc;
  370. uint8_t size;
  371. for (size = sizeof(*p_desc); size > 0; --size) {
  372. *pu8_temp-- = 0;
  373. }
  374. }
  375. }
  376. }
  377. #endif
  378. /*
  379. FUNCTION : si_mhl_tx_parse_detailed_timing_descriptor()
  380. PURPOSE : Parse the detailed timing section of EDID Block 0 and
  381. print their decoded meaning to the screen.
  382. INPUT PARAMS : Pointer to the array where the data read from EDID
  383. Block0 is stored.
  384. Offset to the beginning of the Detailed Timing Descriptor
  385. data.
  386. Block indicator to distinguish between block #0 and blocks
  387. #2, #3
  388. OUTPUT PARAMS: None
  389. GLOBALS USED : None
  390. RETURNS : true if valid timing, false if not
  391. */
  392. static bool si_mhl_tx_parse_detailed_timing_descriptor(
  393. edid_3d_data_p mhl_edid_3d_data,
  394. P_18_byte_descriptor_u p_desc ,
  395. uint8_t Block, uint8_t *p_is_timing,
  396. PMHL2_video_descriptor_t pMHL2_video_descriptor)
  397. {
  398. uint8_t tmp_byte;
  399. uint8_t i;
  400. uint16_t tmp_word;
  401. *p_is_timing = 0;
  402. tmp_word = p_desc->dtd.pixel_clock_low + 256 * p_desc->dtd.pixel_clock_high;
  403. /* 18 byte partition is used as either for Monitor Name or for Monitor Range Limits or it is unused */
  404. if (tmp_word == 0x00) {
  405. /* if called from Block #0 and first 2 bytes are 0 => either Monitor Name or for Monitor Range Limits */
  406. if (Block == EDID_BLOCK_0) {
  407. if (0xFC == p_desc->name.data_type_tag) {
  408. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  409. "Monitor Name: ");
  410. for (i = 0; i < 13; i++) {
  411. // TODO: FD, TBI
  412. pr_debug("%c", p_desc->name.ascii_name[i]); /* Display monitor name */
  413. #if 0
  414. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  415. "%c", p_desc->name.ascii_name[i]); /* Display monitor name */
  416. #endif
  417. }
  418. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context, "\n");
  419. } else if (0xFD == p_desc->name.data_type_tag) {
  420. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  421. "Monitor Range Limits:\n\n");
  422. //i = 0;
  423. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  424. "Min Vertical Rate in Hz: %d\n",
  425. (int)p_desc->range_limits.min_vertical_rate_in_Hz);
  426. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  427. "Max Vertical Rate in Hz: %d\n",
  428. (int)p_desc->range_limits.max_vertical_rate_in_Hz);
  429. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  430. "Min Horizontal Rate in KHz: %d\n",
  431. (int)p_desc->range_limits.min_horizontal_rate_in_KHz);
  432. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  433. "Max Horizontal Rate in KHz: %d\n",
  434. (int)p_desc->range_limits.max_horizontal_rate_in_KHz);
  435. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  436. "Max Supported pixel clock rate in MHz/10: %d\n",
  437. (int)p_desc->range_limits.max_pixel_clock_in_MHz_div_10);
  438. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  439. "Tag for secondary timing formula (00h=not used): %d\n",
  440. (int)p_desc->range_limits.tag_secondary_formula);
  441. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"\n");
  442. }
  443. } else if (Block == EDID_BLOCK_2_3) {
  444. /* if called from block #2 or #3 and first 2 bytes are 0x00 (padding) then this
  445. descriptor partition is not used and parsing should be stopped
  446. */
  447. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  448. "No More Detailed descriptors in this block\n");
  449. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context, "\n");
  450. return false;
  451. }
  452. } else {
  453. /* first 2 bytes are not 0 => this is a detailed timing descriptor from either block */
  454. uint32_t pixel_clock_frequency;
  455. uint16_t columns,rows,vertical_sync_period_in_lines;
  456. uint32_t vertical_refresh_rate_in_milliHz,horizontal_sync_frequency_in_Hz,horizontal_sync_period_in_pixels;
  457. *p_is_timing = 1;
  458. pixel_clock_frequency = (uint32_t)tmp_word * 10000;
  459. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  460. "Pixel Clock: %d.%02d MHz or %d Hz (0x%x Hz)\n",
  461. tmp_word/100, tmp_word%100,pixel_clock_frequency,pixel_clock_frequency);
  462. columns = p_desc->dtd.horz_active_7_0 + 256 * p_desc->dtd.horz_active_blanking_high.horz_active_11_8;
  463. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  464. "Horizontal Active Pixels: %d\n", columns);
  465. tmp_word = p_desc->dtd.horz_blanking_7_0 + 256 * p_desc->dtd.horz_active_blanking_high.horz_blanking_11_8;
  466. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  467. "Horizontal Blanking (Pixels): %d\n", tmp_word);
  468. horizontal_sync_period_in_pixels = (uint32_t)columns + (uint32_t)tmp_word;
  469. horizontal_sync_frequency_in_Hz = pixel_clock_frequency/horizontal_sync_period_in_pixels;
  470. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  471. "horizontal period %u pixels, "\
  472. "horizontal_sync_frequency_in_Hz: %u Hz\n",
  473. horizontal_sync_period_in_pixels,horizontal_sync_frequency_in_Hz);
  474. rows = p_desc->dtd.vert_active_7_0 + 256 * p_desc->dtd.vert_active_blanking_high.vert_active_11_8;
  475. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  476. "Vertical Active (Lines): %u\n", rows);
  477. tmp_word = p_desc->dtd.vert_blanking_7_0 + 256 * p_desc->dtd.vert_active_blanking_high.vert_blanking_11_8;
  478. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  479. "Vertical Blanking (Lines): %u\n", tmp_word);
  480. vertical_sync_period_in_lines = rows + tmp_word;
  481. vertical_refresh_rate_in_milliHz = horizontal_sync_frequency_in_Hz*1000/(vertical_sync_period_in_lines);
  482. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  483. "vertical period %u lines, frequency %u MilliHz\n",
  484. vertical_sync_period_in_lines,vertical_refresh_rate_in_milliHz);
  485. tmp_word = p_desc->dtd.horz_sync_offset_7_0 + 256 * p_desc->dtd.hs_offset_hs_pulse_width_vs_offset_vs_pulse_width.horzSyncOffset9_8;
  486. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  487. "Horizontal Sync Offset (Pixels): %d\n", tmp_word);
  488. tmp_word = p_desc->dtd.horz_sync_pulse_width7_0 + 256 * p_desc->dtd.hs_offset_hs_pulse_width_vs_offset_vs_pulse_width.horz_sync_pulse_width_9_8;
  489. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  490. "Horizontal Sync Pulse Width (Pixels): %d\n", tmp_word);
  491. tmp_word = p_desc->dtd.vert_sync_offset_width.vert_sync_offset_3_0 + 16 * p_desc->dtd.hs_offset_hs_pulse_width_vs_offset_vs_pulse_width.vert_sync_offset_5_4;
  492. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  493. "Vertical Sync Offset (Lines): %d\n", tmp_word);
  494. tmp_word = p_desc->dtd.vert_sync_offset_width.vert_sync_pulse_width_3_0
  495. + 16 * p_desc->dtd.hs_offset_hs_pulse_width_vs_offset_vs_pulse_width.vert_sync_pulse_width_5_4;
  496. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  497. "Vertical Sync Pulse Width (Lines): %d\n", tmp_word);
  498. tmp_word = p_desc->dtd.horz_image_size_in_mm_7_0
  499. + 256 * p_desc->dtd.image_size_high.horz_image_size_in_mm_11_8;
  500. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  501. "Horizontal Image Size (mm): %d\n", tmp_word);
  502. tmp_word = p_desc->dtd.vert_image_size_in_mm_7_0
  503. + 256 * p_desc->dtd.image_size_high.vert_image_size_in_mm_11_8;
  504. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  505. "Vertical Image Size (mm): %d\n", tmp_word);
  506. tmp_byte = p_desc->dtd.horz_border_in_lines;
  507. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  508. "Horizontal Border (Pixels): %d\n", (int)tmp_byte);
  509. tmp_byte = p_desc->dtd.vert_border_in_pixels;
  510. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  511. "Vertical Border (Lines): %d\n", (int)tmp_byte);
  512. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context, "%sInterlaced\n",p_desc->dtd.flags.interlaced ? "" : "Non-" );
  513. switch (p_desc->dtd.flags.stereo_bits_2_1)
  514. {
  515. case 0:
  516. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  517. "Normal Display, No Stereo\n");
  518. break;
  519. case 1:
  520. if (0 == p_desc->dtd.flags.stereo_bit_0) {
  521. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  522. "Field sequential stereo, right image when "\
  523. "stereo sync signal == 1\n");
  524. } else {
  525. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  526. "2-way interleaved stereo, right image on "\
  527. "even lines\n");
  528. }
  529. break;
  530. case 2:
  531. if (0 == p_desc->dtd.flags.stereo_bit_0) {
  532. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  533. "field-sequential stereo, left image when "\
  534. "stereo sync signal == 1\n");
  535. } else {
  536. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  537. "2-way interleaved stereo, left image on even "\
  538. "lines.\n");
  539. }
  540. break;
  541. case 3:
  542. if (0 == p_desc->dtd.flags.stereo_bit_0) {
  543. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  544. "4-way interleaved stereo\n");
  545. } else {
  546. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  547. "side-by-side interleaved stereo.\n");
  548. }
  549. break;
  550. }
  551. switch ( p_desc->dtd.flags.sync_signal_type )
  552. {
  553. case 0x0:
  554. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  555. "Analog Composite\n");
  556. break;
  557. case 0x1:
  558. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  559. "Bipolar Analog Composite\n");
  560. break;
  561. case 0x2:
  562. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  563. "Digital Composite\n");
  564. break;
  565. case 0x3:
  566. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  567. "Digital Separate\n");
  568. break;
  569. }
  570. if (pMHL2_video_descriptor) {
  571. uint8_t this_mode_doable=0;
  572. if ((this_mode_doable=qualify_pixel_clock_for_mhl((void*)mhl_edid_3d_data,pixel_clock_frequency,24))) {
  573. display_timing_enumeration_callback(mhl_edid_3d_data, columns,
  574. rows, 24, vertical_refresh_rate_in_milliHz,
  575. *pMHL2_video_descriptor);
  576. }
  577. if (this_mode_doable |=qualify_pixel_clock_for_mhl((void*)mhl_edid_3d_data,pixel_clock_frequency,16)) {
  578. display_timing_enumeration_callback(mhl_edid_3d_data, columns,
  579. rows, 16, vertical_refresh_rate_in_milliHz,
  580. *pMHL2_video_descriptor);
  581. }
  582. if (!this_mode_doable) {
  583. return false;
  584. }
  585. }
  586. }
  587. return true;
  588. }
  589. /*
  590. static uint8_t si_mhl_tx_parse_861_long_descriptors(edid_3d_data_p mhl_edid_3d_data,uint8_t *p_EDID_block_data)
  591. {
  592. PCEA_extension_t p_CEA_extension = (PCEA_extension_t)p_EDID_block_data;
  593. if (!p_CEA_extension->byte_offset_to_18_byte_descriptors) {
  594. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  595. "EDID -> No Detailed Descriptors\n");
  596. return EDID_NO_DETAILED_DESCRIPTORS;
  597. } else {
  598. uint8_t *puc_next_block;
  599. uint8_t descriptor_num = 1;
  600. union
  601. {
  602. uint8_t *puc_data_block;
  603. P_18_byte_descriptor_u p_long_descriptors;
  604. }p_data_u;
  605. p_data_u.p_long_descriptors= (P_18_byte_descriptor_u)(((uint8_t *)p_CEA_extension) + p_CEA_extension->byte_offset_to_18_byte_descriptors);
  606. puc_next_block = ((uint8_t *)p_CEA_extension) + EDID_BLOCK_SIZE;
  607. while ((uint8_t *)(p_data_u.p_long_descriptors + 1) < puc_next_block) {
  608. uint8_t is_timing=0;
  609. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  610. "Parse Results - CEA-861 Long Descriptor #%d:\n",
  611. (int) descriptor_num);
  612. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  613. "===============================================================\n");
  614. if (!si_mhl_tx_parse_detailed_timing_descriptor(mhl_edid_3d_data,p_data_u.p_long_descriptors, EDID_BLOCK_2_3,&is_timing,NULL)) {
  615. break;
  616. }
  617. p_data_u.p_long_descriptors++;
  618. descriptor_num++;
  619. }
  620. return EDID_LONG_DESCRIPTORS_OK;
  621. }
  622. }
  623. */
  624. #ifdef CONFIG_MTK_HDMI_3D_SUPPORT
  625. static void si_mhl_tx_prune_edid(edid_3d_data_p mhl_edid_3d_data)
  626. {
  627. PEDID_block0_t p_EDID_block_0 = (PEDID_block0_t)&mhl_edid_3d_data->EDID_block_data[0];
  628. uint8_t dtd_limit;
  629. PCEA_extension_t p_CEA_extension = (PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE];
  630. Pblock_map_t p_block_map = NULL;
  631. uint8_t *pb_limit;
  632. union
  633. {
  634. uint8_t *puc_data_block;
  635. P_18_byte_descriptor_u p_long_descriptors;
  636. }p_data_u;
  637. if (EDID_EXTENSION_BLOCK_MAP == p_CEA_extension->tag) {
  638. /* save to overwrite later */
  639. p_block_map = (Pblock_map_t)p_CEA_extension;
  640. /* advance to next block */
  641. p_CEA_extension++;
  642. }
  643. pb_limit = (uint8_t *)(p_CEA_extension+1);
  644. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  645. "mhl_tx: %s\n",__FUNCTION__);
  646. p_data_u.puc_data_block = (uint8_t *)p_CEA_extension + p_CEA_extension->byte_offset_to_18_byte_descriptors;
  647. DUMP_EDID_BLOCK(0,p_EDID_block_0,sizeof(*p_EDID_block_0)) /* no semicolon needed here */
  648. /* zero out checksums before modifying data */
  649. p_CEA_extension->checksum=0;
  650. p_EDID_block_0->checksum = 0;
  651. /* Is there an HDMI VSDB? */
  652. if (mhl_edid_3d_data->parse_data.p_HDMI_vsdb) {
  653. PHDMI_LLC_vsdb_payload_t p_HDMI_vendor_specific_payload = &mhl_edid_3d_data->parse_data.p_HDMI_vsdb->payload_u.HDMI_LLC;
  654. uint8_t *p_next_db = (uint8_t *)p_HDMI_vendor_specific_payload +mhl_edid_3d_data->parse_data.p_HDMI_vsdb->header.fields.length_following_header;
  655. /* if deep color information is provided... */
  656. if (((uint8_t *)&p_HDMI_vendor_specific_payload->byte6) < p_next_db) {
  657. p_HDMI_vendor_specific_payload->byte6.DC_Y444 =0;
  658. p_HDMI_vendor_specific_payload->byte6.DC_30bit=0;
  659. p_HDMI_vendor_specific_payload->byte6.DC_36bit=0;
  660. p_HDMI_vendor_specific_payload->byte6.DC_48bit=0;
  661. }
  662. }
  663. /* prune the DTDs in block 0 */
  664. dtd_limit = sizeof(p_EDID_block_0->detailed_timing_descriptors)/sizeof(p_EDID_block_0->detailed_timing_descriptors[0]);
  665. si_mhl_tx_prune_dtd_list(mhl_edid_3d_data,(P_18_byte_descriptor_u)&p_EDID_block_0->detailed_timing_descriptors[0],dtd_limit);
  666. DUMP_EDID_BLOCK(0,p_EDID_block_0,sizeof(*p_EDID_block_0)) /* no semicolon needed here */
  667. DUMP_EDID_BLOCK(0,p_CEA_extension,sizeof(*p_CEA_extension)) /* no semicolon needed here */
  668. /* prune the DTDs in the CEA-861D extension */
  669. dtd_limit = (uint8_t)p_CEA_extension->version_u.version3.misc_support.total_number_detailed_timing_descriptors_in_entire_EDID;
  670. si_mhl_tx_prune_dtd_list(mhl_edid_3d_data,&p_data_u.p_long_descriptors[0],dtd_limit);
  671. /* adjust the mask according to which 2D VICs were set to zero */
  672. if (mhl_edid_3d_data->parse_data.p_3d_mask) {
  673. uint8_t lower_mask;
  674. uint32_t mask32;
  675. int8_t index = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[0]->header.fields.length_following_header-1;
  676. index = (index > 15) ? 15 : index;
  677. mask32 = 0xFFFF00 >> (15 - index);
  678. lower_mask = (index > 7) ? 0x7F : (0x7F >> (7 - index));
  679. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  680. "3d mask 15..8: 0x%02x",
  681. (uint16_t)mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_15_8);
  682. for (
  683. ; index >= 8
  684. ; mask32>>=1,lower_mask >>=1, --index) {
  685. if (0 == mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[0]->short_descriptors[index].VIC) {
  686. uint8_t lower_bits,upper_bits;
  687. uint8_t upper_mask;
  688. upper_mask = (uint8_t)mask32;
  689. /* preserve the lower bits */
  690. lower_bits = lower_mask & mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_15_8;
  691. /* and out the bit in question */
  692. upper_bits = upper_mask & mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_15_8;
  693. /* adjust the positions of the upper bits */
  694. upper_bits >>=1;
  695. mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_15_8 = lower_bits | upper_bits;
  696. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  697. "3d mask 15..8: 0x%02x",
  698. (uint16_t)mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_15_8);
  699. }
  700. }
  701. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  702. "3d mask 7..0: 0x%02x",
  703. (uint16_t)mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_7_0);
  704. lower_mask = 0x7F >> (7 - index);
  705. for (
  706. ; index >= 0
  707. ; mask32>>=1,lower_mask >>=1, --index) {
  708. if (0 == mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[0]->short_descriptors[index].VIC) {
  709. uint8_t lower_bits,upper_bits;
  710. uint8_t upper_mask;
  711. upper_mask = (uint8_t)mask32;
  712. /* preserve the lower bits */
  713. lower_bits = lower_mask & mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_7_0;
  714. /* AND out the bit in question */
  715. upper_bits = upper_mask & mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_7_0;
  716. /* adjust the positions of the upper bits */
  717. upper_bits >>=1;
  718. mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_7_0 = lower_bits | upper_bits;
  719. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  720. "3d mask 7..0: 0x%02x\n",
  721. (uint16_t)mhl_edid_3d_data->parse_data.p_3d_mask->_3D_mask_7_0);
  722. }
  723. }
  724. }
  725. if (mhl_edid_3d_data->parse_data.p_three_d) {
  726. uint8_t num_3D_structure_bytes_pruned=0;
  727. union
  728. {
  729. P_3D_structure_and_detail_entry_u p_3D;
  730. P_3D_structure_and_detail_entry_sans_byte1_t p_sans_byte_1;
  731. P_3D_structure_and_detail_entry_with_byte1_t p_with_byte_1;
  732. uint8_t *p_as_bytes;
  733. }p_3D_u;
  734. uint32_t deletion_mask=0;
  735. uint8_t limit_2D_VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[0]->header.fields.length_following_header;
  736. /*
  737. prior to moving things around,
  738. make a bitmap of the positions of the VICs that are zero
  739. */
  740. {
  741. uint8_t i;
  742. uint32_t this_bit;
  743. for (i =0,this_bit=1; i < limit_2D_VIC;++i,this_bit<<=1)
  744. {
  745. uint8_t VIC;
  746. VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[0]->short_descriptors[i].VIC;
  747. if (0 == VIC)
  748. {
  749. // set the bit that corresponds to the VIC that was set to zero
  750. deletion_mask |= this_bit;
  751. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"vic: 0x%02x deletion_mask:0x%08x this_bit:0x%08x\n"
  752. ,VIC ,deletion_mask ,this_bit
  753. );
  754. }
  755. }
  756. }
  757. p_3D_u.p_3D = mhl_edid_3d_data->parse_data.p_three_d;
  758. while ( p_3D_u.p_as_bytes < mhl_edid_3d_data->parse_data.p_3d_limit) {
  759. uint8_t _2D_VIC_order = p_3D_u.p_sans_byte_1->byte0._2D_VIC_order;
  760. _3D_structure_e _3D_structure = p_3D_u.p_sans_byte_1->byte0._3D_structure;
  761. uint8_t VIC;
  762. VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[0]->short_descriptors[_2D_VIC_order].VIC;
  763. if (0 == VIC) {
  764. /* delete this 3D_Structure/3D_detail information */
  765. uint8_t *pSrc,*pDest=p_3D_u.p_as_bytes;
  766. if (_3D_structure < tdsSideBySide) {
  767. pSrc = (uint8_t *)(p_3D_u.p_sans_byte_1+1);
  768. num_3D_structure_bytes_pruned += sizeof(*p_3D_u.p_sans_byte_1);
  769. } else {
  770. pSrc = (uint8_t *)(p_3D_u.p_with_byte_1+1);
  771. num_3D_structure_bytes_pruned += sizeof(*p_3D_u.p_with_byte_1);
  772. }
  773. while (pSrc < pb_limit) {
  774. *pDest++=*pSrc++;
  775. }
  776. while (pDest < pb_limit) {
  777. *pDest++=0;
  778. }
  779. } else {
  780. uint8_t i;
  781. uint8_t limit = _2D_VIC_order;
  782. uint32_t this_bit;
  783. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"2D vic order: 0x%02x deletion_mask:0x%08x\n"
  784. ,_2D_VIC_order
  785. ,deletion_mask
  786. );
  787. for (i = 0,this_bit=1; i < limit;++i,this_bit<<=1)
  788. {
  789. if (this_bit & deletion_mask)
  790. {
  791. _2D_VIC_order--;
  792. }
  793. }
  794. p_3D_u.p_sans_byte_1->byte0._2D_VIC_order = _2D_VIC_order;
  795. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"2D vic order: 0x%02x this_bit:0x%08x\n"
  796. ,_2D_VIC_order
  797. ,this_bit
  798. );
  799. if (_3D_structure < tdsSideBySide) {
  800. p_3D_u.p_sans_byte_1++;
  801. } else {
  802. p_3D_u.p_with_byte_1++;
  803. }
  804. }
  805. }
  806. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"num_3D_structure_bytes_pruned:0x%x "
  807. "byte14: 0x%02x "
  808. "offset to DTDs: 0x%x "
  809. "vsdb header: 0x%x\n"
  810. ,num_3D_structure_bytes_pruned
  811. ,*((uint8_t *)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14)
  812. ,p_CEA_extension->byte_offset_to_18_byte_descriptors
  813. ,*((uint8_t *)&mhl_edid_3d_data->parse_data.p_HDMI_vsdb->header)
  814. );
  815. mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14.HDMI_3D_len -= num_3D_structure_bytes_pruned;
  816. p_CEA_extension->byte_offset_to_18_byte_descriptors -= num_3D_structure_bytes_pruned;
  817. mhl_edid_3d_data->parse_data.p_HDMI_vsdb->header.fields.length_following_header -= num_3D_structure_bytes_pruned;
  818. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"num_3D_structure_bytes_pruned:0x%x "
  819. "byte14: 0x%02x "
  820. "offset to DTDs: 0x%x "
  821. "vsdb header: 0x%x\n"
  822. ,num_3D_structure_bytes_pruned
  823. ,*((uint8_t *)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14)
  824. ,p_CEA_extension->byte_offset_to_18_byte_descriptors
  825. ,*((uint8_t *)&mhl_edid_3d_data->parse_data.p_HDMI_vsdb->header)
  826. );
  827. }
  828. /* now prune the HDMI VSDB VIC list */
  829. if (mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15) {
  830. uint8_t length_VIC= mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14.HDMI_VIC_len;
  831. if (0 ==length_VIC) {
  832. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  833. "length_VIC:%d \n",(uint16_t)length_VIC);
  834. } else {
  835. uint8_t i,num_HDMI_VICs_pruned=0;
  836. uint8_t inner_loop_limit;
  837. uint8_t outer_loop_limit;
  838. inner_loop_limit = length_VIC;
  839. outer_loop_limit = length_VIC - 1;
  840. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  841. "length_VIC:%d inner_loop_limit: %d outer_loop_limit: %d \n",
  842. (uint16_t)length_VIC,(uint16_t)inner_loop_limit,
  843. (uint16_t)outer_loop_limit);
  844. for (i=0; i < outer_loop_limit;) {
  845. if (0 == mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[i]) {
  846. uint8_t j,prev;
  847. for (prev=i,j = i+1; j < inner_loop_limit;++j,++prev) {
  848. uint16_t VIC0,VIC1;
  849. VIC0 = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[prev];
  850. VIC1 = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[j];
  851. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  852. "replacing VIC: %3d at index: %3d with "\
  853. "VIC:%3d from index: %3d \n"
  854. ,VIC0
  855. ,(uint16_t)prev
  856. ,VIC1
  857. ,(uint16_t)j
  858. );
  859. mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[prev]
  860. = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[j];
  861. }
  862. /* we just removed one */
  863. num_HDMI_VICs_pruned++;
  864. inner_loop_limit--;
  865. outer_loop_limit--;
  866. } else {
  867. /* this mode is doable on MHL, so move on to the next index */
  868. ++i;
  869. }
  870. }
  871. /* check the last one */
  872. if (0 == mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[outer_loop_limit]) {
  873. num_HDMI_VICs_pruned++;
  874. inner_loop_limit--;
  875. }
  876. DUMP_EDID_BLOCK(0,p_CEA_extension,sizeof(*p_CEA_extension)) /* no semicolon needed here */
  877. /* now move all other data up */
  878. if (num_HDMI_VICs_pruned) {
  879. uint8_t *pb_dest = (uint8_t *)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[inner_loop_limit];
  880. uint8_t *pb_src = (uint8_t *)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[length_VIC];
  881. SII_ASSERT(EDID_BLOCK_SIZE==sizeof(*p_CEA_extension),("\n\n unexpected extension size\n\n"));
  882. while(pb_src < pb_limit) {
  883. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  884. "moving data up %02x(0x%02x) <- %02x(0x%02x)\n",
  885. pb_dest,(uint16_t)*pb_dest,pb_src,(uint16_t)*pb_src);
  886. *pb_dest++=*pb_src++;
  887. }
  888. while(pb_dest < pb_limit) {
  889. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  890. "clearing data %02x <- 0\n",pb_dest);
  891. *pb_dest++=0;
  892. }
  893. }
  894. mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14.HDMI_VIC_len = inner_loop_limit;
  895. p_CEA_extension->byte_offset_to_18_byte_descriptors -= num_HDMI_VICs_pruned;
  896. MHL_TX_EDID_INFO(,"%p\n",mhl_edid_3d_data->parse_data.p_HDMI_vsdb);
  897. if (mhl_edid_3d_data->parse_data.p_HDMI_vsdb){
  898. mhl_edid_3d_data->parse_data.p_HDMI_vsdb->header.fields.length_following_header -= num_HDMI_VICs_pruned;
  899. }else if (num_HDMI_VICs_pruned){
  900. MHL_TX_DBG_ERR(,"How can you have HDMI vics to prune if you have no HDMI VSDB?\n");
  901. }
  902. }
  903. }
  904. /* Now prune the SVD list and move the CEA 861-D data blocks and DTDs up */
  905. {
  906. uint8_t i,num_CEA_VICs_pruned=0;
  907. /*
  908. pack each vdb to eliminate the bytes that have been zeroed.
  909. */
  910. int8_t vdb_index;
  911. for (vdb_index =mhl_edid_3d_data->parse_data.num_video_data_blocks-1
  912. ;vdb_index >= 0 ;--vdb_index) {
  913. uint8_t inner_loop_limit = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->header.fields.length_following_header;
  914. if (inner_loop_limit) {
  915. uint8_t outer_loop_limit = inner_loop_limit-1;
  916. for (i=0; i < outer_loop_limit;) {
  917. if (0 == mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[i].VIC) {
  918. uint8_t j,prev;
  919. num_CEA_VICs_pruned++;
  920. for (prev=i,j = i+1; j < inner_loop_limit;++j,++prev) {
  921. uint16_t VIC0,VIC1;
  922. VIC0 = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[prev].VIC;
  923. VIC1 = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[j].VIC;
  924. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  925. "replacing SVD:%6s 0x%02x at index: 0x%02x with "\
  926. "SVD:%6s 0x%02x from index: 0x%02x \n"
  927. ,mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->
  928. short_descriptors[prev].native ? "Native":""
  929. ,VIC0
  930. ,(uint16_t)prev
  931. ,mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->
  932. short_descriptors[j].native ? "Native":""
  933. ,VIC1
  934. ,(uint16_t)j
  935. );
  936. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[prev]
  937. = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[j];
  938. }
  939. /* we just removed one */
  940. inner_loop_limit--;
  941. outer_loop_limit--;
  942. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context
  943. ,"outer_loop_limit:0x%x inner_loop_limit:0x%x\n"
  944. , (uint16_t)outer_loop_limit
  945. , (uint16_t)inner_loop_limit
  946. );
  947. } else {
  948. /* this mode is doable on MHL, so move on to the next index */
  949. ++i;
  950. }
  951. }
  952. /* check the last one */
  953. if (0 == mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[outer_loop_limit].VIC) {
  954. num_CEA_VICs_pruned++;
  955. inner_loop_limit--;
  956. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[outer_loop_limit].native=0;
  957. }
  958. DUMP_EDID_BLOCK(0,p_CEA_extension,sizeof(*p_CEA_extension)) /* no semicolon needed here */
  959. /* now move all other data up */
  960. {
  961. uint8_t *pb_dest = (uint8_t *)&mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[inner_loop_limit];
  962. uint8_t *pb_src= (uint8_t *)&mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->header.fields.length_following_header];
  963. SII_ASSERT(EDID_BLOCK_SIZE==sizeof(*p_CEA_extension),("\n\n unexpected extension size\n\n"));
  964. while(pb_src < pb_limit) {
  965. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  966. "moving data up %p(0x%02x) <- %p(0x%02x)\n",
  967. pb_dest,(uint16_t)*pb_dest,pb_src,(uint16_t)*pb_src);
  968. *pb_dest++=*pb_src++;
  969. }
  970. while(pb_dest < pb_limit) {
  971. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  972. "clearing data %02x <- 0\n", *pb_dest);
  973. *pb_dest++=0;
  974. }
  975. }
  976. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  977. "CEA-861-D DTDs began at 0x%02x" \
  978. "CEA-861-D SVD count: 0x%x\n"
  979. ,(uint16_t)p_CEA_extension->byte_offset_to_18_byte_descriptors
  980. ,(uint16_t)mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->
  981. header.fields.length_following_header);
  982. p_CEA_extension->byte_offset_to_18_byte_descriptors -= num_CEA_VICs_pruned;
  983. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->header.fields.length_following_header = inner_loop_limit;
  984. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  985. "CEA-861-D DTDs now begin at 0x%02x" \
  986. "CEA-861-D SVD count: 0x%x\n"
  987. ,(uint16_t)p_CEA_extension->byte_offset_to_18_byte_descriptors
  988. ,(uint16_t)mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->
  989. header.fields.length_following_header);
  990. DUMP_EDID_BLOCK(0,p_CEA_extension,sizeof(*p_CEA_extension)) /* no semicolon needed here */
  991. }
  992. }
  993. }
  994. /* re-compute the checksum(s) */
  995. SII_ASSERT(EDID_BLOCK_SIZE==sizeof(*p_EDID_block_0),("\n\n unexpected size for block 0\n\n"));
  996. SII_ASSERT(EDID_BLOCK_SIZE==sizeof(*p_CEA_extension),("\n\n unexpected size for CEA extension\n\n"));
  997. if (p_block_map) {
  998. PCEA_extension_t p_CEA_extensionDest=(PCEA_extension_t)p_block_map;
  999. *p_CEA_extensionDest = *p_CEA_extension;
  1000. }
  1001. p_EDID_block_0->checksum = calculate_generic_checksum((uint8_t *)p_EDID_block_0,0,sizeof(*p_EDID_block_0));
  1002. p_CEA_extension->checksum=calculate_generic_checksum((uint8_t *)p_CEA_extension,0,sizeof(*p_CEA_extension));
  1003. DUMP_EDID_BLOCK(0,p_CEA_extension,sizeof(*p_CEA_extension)) /* no semicolon needed here */
  1004. /*
  1005. can be optimized: adjust all pointers into the EDID along the way of pruning the contents, instead of re-parsing here
  1006. */
  1007. #ifndef EDID_PASSTHROUGH //(
  1008. if (0 == si_mhl_tx_drv_set_upstream_edid(mhl_edid_3d_data->drv_context,mhl_edid_3d_data->EDID_block_data,2*EDID_BLOCK_SIZE))
  1009. #endif //)
  1010. {
  1011. SET_3D_FLAG(mhl_edid_3d_data,FLAGS_EDID_READ_DONE)
  1012. si_mhl_tx_drv_enable_video_path(mhl_edid_3d_data->drv_context);
  1013. }
  1014. }
  1015. #endif
  1016. /*
  1017. */
  1018. static uint8_t IsQualifiedMhlVIC(edid_3d_data_p mhl_edid_3d_data,uint8_t VIC,PMHL2_video_descriptor_t p_mhl2_video_descriptor)
  1019. {
  1020. uint8_t ret_val=0;
  1021. if (VIC > 0) {
  1022. ret_val= is_MHL_timing_mode(mhl_edid_3d_data,VIC_info[VIC].columns, VIC_info[VIC].rows, VIC_info[VIC].field_rate_in_milliHz,p_mhl2_video_descriptor,VIC);
  1023. if (vif_dual_frame_rate == VIC_info[VIC].fields.frame_rate_info) {
  1024. uint32_t field_rate_in_milliHz;
  1025. switch(VIC_info[VIC].field_rate_in_milliHz)
  1026. {
  1027. case 24000: /* 23.97 */
  1028. field_rate_in_milliHz = 23970;
  1029. break;
  1030. case 30000: /* 29.97 */
  1031. field_rate_in_milliHz = 29970;
  1032. break;
  1033. case 60000: /* 59.94 */
  1034. field_rate_in_milliHz = 59940;
  1035. break;
  1036. case 120000: /* 119.88 */
  1037. field_rate_in_milliHz = 119880;
  1038. break;
  1039. case 240000: /* 239.76 */
  1040. field_rate_in_milliHz = 239760;
  1041. break;
  1042. default: /* error or unknown case */
  1043. field_rate_in_milliHz=0;
  1044. break;
  1045. }
  1046. ret_val |= is_MHL_timing_mode(mhl_edid_3d_data,VIC_info[VIC].columns, VIC_info[VIC].rows, field_rate_in_milliHz,p_mhl2_video_descriptor,VIC);
  1047. }
  1048. }
  1049. return ret_val;
  1050. }
  1051. /* HDMI_VIC is a place holder, and not actually stored */
  1052. #define hdmi_vic_infoEntry(HDMI_VIC,columns,rows,FieldRate0,FieldRate1,pixel_clock_0,pixel_clock_1) \
  1053. {columns,rows,FieldRate0,FieldRate1,pixel_clock_0,pixel_clock_1}
  1054. PLACE_IN_CODE_SEG HDMI_VIC_info_t hdmi_vic_info[]=
  1055. {
  1056. hdmi_vic_infoEntry( 0, 0, 0, 0, 0, 0, 0)
  1057. ,hdmi_vic_infoEntry( 1,3840,2160,30000,29970, 297000000,296703000)
  1058. ,hdmi_vic_infoEntry( 2,3840,2160,25000,25000, 297000000,297000000)
  1059. ,hdmi_vic_infoEntry( 3,3840,2160,24000,23976, 297000000,296703000)
  1060. ,hdmi_vic_infoEntry( 4,4096,2160,24000,24000, 297000000,297000000)
  1061. };
  1062. /*
  1063. */
  1064. static uint8_t is_qualified_mhl_hdmi_vic(edid_3d_data_p mhl_edid_3d_data,uint8_t VIC,PMHL2_video_descriptor_t pMHL2_video_descriptor)
  1065. {
  1066. uint8_t ret_val=0;
  1067. if (qualify_pixel_clock_for_mhl(mhl_edid_3d_data, hdmi_vic_info[VIC].pixel_clock_0, 24)) {
  1068. display_timing_enumeration_callback(mhl_edid_3d_data,
  1069. hdmi_vic_info[VIC].columns, hdmi_vic_info[VIC].rows, 24,
  1070. hdmi_vic_info[VIC].field_rate_0_in_milliHz,
  1071. *pMHL2_video_descriptor);
  1072. ret_val = 1;
  1073. }
  1074. if (qualify_pixel_clock_for_mhl(mhl_edid_3d_data,hdmi_vic_info[VIC].pixel_clock_0, 16)) {
  1075. display_timing_enumeration_callback(mhl_edid_3d_data,
  1076. hdmi_vic_info[VIC].columns, hdmi_vic_info[VIC].rows, 16,
  1077. hdmi_vic_info[VIC].field_rate_0_in_milliHz,*pMHL2_video_descriptor);
  1078. ret_val = 1;
  1079. }
  1080. if (hdmi_vic_info[VIC].pixel_clock_0 != hdmi_vic_info[VIC].pixel_clock_1) {
  1081. if (qualify_pixel_clock_for_mhl(mhl_edid_3d_data,hdmi_vic_info[VIC].pixel_clock_1, 24)) {
  1082. display_timing_enumeration_callback(mhl_edid_3d_data,
  1083. hdmi_vic_info[VIC].columns, hdmi_vic_info[VIC].rows, 24,
  1084. hdmi_vic_info[VIC].field_rate_1_in_milliHz,
  1085. *pMHL2_video_descriptor);
  1086. ret_val = 1;
  1087. }
  1088. if (qualify_pixel_clock_for_mhl(mhl_edid_3d_data,hdmi_vic_info[VIC].pixel_clock_1, 16)) {
  1089. display_timing_enumeration_callback(mhl_edid_3d_data,
  1090. hdmi_vic_info[VIC].columns, hdmi_vic_info[VIC].rows, 16,
  1091. hdmi_vic_info[VIC].field_rate_1_in_milliHz,
  1092. *pMHL2_video_descriptor);
  1093. ret_val = 1;
  1094. }
  1095. }
  1096. return ret_val;
  1097. }
  1098. void si_mhl_tx_enumerate_hdmi_vsdb(edid_3d_data_p mhl_edid_3d_data)
  1099. {
  1100. int8_t vdb_index=0;
  1101. if (mhl_edid_3d_data->parse_data.p_HDMI_vsdb) {
  1102. PHDMI_LLC_vsdb_payload_t p_HDMI_vendor_specific_payload = &mhl_edid_3d_data->parse_data.p_HDMI_vsdb->payload_u.HDMI_LLC;
  1103. uint8_t *p_next_db = (uint8_t *)p_HDMI_vendor_specific_payload +mhl_edid_3d_data->parse_data.p_HDMI_vsdb->header.fields.length_following_header;
  1104. /* if 3D_present field is included */
  1105. if (mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15) {
  1106. if (((uint8_t *)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte13) < p_next_db) {
  1107. uint8_t hdmi3D_present = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte13._3D_present;
  1108. uint8_t hdmi_3D_multi_present = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte13._3D_multi_present;
  1109. /* if HDMI_VIC_len is present... */
  1110. if (((uint8_t *)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14) < p_next_db) {
  1111. uint8_t length_VIC;
  1112. uint8_t index;
  1113. MHL2_video_descriptor_t mhl2_video_descriptor;
  1114. length_VIC = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14.HDMI_VIC_len;
  1115. mhl2_video_descriptor.left_right = 0;
  1116. mhl2_video_descriptor.top_bottom = 0;
  1117. mhl2_video_descriptor.frame_sequential= 0;
  1118. for (index = 0; index < length_VIC;++index) {
  1119. uint8_t VIC;
  1120. VIC = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[index];
  1121. if (!is_qualified_mhl_hdmi_vic(mhl_edid_3d_data,VIC,&mhl2_video_descriptor)) {
  1122. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1123. "'can't do HDMI VIC:%d\n",(uint16_t)VIC);
  1124. mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[index] = 0;
  1125. }
  1126. }
  1127. if (hdmi3D_present) {
  1128. uint8_t length_3D;
  1129. PHDMI_3D_sub_block_t pThree3DSubBlock= (PHDMI_3D_sub_block_t)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[length_VIC];
  1130. union
  1131. {
  1132. P_3D_structure_and_detail_entry_u p_3D;
  1133. P_3D_structure_and_detail_entry_sans_byte1_t p_sans_byte_1;
  1134. P_3D_structure_and_detail_entry_with_byte1_t p_with_byte_1;
  1135. uint8_t *p_as_bytes;
  1136. }p_3D_u;
  1137. uint8_t limit;
  1138. p_3D_u.p_3D=NULL;
  1139. length_3D = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14.HDMI_3D_len;
  1140. limit =mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->header.fields.length_following_header;
  1141. /* only do the first 16 */
  1142. limit = (limit > 16)?16:limit;
  1143. switch(hdmi_3D_multi_present)
  1144. {
  1145. case 0x00:
  1146. /* 3D_Structure_ALL_15..0 and 3D_MASK_15..0 fields are not present */
  1147. p_3D_u.p_3D = &pThree3DSubBlock->hDMI_3D_sub_block_sans_all_AND_mask._3D_structure_and_detail_list[0];
  1148. break;
  1149. case 0x01:
  1150. /*
  1151. 3D_Structure_ALL_15..0 is present and assigns 3D formats
  1152. to all of the VICs listed in the first 16 entries in the EDID
  1153. 3D_mask_15..0 is not present
  1154. */
  1155. {
  1156. P_3D_structure_all_t p_3D_structure_all=(P_3D_structure_all_t)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[length_VIC];
  1157. mhl2_video_descriptor.left_right = p_3D_structure_all->_3D_structure_all_7_0.side_by_side;
  1158. mhl2_video_descriptor.top_bottom = p_3D_structure_all->_3D_structure_all_15_8.top_bottom;
  1159. mhl2_video_descriptor.frame_sequential= p_3D_structure_all->_3D_structure_all_15_8.frame_packing;
  1160. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1161. for (index = 0; index < limit;++index) {
  1162. uint8_t VIC;
  1163. VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[index].VIC;
  1164. if (VIC) {
  1165. if (!IsQualifiedMhlVIC(mhl_edid_3d_data,VIC,&mhl2_video_descriptor)) {
  1166. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[index].VIC=0;
  1167. }
  1168. }
  1169. }
  1170. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1171. length_3D -= sizeof(*p_3D_structure_all);
  1172. }
  1173. p_3D_u.p_3D = &pThree3DSubBlock->HDMI_3D_sub_block_sans_mask._3D_structure_and_detail_list[0];
  1174. break;
  1175. case 0x02:
  1176. /*
  1177. 3D_Structure_ALL_15..0 and 3D_mask_15..0 are present and
  1178. assign 3D formats to some of the VICS listed in the first
  1179. 16 entries in the EDID
  1180. */
  1181. {
  1182. P_3D_structure_all_t p_3D_structure_all=(P_3D_structure_all_t)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->vicList[length_VIC];
  1183. P_3D_mask_t p3DMask = (P_3D_mask_t)(p_3D_structure_all+1);
  1184. uint8_t mask;
  1185. mhl2_video_descriptor.left_right = p_3D_structure_all->_3D_structure_all_7_0.side_by_side;
  1186. mhl2_video_descriptor.top_bottom = p_3D_structure_all->_3D_structure_all_15_8.top_bottom;
  1187. mhl2_video_descriptor.frame_sequential= p_3D_structure_all->_3D_structure_all_15_8.frame_packing;
  1188. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1189. for (mask=1,index = 0; (mask > 0) && (index < limit);++index,mask<<=1) {
  1190. uint8_t VIC;
  1191. MHL2_video_descriptor_t this_MHL2_video_descriptor;
  1192. if (mask & p3DMask->_3D_mask_7_0) {
  1193. this_MHL2_video_descriptor = mhl2_video_descriptor;
  1194. } else {
  1195. this_MHL2_video_descriptor.left_right = 0;
  1196. this_MHL2_video_descriptor.top_bottom = 0;
  1197. this_MHL2_video_descriptor.frame_sequential= 0;
  1198. }
  1199. VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[index].VIC;
  1200. if (VIC) {
  1201. if (!IsQualifiedMhlVIC(mhl_edid_3d_data,VIC,&mhl2_video_descriptor)) {
  1202. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[index].VIC=0;
  1203. }
  1204. }
  1205. }
  1206. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1207. for (mask=1;(mask > 0) && (index < limit);++index,mask<<=1) {
  1208. uint8_t VIC;
  1209. MHL2_video_descriptor_t this_MHL2_video_descriptor;
  1210. if (mask & p3DMask->_3D_mask_15_8) {
  1211. this_MHL2_video_descriptor = mhl2_video_descriptor;
  1212. } else {
  1213. this_MHL2_video_descriptor.left_right = 0;
  1214. this_MHL2_video_descriptor.top_bottom = 0;
  1215. this_MHL2_video_descriptor.frame_sequential= 0;
  1216. }
  1217. VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[index].VIC;
  1218. if (VIC) {
  1219. if (!IsQualifiedMhlVIC(mhl_edid_3d_data,VIC,&mhl2_video_descriptor)) {
  1220. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[index].VIC=0;
  1221. }
  1222. }
  1223. }
  1224. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1225. length_3D -= sizeof(*p_3D_structure_all);
  1226. length_3D -= sizeof(*p3DMask);
  1227. }
  1228. p_3D_u.p_3D = &pThree3DSubBlock->HDMI_3D_sub_block_with_all_AND_mask._3D_structure_and_detail_list[0];
  1229. mhl_edid_3d_data->parse_data.p_3d_mask = &pThree3DSubBlock->HDMI_3D_sub_block_with_all_AND_mask._3D_mask;
  1230. break;
  1231. case 0x03:
  1232. /*
  1233. Reserved for future use.
  1234. 3D_Structure_ALL_15..0 and 3D_mask_15..0 are NOT present
  1235. */
  1236. p_3D_u.p_3D = &pThree3DSubBlock->hDMI_3D_sub_block_sans_all_AND_mask._3D_structure_and_detail_list[0];
  1237. break;
  1238. }
  1239. mhl_edid_3d_data->parse_data.p_three_d =p_3D_u.p_3D;
  1240. mhl_edid_3d_data->parse_data.p_3d_limit = &p_3D_u.p_as_bytes[length_3D];
  1241. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1242. while ( p_3D_u.p_as_bytes < mhl_edid_3d_data->parse_data.p_3d_limit) {
  1243. uint8_t _2D_VIC_order = p_3D_u.p_sans_byte_1->byte0._2D_VIC_order;
  1244. _3D_structure_e _3D_structure = p_3D_u.p_sans_byte_1->byte0._3D_structure;
  1245. uint8_t VIC;
  1246. VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[_2D_VIC_order].VIC;
  1247. /* this VIC position might have gotten disqualified already */
  1248. if (VIC) {
  1249. mhl2_video_descriptor.left_right = 0;
  1250. mhl2_video_descriptor.top_bottom = 0;
  1251. mhl2_video_descriptor.frame_sequential = 0;
  1252. switch(_3D_structure)
  1253. {
  1254. case tdsSideBySide:
  1255. {
  1256. //re-visit uint8_t _3D_detail = p_3D_u.p_with_byte_1->byte1._3D_detail;
  1257. mhl2_video_descriptor.left_right = 1;
  1258. }
  1259. break;
  1260. case tdsTopAndBottom:
  1261. mhl2_video_descriptor.top_bottom = 1;
  1262. break;
  1263. case tdsFramePacking:
  1264. mhl2_video_descriptor.frame_sequential = 1;
  1265. break;
  1266. }
  1267. if (!IsQualifiedMhlVIC(mhl_edid_3d_data,VIC,&mhl2_video_descriptor)) {
  1268. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[vdb_index]->short_descriptors[_2D_VIC_order].VIC=0;
  1269. }
  1270. }
  1271. if (_3D_structure < tdsSideBySide) {
  1272. p_3D_u.p_sans_byte_1++;
  1273. } else {
  1274. p_3D_u.p_with_byte_1++;
  1275. }
  1276. }
  1277. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1278. }
  1279. }
  1280. }
  1281. }
  1282. }
  1283. }
  1284. static void si_mhl_tx_display_timing_enumeration_end(edid_3d_data_p mhl_edid_3d_data)
  1285. {
  1286. mhl_edid_3d_data->parse_data.flags.parse_3d_in_progress = 0;
  1287. /* finish off with any 3D modes reported via the HDMI VSDB */
  1288. si_mhl_tx_enumerate_hdmi_vsdb(mhl_edid_3d_data);
  1289. /* notify the app (board specific) layer */
  1290. display_timing_enumeration_end(mhl_edid_3d_data);
  1291. SET_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_DONE);
  1292. #ifdef CONFIG_MTK_HDMI_3D_SUPPORT
  1293. si_mhl_tx_prune_edid(mhl_edid_3d_data);
  1294. #else
  1295. SET_3D_FLAG(mhl_edid_3d_data,FLAGS_EDID_READ_DONE)
  1296. si_mhl_tx_drv_enable_video_path(mhl_edid_3d_data->drv_context); // //TODO: FD, TBI, debug?
  1297. #endif
  1298. }
  1299. static void CheckForAll3DBurstDone(edid_3d_data_p mhl_edid_3d_data)
  1300. {
  1301. if (TEST_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_VIC_DONE)){
  1302. if (TEST_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_DTD_DONE)) {
  1303. if (!TEST_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_DONE)) {
  1304. si_mhl_tx_display_timing_enumeration_end(mhl_edid_3d_data);
  1305. }
  1306. }
  1307. }
  1308. }
  1309. /*
  1310. */
  1311. void si_mhl_tx_process_3d_vic_burst(
  1312. void *context
  1313. , PMHL2_video_format_data_t p_write_burst_data /* from 3D_REQ */
  1314. )
  1315. {
  1316. edid_3d_data_p mhl_edid_3d_data=(edid_3d_data_p)context;
  1317. uint8_t block_index = 0;
  1318. PMHL2_video_descriptor_t p_mhl2_video_descriptor;
  1319. //re-visit uint8_t edidLimit = mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte14.HDMI_3D_len;
  1320. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"burstEntryCount3D_VIC: %d\n",mhl_edid_3d_data->parse_data.burst_entry_count_3d_vic);
  1321. if ( mhl_edid_3d_data->parse_data.flags.parse_3d_in_progress) {
  1322. /* check to see if it's time to move on to the next block */
  1323. if (mhl_edid_3d_data->parse_data.vic_2d_index >= mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[mhl_edid_3d_data->parse_data.video_data_block_index]->header.fields.length_following_header) {
  1324. mhl_edid_3d_data->parse_data.video_data_block_index++;
  1325. if ( mhl_edid_3d_data->parse_data.video_data_block_index >= mhl_edid_3d_data->parse_data.num_video_data_blocks){
  1326. SET_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_VIC_DONE)
  1327. CheckForAll3DBurstDone(mhl_edid_3d_data);
  1328. return;
  1329. }
  1330. }
  1331. if (mhl_edid_3d_data->parse_data.burst_entry_count_3d_vic < mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[mhl_edid_3d_data->parse_data.video_data_block_index]->header.fields.length_following_header) {
  1332. /* each SVD is 1 byte long */
  1333. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1334. for (/* block_index is set to zero above */
  1335. ;(block_index < p_write_burst_data->num_entries_this_burst)
  1336. &&
  1337. (mhl_edid_3d_data->parse_data.burst_entry_count_3d_vic < p_write_burst_data->total_entries )
  1338. ;++block_index
  1339. ,++mhl_edid_3d_data->parse_data.burst_entry_count_3d_vic
  1340. ,++mhl_edid_3d_data->parse_data.vic_2d_index) {
  1341. uint8_t VIC;
  1342. uint8_t this_mode_doable=0;
  1343. /* check to see if it's time to move on to the next block */
  1344. if (mhl_edid_3d_data->parse_data.vic_2d_index >= mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[mhl_edid_3d_data->parse_data.video_data_block_index]->header.fields.length_following_header) {
  1345. mhl_edid_3d_data->parse_data.video_data_block_index++;
  1346. if ( mhl_edid_3d_data->parse_data.video_data_block_index >= mhl_edid_3d_data->parse_data.num_video_data_blocks){
  1347. SET_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_VIC_DONE)
  1348. break;
  1349. }
  1350. }
  1351. p_mhl2_video_descriptor = &p_write_burst_data->video_descriptors[block_index];
  1352. VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[mhl_edid_3d_data->parse_data.video_data_block_index]->short_descriptors[mhl_edid_3d_data->parse_data.vic_2d_index].VIC;
  1353. if (VIC) {
  1354. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1355. "short Descriptor[%d] 3D VIC: %d %s %s %s\n"
  1356. ,mhl_edid_3d_data->parse_data.burst_entry_count_3d_vic
  1357. ,VIC
  1358. ,p_mhl2_video_descriptor->left_right ?psz_left_right :psz_space
  1359. ,p_mhl2_video_descriptor->top_bottom ?psz_top_bottom :psz_space
  1360. ,p_mhl2_video_descriptor->frame_sequential?psz_frame_sequential:psz_space
  1361. );
  1362. this_mode_doable = IsQualifiedMhlVIC(mhl_edid_3d_data,VIC,p_mhl2_video_descriptor);
  1363. if (!this_mode_doable) {
  1364. /* prune this mode from EDID */
  1365. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1366. "'can't do CEA VIC:%d\n",(uint16_t)VIC);
  1367. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[mhl_edid_3d_data->parse_data.video_data_block_index]->short_descriptors[mhl_edid_3d_data->parse_data.vic_2d_index].VIC = 0;
  1368. }
  1369. }
  1370. }
  1371. DUMP_EDID_BLOCK(0,(PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE],EDID_BLOCK_SIZE) /* no semicolon needed here */
  1372. }
  1373. if ( mhl_edid_3d_data->parse_data.burst_entry_count_3d_vic >= p_write_burst_data->total_entries ) {
  1374. SET_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_VIC_DONE)
  1375. }
  1376. CheckForAll3DBurstDone(mhl_edid_3d_data);
  1377. }
  1378. }
  1379. void check_3d_dtd_sequence_done(edid_3d_data_p mhl_edid_3d_data
  1380. ,PMHL2_video_format_data_t p_write_burst_data,uint8_t dtd_limit)
  1381. {
  1382. int flag=0;
  1383. if (mhl_edid_3d_data->parse_data.cea_861_dtd_index>= dtd_limit) {
  1384. flag = 1;
  1385. }
  1386. if ( mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd >= p_write_burst_data->total_entries ) {
  1387. flag =1;
  1388. }
  1389. if (flag) {
  1390. SET_3D_FLAG(mhl_edid_3d_data, FLAGS_BURST_3D_DTD_DONE)
  1391. if (TEST_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_VIC_DONE)) {
  1392. if (!TEST_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_DONE)) {
  1393. si_mhl_tx_display_timing_enumeration_end(mhl_edid_3d_data);
  1394. }
  1395. }
  1396. }
  1397. }
  1398. void si_mhl_tx_process_3d_dtd_burst(void *context,PMHL2_video_format_data_t p_write_burst_data)
  1399. {
  1400. edid_3d_data_p mhl_edid_3d_data =(edid_3d_data_p)context;
  1401. PMHL2_video_descriptor_t p_mhl2_video_descriptor;
  1402. int burst_index=0;
  1403. uint8_t is_timing=0;
  1404. PCEA_extension_t p_CEA_extension = (PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE];
  1405. uint8_t dtd_limit = (uint8_t)p_CEA_extension->version_u.version3.misc_support.total_number_detailed_timing_descriptors_in_entire_EDID;
  1406. if ( mhl_edid_3d_data->parse_data.flags.parse_3d_in_progress) {
  1407. if (!TEST_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_DTD_VESA_DONE)) {
  1408. PEDID_block0_t p_EDID_block_0 = (PEDID_block0_t)&mhl_edid_3d_data->EDID_block_data[0];
  1409. /*
  1410. up to four DTDs are possible in the base VESA EDID
  1411. this will be covered by a single burst.
  1412. */
  1413. for (/* burst_index is set to zero above */
  1414. ;(burst_index < p_write_burst_data->num_entries_this_burst)
  1415. &&
  1416. (mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd < p_write_burst_data->total_entries )
  1417. &&
  1418. (mhl_edid_3d_data->parse_data.vesa_dtd_index < sizeof(p_EDID_block_0->detailed_timing_descriptors)/sizeof(p_EDID_block_0->detailed_timing_descriptors[0]))
  1419. ;++mhl_edid_3d_data->parse_data.vesa_dtd_index) {
  1420. P_18_byte_descriptor_u p_desc = (P_18_byte_descriptor_u)&p_EDID_block_0->detailed_timing_descriptors[mhl_edid_3d_data->parse_data.vesa_dtd_index];
  1421. bool is_valid=0;
  1422. p_mhl2_video_descriptor = &p_write_burst_data->video_descriptors[burst_index];
  1423. is_valid = si_mhl_tx_parse_detailed_timing_descriptor(
  1424. mhl_edid_3d_data, p_desc, EDID_BLOCK_0,
  1425. &is_timing, p_mhl2_video_descriptor);
  1426. /* only count it if it's a valid timing */
  1427. if (is_timing) {
  1428. if (is_valid) {
  1429. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1430. "VESA DTD index: %d burst index:%d DTD SP "\
  1431. "index:%d %s %s %s\n"
  1432. ,(uint16_t)mhl_edid_3d_data->parse_data.vesa_dtd_index,(uint16_t)burst_index,(uint16_t)mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd
  1433. ,p_mhl2_video_descriptor->left_right ?psz_left_right :psz_space
  1434. ,p_mhl2_video_descriptor->top_bottom ?psz_top_bottom :psz_space
  1435. ,p_mhl2_video_descriptor->frame_sequential?psz_frame_sequential:psz_space
  1436. );
  1437. } else {
  1438. /* mark this mode for pruning by setting horizontal active to zero */
  1439. p_desc->dtd.horz_active_7_0 = 0;
  1440. p_desc->dtd.horz_active_blanking_high.horz_active_11_8= 0;
  1441. }
  1442. burst_index++;
  1443. mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd++;
  1444. } else {
  1445. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1446. "VESA DTD index: %d\n",
  1447. (uint16_t)mhl_edid_3d_data->parse_data.vesa_dtd_index);
  1448. }
  1449. }
  1450. if (mhl_edid_3d_data->parse_data.vesa_dtd_index >= sizeof(p_EDID_block_0->detailed_timing_descriptors)/sizeof(p_EDID_block_0->detailed_timing_descriptors[0])) {
  1451. /* we got past the VESA DTDs in this burst */
  1452. SET_3D_FLAG(mhl_edid_3d_data, FLAGS_BURST_3D_DTD_VESA_DONE)
  1453. } else {
  1454. check_3d_dtd_sequence_done(mhl_edid_3d_data,p_write_burst_data,dtd_limit);
  1455. /* more VESA DTDs to process in next burst */
  1456. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"%s\n",TEST_3D_FLAG(mhl_edid_3d_data,FLAGS_BURST_3D_DTD_DONE)
  1457. ?"3D DTD descriptors exhausted"
  1458. :"more VESA DTDs to process");
  1459. return;
  1460. }
  1461. }
  1462. {
  1463. PCEA_extension_t p_CEA_extension = (PCEA_extension_t)&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE];
  1464. uint8_t dtd_limit = (uint8_t)p_CEA_extension->version_u.version3.misc_support.total_number_detailed_timing_descriptors_in_entire_EDID;
  1465. union
  1466. {
  1467. uint8_t *puc_data_block;
  1468. P_18_byte_descriptor_u p_long_descriptors;
  1469. }p_data_u;
  1470. p_data_u.p_long_descriptors= (P_18_byte_descriptor_u)(((uint8_t *)p_CEA_extension) + p_CEA_extension->byte_offset_to_18_byte_descriptors);
  1471. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context
  1472. ,"continuing with CEA-861-D/E DTDs"
  1473. "\n\tburst_index: %d"
  1474. "\n\tburst_entry_count_3d_dtd: %d"
  1475. "\n\tnum_entries_this_burst: %d"
  1476. "\n\ttotal_entries:%d"
  1477. "\n\tdtd_limit:%d"
  1478. "\n\toffsetTo18_byte_descriptors:0x%x\n"
  1479. ,burst_index
  1480. ,mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd
  1481. ,p_write_burst_data->num_entries_this_burst
  1482. ,p_write_burst_data->total_entries
  1483. ,dtd_limit
  1484. ,p_CEA_extension->byte_offset_to_18_byte_descriptors
  1485. );
  1486. /* continue with CEA-861-D/E DTDs when done with VESA DTDs */
  1487. for (/* burst_index is set to zero above */
  1488. ;(burst_index < p_write_burst_data->num_entries_this_burst)
  1489. &&
  1490. (mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd < p_write_burst_data->total_entries )
  1491. &&
  1492. (mhl_edid_3d_data->parse_data.cea_861_dtd_index < dtd_limit)
  1493. ;++mhl_edid_3d_data->parse_data.cea_861_dtd_index) {
  1494. P_18_byte_descriptor_u p_desc = &p_data_u.p_long_descriptors[mhl_edid_3d_data->parse_data.cea_861_dtd_index];
  1495. bool is_valid=0;
  1496. p_mhl2_video_descriptor = &p_write_burst_data->video_descriptors[burst_index];
  1497. is_valid=si_mhl_tx_parse_detailed_timing_descriptor(mhl_edid_3d_data,p_desc, EDID_BLOCK_2_3,&is_timing,p_mhl2_video_descriptor);
  1498. /* only count it if it's a valid timing */
  1499. if (is_timing) {
  1500. if (is_valid) {
  1501. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1502. "CEA-861 DTD index: %d burst index:%d DTD "\
  1503. "SP index:%d %s %s %s\n\n"
  1504. ,(uint16_t)mhl_edid_3d_data->parse_data.cea_861_dtd_index,(uint16_t)burst_index,(uint16_t)mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd
  1505. ,p_mhl2_video_descriptor->left_right ?psz_left_right :psz_space
  1506. ,p_mhl2_video_descriptor->top_bottom ?psz_top_bottom :psz_space
  1507. ,p_mhl2_video_descriptor->frame_sequential?psz_frame_sequential:psz_space
  1508. );
  1509. } else {
  1510. /* mark this mode for pruning by setting horizontal active to zero */
  1511. p_desc->dtd.horz_active_7_0 = 0;
  1512. p_desc->dtd.horz_active_blanking_high.horz_active_11_8= 0;
  1513. }
  1514. ++burst_index;
  1515. ++mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd;
  1516. } else {
  1517. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1518. "CEA-861 DTD index: %d\n",
  1519. (uint16_t)mhl_edid_3d_data->parse_data.vesa_dtd_index);
  1520. }
  1521. }
  1522. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1523. "DTD burst complete\n");
  1524. check_3d_dtd_sequence_done(mhl_edid_3d_data,p_write_burst_data,dtd_limit);
  1525. }
  1526. }
  1527. }
  1528. /*
  1529. FUNCTION : si_mhl_tx_parse_established_timing()
  1530. PURPOSE : Parse the established timing section of EDID Block 0 and
  1531. print their decoded meaning to the screen.
  1532. INPUT PARAMS : Pointer to the array where the data read from EDID
  1533. Block0 is stored.
  1534. OUTPUT PARAMS: None
  1535. GLOBALS USED : None
  1536. RETURNS : Void
  1537. */
  1538. #define STRINGIZE(x) #x
  1539. #define DUMP_OFFSET(c,s,m) MHL_TX_EDID_INFO(c->dev_context, STRINGIZE(m)" offset:%x\n",SII_OFFSETOF(s,m) );
  1540. #define DUMP_ESTABLISHED_TIMING(context,group,width,height,refresh,progressive) \
  1541. if (p_EDID_block_0->group.et##width##x##height##_##refresh##Hz##progressive) { \
  1542. MHL_TX_EDID_INFO(context->dev_context, STRINGIZE(group)"."STRINGIZE(width)"x"STRINGIZE(height)"_"STRINGIZE(refresh)"Hz"STRINGIZE(progressive)"\n"); \
  1543. if (!is_MHL_timing_mode(mhl_edid_3d_data,width, height, refresh*1000,NULL,0)) { \
  1544. p_EDID_block_0->group.et##width##x##height##_##refresh##Hz##progressive = 0; \
  1545. } \
  1546. }
  1547. /*
  1548. static void si_mhl_tx_parse_established_timing (edid_3d_data_p mhl_edid_3d_data,PEDID_block0_t p_EDID_block_0)
  1549. {
  1550. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,header_data[0]);
  1551. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,id_manufacturer_name);
  1552. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,id_product_code);
  1553. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,serial_number[0]);
  1554. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,week_of_manufacture);
  1555. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,year_of_manufacture);
  1556. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,EDID_version);
  1557. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,EDID_revision);
  1558. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,video_input_definition);
  1559. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,horz_screen_size_or_aspect_ratio);
  1560. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,vert_screen_size_or_aspect_ratio);
  1561. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,display_transfer_characteristic);
  1562. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,feature_support);
  1563. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,red_green_bits_1_0);
  1564. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,blue_white_bits_1_0);
  1565. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,red_x);
  1566. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,red_y);
  1567. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,green_x);
  1568. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,green_y);
  1569. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,blue_x);
  1570. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,blue_y);
  1571. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,white_x);
  1572. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,white_y);
  1573. p_EDID_block_0->established_timings_II.et1280x1024_75Hz = 0;
  1574. p_EDID_block_0->manufacturers_timings.et1152x870_75Hz = 0;
  1575. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1576. "Parsing Established Timing:\n");
  1577. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1578. "===========================\n");
  1579. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,established_timings_I)
  1580. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_I,720,400,70,)
  1581. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_I,720,400,88,)
  1582. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_I,640,480,60,)
  1583. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_I,640,480,67,)
  1584. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_I,640,480,72,)
  1585. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_I,640,480,75,)
  1586. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_I,800,600,56,)
  1587. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_I,800,600,60,)
  1588. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_II, 800, 600,72,)
  1589. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_II, 800, 600,75,)
  1590. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_II, 832, 624,75,)
  1591. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_II,1024, 768,87,I)
  1592. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_II,1024, 768,60,)
  1593. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_II,1024, 768,70,)
  1594. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_II,1024, 768,75,)
  1595. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, established_timings_II,1280,1024,75,)
  1596. DUMP_OFFSET(mhl_edid_3d_data, EDID_block0_t,manufacturers_timings)
  1597. DUMP_ESTABLISHED_TIMING(mhl_edid_3d_data, manufacturers_timings,1152,870,75,)
  1598. if( (!p_EDID_block_0->header_data[0])
  1599. &&(0 == *((uint8_t *)&p_EDID_block_0->established_timings_II) )
  1600. &&(!p_EDID_block_0->header_data[2])
  1601. ) {
  1602. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1603. "No established video modes\n");
  1604. }
  1605. }
  1606. */
  1607. /*
  1608. FUNCTION : si_mhl_tx_parse_standard_timing()
  1609. PURPOSE : Parse the standard timing section of EDID Block 0 and
  1610. print their decoded meaning to the screen.
  1611. INPUT PARAMS : Pointer to the array where the data read from EDID
  1612. Block0 is stored.
  1613. OUTPUT PARAMS: None
  1614. GLOBALS USED : None
  1615. RETURNS : Void
  1616. */
  1617. /*
  1618. static void si_mhl_tx_parse_standard_timing(edid_3d_data_p mhl_edid_3d_data,PEDID_block0_t p_EDID_block_0)
  1619. {
  1620. uint8_t i;
  1621. uint8_t AR_code;
  1622. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context, "Parsing Standard Timing:\n");
  1623. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context, "========================\n");
  1624. for (i = 0; i < sizeof(p_EDID_block_0->standard_timings)/sizeof(p_EDID_block_0->standard_timings[0]); i += 2) {
  1625. if (
  1626. (1 == p_EDID_block_0->standard_timings[i].horz_pix_div_8_minus_31)
  1627. && (1 == p_EDID_block_0->standard_timings[i].field_refresh_rate_minus_60)
  1628. && (0 == p_EDID_block_0->standard_timings[i].image_aspect_ratio)
  1629. ) {
  1630. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1631. "Standard Timing Undefined\n");
  1632. } else {
  1633. uint16_t horz_active=(uint16_t)((p_EDID_block_0->standard_timings[i].horz_pix_div_8_minus_31 + 31)*8);
  1634. uint16_t vert_active=0;
  1635. uint16_t refresh_rate_in_milliHz = (uint16_t)(p_EDID_block_0->standard_timings[i].field_refresh_rate_minus_60+ 60)*1000;
  1636. char *psz_ratio_string="";
  1637. AR_code = p_EDID_block_0->standard_timings[i].image_aspect_ratio;
  1638. switch(AR_code)
  1639. {
  1640. case iar_16_to_10:
  1641. psz_ratio_string = "16:10";
  1642. vert_active = horz_active * 10/16;
  1643. break;
  1644. case iar_4_to_3:
  1645. psz_ratio_string = "4:3";
  1646. vert_active = horz_active * 3/ 4;
  1647. break;
  1648. case iar_5_to_4:
  1649. psz_ratio_string = "5:4";
  1650. vert_active = horz_active * 4/ 5;
  1651. break;
  1652. case iar_16_to_9:
  1653. psz_ratio_string = "16:9";
  1654. vert_active = horz_active * 9/16;
  1655. break;
  1656. }
  1657. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1658. "Aspect Ratio: %5s %4d x %4d at %3d Hz.\n",
  1659. psz_ratio_string, horz_active,vert_active,
  1660. refresh_rate_in_milliHz);
  1661. if (!is_MHL_timing_mode(mhl_edid_3d_data,horz_active, vert_active, refresh_rate_in_milliHz,NULL,0)) {
  1662. p_EDID_block_0->standard_timings[i].horz_pix_div_8_minus_31 = 1;
  1663. p_EDID_block_0->standard_timings[i].field_refresh_rate_minus_60 = 1;
  1664. p_EDID_block_0->standard_timings[i].image_aspect_ratio = 0;
  1665. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1666. "Disabled\n\n");
  1667. }
  1668. }
  1669. }
  1670. }
  1671. */
  1672. /*
  1673. FUNCTION : si_mhl_tx_parse_block_zero_timing_descriptors()
  1674. PURPOSE : Parse EDID Block 0 timing descriptors per EEDID 1.3
  1675. standard. printf() values to screen.
  1676. INPUT PARAMS : Pointer to the 128 byte array where the data read from EDID
  1677. Block0 is stored.
  1678. OUTPUT PARAMS: None
  1679. GLOBALS USED : None
  1680. RETURNS : Void
  1681. */
  1682. #if 0
  1683. static void si_mhl_tx_parse_block_zero_timing_descriptors(edid_3d_data_p mhl_edid_3d_data,PEDID_block0_t p_EDID_block_0)
  1684. {
  1685. uint8_t i;
  1686. uint8_t is_timing=0;
  1687. si_mhl_tx_parse_established_timing(mhl_edid_3d_data,p_EDID_block_0);
  1688. si_mhl_tx_parse_standard_timing(mhl_edid_3d_data,p_EDID_block_0);
  1689. for (i = 0; i < sizeof(p_EDID_block_0->detailed_timing_descriptors)/sizeof(p_EDID_block_0->detailed_timing_descriptors[0]); i++) {
  1690. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1691. "Parse Results, EDID Block #0, Detailed Descriptor Number %d:\n",
  1692. (int)i);
  1693. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1694. "===========================================================\n\n");
  1695. si_mhl_tx_parse_detailed_timing_descriptor(mhl_edid_3d_data,(P_18_byte_descriptor_u)&p_EDID_block_0->detailed_timing_descriptors[i], EDID_BLOCK_0,&is_timing,NULL);
  1696. }
  1697. }
  1698. #endif
  1699. /*
  1700. FUNCTION : bool si_mhl_tx_do_edid_checksum()
  1701. PURPOSE : Calculte checksum of the 128 byte block pointed to by the
  1702. pointer passed as parameter
  1703. INPUT PARAMS : Pointer to a 128 byte block whose checksum needs to be
  1704. calculated
  1705. OUTPUT PARAMS: None
  1706. GLOBALS USED : None
  1707. RETURNS : true if chcksum is 0. false if not.
  1708. */
  1709. static bool si_mhl_tx_do_edid_checksum(uint8_t *p_EDID_block_data)
  1710. {
  1711. uint8_t i;
  1712. uint8_t checksum = 0;
  1713. for (i = 0; i < EDID_BLOCK_SIZE; i++) {
  1714. checksum += p_EDID_block_data[i];
  1715. }
  1716. if (checksum) {
  1717. return false;
  1718. }
  1719. return true;
  1720. }
  1721. /*
  1722. FUNCTION : bool si_mhl_tx_check_edid_header()
  1723. PURPOSE : Checks if EDID header is correct per VESA E-EDID standard
  1724. Must be 00 FF FF FF FF FF FF 00
  1725. INPUT PARAMS : Pointer to EDID parser context area
  1726. Pointer to 1st EDID block
  1727. OUTPUT PARAMS: None
  1728. GLOBALS USED : None
  1729. RETURNS : true if Header is correct. false if not.
  1730. */
  1731. /* Block 0 */
  1732. #define EDID_OFFSET_HEADER_FIRST_00 0x00
  1733. #define EDID_OFFSET_HEADER_FIRST_FF 0x01
  1734. #define EDID_OFFSET_HEADER_LAST_FF 0x06
  1735. #define EDID_OFFSET_HEADER_LAST_00 0x07
  1736. static bool si_mhl_tx_check_edid_header(edid_3d_data_p mhl_edid_3d_data,
  1737. PEDID_block0_t p_EDID_block_0)
  1738. {
  1739. uint8_t i = 0;
  1740. if (0 != p_EDID_block_0->header_data[EDID_OFFSET_HEADER_FIRST_00]) {
  1741. DUMP_EDID_BLOCK(1,p_EDID_block_0,sizeof(*p_EDID_block_0))
  1742. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context
  1743. ,"EDID 0 first check failed\n\n\n");
  1744. return false;
  1745. }
  1746. for (i = EDID_OFFSET_HEADER_FIRST_FF; i <= EDID_OFFSET_HEADER_LAST_FF; i++) {
  1747. if(0xFF != p_EDID_block_0->header_data[i]) {
  1748. DUMP_EDID_BLOCK(1,p_EDID_block_0,sizeof(*p_EDID_block_0))
  1749. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context
  1750. ,"EDID -1 check failed\n");
  1751. return false;
  1752. }
  1753. }
  1754. if (0x00 != p_EDID_block_0->header_data[EDID_OFFSET_HEADER_LAST_00]) {
  1755. DUMP_EDID_BLOCK(1,p_EDID_block_0,sizeof(*p_EDID_block_0))
  1756. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context
  1757. ,"EDID 0 last check failed\n");
  1758. return false;
  1759. }
  1760. return true;
  1761. }
  1762. void SiiMhlTxMakeItDVI(edid_3d_data_p mhl_edid_3d_data,PEDID_block0_t p_EDID_block_0)
  1763. {
  1764. /* Make it DVI */
  1765. mhl_edid_3d_data->parse_data.HDMI_sink = false;
  1766. {
  1767. uint8_t *p_EDID_block_data =(uint8_t *)p_EDID_block_0;
  1768. uint8_t counter;
  1769. p_EDID_block_0->extension_flag = 0;
  1770. // blank out the second block of the upstream EDID
  1771. MHL_TX_DBG_INFO(mhl_edid_3d_data->dev_context,
  1772. "DVI EDID ...Setting second block to 0xFF %d\n",
  1773. (uint16_t)EDID_REV_ADDR_ERROR);
  1774. p_EDID_block_data += EDID_BLOCK_SIZE;
  1775. for (counter = 0; counter < EDID_BLOCK_SIZE; counter++)
  1776. p_EDID_block_data[counter] = 0xFF;
  1777. }
  1778. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context
  1779. ,"EDID: second block now all 0xFF\n");
  1780. }
  1781. #ifdef CONFIG_MTK_HDMI_3D_SUPPORT
  1782. static void SiiMhlTx3dReqForNonTranscodeMode( edid_3d_data_p mhl_edid_3d_data )
  1783. {
  1784. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1785. "Mhl2Tx: outputMode: %s\n",
  1786. mhl_edid_3d_data->parse_data.HDMI_sink ? "HDMI":"DVI");
  1787. if (mhl_edid_3d_data->parse_data.HDMI_sink) {
  1788. if (0x20 <= si_get_peer_mhl_version(mhl_edid_3d_data->dev_context)) {
  1789. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1790. "MHL 2.x sink detected\n");
  1791. mhl_edid_3d_data->parse_data.flags.parse_3d_in_progress = 1;
  1792. display_timing_enumeration_begin(mhl_edid_3d_data);
  1793. /* tell the sink to begin sending 3D write bursts */
  1794. si_mhl_tx_set_int( mhl_edid_3d_data->dev_context,MHL_RCHANGE_INT, MHL2_INT_3D_REQ,0);
  1795. mhl_edid_3d_data->parse_data.video_data_block_index=0;
  1796. mhl_edid_3d_data->parse_data.burst_entry_count_3d_dtd=0;
  1797. mhl_edid_3d_data->parse_data.vesa_dtd_index=0;
  1798. mhl_edid_3d_data->parse_data.burst_entry_count_3d_vic=0;
  1799. mhl_edid_3d_data->parse_data.vic_2d_index=0;
  1800. mhl_edid_3d_data->parse_data.vic_3d_index=0;
  1801. mhl_edid_3d_data->parse_data.cea_861_dtd_index=0;
  1802. SET_3D_FLAG(mhl_edid_3d_data, FLAGS_SENT_3D_REQ)
  1803. CLR_3D_FLAG(mhl_edid_3d_data, FLAGS_BURST_3D_DONE)
  1804. CLR_3D_FLAG(mhl_edid_3d_data, FLAGS_BURST_3D_VIC_DONE)
  1805. CLR_3D_FLAG(mhl_edid_3d_data, FLAGS_BURST_3D_DTD_VESA_DONE)
  1806. } else {
  1807. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1808. "MHL 1.x sink detected\n");
  1809. // EDID read need to be done in SW TPI mode, as it is done now, switch back to default TPI mode: HW TPI mode
  1810. si_mhl_tx_drv_set_hw_tpi_mode( mhl_edid_3d_data->drv_context, true );
  1811. si_mhl_tx_prune_edid(mhl_edid_3d_data);
  1812. }
  1813. } else {
  1814. #ifndef EDID_PASSTHROUGH //(
  1815. if (0 == si_mhl_tx_drv_set_upstream_edid(mhl_edid_3d_data->drv_context,mhl_edid_3d_data->EDID_block_data,2*EDID_BLOCK_SIZE))
  1816. #endif //)
  1817. {
  1818. // EDID read need to be done in SW TPI mode, as it is done now, switch back to default TPI mode: HW TPI mode
  1819. si_mhl_tx_drv_set_hw_tpi_mode( mhl_edid_3d_data->drv_context, true );
  1820. SET_3D_FLAG(mhl_edid_3d_data, FLAGS_EDID_READ_DONE);
  1821. si_mhl_tx_drv_enable_video_path(mhl_edid_3d_data->drv_context);
  1822. }
  1823. }
  1824. }
  1825. #endif
  1826. uint8_t CA=0;//Channel/Speaker Allocation.
  1827. uint8_t MAX_channel=2;//Channel.
  1828. uint8_t Samplebit;
  1829. uint8_t Cap_MAX_channel;
  1830. uint8_t Cap_Samplebit;
  1831. uint16_t Cap_SampleRate;
  1832. static uint8_t parse_861_short_descriptors (
  1833. edid_3d_data_p mhl_edid_3d_data
  1834. , uint8_t *p_EDID_block_data)
  1835. {
  1836. uint8_t i;
  1837. uint8_t p_speaker_payload;
  1838. PCEA_extension_t p_CEA_extension;
  1839. CA = 0;
  1840. p_CEA_extension= (PCEA_extension_t)p_EDID_block_data;
  1841. if (EDID_EXTENSION_TAG != p_CEA_extension->tag) {
  1842. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  1843. "EDID -> Non-CEA Extension\n");
  1844. return EDID_EXT_TAG_ERROR;
  1845. } else {
  1846. if (EDID_REV_THREE != p_CEA_extension->revision) {
  1847. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  1848. "EDID -> Non-HDMI EIA-861 Revision ID. Expected %02X. Got %02X\n",
  1849. (int)EDID_REV_THREE, (int)p_CEA_extension->revision);
  1850. return EDID_REV_ADDR_ERROR;
  1851. } else {
  1852. PCEA_extension_version_3_t p_CEA_extension_version_3 = &p_CEA_extension->version_u.version3;
  1853. union
  1854. {
  1855. uint8_t *puc_data_block;
  1856. PCEA_data_block_collection_t p_CEA_data_block;
  1857. }p_data_u;
  1858. uint8_t *puc_long_descriptors;
  1859. /* block offset where long descriptors start */
  1860. puc_long_descriptors= ((uint8_t *)p_CEA_extension) + p_CEA_extension->byte_offset_to_18_byte_descriptors;
  1861. /* byte #3 of CEA extension version 3 */
  1862. mhl_edid_3d_data->parse_data.underscan = p_CEA_extension_version_3->misc_support.underscan_IT_formats_by_default?1:0;
  1863. mhl_edid_3d_data->parse_data.basic_audio = p_CEA_extension_version_3->misc_support.basic_audio_support?1:0;
  1864. mhl_edid_3d_data->parse_data.YCbCr_4_4_4 = p_CEA_extension_version_3->misc_support.YCrCb444_support;
  1865. mhl_edid_3d_data->parse_data.YCbCr_4_2_2 = p_CEA_extension_version_3->misc_support.YCrCb422_support;
  1866. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1867. "misc support index-> %02x\n",
  1868. *((uint8_t *)&p_CEA_extension_version_3->misc_support) );
  1869. #ifdef NEVER
  1870. /* choose output color depth in order of preference */
  1871. if (mhl_edid_3d_data->parse_data.YCbCr_4_4_4) {
  1872. si_mhl_tx_drv_set_output_color_space( mhl_edid_3d_data->drv_context,BIT_EDID_FIELD_FORMAT_YCbCr444 );
  1873. } else if (mhl_edid_3d_data->parse_data.YCbCr_4_2_2) {
  1874. si_mhl_tx_drv_set_output_color_space( mhl_edid_3d_data->drv_context,BIT_EDID_FIELD_FORMAT_YCbCr422 );
  1875. } else {
  1876. si_mhl_tx_drv_set_output_color_space( mhl_edid_3d_data->drv_context,BIT_EDID_FIELD_FORMAT_HDMI_TO_RGB);
  1877. }
  1878. #endif // NEVER
  1879. p_data_u.puc_data_block = &p_CEA_extension->version_u.version3.Offset4_u.data_block_collection[0];
  1880. while (p_data_u.puc_data_block < puc_long_descriptors) {
  1881. data_block_tag_code_e tag_code;
  1882. uint8_t data_block_length;
  1883. tag_code = p_data_u.p_CEA_data_block->header.fields.tag_code;
  1884. data_block_length = p_data_u.p_CEA_data_block->header.fields.length_following_header;
  1885. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1886. "tag_code:%d data_block_length:%d\n",
  1887. tag_code,data_block_length);
  1888. if (( p_data_u.puc_data_block + data_block_length) > puc_long_descriptors) {
  1889. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  1890. "EDID -> V Descriptor Overflow\n");
  1891. return EDID_V_DESCR_OVERFLOW;
  1892. }
  1893. i = 0; /* num of short video descriptors in current data block */
  1894. switch (tag_code)
  1895. {
  1896. case DBTC_VIDEO_DATA_BLOCK:
  1897. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1898. "DBTC_VIDEO_DATA_BLOCK:\n");
  1899. if (mhl_edid_3d_data->parse_data.num_video_data_blocks < NUM_VIDEO_DATA_BLOCKS_LIMIT) {
  1900. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[mhl_edid_3d_data->parse_data.num_video_data_blocks] = (p_video_data_block_t)p_data_u.puc_data_block;
  1901. /* each SVD is 1 byte long */
  1902. while (i < data_block_length) {
  1903. uint8_t VIC;
  1904. VIC = mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[mhl_edid_3d_data->parse_data.num_video_data_blocks]->short_descriptors[i].VIC;
  1905. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1906. "short desc[%d]: VIC: %d\n",i,VIC);
  1907. // update_av_info_edid(true, VIC, 0);
  1908. mhl_event_notify(mhl_edid_3d_data->dev_context, MHL_TX_EVENT_EDID_UPDATE, VIC, NULL);
  1909. if (!IsQualifiedMhlVIC(mhl_edid_3d_data,VIC,NULL)) {
  1910. mhl_edid_3d_data->parse_data.p_video_data_blocks_2d[mhl_edid_3d_data->parse_data.num_video_data_blocks]->short_descriptors[i].VIC = 0;
  1911. }
  1912. i++;
  1913. }
  1914. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  1915. "EDID -> %d descriptors in Short Descriptor Video Block\n",i);
  1916. mhl_edid_3d_data->parse_data.num_video_data_blocks++;
  1917. }
  1918. break;
  1919. case DBTC_AUDIO_DATA_BLOCK:
  1920. {
  1921. Paudio_data_block_t p_audio_data_block = (Paudio_data_block_t) p_data_u.puc_data_block;
  1922. uint8_t A_descriptor_index = 0;
  1923. uint8_t AudioFormatCode;
  1924. while (i < data_block_length/sizeof(p_audio_data_block->short_audio_descriptors[0]) ) {
  1925. mhl_edid_3d_data->parse_data.audio_descriptors[A_descriptor_index]
  1926. = p_audio_data_block->short_audio_descriptors[i];
  1927. pr_info("\n(uint8_t)p_audio_data_block->short_audio_descriptors[%d].max_channels_minus_one: %d",i,(uint8_t)p_audio_data_block->short_audio_descriptors[i].max_channels_minus_one);
  1928. AudioFormatCode =p_audio_data_block->short_audio_descriptors[i].audio_format_code;
  1929. pr_info("\nAudio Format Code %i",(int)AudioFormatCode);
  1930. switch (AudioFormatCode){
  1931. case 1: pr_info("Liniar PCM"); break;
  1932. case 2: pr_info("AC-3"); break;
  1933. case 3: pr_info("MPEG-1"); break;
  1934. case 4: pr_info("MP3"); break;
  1935. case 5: pr_info("MPEG2"); break;
  1936. case 6: pr_info("ACC"); break;
  1937. case 7: pr_info("DTS"); break;
  1938. case 8: pr_info("ATRAC"); break;
  1939. default: pr_info("reserved");
  1940. }
  1941. if(AudioFormatCode==1){
  1942. MAX_channel=(uint8_t)p_audio_data_block->short_audio_descriptors[i].max_channels_minus_one+1;
  1943. pr_info("\nMax N of channels %d",MAX_channel);
  1944. pr_info("\nFs: ");
  1945. if(MAX_channel>2){
  1946. MAX_channel=8;
  1947. Cap_MAX_channel = HDMI_CHANNEL_8;
  1948. /*
  1949. if(p_audio_data_block->short_audio_descriptors[i].freq_32_Khz){
  1950. pr_info(" AUDIO_32K_8CH");
  1951. siHdmiTx_AudioSel(AUDIO_32K_8CH);
  1952. }
  1953. else if(p_audio_data_block->short_audio_descriptors[i].freq_44_1_KHz){
  1954. pr_info(" AUDIO_44K_8CH");
  1955. siHdmiTx_AudioSel(AUDIO_44K_8CH);
  1956. }
  1957. else if(p_audio_data_block->short_audio_descriptors[i].freq_48_KHz){
  1958. pr_info(" AUDIO_48K_8CH ");
  1959. siHdmiTx_AudioSel(AUDIO_48K_8CH);
  1960. }
  1961. else if(p_audio_data_block->short_audio_descriptors[i].freq_96_KHz){
  1962. pr_info(" AUDIO_96K_8CH");
  1963. siHdmiTx_AudioSel(AUDIO_96K_8CH);
  1964. }
  1965. else if(p_audio_data_block->short_audio_descriptors[i].freq_192_KHz){
  1966. pr_info(" AUDIO_192K_8CH ");
  1967. siHdmiTx_AudioSel(AUDIO_192K_8CH);
  1968. Cap_SampleRate = 192;
  1969. }
  1970. */
  1971. if(p_audio_data_block->short_audio_descriptors[i].freq_32_Khz){
  1972. pr_info(" AUDIO_32K_8CH");
  1973. siHdmiTx_AudioSel(AUDIO_32K_8CH);
  1974. Cap_SampleRate = HDMI_SAMPLERATE_32;
  1975. }
  1976. if(p_audio_data_block->short_audio_descriptors[i].freq_44_1_KHz){
  1977. pr_info(" AUDIO_44K_8CH");
  1978. siHdmiTx_AudioSel(AUDIO_44K_8CH);
  1979. Cap_SampleRate = HDMI_SAMPLERATE_44;
  1980. }
  1981. if(p_audio_data_block->short_audio_descriptors[i].freq_48_KHz){
  1982. pr_info(" AUDIO_48K_8CH ");
  1983. Cap_SampleRate = HDMI_SAMPLERATE_48;
  1984. siHdmiTx_AudioSel(AUDIO_48K_8CH);
  1985. }
  1986. if(p_audio_data_block->short_audio_descriptors[i].freq_96_KHz){
  1987. pr_info(" AUDIO_96K_8CH");
  1988. siHdmiTx_AudioSel(AUDIO_96K_8CH);
  1989. Cap_SampleRate = HDMI_SAMPLERATE_96;
  1990. }
  1991. if(p_audio_data_block->short_audio_descriptors[i].freq_192_KHz){
  1992. pr_info(" AUDIO_192K_8CH ");
  1993. siHdmiTx_AudioSel(AUDIO_192K_8CH);
  1994. Cap_SampleRate = HDMI_SAMPLERATE_192;
  1995. }
  1996. }
  1997. else{
  1998. MAX_channel=2;
  1999. Cap_MAX_channel = HDMI_CHANNEL_2;
  2000. /*
  2001. if(p_audio_data_block->short_audio_descriptors[i].freq_32_Khz){
  2002. pr_info(" AUDIO_32K_2CH");
  2003. siHdmiTx_AudioSel(AUDIO_32K_2CH);
  2004. }
  2005. else if(p_audio_data_block->short_audio_descriptors[i].freq_44_1_KHz){
  2006. pr_info(" AUDIO_44K_2CH");
  2007. siHdmiTx_AudioSel(AUDIO_44K_2CH);
  2008. }
  2009. else if(p_audio_data_block->short_audio_descriptors[i].freq_48_KHz){
  2010. pr_info(" AUDIO_48K_2CH ");
  2011. siHdmiTx_AudioSel(AUDIO_48K_2CH);
  2012. }
  2013. else if(p_audio_data_block->short_audio_descriptors[i].freq_96_KHz){
  2014. pr_info(" AUDIO_96K_2CH");
  2015. siHdmiTx_AudioSel(AUDIO_96K_2CH);
  2016. }
  2017. else if(p_audio_data_block->short_audio_descriptors[i].freq_192_KHz){
  2018. pr_info(" AUDIO_192K_2CH ");
  2019. siHdmiTx_AudioSel(AUDIO_192K_2CH);
  2020. }
  2021. */
  2022. if(p_audio_data_block->short_audio_descriptors[i].freq_32_Khz){
  2023. pr_info(" AUDIO_32K_2CH");
  2024. siHdmiTx_AudioSel(AUDIO_32K_2CH);
  2025. Cap_SampleRate = HDMI_SAMPLERATE_32;
  2026. }
  2027. if(p_audio_data_block->short_audio_descriptors[i].freq_44_1_KHz){
  2028. pr_info(" AUDIO_44K_2CH");
  2029. siHdmiTx_AudioSel(AUDIO_44K_2CH);
  2030. Cap_SampleRate = HDMI_SAMPLERATE_44;
  2031. }
  2032. if(p_audio_data_block->short_audio_descriptors[i].freq_48_KHz){
  2033. pr_info(" AUDIO_48K_2CH ");
  2034. siHdmiTx_AudioSel(AUDIO_48K_2CH);
  2035. Cap_SampleRate = HDMI_SAMPLERATE_48;
  2036. }
  2037. if(p_audio_data_block->short_audio_descriptors[i].freq_96_KHz){
  2038. pr_info(" AUDIO_96K_2CH");
  2039. siHdmiTx_AudioSel(AUDIO_96K_2CH);
  2040. Cap_SampleRate = HDMI_SAMPLERATE_96;
  2041. }
  2042. if(p_audio_data_block->short_audio_descriptors[i].freq_192_KHz){
  2043. pr_info(" AUDIO_192K_2CH ");
  2044. siHdmiTx_AudioSel(AUDIO_192K_2CH);
  2045. Cap_SampleRate = HDMI_SAMPLERATE_192;
  2046. }
  2047. }
  2048. if(AudioFormatCode == 1){
  2049. pr_info("Supported length: ");
  2050. if(p_audio_data_block->short_audio_descriptors[i].byte3.audio_code_1_LPCM.res_16_bit){
  2051. pr_info("16bits ");
  2052. Samplebit=16;
  2053. Cap_Samplebit = HDMI_BITWIDTH_16;
  2054. }
  2055. if(p_audio_data_block->short_audio_descriptors[i].byte3.audio_code_1_LPCM.res_20_bit){
  2056. pr_info("20 ");
  2057. Samplebit=20;
  2058. Cap_Samplebit = HDMI_BITWIDTH_20;
  2059. }
  2060. if(p_audio_data_block->short_audio_descriptors[i].byte3.audio_code_1_LPCM.res_24_bit){
  2061. pr_info("24bits ");
  2062. Samplebit=24;
  2063. Cap_Samplebit = HDMI_BITWIDTH_24;
  2064. }
  2065. pr_info("\n");
  2066. }
  2067. }
  2068. A_descriptor_index++;
  2069. i++;
  2070. }
  2071. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  2072. "EDID -> Short Descriptor Audio Block\n");
  2073. }
  2074. break;
  2075. case DBTC_SPEAKER_ALLOCATION_DATA_BLOCK:
  2076. {
  2077. Pspeaker_allocation_data_block_t p_speaker_allocation_data_block = (Pspeaker_allocation_data_block_t) p_data_u.puc_data_block;
  2078. *((Pspeaker_allocation_flags_t)&mhl_edid_3d_data->parse_data.speaker_alloc[i++]) = p_speaker_allocation_data_block->payload.speaker_alloc_flags;
  2079. p_speaker_payload = mhl_edid_3d_data->parse_data.speaker_alloc[i-1];
  2080. pr_info("EDID -> Short Descriptor Speaker Allocation Block\n");
  2081. {
  2082. pr_info("\nSpeakers' allocation: ");
  2083. if(p_speaker_payload & 0x01){
  2084. CA+=0;
  2085. pr_info("FL/FR");
  2086. }
  2087. if( p_speaker_payload& 0x02){
  2088. CA+=0x01;
  2089. pr_info("LFE");
  2090. }
  2091. if( p_speaker_payload & 0x04){
  2092. CA+=0x02;
  2093. pr_info("FC");
  2094. }
  2095. if(p_speaker_payload & 0x08){
  2096. CA+=0x08;
  2097. pr_info("RL/RR");
  2098. }
  2099. if(p_speaker_payload & 0x10){
  2100. CA+=0x04;
  2101. pr_info("RC");
  2102. }
  2103. if(p_speaker_payload& 0x20){
  2104. CA+=0x14;
  2105. pr_info("FLC/FRC");
  2106. }
  2107. if(p_speaker_payload & 0x40){
  2108. CA+=0x08;
  2109. pr_info("RLC/RRC");
  2110. }
  2111. pr_info("\nCA=0x%x\n",CA);
  2112. }
  2113. }
  2114. break;
  2115. case DBTC_USE_EXTENDED_TAG:
  2116. {
  2117. extended_tag_code_t extended_tag_code;
  2118. extended_tag_code = p_data_u.p_CEA_data_block->payload_u.extended_tag;
  2119. switch (extended_tag_code.etc)
  2120. {
  2121. case ETC_VIDEO_CAPABILITY_DATA_BLOCK:
  2122. {
  2123. Pvideo_capability_data_block_t p_video_capability_data_block = (Pvideo_capability_data_block_t)p_data_u.puc_data_block;
  2124. Pvideo_capability_data_payload_t p_payload = &p_video_capability_data_block->payload;
  2125. mhl_edid_3d_data->parse_data.video_capability_flags = *((uint8_t *)p_payload);
  2126. mhl_edid_3d_data->parse_data.p_video_capability_data_block = p_video_capability_data_block;
  2127. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  2128. "EDID -> Short Descriptor Video Capability Block\n");
  2129. }
  2130. break;
  2131. case ETC_COLORIMETRY_DATA_BLOCK:
  2132. {
  2133. Pcolorimetry_data_block_t p_colorimetry_data_block = (Pcolorimetry_data_block_t)p_data_u.puc_data_block;
  2134. Pcolorimetry_data_payload_t p_payload= &p_colorimetry_data_block->payload;
  2135. mhl_edid_3d_data->parse_data.colorimetry_support_flags = p_payload->ci_data.xvYCC;
  2136. mhl_edid_3d_data->parse_data.meta_data_profile = p_payload->cm_meta_data.meta_data;
  2137. }
  2138. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  2139. "EDID -> Short Descriptor Colorimetry Block\n");
  2140. break;
  2141. }
  2142. }
  2143. break;
  2144. case DBTC_VENDOR_SPECIFIC_DATA_BLOCK:
  2145. {
  2146. P_vsdb_t p_vsdb = (P_vsdb_t) p_data_u.puc_data_block;
  2147. uint8_t *puc_next_db = ((uint8_t *)&p_vsdb->header) + sizeof(p_vsdb->header) + data_block_length;
  2148. #ifdef CONFIG_MTK_HDMI_3D_SUPPORT
  2149. extern bool MHL_3D_Support;
  2150. MHL_3D_Support = false;
  2151. #endif
  2152. // TODO: FD, TBI, any chance of MHL OUI here? 0x030C00 is HDMI OUI
  2153. if ( (p_vsdb->IEEE_OUI[0] == 0x03)
  2154. && (p_vsdb->IEEE_OUI[1] == 0x0C)
  2155. && (p_vsdb->IEEE_OUI[2] == 0x00)
  2156. ) {
  2157. PHDMI_LLC_vsdb_payload_t p_HDMI_vendor_specific_payload = &p_vsdb->payload_u.HDMI_LLC;
  2158. mhl_edid_3d_data->parse_data.p_HDMI_vsdb = p_vsdb;
  2159. SII_ASSERT (5 <= data_block_length,("unexpected data_block_length\n"));
  2160. mhl_edid_3d_data->parse_data.HDMI_sink = true;
  2161. *((PHDMI_LLC_BA_t)&mhl_edid_3d_data->parse_data.CEC_A_B) = p_HDMI_vendor_specific_payload->B_A; /* CEC Physical address */
  2162. *((PHDMI_LLC_DC_t)&mhl_edid_3d_data->parse_data.CEC_C_D) = p_HDMI_vendor_specific_payload->D_C;
  2163. /* Offset of 3D_Present bit in VSDB */
  2164. if (p_HDMI_vendor_specific_payload->byte8.latency_fields_present) {
  2165. if(p_HDMI_vendor_specific_payload->byte8.I_latency_fields_present) {
  2166. mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15= &p_HDMI_vendor_specific_payload->vsdb_fields_byte_9_through_byte_15.vsdb_all_fields_byte_9_through_byte_15.byte_13_through_byte_15;
  2167. } else {
  2168. mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15 = &p_HDMI_vendor_specific_payload->vsdb_fields_byte_9_through_byte_15.vsdb_all_fields_byte_9_through_byte_15_sans_interlaced_latency.byte_13_through_byte_15;
  2169. }
  2170. } else {
  2171. if(p_HDMI_vendor_specific_payload->byte8.I_latency_fields_present) {
  2172. mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15 = &p_HDMI_vendor_specific_payload->vsdb_fields_byte_9_through_byte_15.vsdb_all_fields_byte_9_through_byte_15_sans_progressive_latency.byte_13_through_byte_15;
  2173. } else {
  2174. mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15 = &p_HDMI_vendor_specific_payload->vsdb_fields_byte_9_through_byte_15.vsdb_all_fields_byte_9_through_byte_15_sans_all_latency.byte_13_through_byte_15;
  2175. }
  2176. }
  2177. if ( ((uint8_t *)&mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte13) >= puc_next_db ) {
  2178. mhl_edid_3d_data->parse_data._3D_supported = false;
  2179. } else if (mhl_edid_3d_data->parse_data.p_byte_13_through_byte_15->byte13._3D_present) {
  2180. mhl_edid_3d_data->parse_data._3D_supported = true;
  2181. #ifdef CONFIG_MTK_HDMI_3D_SUPPORT
  2182. MHL_3D_Support= true;
  2183. #endif
  2184. } else {
  2185. mhl_edid_3d_data->parse_data._3D_supported = false;
  2186. #ifdef CONFIG_MTK_HDMI_3D_SUPPORT
  2187. MHL_3D_Support= false;
  2188. #endif
  2189. }
  2190. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  2191. "EDID indicates %s3D support\n",
  2192. mhl_edid_3d_data->parse_data._3D_supported?"":"NO " );
  2193. } else {
  2194. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"check VS IEEE code failed!\n");
  2195. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"00:%02X, 01:%02X, 02:%02X\n", p_vsdb->IEEE_OUI[0], p_vsdb->IEEE_OUI[1],p_vsdb->IEEE_OUI[2]);
  2196. mhl_edid_3d_data->parse_data.HDMI_sink = false;
  2197. }
  2198. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  2199. "EDID -> Short Descriptor Vendor Block\n\n");
  2200. }
  2201. break;
  2202. case DBTC_TERMINATOR:
  2203. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  2204. "found terminator tag code\n");
  2205. return EDID_SHORT_DESCRIPTORS_OK;
  2206. break;
  2207. default:
  2208. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  2209. "EDID -> Unknown Tag Code:0x%02x\n",(uint16_t)tag_code);
  2210. return EDID_UNKNOWN_TAG_CODE;
  2211. }
  2212. p_data_u.puc_data_block += sizeof(p_data_u.p_CEA_data_block->header)+ data_block_length;
  2213. }
  2214. return EDID_SHORT_DESCRIPTORS_OK;
  2215. }
  2216. }
  2217. }
  2218. static uint8_t parse_861_block(edid_3d_data_p mhl_edid_3d_data,uint8_t *p_EDID_block_data)
  2219. {
  2220. uint8_t err_code;
  2221. PCEA_extension_t p_CEA_extension = (PCEA_extension_t)p_EDID_block_data;
  2222. mhl_edid_3d_data->parse_data.p_HDMI_vsdb = NULL;
  2223. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"tag:place holder EDID block:%p\n",p_EDID_block_data);
  2224. if (EDID_EXTENSION_BLOCK_MAP == p_CEA_extension->tag) {
  2225. Pblock_map_t p_block_map = (Pblock_map_t)p_EDID_block_data;
  2226. int i;
  2227. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"Edid: Block Map\n");
  2228. /* loop limit is adjusted by one to account for block map */
  2229. for(i=0;i<mhl_edid_3d_data->parse_data.num_EDID_extensions-1;++i) {
  2230. if (EDID_EXTENSION_TAG != p_block_map->block_tags[i]) {
  2231. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"Edid: Adjusting number of extensions according to Block Map\n");
  2232. mhl_edid_3d_data->parse_data.num_EDID_extensions=i; /* include block map in count */
  2233. break;
  2234. }
  2235. }
  2236. return EDID_OK;
  2237. } else {
  2238. err_code = parse_861_short_descriptors(mhl_edid_3d_data,p_EDID_block_data);
  2239. if (err_code != EDID_SHORT_DESCRIPTORS_OK) {
  2240. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  2241. "EDID: Non-HDMI extension Errcode:%d\n",(uint16_t)err_code);
  2242. return err_code;
  2243. }
  2244. #if 0
  2245. /* adjust */
  2246. err_code = si_mhl_tx_parse_861_long_descriptors(mhl_edid_3d_data,p_EDID_block_data);
  2247. if (err_code != EDID_LONG_DESCRIPTORS_OK) {
  2248. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  2249. "EDID: Errcode:%d\n",(uint16_t)err_code);
  2250. return err_code;
  2251. }
  2252. #endif
  2253. }
  2254. return EDID_OK;
  2255. }
  2256. void si_mhl_tx_handle_atomic_hw_edid_read_complete(edid_3d_data_p mhl_edid_3d_data,struct cbus_req *req)
  2257. {
  2258. PEDID_block0_t p_EDID_block_0 = (PEDID_block0_t)&mhl_edid_3d_data->EDID_block_data[0];
  2259. uint8_t counter;
  2260. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"tag: Entire EDID Read complete\n");
  2261. #ifdef EDID_PASSTHROUGH //(
  2262. si_mhl_tx_drv_set_upstream_edid(mhl_edid_3d_data->drv_context,mhl_edid_3d_data->EDID_block_data,2*EDID_BLOCK_SIZE);
  2263. #endif //)
  2264. /* Parse EDID Block #0 Desctiptors */
  2265. //si_mhl_tx_parse_block_zero_timing_descriptors(mhl_edid_3d_data,p_EDID_block_0);
  2266. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context
  2267. ,"EDID -> Number of 861 Extensions = %d\n"
  2268. , (uint16_t)p_EDID_block_0->extension_flag );
  2269. mhl_edid_3d_data->parse_data.num_EDID_extensions = p_EDID_block_0->extension_flag;
  2270. if (0 == p_EDID_block_0->extension_flag) {
  2271. /* No extensions to worry about */
  2272. DUMP_EDID_BLOCK(0,(uint8_t *)p_EDID_block_0,EDID_BLOCK_SIZE)
  2273. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context
  2274. ,"EDID -> no extensions, assuming DVI. tag offset:0x%x\n"
  2275. , SII_OFFSETOF(EDID_block0_t,extension_flag));
  2276. mhl_edid_3d_data->parse_data.HDMI_sink = false;
  2277. SiiMhlTxMakeItDVI(mhl_edid_3d_data,p_EDID_block_0);
  2278. } else {
  2279. uint8_t Result = EDID_OK;
  2280. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context," tag:place holder \n");
  2281. /* number of extensions is one less than number of blocks */
  2282. for (counter = 1; counter <= mhl_edid_3d_data->parse_data.num_EDID_extensions;++counter) {
  2283. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context," counter:%d tag:place holder EDID block:%p\n",counter,&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE * counter]);
  2284. Result = parse_861_block(mhl_edid_3d_data,&mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE * counter]);
  2285. if (EDID_OK != Result) {
  2286. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context
  2287. ,"EDID -> Extension[%d] is not HDMI: Result:%d\n"
  2288. , counter
  2289. ,(uint16_t)Result);
  2290. SiiMhlTxMakeItDVI(mhl_edid_3d_data,p_EDID_block_0);
  2291. Result = EDID_OK;
  2292. }
  2293. }
  2294. }
  2295. /*
  2296. * Since our working copy of the block zero EDID gets modified,
  2297. * we must re-compute its checksum
  2298. */
  2299. p_EDID_block_0->checksum = 0;
  2300. p_EDID_block_0->checksum = calculate_generic_checksum((uint8_t *)p_EDID_block_0,0,sizeof(*p_EDID_block_0));
  2301. #ifdef CONFIG_MTK_HDMI_3D_SUPPORT
  2302. SiiMhlTx3dReqForNonTranscodeMode(mhl_edid_3d_data);
  2303. #endif
  2304. }
  2305. /*
  2306. EXPORTED FUNCTIONS
  2307. */
  2308. void si_mhl_tx_initiate_edid_sequence(void *context)
  2309. {
  2310. edid_3d_data_p mhl_edid_3d_data =(edid_3d_data_p)context;
  2311. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"tag:\n");
  2312. mhl_edid_3d_data->parse_data.num_video_data_blocks=0;
  2313. /*
  2314. Initiate the EDID reading sequence see
  2315. SiiMhlTxMscCommandDone for additional processing.
  2316. */
  2317. si_edid_reset(mhl_edid_3d_data);
  2318. si_mhl_tx_request_first_edid_block( mhl_edid_3d_data->dev_context);
  2319. }
  2320. int si_mhl_tx_get_num_cea_861_extensions(void *context, uint8_t block_number)
  2321. {
  2322. edid_3d_data_p mhl_edid_3d_data =(edid_3d_data_p)context;
  2323. PEDID_block0_t p_EDID_block_0 = (PEDID_block0_t) &mhl_edid_3d_data->EDID_block_data;
  2324. uint8_t limit_blocks = sizeof(mhl_edid_3d_data->EDID_block_data) /
  2325. EDID_BLOCK_SIZE;
  2326. uint8_t *pb_data = &mhl_edid_3d_data->EDID_block_data[EDID_BLOCK_SIZE * block_number];
  2327. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,"block number:%d pb_data:%x\n",block_number,pb_data);
  2328. if (ne_SUCCESS == si_mhl_tx_drv_get_edid_fifo_next_block(mhl_edid_3d_data->drv_context, pb_data)) {
  2329. if (0 == block_number) {
  2330. if (!si_mhl_tx_check_edid_header(mhl_edid_3d_data,p_EDID_block_0)) {
  2331. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,"EDID -> Incorrect Header pb_data:%x\n",pb_data);
  2332. DUMP_EDID_BLOCK(1,pb_data,sizeof(*p_EDID_block_0)) /* no semicolon needed here */
  2333. if (si_mhl_tx_check_edid_header(mhl_edid_3d_data,(PEDID_block0_t)&mhl_edid_3d_data->EDID_block_data[1])) {
  2334. // return ne_BAD_HEADER_OFFSET_BY_1;
  2335. }
  2336. }
  2337. }
  2338. if (! si_mhl_tx_do_edid_checksum(pb_data)) {
  2339. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,"EDID -> Checksum Error pb_data:%x\n",pb_data);
  2340. DUMP_EDID_BLOCK(1,pb_data,EDID_BLOCK_SIZE) /* no semicolon needed here */
  2341. // return ne_BAD_CHECKSUM;
  2342. }
  2343. if(p_EDID_block_0->extension_flag < limit_blocks) {
  2344. return p_EDID_block_0->extension_flag;
  2345. } else {
  2346. MHL_TX_DBG_ERR(mhl_edid_3d_data->dev_context,
  2347. "not enough room for %d extension\n",
  2348. p_EDID_block_0->extension_flag);
  2349. return (int)limit_blocks-1;
  2350. }
  2351. } else {
  2352. return ne_NO_HPD;
  2353. }
  2354. }
  2355. int si_edid_sink_is_hdmi ( void *context )
  2356. {
  2357. edid_3d_data_p mhl_edid_3d_data =(edid_3d_data_p)context;
  2358. return mhl_edid_3d_data->parse_data.HDMI_sink;
  2359. }
  2360. int si_edid_quantization_range_selectable( void *context )
  2361. {
  2362. edid_3d_data_p mhl_edid_3d_data =(edid_3d_data_p)context;
  2363. return mhl_edid_3d_data->parse_data.video_capability_flags & 0x80;
  2364. }
  2365. int si_edid_sink_supports_YCbCr422 ( void *context )
  2366. {
  2367. edid_3d_data_p mhl_edid_3d_data =(edid_3d_data_p)context;
  2368. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  2369. "Mhl2Tx: YCbCr422 support:%s\n",
  2370. mhl_edid_3d_data->parse_data.YCbCr_4_2_2?"Yup":"Nope");
  2371. return mhl_edid_3d_data->parse_data.YCbCr_4_2_2;
  2372. }
  2373. int si_edid_sink_supports_YCbCr444 ( void *context )
  2374. {
  2375. edid_3d_data_p mhl_edid_3d_data =(edid_3d_data_p)context;
  2376. MHL_TX_EDID_INFO(mhl_edid_3d_data->dev_context,
  2377. "Mhl2Tx: YCbCr444 support:%s\n",
  2378. mhl_edid_3d_data->parse_data.YCbCr_4_4_4?"Yup":"Nope");
  2379. return mhl_edid_3d_data->parse_data.YCbCr_4_4_4;
  2380. }
  2381. int si_edid_find_pixel_clock_from_HDMI_VIC(void *context, uint8_t vic)
  2382. {
  2383. return hdmi_vic_info[vic].pixel_clock_0;
  2384. }
  2385. int si_edid_find_pixel_clock_from_AVI_VIC(void *context, uint8_t vic)
  2386. {
  2387. return calculate_pixel_clock(context
  2388. , (uint16_t)VIC_info[vic].columns
  2389. , (uint16_t)VIC_info[vic].rows
  2390. , (uint32_t)VIC_info[vic].field_rate_in_milliHz
  2391. , vic
  2392. );
  2393. }
  2394. int si_edid_read_done(void *context)
  2395. {
  2396. edid_3d_data_p mhl_edid_3d_data =(edid_3d_data_p)context;
  2397. return TEST_3D_FLAG(mhl_edid_3d_data,FLAGS_EDID_READ_DONE);
  2398. }
  2399. void si_edid_reset( edid_3d_data_p mhl_edid_3d_data )
  2400. {
  2401. int i;
  2402. uint8_t *pData=(uint8_t *) &mhl_edid_3d_data->parse_data;
  2403. /* clear out EDID parse results */
  2404. for (i=0; i < sizeof(mhl_edid_3d_data->parse_data);++i) {
  2405. pData[i]=0;
  2406. }
  2407. CLR_3D_FLAG(mhl_edid_3d_data, FLAGS_EDID_READ_DONE);
  2408. }
  2409. void *si_edid_create_context(void *dev_context,void *drv_context)
  2410. {
  2411. edid_3d_data_p temp;
  2412. temp = (edid_3d_data_p )kmalloc(sizeof(edid_3d_data_t),GFP_KERNEL);
  2413. if (temp) {
  2414. memset((void *)temp,0,sizeof(*temp));
  2415. temp->dev_context=dev_context;
  2416. temp->drv_context=drv_context;
  2417. }
  2418. return (void *)temp;
  2419. }
  2420. void si_edid_destroy_context(void *context)
  2421. {
  2422. if (context) {
  2423. memset(context,0,sizeof(edid_3d_data_t));
  2424. kfree(context);
  2425. }
  2426. }
  2427. #if 1//def ENABLE_EDID_DEBUG_PRINT //(
  2428. void dump_EDID_block_impl(const char *pszFunction, int iLineNum,uint8_t override,uint8_t *pData,uint16_t length)
  2429. {
  2430. uint16_t i;
  2431. pr_debug("%s:%d EDID DATA:\n",pszFunction,iLineNum);
  2432. for (i = 0; i < length; )
  2433. {
  2434. uint16_t j;
  2435. uint16_t temp = i;
  2436. for(j=0; (j < 16)&& (i<length);++j,++i)
  2437. {
  2438. pr_debug("%02X ", pData[i]);
  2439. }
  2440. pr_debug(" | ");
  2441. for(j=0; (j < 16)&& (temp<length);++j,++temp)
  2442. {
  2443. pr_debug("%c",((pData[temp]>=' ')&&(pData[temp]<='z'))?pData[temp]:'.');
  2444. }
  2445. pr_debug("\n");
  2446. }
  2447. }
  2448. #endif //)