lcm_drv.h 20 KB

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  1. #ifndef __LCM_DRV_H__
  2. #define __LCM_DRV_H__
  3. #include <linux/device.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/regulator/consumer.h>
  6. #ifndef ARY_SIZE
  7. #define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
  8. #endif
  9. /* --------------------------------------------------------------------------- */
  10. /* common enumerations */
  11. typedef enum {
  12. LCM_TYPE_DBI = 0,
  13. LCM_TYPE_DPI,
  14. LCM_TYPE_DSI
  15. } LCM_TYPE;
  16. typedef enum {
  17. LCM_CTRL_NONE = 0,
  18. LCM_CTRL_SERIAL_DBI,
  19. LCM_CTRL_PARALLEL_DBI,
  20. LCM_CTRL_GPIO
  21. } LCM_CTRL;
  22. typedef enum {
  23. LCM_POLARITY_RISING = 0,
  24. LCM_POLARITY_FALLING = 1
  25. } LCM_POLARITY;
  26. typedef enum {
  27. LCM_CLOCK_PHASE_0 = 0,
  28. LCM_CLOCK_PHASE_90 = 1
  29. } LCM_CLOCK_PHASE;
  30. typedef enum {
  31. LCM_COLOR_ORDER_RGB = 0,
  32. LCM_COLOR_ORDER_BGR = 1
  33. } LCM_COLOR_ORDER;
  34. typedef enum {
  35. LCM_DRIVING_CURRENT_DEFAULT,
  36. LCM_DRIVING_CURRENT_8MA = (1 << 0),
  37. LCM_DRIVING_CURRENT_4MA = (1 << 1),
  38. LCM_DRIVING_CURRENT_2MA = (1 << 2),
  39. LCM_DRIVING_CURRENT_SLEW_CNTL = (1 << 3),
  40. LCM_DRIVING_CURRENT_6575_4MA = (1 << 4),
  41. LCM_DRIVING_CURRENT_6575_8MA = (3 << 4),
  42. LCM_DRIVING_CURRENT_6575_12MA = (2 << 4),
  43. LCM_DRIVING_CURRENT_6575_16MA = (4 << 4),
  44. LCM_DRIVING_CURRENT_6MA,
  45. LCM_DRIVING_CURRENT_10MA,
  46. LCM_DRIVING_CURRENT_12MA,
  47. LCM_DRIVING_CURRENT_14MA,
  48. LCM_DRIVING_CURRENT_16MA,
  49. LCM_DRIVING_CURRENT_20MA,
  50. LCM_DRIVING_CURRENT_24MA,
  51. LCM_DRIVING_CURRENT_28MA,
  52. LCM_DRIVING_CURRENT_32MA
  53. } LCM_DRIVING_CURRENT;
  54. typedef enum {
  55. LCM_INTERFACE_NOTDEFINED = 0,
  56. LCM_INTERFACE_DSI0,
  57. LCM_INTERFACE_DSI1,
  58. LCM_INTERFACE_DSI_DUAL,
  59. LCM_INTERFACE_DPI0,
  60. LCM_INTERFACE_DPI1,
  61. LCM_INTERFACE_DBI0
  62. } LCM_INTERFACE_ID;
  63. typedef enum {
  64. LCM_IOCTL_NULL = 0,
  65. } LCM_IOCTL;
  66. /* DBI related enumerations */
  67. typedef enum {
  68. LCM_DBI_CLOCK_FREQ_104M = 0,
  69. LCM_DBI_CLOCK_FREQ_52M,
  70. LCM_DBI_CLOCK_FREQ_26M,
  71. LCM_DBI_CLOCK_FREQ_13M,
  72. LCM_DBI_CLOCK_FREQ_7M
  73. } LCM_DBI_CLOCK_FREQ;
  74. typedef enum {
  75. LCM_DBI_DATA_WIDTH_8BITS = 0,
  76. LCM_DBI_DATA_WIDTH_9BITS = 1,
  77. LCM_DBI_DATA_WIDTH_16BITS = 2,
  78. LCM_DBI_DATA_WIDTH_18BITS = 3,
  79. LCM_DBI_DATA_WIDTH_24BITS = 4,
  80. LCM_DBI_DATA_WIDTH_32BITS = 5
  81. } LCM_DBI_DATA_WIDTH;
  82. typedef enum {
  83. LCM_DBI_CPU_WRITE_8_BITS = 8,
  84. LCM_DBI_CPU_WRITE_16_BITS = 16,
  85. LCM_DBI_CPU_WRITE_32_BITS = 32,
  86. } LCM_DBI_CPU_WRITE_BITS;
  87. typedef enum {
  88. LCM_DBI_FORMAT_RGB332 = 0,
  89. LCM_DBI_FORMAT_RGB444 = 1,
  90. LCM_DBI_FORMAT_RGB565 = 2,
  91. LCM_DBI_FORMAT_RGB666 = 3,
  92. LCM_DBI_FORMAT_RGB888 = 4
  93. } LCM_DBI_FORMAT;
  94. typedef enum {
  95. LCM_DBI_TRANS_SEQ_MSB_FIRST = 0,
  96. LCM_DBI_TRANS_SEQ_LSB_FIRST = 1
  97. } LCM_DBI_TRANS_SEQ;
  98. typedef enum {
  99. LCM_DBI_PADDING_ON_LSB = 0,
  100. LCM_DBI_PADDING_ON_MSB = 1
  101. } LCM_DBI_PADDING;
  102. typedef enum {
  103. LCM_DBI_TE_MODE_DISABLED = 0,
  104. LCM_DBI_TE_MODE_VSYNC_ONLY = 1,
  105. LCM_DBI_TE_MODE_VSYNC_OR_HSYNC = 2,
  106. } LCM_DBI_TE_MODE;
  107. typedef enum {
  108. LCM_DBI_TE_VS_WIDTH_CNT_DIV_8 = 0,
  109. LCM_DBI_TE_VS_WIDTH_CNT_DIV_16 = 1,
  110. LCM_DBI_TE_VS_WIDTH_CNT_DIV_32 = 2,
  111. LCM_DBI_TE_VS_WIDTH_CNT_DIV_64 = 3,
  112. } LCM_DBI_TE_VS_WIDTH_CNT_DIV;
  113. /* DPI related enumerations */
  114. typedef enum {
  115. LCM_DPI_FORMAT_RGB565 = 0,
  116. LCM_DPI_FORMAT_RGB666 = 1,
  117. LCM_DPI_FORMAT_RGB888 = 2
  118. } LCM_DPI_FORMAT;
  119. typedef enum {
  120. LCM_SERIAL_CLOCK_FREQ_104M = 0,
  121. LCM_SERIAL_CLOCK_FREQ_26M,
  122. LCM_SERIAL_CLOCK_FREQ_52M
  123. } LCM_SERIAL_CLOCK_FREQ;
  124. typedef enum {
  125. LCM_SERIAL_CLOCK_DIV_2 = 0,
  126. LCM_SERIAL_CLOCK_DIV_4 = 1,
  127. LCM_SERIAL_CLOCK_DIV_8 = 2,
  128. LCM_SERIAL_CLOCK_DIV_16 = 3,
  129. } LCM_SERIAL_CLOCK_DIV;
  130. /* DSI related enumerations */
  131. typedef enum {
  132. CMD_MODE = 0,
  133. SYNC_PULSE_VDO_MODE = 1,
  134. SYNC_EVENT_VDO_MODE = 2,
  135. BURST_VDO_MODE = 3
  136. } LCM_DSI_MODE_CON;
  137. typedef enum {
  138. LCM_ONE_LANE = 1,
  139. LCM_TWO_LANE = 2,
  140. LCM_THREE_LANE = 3,
  141. LCM_FOUR_LANE = 4,
  142. } LCM_LANE_NUM;
  143. typedef enum {
  144. LCM_DSI_FORMAT_RGB565 = 0,
  145. LCM_DSI_FORMAT_RGB666 = 1,
  146. LCM_DSI_FORMAT_RGB888 = 2
  147. } LCM_DSI_FORMAT;
  148. typedef enum {
  149. LCM_DSI_TRANS_SEQ_MSB_FIRST = 0,
  150. LCM_DSI_TRANS_SEQ_LSB_FIRST = 1
  151. } LCM_DSI_TRANS_SEQ;
  152. typedef enum {
  153. LCM_DSI_PADDING_ON_LSB = 0,
  154. LCM_DSI_PADDING_ON_MSB = 1
  155. } LCM_DSI_PADDING;
  156. typedef enum {
  157. LCM_PACKED_PS_16BIT_RGB565 = 0,
  158. LCM_LOOSELY_PS_18BIT_RGB666 = 1,
  159. LCM_PACKED_PS_24BIT_RGB888 = 2,
  160. LCM_PACKED_PS_18BIT_RGB666 = 3
  161. } LCM_PS_TYPE;
  162. typedef enum {
  163. LCM_DSI_6589_PLL_CLOCK_NULL = 0,
  164. LCM_DSI_6589_PLL_CLOCK_201_5 = 1,
  165. LCM_DSI_6589_PLL_CLOCK_208 = 2,
  166. LCM_DSI_6589_PLL_CLOCK_214_5 = 3,
  167. LCM_DSI_6589_PLL_CLOCK_221 = 4,
  168. LCM_DSI_6589_PLL_CLOCK_227_5 = 5,
  169. LCM_DSI_6589_PLL_CLOCK_234 = 6,
  170. LCM_DSI_6589_PLL_CLOCK_240_5 = 7,
  171. LCM_DSI_6589_PLL_CLOCK_247 = 8,
  172. LCM_DSI_6589_PLL_CLOCK_253_5 = 9,
  173. LCM_DSI_6589_PLL_CLOCK_260 = 10,
  174. LCM_DSI_6589_PLL_CLOCK_266_5 = 11,
  175. LCM_DSI_6589_PLL_CLOCK_273 = 12,
  176. LCM_DSI_6589_PLL_CLOCK_279_5 = 13,
  177. LCM_DSI_6589_PLL_CLOCK_286 = 14,
  178. LCM_DSI_6589_PLL_CLOCK_292_5 = 15,
  179. LCM_DSI_6589_PLL_CLOCK_299 = 16,
  180. LCM_DSI_6589_PLL_CLOCK_305_5 = 17,
  181. LCM_DSI_6589_PLL_CLOCK_312 = 18,
  182. LCM_DSI_6589_PLL_CLOCK_318_5 = 19,
  183. LCM_DSI_6589_PLL_CLOCK_325 = 20,
  184. LCM_DSI_6589_PLL_CLOCK_331_5 = 21,
  185. LCM_DSI_6589_PLL_CLOCK_338 = 22,
  186. LCM_DSI_6589_PLL_CLOCK_344_5 = 23,
  187. LCM_DSI_6589_PLL_CLOCK_351 = 24,
  188. LCM_DSI_6589_PLL_CLOCK_357_5 = 25,
  189. LCM_DSI_6589_PLL_CLOCK_364 = 26,
  190. LCM_DSI_6589_PLL_CLOCK_370_5 = 27,
  191. LCM_DSI_6589_PLL_CLOCK_377 = 28,
  192. LCM_DSI_6589_PLL_CLOCK_383_5 = 29,
  193. LCM_DSI_6589_PLL_CLOCK_390 = 30,
  194. LCM_DSI_6589_PLL_CLOCK_396_5 = 31,
  195. LCM_DSI_6589_PLL_CLOCK_403 = 32,
  196. LCM_DSI_6589_PLL_CLOCK_409_5 = 33,
  197. LCM_DSI_6589_PLL_CLOCK_416 = 34,
  198. LCM_DSI_6589_PLL_CLOCK_422_5 = 35,
  199. LCM_DSI_6589_PLL_CLOCK_429 = 36,
  200. LCM_DSI_6589_PLL_CLOCK_435_5 = 37,
  201. LCM_DSI_6589_PLL_CLOCK_442 = 38,
  202. LCM_DSI_6589_PLL_CLOCK_448_5 = 39,
  203. LCM_DSI_6589_PLL_CLOCK_455 = 40,
  204. LCM_DSI_6589_PLL_CLOCK_461_5 = 41,
  205. LCM_DSI_6589_PLL_CLOCK_468 = 42,
  206. LCM_DSI_6589_PLL_CLOCK_474_5 = 43,
  207. LCM_DSI_6589_PLL_CLOCK_481 = 44,
  208. LCM_DSI_6589_PLL_CLOCK_487_5 = 45,
  209. LCM_DSI_6589_PLL_CLOCK_494 = 46,
  210. LCM_DSI_6589_PLL_CLOCK_500_5 = 47,
  211. LCM_DSI_6589_PLL_CLOCK_507 = 48,
  212. LCM_DSI_6589_PLL_CLOCK_513_5 = 49,
  213. LCM_DSI_6589_PLL_CLOCK_520 = 50,
  214. } LCM_DSI_PLL_CLOCK;
  215. /* --------------------------------------------------------------------------- */
  216. typedef struct {
  217. LCM_COLOR_ORDER color_order;
  218. LCM_DBI_TRANS_SEQ trans_seq;
  219. LCM_DBI_PADDING padding;
  220. LCM_DBI_FORMAT format;
  221. LCM_DBI_DATA_WIDTH width;
  222. } LCM_DBI_DATA_FORMAT;
  223. typedef struct {
  224. LCM_POLARITY cs_polarity;
  225. LCM_POLARITY clk_polarity;
  226. LCM_CLOCK_PHASE clk_phase;
  227. unsigned int is_non_dbi_mode;
  228. LCM_SERIAL_CLOCK_FREQ clock_base;
  229. LCM_SERIAL_CLOCK_DIV clock_div;
  230. /* //////////////////////////////////MT6575 added params, and if lcm driver is for 6575, only care these below params */
  231. unsigned int css;
  232. unsigned int csh;
  233. unsigned int rd_1st;
  234. unsigned int rd_2nd;
  235. unsigned int wr_1st;
  236. unsigned int wr_2nd;
  237. unsigned int sif_3wire;
  238. unsigned int sif_sdi;
  239. LCM_POLARITY sif_1st_pol;
  240. LCM_POLARITY sif_sck_def;
  241. unsigned int sif_div2;
  242. unsigned int sif_hw_cs;
  243. /* ////////////////////////////////// */
  244. } LCM_DBI_SERIAL_PARAMS;
  245. typedef struct {
  246. /* timing parameters */
  247. unsigned int write_setup;
  248. unsigned int write_hold;
  249. unsigned int write_wait;
  250. unsigned int read_setup;
  251. unsigned int read_hold;
  252. unsigned int read_latency;
  253. unsigned int wait_period;
  254. /*only for 6575 */
  255. unsigned int cs_high_width;
  256. } LCM_DBI_PARALLEL_PARAMS;
  257. typedef struct {
  258. LCM_COLOR_ORDER color_order;
  259. LCM_DSI_TRANS_SEQ trans_seq;
  260. LCM_DSI_PADDING padding;
  261. LCM_DSI_FORMAT format;
  262. } LCM_DSI_DATA_FORMAT;
  263. typedef struct {
  264. LCM_DSI_MODE_CON mode;
  265. unsigned int cmd_if;
  266. unsigned int addr;
  267. unsigned int val[4];
  268. } LCM_DSI_MODE_SWITCH_CMD;
  269. typedef struct {
  270. unsigned int compress_ratio;
  271. unsigned int lr_mode_en;
  272. unsigned int vlc_disable;
  273. unsigned int vlc_config;
  274. } LCM_UFOE_CONFIG_PARAMS;
  275. /* --------------------------------------------------------------------------- */
  276. typedef struct {
  277. /* common parameters for serial & parallel interface */
  278. unsigned int port;
  279. LCM_DBI_CLOCK_FREQ clock_freq;
  280. LCM_DBI_DATA_WIDTH data_width;
  281. LCM_DBI_DATA_FORMAT data_format;
  282. LCM_DBI_CPU_WRITE_BITS cpu_write_bits;
  283. LCM_DRIVING_CURRENT io_driving_current;
  284. LCM_DRIVING_CURRENT msb_io_driving_current;
  285. LCM_DRIVING_CURRENT ctrl_io_driving_current;
  286. /* tearing control */
  287. LCM_DBI_TE_MODE te_mode;
  288. LCM_POLARITY te_edge_polarity;
  289. unsigned int te_hs_delay_cnt;
  290. unsigned int te_vs_width_cnt;
  291. LCM_DBI_TE_VS_WIDTH_CNT_DIV te_vs_width_cnt_div;
  292. /* particular parameters for serial & parallel interface */
  293. LCM_DBI_SERIAL_PARAMS serial;
  294. LCM_DBI_PARALLEL_PARAMS parallel;
  295. } LCM_DBI_PARAMS;
  296. typedef struct {
  297. /*
  298. Pixel Clock Frequency = 26MHz * mipi_pll_clk_div1
  299. / (mipi_pll_clk_ref + 1)
  300. / (2 * mipi_pll_clk_div2)
  301. / dpi_clk_div
  302. */
  303. unsigned int mipi_pll_clk_ref; /* 0..1 */
  304. unsigned int mipi_pll_clk_div1; /* 0..63 */
  305. unsigned int mipi_pll_clk_div2; /* 0..15 */
  306. unsigned int mipi_pll_clk_fbk_div; /* PCLK=> 8: 26MHz, 10: 35MHz, 12: 40MHz */
  307. unsigned int dpi_clk_div; /* 2..32 */
  308. unsigned int dpi_clk_duty; /* (dpi_clk_div - 1) .. 31 */
  309. unsigned int PLL_CLOCK;
  310. unsigned int dpi_clock;
  311. unsigned int ssc_disable;
  312. unsigned int ssc_range;
  313. unsigned int width;
  314. unsigned int height;
  315. unsigned int bg_width;
  316. unsigned int bg_height;
  317. /* polarity parameters */
  318. LCM_POLARITY clk_pol;
  319. LCM_POLARITY de_pol;
  320. LCM_POLARITY vsync_pol;
  321. LCM_POLARITY hsync_pol;
  322. /* timing parameters */
  323. unsigned int hsync_pulse_width;
  324. unsigned int hsync_back_porch;
  325. unsigned int hsync_front_porch;
  326. unsigned int vsync_pulse_width;
  327. unsigned int vsync_back_porch;
  328. unsigned int vsync_front_porch;
  329. /* output format parameters */
  330. LCM_DPI_FORMAT format;
  331. LCM_COLOR_ORDER rgb_order;
  332. unsigned int is_serial_output;
  333. unsigned int i2x_en;
  334. unsigned int i2x_edge;
  335. unsigned int embsync;
  336. unsigned int lvds_tx_en;
  337. unsigned int bit_swap;
  338. /* intermediate buffers parameters */
  339. unsigned int intermediat_buffer_num; /* 2..3 */
  340. /* iopad parameters */
  341. LCM_DRIVING_CURRENT io_driving_current;
  342. LCM_DRIVING_CURRENT msb_io_driving_current;
  343. LCM_DRIVING_CURRENT lsb_io_driving_current;
  344. LCM_DRIVING_CURRENT ctrl_io_driving_current;
  345. } LCM_DPI_PARAMS;
  346. /* --------------------------------------------------------------------------- */
  347. typedef struct {
  348. unsigned char cmd;
  349. unsigned char count;
  350. unsigned char para_list[2];
  351. } LCM_esd_check_item;
  352. typedef enum {
  353. DUAL_DSI_NONE = 0x0,
  354. DUAL_DSI_CMD = 0x1,
  355. DUAL_DSI_VDO = 0x2,
  356. } DUAL_DSI_TYPE;
  357. typedef enum {
  358. MIPITX_PHY_LANE_0 = 0,
  359. MIPITX_PHY_LANE_1,
  360. MIPITX_PHY_LANE_2,
  361. MIPITX_PHY_LANE_3,
  362. MIPITX_PHY_LANE_CK,
  363. MIPITX_PHY_LANE_RX,
  364. MIPITX_PHY_LANE_NUM
  365. } MIPITX_PHY_LANE_SWAP;
  366. typedef enum {
  367. MIPITX_PHY_PORT_0 = 0,
  368. MIPITX_PHY_PORT_1,
  369. MIPITX_PHY_PORT_NUM
  370. } MIPITX_PHY_PORT;
  371. typedef struct {
  372. unsigned int slice_width;
  373. unsigned int slice_hight;
  374. unsigned int bit_per_pixel;
  375. unsigned int slice_mode;
  376. unsigned int rgb_swap;
  377. unsigned int dsc_cfg;
  378. unsigned int dsc_line_buf_depth;
  379. unsigned int bit_per_channel;
  380. unsigned int rct_on;
  381. unsigned int bp_enable;
  382. unsigned int dec_delay;
  383. unsigned int xmit_delay;
  384. unsigned int scale_value;
  385. unsigned int increment_interval;
  386. unsigned int line_bpg_offset;
  387. unsigned int decrement_interval;
  388. unsigned int nfl_bpg_offset;
  389. unsigned int slice_bpg_offset;
  390. unsigned int initial_offset;
  391. unsigned int final_offset;
  392. unsigned int flatness_minqp;
  393. unsigned int flatness_maxqp;
  394. unsigned int rc_mode1_size;
  395. } LCM_DSC_CONFIG_PARAMS;
  396. typedef struct {
  397. LCM_DSI_MODE_CON mode;
  398. LCM_DSI_MODE_CON switch_mode;
  399. unsigned int DSI_WMEM_CONTI;
  400. unsigned int DSI_RMEM_CONTI;
  401. unsigned int VC_NUM;
  402. LCM_LANE_NUM LANE_NUM;
  403. LCM_DSI_DATA_FORMAT data_format;
  404. /* intermediate buffers parameters */
  405. unsigned int intermediat_buffer_num; /* 2..3 */
  406. LCM_PS_TYPE PS;
  407. unsigned int word_count;
  408. unsigned int packet_size;
  409. unsigned int packet_size_mult;
  410. unsigned int vertical_sync_active;
  411. unsigned int vertical_backporch;
  412. unsigned int vertical_frontporch;
  413. unsigned int vertical_frontporch_for_low_power;
  414. unsigned int vertical_active_line;
  415. unsigned int horizontal_sync_active;
  416. unsigned int horizontal_backporch;
  417. unsigned int horizontal_frontporch;
  418. unsigned int horizontal_blanking_pixel;
  419. unsigned int horizontal_active_pixel;
  420. unsigned int horizontal_bllp;
  421. unsigned int line_byte;
  422. unsigned int horizontal_sync_active_byte;
  423. unsigned int horizontal_backporch_byte;
  424. unsigned int horizontal_frontporch_byte;
  425. unsigned int rgb_byte;
  426. unsigned int horizontal_sync_active_word_count;
  427. unsigned int horizontal_backporch_word_count;
  428. unsigned int horizontal_frontporch_word_count;
  429. unsigned char HS_TRAIL;
  430. unsigned char HS_ZERO;
  431. unsigned char HS_PRPR;
  432. unsigned char LPX;
  433. unsigned char TA_SACK;
  434. unsigned char TA_GET;
  435. unsigned char TA_SURE;
  436. unsigned char TA_GO;
  437. unsigned char CLK_TRAIL;
  438. unsigned char CLK_ZERO;
  439. unsigned char LPX_WAIT;
  440. unsigned char CONT_DET;
  441. unsigned char CLK_HS_PRPR;
  442. unsigned char CLK_HS_POST;
  443. unsigned char DA_HS_EXIT;
  444. unsigned char CLK_HS_EXIT;
  445. unsigned int pll_select;
  446. unsigned int pll_div1;
  447. unsigned int pll_div2;
  448. unsigned int fbk_div;
  449. unsigned int pll_prediv;
  450. unsigned int pll_posdiv;
  451. unsigned int pll_s2qdiv;
  452. unsigned int fbk_sel;
  453. unsigned int rg_bir;
  454. unsigned int rg_bic;
  455. unsigned int rg_bp;
  456. unsigned int PLL_CLOCK;
  457. unsigned int dsi_clock;
  458. unsigned int ssc_disable;
  459. unsigned int ssc_range;
  460. unsigned int compatibility_for_nvk;
  461. unsigned int cont_clock;
  462. unsigned int ufoe_enable;
  463. unsigned int dsc_enable;
  464. LCM_UFOE_CONFIG_PARAMS ufoe_params;
  465. LCM_DSC_CONFIG_PARAMS dsc_params;
  466. unsigned int edp_panel;
  467. unsigned int customization_esd_check_enable;
  468. unsigned int esd_check_enable;
  469. unsigned int lcm_int_te_monitor;
  470. unsigned int lcm_int_te_period;
  471. unsigned int lcm_ext_te_monitor;
  472. unsigned int lcm_ext_te_enable;
  473. unsigned int noncont_clock;
  474. unsigned int noncont_clock_period;
  475. unsigned int clk_lp_per_line_enable;
  476. LCM_esd_check_item lcm_esd_check_table[3];
  477. unsigned int switch_mode_enable;
  478. DUAL_DSI_TYPE dual_dsi_type;
  479. unsigned int lane_swap_en;
  480. MIPITX_PHY_LANE_SWAP lane_swap[MIPITX_PHY_PORT_NUM][MIPITX_PHY_LANE_NUM];
  481. unsigned int vertical_vfp_lp;
  482. unsigned int PLL_CLOCK_lp;
  483. unsigned int ulps_sw_enable;
  484. unsigned int null_packet_en;
  485. unsigned int mixmode_enable;
  486. unsigned int mixmode_mipi_clock;
  487. unsigned int pwm_fps;
  488. unsigned int send_frame_enable;
  489. unsigned int lfr_enable;
  490. unsigned int lfr_mode;
  491. unsigned int lfr_type;
  492. unsigned int lfr_skip_num;
  493. unsigned int ext_te_edge;
  494. unsigned int eint_disable;
  495. } LCM_DSI_PARAMS;
  496. /* --------------------------------------------------------------------------- */
  497. typedef struct {
  498. LCM_TYPE type;
  499. LCM_CTRL ctrl; /* ! how to control LCM registers */
  500. LCM_INTERFACE_ID lcm_if;
  501. LCM_INTERFACE_ID lcm_cmd_if;
  502. /* common parameters */
  503. unsigned int lcm_x;
  504. unsigned int lcm_y;
  505. unsigned int width;
  506. unsigned int height;
  507. unsigned int virtual_width;
  508. unsigned int virtual_height;
  509. unsigned int io_select_mode; /* DBI or DPI should select IO mode according to chip spec */
  510. /* particular parameters */
  511. LCM_DBI_PARAMS dbi;
  512. LCM_DPI_PARAMS dpi;
  513. LCM_DSI_PARAMS dsi;
  514. unsigned int physical_width;
  515. unsigned int physical_height;
  516. unsigned int od_table_size;
  517. void *od_table;
  518. } LCM_PARAMS;
  519. #if defined(MTK_LCM_DEVICE_TREE_SUPPORT)
  520. typedef struct {
  521. char data;
  522. char padding[131];
  523. } LCM_DATA_T1;
  524. typedef struct {
  525. char cmd;
  526. char data;
  527. char padding[130];
  528. } LCM_DATA_T2;
  529. typedef struct {
  530. char cmd;
  531. char size;
  532. char data[128];
  533. char padding[2];
  534. } LCM_DATA_T3;
  535. typedef struct {
  536. char cmd;
  537. char location;
  538. char data;
  539. char padding[129];
  540. } LCM_DATA_T4;
  541. typedef struct {
  542. char size;
  543. char cmd[128];
  544. char padding[3];
  545. } LCM_DATA_T5;
  546. typedef struct {
  547. char func;
  548. char type;
  549. char size;
  550. char padding;
  551. union {
  552. LCM_DATA_T1 data_t1;
  553. LCM_DATA_T2 data_t2;
  554. LCM_DATA_T3 data_t3;
  555. LCM_DATA_T4 data_t4;
  556. LCM_DATA_T5 data_t5;
  557. };
  558. } LCM_DATA;
  559. typedef struct {
  560. unsigned int parsing;
  561. unsigned int id;
  562. unsigned int init_size;
  563. unsigned int compare_id_size;
  564. unsigned int suspend_size;
  565. unsigned int backlight_size;
  566. LCM_PARAMS params;
  567. LCM_DATA init[256];
  568. LCM_DATA compare_id[32];
  569. LCM_DATA suspend[32];
  570. LCM_DATA backlight[32];
  571. } LCM_DTS;
  572. #endif
  573. /* --------------------------------------------------------------------------- */
  574. #define REGFLAG_ESCAPE_ID (0x00)
  575. #define REGFLAG_DELAY_MS_V3 (0xFF)
  576. typedef struct {
  577. unsigned char id;
  578. unsigned char cmd;
  579. unsigned char count;
  580. unsigned char para_list[128];
  581. } LCM_setting_table_V3;
  582. typedef struct {
  583. void (*set_reset_pin)(unsigned int value);
  584. void (*set_chip_select)(unsigned int value);
  585. int (*set_gpio_out)(unsigned int gpio, unsigned int value);
  586. void (*udelay)(unsigned int us);
  587. void (*mdelay)(unsigned int ms);
  588. void (*rar)(unsigned int ms);
  589. void (*send_cmd)(unsigned int cmd);
  590. void (*send_data)(unsigned int data);
  591. unsigned int (*read_data)(void);
  592. void (*dsi_set_cmdq_V3)(LCM_setting_table_V3 *para_list, unsigned int size,
  593. unsigned char force_update);
  594. void (*dsi_set_cmdq_V2)(unsigned cmd, unsigned char count, unsigned char *para_list,
  595. unsigned char force_update);
  596. void (*dsi_set_cmdq)(unsigned int *pdata, unsigned int queue_size,
  597. unsigned char force_update);
  598. void (*dsi_set_null)(unsigned cmd, unsigned char count, unsigned char *para_list,
  599. unsigned char force_update);
  600. void (*dsi_write_cmd)(unsigned int cmd);
  601. void (*dsi_write_regs)(unsigned int addr, unsigned int *para, unsigned int nums);
  602. unsigned int (*dsi_read_reg)(void);
  603. unsigned int (*dsi_dcs_read_lcm_reg)(unsigned char cmd);
  604. unsigned int (*dsi_dcs_read_lcm_reg_v2)(unsigned char cmd, unsigned char *buffer,
  605. unsigned char buffer_size);
  606. void (*wait_transfer_done)(void);
  607. /** FIXME: GPIO mode should not be configured in lcm driver
  608. REMOVE ME after GPIO customization is done
  609. */
  610. int (*set_gpio_mode)(unsigned int pin, unsigned int mode);
  611. int (*set_gpio_dir)(unsigned int pin, unsigned int dir);
  612. int (*set_gpio_pull_enable)(unsigned int pin, unsigned char pull_en);
  613. long (*set_gpio_lcd_enp_bias)(unsigned int value);
  614. void (*dsi_set_cmdq_V11)(void *cmdq, unsigned int *pdata, unsigned int queue_size,
  615. unsigned char force_update);
  616. void (*dsi_set_cmdq_V22)(void *cmdq, unsigned cmd, unsigned char count,
  617. unsigned char *para_list, unsigned char force_update);
  618. void (*dsi_swap_port)(int swap);
  619. void (*dsi_set_cmdq_V23)(void *cmdq, unsigned cmd, unsigned char count,
  620. unsigned char *para_list, unsigned char force_update); /* dual */
  621. } LCM_UTIL_FUNCS;
  622. typedef enum {
  623. LCM_DRV_IOCTL_ENABLE_CMD_MODE = 0x100,
  624. } LCM_DRV_IOCTL_CMD;
  625. typedef struct {
  626. const char *name;
  627. void (*set_util_funcs)(const LCM_UTIL_FUNCS *util);
  628. void (*get_params)(LCM_PARAMS *params);
  629. void (*init)(void);
  630. void (*suspend)(void);
  631. void (*resume)(void);
  632. /* for power-on sequence refinement */
  633. void (*init_power)(void);
  634. void (*suspend_power)(void);
  635. void (*resume_power)(void);
  636. void (*update)(unsigned int x, unsigned int y, unsigned int width, unsigned int height);
  637. unsigned int (*compare_id)(void);
  638. #if defined(MTK_LCM_DEVICE_TREE_SUPPORT)
  639. void (*parse_dts)(const LCM_DTS *DTS, unsigned char force_update);
  640. #endif
  641. /* /////////////////////////CABC backlight related function */
  642. void (*set_backlight)(unsigned int level);
  643. void (*set_backlight_cmdq)(void *handle, unsigned int level);
  644. void (*set_pwm)(unsigned int divider);
  645. unsigned int (*get_pwm)(unsigned int divider);
  646. void (*set_backlight_mode)(unsigned int mode);
  647. /* ///////////////////////// */
  648. int (*adjust_fps)(void *cmdq, int fps, LCM_PARAMS *params);
  649. /* ///////////ESD_RECOVERY////////////////////// */
  650. unsigned int (*esd_check)(void);
  651. unsigned int (*esd_recover)(void);
  652. unsigned int (*check_status)(void);
  653. unsigned int (*ata_check)(unsigned char *buffer);
  654. void (*read_fb)(unsigned char *buffer);
  655. int (*ioctl)(LCM_DRV_IOCTL_CMD cmd, unsigned int data);
  656. /* /////////////////////////////////////////////// */
  657. void (*enter_idle)(void);
  658. void (*exit_idle)(void);
  659. void (*change_fps)(unsigned int mode);
  660. /* //switch mode */
  661. void *(*switch_mode)(int mode);
  662. void (*set_cmd)(void *handle, int *mode, unsigned int cmd_num);
  663. void (*set_lcm_cmd)(void *handle, unsigned int *lcm_cmd, unsigned int *lcm_count,
  664. unsigned int *lcm_value);
  665. /* /////////////PWM///////////////////////////// */
  666. void (*set_pwm_for_mix)(int enable);
  667. } LCM_DRIVER;
  668. #if defined(CONFIG_ARCH_MT6735) ||\
  669. defined(CONFIG_ARCH_MT6735M) ||\
  670. defined(CONFIG_ARCH_MT6753) ||\
  671. defined(CONFIG_ARCH_MT6580)
  672. extern LCM_DRIVER *lcm_driver_list[];
  673. extern unsigned int lcm_count;
  674. #endif
  675. /* --------------------------------------------------------------------------- */
  676. /* LCM Driver Functions */
  677. /* --------------------------------------------------------------------------- */
  678. const LCM_DRIVER *LCM_GetDriver(void);
  679. unsigned char which_lcd_module_triple(void);
  680. int lcm_vgp_supply_enable(void);
  681. int lcm_vgp_supply_disable(void);
  682. #endif /* __LCM_DRV_H__ */