mt8193_gpio.c 6.8 KB

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  1. #define pr_fmt(fmt) "mt8193-gpio: " fmt
  2. #include <generated/autoconf.h>
  3. #include <linux/mm.h>
  4. #include <linux/init.h>
  5. #include <linux/fb.h>
  6. #include <linux/delay.h>
  7. #include <linux/device.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/kthread.h>
  10. #include <linux/rtpm_prio.h>
  11. #include <linux/vmalloc.h>
  12. #include <asm/uaccess.h>
  13. #include <asm/atomic.h>
  14. #include <asm/cacheflush.h>
  15. #include <asm/io.h>
  16. #include <mach/irqs.h>
  17. #include <linux/miscdevice.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/fs.h>
  20. #include <linux/file.h>
  21. #include <linux/mm.h>
  22. #include <linux/cdev.h>
  23. #include <asm/tlbflush.h>
  24. #include <asm/page.h>
  25. #include <asm/io.h>
  26. #include <asm/uaccess.h>
  27. #include <linux/slab.h>
  28. #include <generated/autoconf.h>
  29. #include <linux/module.h>
  30. #include <linux/mm.h>
  31. #include <linux/init.h>
  32. #include <linux/fb.h>
  33. #include <linux/delay.h>
  34. #include <linux/device.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/kthread.h>
  37. #include <linux/rtpm_prio.h>
  38. #include <asm/uaccess.h>
  39. #include <asm/atomic.h>
  40. #include <asm/cacheflush.h>
  41. #include <asm/io.h>
  42. #include <mach/irqs.h>
  43. #include <linux/vmalloc.h>
  44. #include <asm/uaccess.h>
  45. #include "mt8193_pinmux.h"
  46. #include "mt8193_gpio.h"
  47. #include "mt8193.h"
  48. /* config gpio input/output low/high */
  49. int GPIO_Config(u32 u4GpioNum, u8 u1Mode, u8 u1Value)
  50. {
  51. int ret = 0;
  52. u32 u4PadNum = 0;
  53. u32 u4Tmp = 0;
  54. if (u4GpioNum > GPIO_PIN_MAX) {
  55. pr_err("[PINMUX] Invalid GPIO NUM %d\n", u4GpioNum);
  56. return PINMUX_RET_INVALID_ARG;
  57. }
  58. u4PadNum = _au4GpioTbl[u4GpioNum];
  59. pr_debug("[PINMUX] GPIO_Config() %d, %d, %d, %d\n", u4GpioNum, u4PadNum, u1Mode, u1Value);
  60. if (u4PadNum >= PIN_NFD6 && u4PadNum <= PIN_NFD0) {
  61. /* NFI ND GROUP. function 1 is gpio*/
  62. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION1);
  63. } else if (u4PadNum >= PIN_G0 && u4PadNum <= PIN_VSYNC) {
  64. /* GRB OUT GROUP. function 0 is gpio */
  65. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION0);
  66. } else if (u4PadNum >= PIN_CEC && u4PadNum <= PIN_HTPLG) {
  67. /* HDMI GROUP. function 2 is gpio */
  68. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION2);
  69. } else if (u4PadNum >= PIN_I2S_DATA && u4PadNum <= PIN_I2S_BCK) {
  70. /* audio GROUP. function 3 is gpio */
  71. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION3);
  72. } else if (u4PadNum == PIN_DPI1CK) {
  73. /* RGB_IN2 group. function 2 is gpio*/
  74. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION2);
  75. } else if (u4PadNum >= PIN_DPI1D7 && u4PadNum <= PIN_DPI1D0) {
  76. /* RGB_IN1 GROUP. function 3 is gpio */
  77. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION3);
  78. } else if (u4PadNum >= PIN_DPI0CK && u4PadNum <= PIN_DPI0D3) {
  79. /* RGB_IN1 GROUP. function 2 is gpio */
  80. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION2);
  81. } else if (u4PadNum >= PIN_DPI0D2 && u4PadNum <= PIN_DPI0D0) {
  82. /* RGB_IN1 GROUP. function 1 is gpio */
  83. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION1);
  84. } else if (u4PadNum >= PIN_SDA && u4PadNum <= PIN_SCL) {
  85. /* I2C_SLAVE GROUP. function 1 is gpio */
  86. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION1);
  87. } else if (u4PadNum >= PIN_NRNB && u4PadNum <= PIN_NLD7) {
  88. /* NFI_6583 GROUP. function 2 is gpio */
  89. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION2);
  90. } else if (u4PadNum >= PIN_NLD6 && u4PadNum <= PIN_NLD3) {
  91. /* NFI_6583 GROUP. function 3 is gpio */
  92. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION3);
  93. } else if (u4PadNum >= PIN_NLD2 && u4PadNum <= PIN_NLD0) {
  94. /* NFI_6583 GROUP. function 2 is gpio */
  95. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION2);
  96. } else if (u4PadNum == PIN_INT) {
  97. /* INTERRUPT group. function 3 is gpio*/
  98. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION3);
  99. } else if (u4PadNum >= PIN_NLD2 && u4PadNum <= PIN_NLD0) {
  100. /* NFI_6583 GROUP. function 2 is gpio */
  101. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION2);
  102. } else if (u4PadNum == PIN_NFRBN) {
  103. /* NFI_ND group. function 1 is gpio*/
  104. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION1);
  105. } else if (u4PadNum >= PIN_NFCLE && u4PadNum <= PIN_NFALE) {
  106. /* NFI ND GROUP. function 3 is gpio*/
  107. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION3);
  108. } else if (u4PadNum >= PIN_NFWEN && u4PadNum <= PIN_NFD7) {
  109. /* NFI ND GROUP. function 2 is gpio*/
  110. ret = mt8193_pinset(u4PadNum, PINMUX_FUNCTION2);
  111. } else {
  112. pr_err("[PINMUX] GPIO CFG ERROR !\n");
  113. return PINMUX_RET_INVALID_ARG;
  114. }
  115. if (u1Mode == MT8193_GPIO_OUTPUT) {
  116. /* output*/
  117. if (u4GpioNum >= 32 && u4GpioNum <= 63) {
  118. u4Tmp = CKGEN_READ32(REG_RW_GPIO_EN_1);
  119. u4Tmp |= (1 << (u4GpioNum-32));
  120. CKGEN_WRITE32(REG_RW_GPIO_EN_1, u4Tmp);
  121. u4Tmp = CKGEN_READ32(REG_RW_GPIO_OUT_1);
  122. if (u1Value == MT8193_GPIO_HIGH)
  123. u4Tmp |= (1 << (u4GpioNum-32));
  124. else
  125. u4Tmp &= (~(1 << (u4GpioNum-32)));
  126. CKGEN_WRITE32(REG_RW_GPIO_OUT_1, u4Tmp);
  127. } else if (u4GpioNum >= 0 && u4GpioNum <= 31) {
  128. /* work around method for gpio0~gpio31 */
  129. u32 u4PdShift = 0;
  130. u32 u4PuShift = 0;
  131. u4PdShift = _au4PinmuxPadPuPdTbl[u4PadNum][0];
  132. u4PuShift = _au4PinmuxPadPuPdTbl[u4PadNum][1];
  133. u4Tmp = CKGEN_READ32(REG_RW_GPIO_EN_0);
  134. if (u1Value == MT8193_GPIO_HIGH) {
  135. /* for output high, set en as 0. set pad pd as 0, set pad pu as 1 */
  136. u4Tmp &= (~(1 << u4GpioNum));
  137. CKGEN_WRITE32(REG_RW_GPIO_EN_0, u4Tmp);
  138. if (u4PdShift <= 31) {
  139. u4Tmp = CKGEN_READ32(REG_RW_PAD_PD0);
  140. u4Tmp &= (~(1 << u4PdShift));
  141. CKGEN_WRITE32(REG_RW_PAD_PD0, u4Tmp);
  142. u4Tmp = CKGEN_READ32(REG_RW_PAD_PU0);
  143. u4Tmp |= (1 << u4PdShift);
  144. CKGEN_WRITE32(REG_RW_PAD_PU0, u4Tmp);
  145. } else if (u4PdShift >= 32 && u4PdShift <= 63) {
  146. u4Tmp = CKGEN_READ32(REG_RW_PAD_PD1);
  147. u4Tmp &= (~(1 << (u4PdShift - 31)));
  148. CKGEN_WRITE32(REG_RW_PAD_PD1, u4Tmp);
  149. u4Tmp = CKGEN_READ32(REG_RW_PAD_PU1);
  150. u4Tmp |= (1 << (u4PdShift - 31));
  151. CKGEN_WRITE32(REG_RW_PAD_PU1, u4Tmp);
  152. }
  153. } else {
  154. /* for output low, just set en as 1 */
  155. u4Tmp |= (1 << u4GpioNum);
  156. CKGEN_WRITE32(REG_RW_GPIO_EN_0, u4Tmp);
  157. }
  158. /* CKGEN_WRITE32(REG_RW_GPIO_OUT_0, u4Tmp); */
  159. }
  160. } else {
  161. /* input*/
  162. if (u4GpioNum >= 32 && u4GpioNum <= 63) {
  163. u4Tmp = CKGEN_READ32(REG_RW_GPIO_EN_1);
  164. u4Tmp &= (~(1 << (u4GpioNum-32)));
  165. CKGEN_WRITE32(REG_RW_GPIO_EN_1, u4Tmp);
  166. } else if (u4GpioNum >= 0 && u4GpioNum <= 31) {
  167. u4Tmp = CKGEN_READ32(REG_RW_GPIO_EN_0);
  168. u4Tmp &= (~(1 << u4GpioNum));
  169. CKGEN_WRITE32(REG_RW_GPIO_EN_0, u4Tmp);
  170. }
  171. }
  172. return PINMUX_RET_OK;
  173. }
  174. /* return MT8193_GPIO_HIGH or MT8193_GPIO_LOW */
  175. u8 GPIO_Input(u32 u4GpioNum)
  176. {
  177. u32 u4Tmp = 0;
  178. u8 u1Val = MT8193_GPIO_LOW;
  179. if (u4GpioNum >= 32 && u4GpioNum <= 63) {
  180. u4Tmp = CKGEN_READ32(REG_RW_GPIO_IN_1);
  181. u1Val = (u4Tmp & (1 << (u4GpioNum-32))) ? MT8193_GPIO_HIGH : MT8193_GPIO_LOW;
  182. } else if (u4GpioNum >= 0 && u4GpioNum <= 31) {
  183. u4Tmp = CKGEN_READ32(REG_RW_GPIO_IN_0);
  184. u1Val = (u4Tmp & (1 << u4GpioNum)) ? MT8193_GPIO_HIGH : MT8193_GPIO_LOW;
  185. }
  186. return u1Val;
  187. }
  188. int GPIO_Output(u32 u4GpioNum, u32 u4High)
  189. {
  190. int ret = 0;
  191. ret = GPIO_Config(u4GpioNum, MT8193_GPIO_OUTPUT, u4High);
  192. return ret;
  193. }