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mt6735
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pwrap_hal.h

pwrap_hal.h 91 KB
Cronologia Originale

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  1. #ifndef __PMIC_WRAP_REGS_H__
    2. 

  2. #define __PMIC_WRAP_REGS_H__
    3. 

  3. #ifndef CONFIG_OF
    4. 

  4. #include <mach/mt_reg_base.h>
    5. 

  5. #include <mach/mt_irq.h>
    6. 

  6. #endif
    7. 

  7. 

  8. #include "mt-plat/sync_write.h"
    9. 

  9. 

  10. #define PMIC_WRAP_DEBUG
    11. 

  11. 

  12. #define PWRAPTAG                "[PWRAP] "
    13. 

  13. #ifdef PMIC_WRAP_DEBUG
    14. 

  14. #define PWRAPDEB(fmt, arg...)     printk(PWRAPTAG "cpuid=%d," fmt, raw_smp_processor_id(), ##arg)
    15. 

  15.   /* #define PWRAPLOG(fmt, arg...)   printk(PWRAPTAG fmt,##arg) */
    16. 

  16. #define PWRAPFUC(fmt, arg...)     printk(PWRAPTAG "cpuid=%d,%s\n", raw_smp_processor_id(), __func__)
    17. 

  17.   /* #define PWRAPFUC(fmt, arg...)   printk(PWRAPTAG "%s\n", __FUNCTION__) */
    18. 

  18. #endif
    19. 

  19. /* typedef unsigned int        u32; */
    20. 

  20. /* typedef signed int          s32; */
    21. 

  21. #define PWRAPLOG(fmt, arg...)   printk(PWRAPTAG fmt, ##arg)
    22. 

  22. #define PWRAPERR(fmt, arg...)   printk(PWRAPTAG "ERROR,line=%d " fmt, __LINE__, ##arg)
    23. 

  23. #define PWRAPREG(fmt, arg...)   printk(PWRAPTAG fmt, ##arg)
    24. 

  24. 

  25. /************************ROME BringUp *********************/
    26. 

  26. /* #define PMIC_WRAP_NO_PMIC   ///TODO: Fix me //if BringUp doesn't had PMIC, need open this */
    27. 

  27. /**********************************************************/
    28. 

  28. #define SLV_6328
    29. 

  29. /* #define SLV_6332 */
    30. 

  30. 

  31. #ifdef CONFIG_OF
    32. 

  32. extern void __iomem *pwrap_base;
    33. 

  33. #define PMIC_WRAP_BASE		(pwrap_base)
    34. 

  34. #define MT_PMIC_WRAP_IRQ_ID	(pwrap_irq)
    35. 

  35. #define INFRACFG_AO_REG_BASE	(infracfg_ao_base)
    36. 

  36. #define TOPCKGEN_BASE		(topckgen_base)
    37. 

  37. 

  38. #else
    39. 

  39. #define PMIC_WRAP_BASE (PWRAP_BASE)	/* 0x1000D000 */
    40. 

  40. #define MT_PMIC_WRAP_IRQ_ID PMIC_WRAP_ERR_IRQ_BIT_ID
    41. 

  41. #define INFRACFG_AO_REG_BASE	(INFRACFG_AO_BASE)
    42. 

  42. #define TOPCKGEN_BASE		(CKSYS_BASE)
    43. 

  43. #endif
    44. 

  44. 

  45. /* #define CKSYS_BASE              (INFRA_BASE) */
    46. 

  46. 

  47. #define PMIC_WRAP_REG_RANGE   85.5
    48. 

  48. #define PMIC_WRAP_REG_MAX     0xF000F154
    49. 

  49. 

  50. /* -------macro for timeout setting-------------------------------- */
    51. 

  51. /******************************************************************************
    52. 

  52. global variable and  sys interface
    53. 

  53. ******************************************************************************/
    54. 

  54. #define TIMEOUT_RESET	    0x7D0	/* 2000us */
    55. 

  55. #define TIMEOUT_READ	    0x7D0	/* 2000us */
    56. 

  56. #define TIMEOUT_WAIT_IDLE	0x7D0	/* 2000us */
    57. 

  57. 

  58. /* -------macro for spi clock config-------------------------------- */
    59. 

  59. #define CLK_CFG_4_CLR                       (TOPCKGEN_BASE+0x088)	/* 6582 */
    60. 

  60. #define CLK_CFG_5_CLR                       (TOPCKGEN_BASE+0x098)	/* 6593 */
    61. 

  61. #define CLK_SPI_CK_26M	0x70000
    62. 

  62. 

  63. /* -------macro for spi clock config-------------------------------- */
    64. 

  64. /* #define CLK_CFG_8                       (AP_RGU_BASE+0x164) //6585 */
    65. 

  65. /* #define CLK_CFG_4                       (TOPRGU_BASE+0x150) //6582 */
    66. 

  66. 

  67. /* #define PMIC_WRAP_RDDMY1                ((PMIC_WRAP_BASE+0x14)) */
    68. 

  68. /* #define PMIC_WRAP_SIG_ADR1              ((PMIC_WRAP_BASE+0xD0)) */
    69. 

  69. /* #define PMIC_WRAP_SIG_MODE1             ((PMIC_WRAP_BASE+0xD4)) */
    70. 

  70. /* #define PMIC_WRAP_SIG_VALUE1            ((PMIC_WRAP_BASE+0xD8)) */
    71. 

  71. /* #define PMIC_WRAP_SIG_ERRVAL1           ((PMIC_WRAP_BASE+0xDC)) */
    72. 

  72. /* #define PMIC_WRAP_PMIC_IRQ_ADR          ((PMIC_WRAP_BASE+0x13C)) */
    73. 

  73. /* #define PMIC_WRAP_PMIC_IRQ_MASK         ((PMIC_WRAP_BASE+0x140)) */
    74. 

  74. #if defined(CONFIG_ARCH_MT6735M)
    75. 

  75. 

  76. #include "pwrap_hal_d2.h"
    77. 

  77. 

  78. #else
    79. 

  79. #define PMIC_WRAP_MUX_SEL               ((unsigned int *)(PMIC_WRAP_BASE+0x0))
    80. 

  80. #define PMIC_WRAP_WRAP_EN               ((unsigned int *)(PMIC_WRAP_BASE+0x4))
    81. 

  81. #define PMIC_WRAP_DIO_EN                ((unsigned int *)(PMIC_WRAP_BASE+0x8))
    82. 

  82. #define PMIC_WRAP_SIDLY                 ((unsigned int *)(PMIC_WRAP_BASE+0xC))
    83. 

  83. #define PMIC_WRAP_RDDMY                 ((unsigned int *)(PMIC_WRAP_BASE+0x10))
    84. 

  84. #define PMIC_WRAP_SI_CK_CON             ((unsigned int *)(PMIC_WRAP_BASE+0x14))
    85. 

  85. #define PMIC_WRAP_CSHEXT_WRITE          ((unsigned int *)(PMIC_WRAP_BASE+0x18))
    86. 

  86. #define PMIC_WRAP_CSHEXT_READ           ((unsigned int *)(PMIC_WRAP_BASE+0x1C))
    87. 

  87. #define PMIC_WRAP_CSLEXT_START          ((unsigned int *)(PMIC_WRAP_BASE+0x20))
    88. 

  88. #define PMIC_WRAP_CSLEXT_END            ((unsigned int *)(PMIC_WRAP_BASE+0x24))
    89. 

  89. #define PMIC_WRAP_STAUPD_PRD            ((unsigned int *)(PMIC_WRAP_BASE+0x28))
    90. 

  90. #define PMIC_WRAP_STAUPD_GRPEN          ((unsigned int *)(PMIC_WRAP_BASE+0x2C))
    91. 

  91. #define PMIC_WRAP_EINT_STA0_ADR         ((unsigned int *)(PMIC_WRAP_BASE+0x30))
    92. 

  92. #define PMIC_WRAP_EINT_STA1_ADR         ((unsigned int *)(PMIC_WRAP_BASE+0x34))
    93. 

  93. #define PMIC_WRAP_EINT_STA              ((unsigned int *)(PMIC_WRAP_BASE+0x38))
    94. 

  94. #define PMIC_WRAP_EINT_CLR              ((unsigned int *)(PMIC_WRAP_BASE+0x3C))
    95. 

  95. #define PMIC_WRAP_STAUPD_MAN_TRIG       ((unsigned int *)(PMIC_WRAP_BASE+0x40))
    96. 

  96. #define PMIC_WRAP_STAUPD_STA            ((unsigned int *)(PMIC_WRAP_BASE+0x44))
    97. 

  97. #define PMIC_WRAP_WRAP_STA              ((unsigned int *)(PMIC_WRAP_BASE+0x48))
    98. 

  98. #define PMIC_WRAP_HARB_INIT             ((unsigned int *)(PMIC_WRAP_BASE+0x4C))
    99. 

  99. #define PMIC_WRAP_HARB_HPRIO            ((unsigned int *)(PMIC_WRAP_BASE+0x50))
    100. 

  100. #define PMIC_WRAP_HIPRIO_ARB_EN         ((unsigned int *)(PMIC_WRAP_BASE+0x54))
    101. 

  101. #define PMIC_WRAP_HARB_STA0             ((unsigned int *)(PMIC_WRAP_BASE+0x58))
    102. 

  102. #define PMIC_WRAP_HARB_STA1             ((unsigned int *)(PMIC_WRAP_BASE+0x5C))
    103. 

  103. #define PMIC_WRAP_MAN_EN                ((unsigned int *)(PMIC_WRAP_BASE+0x60))
    104. 

  104. #define PMIC_WRAP_MAN_CMD               ((unsigned int *)(PMIC_WRAP_BASE+0x64))
    105. 

  105. #define PMIC_WRAP_MAN_RDATA             ((unsigned int *)(PMIC_WRAP_BASE+0x68))
    106. 

  106. #define PMIC_WRAP_MAN_VLDCLR            ((unsigned int *)(PMIC_WRAP_BASE+0x6C))
    107. 

  107. #define PMIC_WRAP_WACS0_EN              ((unsigned int *)(PMIC_WRAP_BASE+0x70))
    108. 

  108. #define PMIC_WRAP_INIT_DONE0            ((unsigned int *)(PMIC_WRAP_BASE+0x74))
    109. 

  109. #define PMIC_WRAP_WACS0_CMD             ((unsigned int *)(PMIC_WRAP_BASE+0x78))
    110. 

  110. #define PMIC_WRAP_WACS0_RDATA           ((unsigned int *)(PMIC_WRAP_BASE+0x7C))
    111. 

  111. #define PMIC_WRAP_WACS0_VLDCLR          ((unsigned int *)(PMIC_WRAP_BASE+0x80))
    112. 

  112. #define PMIC_WRAP_WACS1_EN              ((unsigned int *)(PMIC_WRAP_BASE+0x84))
    113. 

  113. #define PMIC_WRAP_INIT_DONE1            ((unsigned int *)(PMIC_WRAP_BASE+0x88))
    114. 

  114. #define PMIC_WRAP_WACS1_CMD             ((unsigned int *)(PMIC_WRAP_BASE+0x8C))
    115. 

  115. #define PMIC_WRAP_WACS1_RDATA           ((unsigned int *)(PMIC_WRAP_BASE+0x90))
    116. 

  116. #define PMIC_WRAP_WACS1_VLDCLR          ((unsigned int *)(PMIC_WRAP_BASE+0x94))
    117. 

  117. #define PMIC_WRAP_WACS2_EN              ((unsigned int *)(PMIC_WRAP_BASE+0x98))
    118. 

  118. #define PMIC_WRAP_INIT_DONE2            ((unsigned int *)(PMIC_WRAP_BASE+0x9C))
    119. 

  119. #define PMIC_WRAP_WACS2_CMD             ((unsigned int *)(PMIC_WRAP_BASE+0xA0))
    120. 

  120. #define PMIC_WRAP_WACS2_RDATA           ((unsigned int *)(PMIC_WRAP_BASE+0xA4))
    121. 

  121. #define PMIC_WRAP_WACS2_VLDCLR          ((unsigned int *)(PMIC_WRAP_BASE+0xA8))
    122. 

  122. #define PMIC_WRAP_WACS3_EN              ((unsigned int *)(PMIC_WRAP_BASE+0xAC))
    123. 

  123. #define PMIC_WRAP_INIT_DONE3            ((unsigned int *)(PMIC_WRAP_BASE+0xB0))
    124. 

  124. #define PMIC_WRAP_WACS3_CMD             ((unsigned int *)(PMIC_WRAP_BASE+0xB4))
    125. 

  125. #define PMIC_WRAP_WACS3_RDATA           ((unsigned int *)(PMIC_WRAP_BASE+0xB8))
    126. 

  126. #define PMIC_WRAP_WACS3_VLDCLR          ((unsigned int *)(PMIC_WRAP_BASE+0xBC))
    127. 

  127. #define PMIC_WRAP_INT_EN                ((unsigned int *)(PMIC_WRAP_BASE+0xC0))
    128. 

  128. #define PMIC_WRAP_INT_FLG_RAW           ((unsigned int *)(PMIC_WRAP_BASE+0xC4))
    129. 

  129. #define PMIC_WRAP_INT_FLG               ((unsigned int *)(PMIC_WRAP_BASE+0xC8))
    130. 

  130. #define PMIC_WRAP_INT_CLR               ((unsigned int *)(PMIC_WRAP_BASE+0xCC))
    131. 

  131. #define PMIC_WRAP_SIG_ADR               ((unsigned int *)(PMIC_WRAP_BASE+0xD0))
    132. 

  132. #define PMIC_WRAP_SIG_MODE              ((unsigned int *)(PMIC_WRAP_BASE+0xD4))
    133. 

  133. #define PMIC_WRAP_SIG_VALUE             ((unsigned int *)(PMIC_WRAP_BASE+0xD8))
    134. 

  134. #define PMIC_WRAP_SIG_ERRVAL            ((unsigned int *)(PMIC_WRAP_BASE+0xDC))
    135. 

  135. #define PMIC_WRAP_CRC_EN                ((unsigned int *)(PMIC_WRAP_BASE+0xE0))
    136. 

  136. #define PMIC_WRAP_TIMER_EN              ((unsigned int *)(PMIC_WRAP_BASE+0xE4))
    137. 

  137. #define PMIC_WRAP_TIMER_STA             ((unsigned int *)(PMIC_WRAP_BASE+0xE8))
    138. 

  138. #define PMIC_WRAP_WDT_UNIT              ((unsigned int *)(PMIC_WRAP_BASE+0xEC))
    139. 

  139. #define PMIC_WRAP_WDT_SRC_EN            ((unsigned int *)(PMIC_WRAP_BASE+0xF0))
    140. 

  140. #define PMIC_WRAP_WDT_FLG               ((unsigned int *)(PMIC_WRAP_BASE+0xF4))
    141. 

  141. #define PMIC_WRAP_DEBUG_INT_SEL         ((unsigned int *)(PMIC_WRAP_BASE+0xF8))
    142. 

  142. #define PMIC_WRAP_DVFS_ADR0             ((unsigned int *)(PMIC_WRAP_BASE+0xFC))
    143. 

  143. #define PMIC_WRAP_DVFS_WDATA0           ((unsigned int *)(PMIC_WRAP_BASE+0x100))
    144. 

  144. #define PMIC_WRAP_DVFS_ADR1             ((unsigned int *)(PMIC_WRAP_BASE+0x104))
    145. 

  145. #define PMIC_WRAP_DVFS_WDATA1           ((unsigned int *)(PMIC_WRAP_BASE+0x108))
    146. 

  146. #define PMIC_WRAP_DVFS_ADR2             ((unsigned int *)(PMIC_WRAP_BASE+0x10C))
    147. 

  147. #define PMIC_WRAP_DVFS_WDATA2           ((unsigned int *)(PMIC_WRAP_BASE+0x110))
    148. 

  148. #define PMIC_WRAP_DVFS_ADR3             ((unsigned int *)(PMIC_WRAP_BASE+0x114))
    149. 

  149. #define PMIC_WRAP_DVFS_WDATA3           ((unsigned int *)(PMIC_WRAP_BASE+0x118))
    150. 

  150. #define PMIC_WRAP_DVFS_ADR4             ((unsigned int *)(PMIC_WRAP_BASE+0x11C))
    151. 

  151. #define PMIC_WRAP_DVFS_WDATA4           ((unsigned int *)(PMIC_WRAP_BASE+0x120))
    152. 

  152. #define PMIC_WRAP_DVFS_ADR5             ((unsigned int *)(PMIC_WRAP_BASE+0x124))
    153. 

  153. #define PMIC_WRAP_DVFS_WDATA5           ((unsigned int *)(PMIC_WRAP_BASE+0x128))
    154. 

  154. #define PMIC_WRAP_DVFS_ADR6             ((unsigned int *)(PMIC_WRAP_BASE+0x12C))
    155. 

  155. #define PMIC_WRAP_DVFS_WDATA6           ((unsigned int *)(PMIC_WRAP_BASE+0x130))
    156. 

  156. #define PMIC_WRAP_DVFS_ADR7             ((unsigned int *)(PMIC_WRAP_BASE+0x134))
    157. 

  157. #define PMIC_WRAP_DVFS_WDATA7           ((unsigned int *)(PMIC_WRAP_BASE+0x138))
    158. 

  158. #define PMIC_WRAP_DVFS_ADR8             ((unsigned int *)(PMIC_WRAP_BASE+0x13C))
    159. 

  159. #define PMIC_WRAP_DVFS_WDATA8           ((unsigned int *)(PMIC_WRAP_BASE+0x140))
    160. 

  160. #define PMIC_WRAP_DVFS_ADR9             ((unsigned int *)(PMIC_WRAP_BASE+0x144))
    161. 

  161. #define PMIC_WRAP_DVFS_WDATA9           ((unsigned int *)(PMIC_WRAP_BASE+0x148))
    162. 

  162. #define PMIC_WRAP_DVFS_ADR10            ((unsigned int *)(PMIC_WRAP_BASE+0x14C))
    163. 

  163. #define PMIC_WRAP_DVFS_WDATA10          ((unsigned int *)(PMIC_WRAP_BASE+0x150))
    164. 

  164. #define PMIC_WRAP_DVFS_ADR11            ((unsigned int *)(PMIC_WRAP_BASE+0x154))
    165. 

  165. #define PMIC_WRAP_DVFS_WDATA11          ((unsigned int *)(PMIC_WRAP_BASE+0x158))
    166. 

  166. #define PMIC_WRAP_DVFS_ADR12            ((unsigned int *)(PMIC_WRAP_BASE+0x15C))
    167. 

  167. #define PMIC_WRAP_DVFS_WDATA12          ((unsigned int *)(PMIC_WRAP_BASE+0x160))
    168. 

  168. #define PMIC_WRAP_DVFS_ADR13            ((unsigned int *)(PMIC_WRAP_BASE+0x164))
    169. 

  169. #define PMIC_WRAP_DVFS_WDATA13          ((unsigned int *)(PMIC_WRAP_BASE+0x168))
    170. 

  170. #define PMIC_WRAP_DVFS_ADR14            ((unsigned int *)(PMIC_WRAP_BASE+0x16C))
    171. 

  171. #define PMIC_WRAP_DVFS_WDATA14          ((unsigned int *)(PMIC_WRAP_BASE+0x170))
    172. 

  172. #define PMIC_WRAP_DVFS_ADR15            ((unsigned int *)(PMIC_WRAP_BASE+0x174))
    173. 

  173. #define PMIC_WRAP_DVFS_WDATA15          ((unsigned int *)(PMIC_WRAP_BASE+0x178))
    174. 

  174. #define PMIC_WRAP_SPMINF_STA            ((unsigned int *)(PMIC_WRAP_BASE+0x17C))
    175. 

  175. #define PMIC_WRAP_CIPHER_KEY_SEL        ((unsigned int *)(PMIC_WRAP_BASE+0x180))
    176. 

  176. #define PMIC_WRAP_CIPHER_IV_SEL         ((unsigned int *)(PMIC_WRAP_BASE+0x184))
    177. 

  177. #define PMIC_WRAP_CIPHER_EN             ((unsigned int *)(PMIC_WRAP_BASE+0x188))
    178. 

  178. #define PMIC_WRAP_CIPHER_RDY            ((unsigned int *)(PMIC_WRAP_BASE+0x18C))
    179. 

  179. #define PMIC_WRAP_CIPHER_MODE           ((unsigned int *)(PMIC_WRAP_BASE+0x190))
    180. 

  180. #define PMIC_WRAP_CIPHER_SWRST          ((unsigned int *)(PMIC_WRAP_BASE+0x194))
    181. 

  181. #define PMIC_WRAP_DCM_EN                ((unsigned int *)(PMIC_WRAP_BASE+0x198))
    182. 

  182. #define PMIC_WRAP_DCM_DBC_PRD           ((unsigned int *)(PMIC_WRAP_BASE+0x19C))
    183. 

  183. #define PMIC_WRAP_EXT_CK                ((unsigned int *)(PMIC_WRAP_BASE+0x1A0))
    184. 

  184. #define PMIC_WRAP_ADC_CMD_ADDR          ((unsigned int *)(PMIC_WRAP_BASE+0x1A4))
    185. 

  185. #define PMIC_WRAP_PWRAP_ADC_CMD         ((unsigned int *)(PMIC_WRAP_BASE+0x1A8))
    186. 

  186. #define PMIC_WRAP_ADC_RDATA_ADDR        ((unsigned int *)(PMIC_WRAP_BASE+0x1AC))
    187. 

  187. #define PMIC_WRAP_GPS_STA               ((unsigned int *)(PMIC_WRAP_BASE+0x1B0))
    188. 

  188. #define PMIC_WRAP_SWRST                 ((unsigned int *)(PMIC_WRAP_BASE+0x1B4))
    189. 

  189. #define PMIC_WRAP_MD_ADC_RDATA_ADDR_LATEST  ((unsigned int *)(PMIC_WRAP_BASE+0x1B8))
    190. 

  190. #define PMIC_WRAP_MD_ADC_RDATA_ADDR_WP  ((unsigned int *)(PMIC_WRAP_BASE+0x1BC))
    191. 

  191. #define PMIC_WRAP_MD_ADC_RDATA_ADDR0    ((unsigned int *)(PMIC_WRAP_BASE+0x1C0))
    192. 

  192. #define PMIC_WRAP_MD_ADC_RDATA_ADDR1    ((unsigned int *)(PMIC_WRAP_BASE+0x1C4))
    193. 

  193. #define PMIC_WRAP_MD_ADC_RDATA_ADDR2    ((unsigned int *)(PMIC_WRAP_BASE+0x1C8))
    194. 

  194. #define PMIC_WRAP_MD_ADC_RDATA_ADDR3    ((unsigned int *)(PMIC_WRAP_BASE+0x1CC))
    195. 

  195. #define PMIC_WRAP_MD_ADC_RDATA_ADDR4    ((unsigned int *)(PMIC_WRAP_BASE+0x1D0))
    196. 

  196. #define PMIC_WRAP_MD_ADC_RDATA_ADDR5    ((unsigned int *)(PMIC_WRAP_BASE+0x1D4))
    197. 

  197. #define PMIC_WRAP_MD_ADC_RDATA_ADDR6    ((unsigned int *)(PMIC_WRAP_BASE+0x1D8))
    198. 

  198. #define PMIC_WRAP_MD_ADC_RDATA_ADDR7    ((unsigned int *)(PMIC_WRAP_BASE+0x1DC))
    199. 

  199. #define PMIC_WRAP_MD_ADC_RDATA_ADDR8    ((unsigned int *)(PMIC_WRAP_BASE+0x1E0))
    200. 

  200. #define PMIC_WRAP_MD_ADC_RDATA_ADDR9    ((unsigned int *)(PMIC_WRAP_BASE+0x1E4))
    201. 

  201. #define PMIC_WRAP_MD_ADC_RDATA_ADDR10   ((unsigned int *)(PMIC_WRAP_BASE+0x1E8))
    202. 

  202. #define PMIC_WRAP_MD_ADC_RDATA_ADDR11   ((unsigned int *)(PMIC_WRAP_BASE+0x1EC))
    203. 

  203. #define PMIC_WRAP_MD_ADC_RDATA_ADDR12   ((unsigned int *)(PMIC_WRAP_BASE+0x1F0))
    204. 

  204. #define PMIC_WRAP_MD_ADC_RDATA_ADDR13   ((unsigned int *)(PMIC_WRAP_BASE+0x1F4))
    205. 

  205. #define PMIC_WRAP_MD_ADC_RDATA_ADDR14   ((unsigned int *)(PMIC_WRAP_BASE+0x1F8))
    206. 

  206. #define PMIC_WRAP_MD_ADC_RDATA_ADDR15   ((unsigned int *)(PMIC_WRAP_BASE+0x1FC))
    207. 

  207. #define PMIC_WRAP_MD_ADC_RDATA_ADDR16   ((unsigned int *)(PMIC_WRAP_BASE+0x200))
    208. 

  208. #define PMIC_WRAP_MD_ADC_RDATA_ADDR17   ((unsigned int *)(PMIC_WRAP_BASE+0x204))
    209. 

  209. #define PMIC_WRAP_MD_ADC_RDATA_ADDR18   ((unsigned int *)(PMIC_WRAP_BASE+0x208))
    210. 

  210. #define PMIC_WRAP_MD_ADC_RDATA_ADDR19   ((unsigned int *)(PMIC_WRAP_BASE+0x20C))
    211. 

  211. #define PMIC_WRAP_MD_ADC_RDATA_ADDR20   ((unsigned int *)(PMIC_WRAP_BASE+0x210))
    212. 

  212. #define PMIC_WRAP_MD_ADC_RDATA_ADDR21   ((unsigned int *)(PMIC_WRAP_BASE+0x214))
    213. 

  213. #define PMIC_WRAP_MD_ADC_RDATA_ADDR22   ((unsigned int *)(PMIC_WRAP_BASE+0x218))
    214. 

  214. #define PMIC_WRAP_MD_ADC_RDATA_ADDR23   ((unsigned int *)(PMIC_WRAP_BASE+0x21C))
    215. 

  215. #define PMIC_WRAP_MD_ADC_RDATA_ADDR24   ((unsigned int *)(PMIC_WRAP_BASE+0x220))
    216. 

  216. #define PMIC_WRAP_MD_ADC_RDATA_ADDR25   ((unsigned int *)(PMIC_WRAP_BASE+0x224))
    217. 

  217. #define PMIC_WRAP_MD_ADC_RDATA_ADDR26   ((unsigned int *)(PMIC_WRAP_BASE+0x228))
    218. 

  218. #define PMIC_WRAP_MD_ADC_RDATA_ADDR27   ((unsigned int *)(PMIC_WRAP_BASE+0x22C))
    219. 

  219. #define PMIC_WRAP_MD_ADC_RDATA_ADDR28   ((unsigned int *)(PMIC_WRAP_BASE+0x230))
    220. 

  220. #define PMIC_WRAP_MD_ADC_RDATA_ADDR29   ((unsigned int *)(PMIC_WRAP_BASE+0x234))
    221. 

  221. #define PMIC_WRAP_MD_ADC_RDATA_ADDR30   ((unsigned int *)(PMIC_WRAP_BASE+0x238))
    222. 

  222. #define PMIC_WRAP_MD_ADC_RDATA_ADDR31   ((unsigned int *)(PMIC_WRAP_BASE+0x23C))
    223. 

  223. #define PMIC_WRAP_MD_ADC_STA0           ((unsigned int *)(PMIC_WRAP_BASE+0x240))
    224. 

  224. #define PMIC_WRAP_MD_ADC_STA1           ((unsigned int *)(PMIC_WRAP_BASE+0x244))
    225. 

  225. #define PMIC_WRAP_MD_ADC_STA2           ((unsigned int *)(PMIC_WRAP_BASE+0x248))
    226. 

  226. 

  227. 

  228. 

  229. /* -----macro for wrapper  regsister-------------------------------------------------------- */
    230. 

  230. #define GET_STAUPD_DLE_CNT(x)        ((x>>0)  & 0x00000007)
    231. 

  231. #define GET_STAUPD_ALE_CNT(x)        ((x>>3)  & 0x00000007)
    232. 

  232. #define GET_STAUPD_FSM(x)            ((x>>6)  & 0x00000007)
    233. 

  233. #define GET_WRAP_CH_DLE_RESTCNT(x)   ((x>>0)  & 0x00000007)
    234. 

  234. #define GET_WRAP_CH_ALE_RESTCNT(x)   ((x>>3)  & 0x00000003)
    235. 

  235. #define GET_WRAP_AG_DLE_RESTCNT(x)   ((x>>5)  & 0x00000003)
    236. 

  236. #define GET_WRAP_CH_W(x)             ((x>>7)  & 0x00000001)
    237. 

  237. #define GET_WRAP_CH_REQ(x)           ((x>>8)  & 0x00000001)
    238. 

  238. #define GET_AG_WRAP_W(x)             ((x>>9)  & 0x00000001)
    239. 

  239. #define GET_AG_WRAP_REQ(x)           ((x>>10) & 0x00000001)
    240. 

  240. #define GET_WRAP_FSM(x)              ((x>>11) & 0x0000000f)
    241. 

  241. #define GET_HARB_WRAP_WDATA(x)       ((x>>0)  & 0x0000ffff)
    242. 

  242. #define GET_HARB_WRAP_ADR(x)         ((x>>16) & 0x00007fff)
    243. 

  243. #define GET_HARB_WRAP_REQ(x)         ((x>>31) & 0x00000001)
    244. 

  244. #define GET_HARB_DLE_EMPTY(x)        ((x>>0)  & 0x00000001)
    245. 

  245. #define GET_HARB_DLE_FULL(x)         ((x>>1)  & 0x00000001)
    246. 

  246. #define GET_HARB_VLD(x)              ((x>>2)  & 0x00000001)
    247. 

  247. #define GET_HARB_DLE_OWN(x)          ((x>>3)  & 0x0000000f)
    248. 

  248. #define GET_HARB_OWN(x)              ((x>>7)  & 0x0000000f)
    249. 

  249. #define GET_HARB_DLE_RESTCNT(x)      ((x>>11) & 0x0000000f)
    250. 

  250. #define GET_AG_HARB_REQ(x)           ((x>>15) & 0x000003ff)
    251. 

  251. #define GET_HARB_WRAP_W(x)           ((x>>25) & 0x00000001)
    252. 

  252. #define GET_HARB_WRAP_REQ0(x)        ((x>>26) & 0x00000001)
    253. 

  253. #define GET_SPI_WDATA(x)             ((x>>0)  & 0x000000ff)
    254. 

  254. #define GET_SPI_OP(x)                ((x>>8)  & 0x0000001f)
    255. 

  255. #define GET_SPI_W(x)                 ((x>>13) & 0x00000001)
    256. 

  256. #define GET_MAN_RDATA(x)             ((x>>0)  & 0x000000ff)
    257. 

  257. #define GET_MAN_FSM(x)               ((x>>8)  & 0x00000007)
    258. 

  258. #define GET_MAN_REQ(x)               ((x>>11) & 0x00000001)
    259. 

  259. #define GET_WACS0_WDATA(x)           ((x>>0)  & 0x0000ffff)
    260. 

  260. #define GET_WACS0_ADR(x)             ((x>>16) & 0x00007fff)
    261. 

  261. #define GET_WACS0_WRITE(x)           ((x>>31) & 0x00000001)
    262. 

  262. #define GET_WACS0_RDATA(x)           ((x>>0)  & 0x0000ffff)
    263. 

  263. #define GET_WACS0_FSM(x)             ((x>>16) & 0x00000007)
    264. 

  264. #define GET_WACS0_REQ(x)             ((x>>19) & 0x00000001)
    265. 

  265. #define GET_SYNC_IDLE0(x)            ((x>>20) & 0x00000001)
    266. 

  266. #define GET_INIT_DONE0(x)            ((x>>21) & 0x00000001)
    267. 

  267. #define GET_SYS_IDLE0(x)             ((x>>22) & 0x00000001)
    268. 

  268. #define GET_WACS0_FIFO_FILLCNT(x)    ((x>>24) & 0x0000000f)
    269. 

  269. #define GET_WACS0_FIFO_FREECNT(x)    ((x>>28) & 0x0000000f)
    270. 

  270. #define GET_WACS1_WDATA(x)           ((x>>0)  & 0x0000ffff)
    271. 

  271. #define GET_WACS1_ADR(x)             ((x>>16) & 0x00007fff)
    272. 

  272. #define GET_WACS1_WRITE(x)           ((x>>31) & 0x00000001)
    273. 

  273. #define GET_WACS1_RDATA(x)           ((x>>0)  & 0x0000ffff)
    274. 

  274. #define GET_WACS1_FSM(x)             ((x>>16) & 0x00000007)
    275. 

  275. #define GET_WACS1_REQ(x)             ((x>>19) & 0x00000001)
    276. 

  276. #define GET_SYNC_IDLE1(x)            ((x>>20) & 0x00000001)
    277. 

  277. #define GET_INIT_DONE1(x)            ((x>>21) & 0x00000001)
    278. 

  278. #define GET_SYS_IDLE1(x)             ((x>>22) & 0x00000001)
    279. 

  279. #define GET_WACS1_FIFO_FILLCNT(x)    ((x>>24) & 0x0000000f)
    280. 

  280. #define GET_WACS1_FIFO_FREECNT(x)    ((x>>28) & 0x0000000f)
    281. 

  281. #define GET_WACS2_WDATA(x)           ((x>>0)  & 0x0000ffff)
    282. 

  282. #define GET_WACS2_ADR(x)             ((x>>16) & 0x00007fff)
    283. 

  283. #define GET_WACS2_WRITE(x)           ((x>>31) & 0x00000001)
    284. 

  284. #define GET_WACS2_RDATA(x)           ((x>>0)  & 0x0000ffff)
    285. 

  285. #define GET_WACS2_FSM(x)             ((x>>16) & 0x00000007)
    286. 

  286. #define GET_WACS2_REQ(x)             ((x>>19) & 0x00000001)
    287. 

  287. #define GET_SYNC_IDLE2(x)            ((x>>20) & 0x00000001)
    288. 

  288. #define GET_INIT_DONE2(x)            ((x>>21) & 0x00000001)
    289. 

  289. #define GET_SYS_IDLE2(x)             ((x>>22) & 0x00000001)
    290. 

  290. #define GET_WACS2_FIFO_FILLCNT(x)    ((x>>24) & 0x0000000f)
    291. 

  291. #define GET_WACS2_FIFO_FREECNT(x)    ((x>>28) & 0x0000000f)
    292. 

  292. #define GET_WACS3_WDATA(x)           ((x>>0)  & 0x0000ffff)
    293. 

  293. #define GET_WACS3_ADR(x)             ((x>>16) & 0x00007fff)
    294. 

  294. #define GET_WACS3_WRITE(x)           ((x>>31) & 0x00000001)
    295. 

  295. #define GET_WACS3_RDATA(x)           ((x>>0)  & 0x0000ffff)
    296. 

  296. #define GET_WACS3_FSM(x)             ((x>>16) & 0x00000007)
    297. 

  297. #define GET_WACS3_REQ(x)             ((x>>19) & 0x00000001)
    298. 

  298. #define GET_SYNC_IDLE3(x)            ((x>>20) & 0x00000001)
    299. 

  299. #define GET_INIT_DONE3(x)            ((x>>21) & 0x00000001)
    300. 

  300. #define GET_SYS_IDLE3(x)             ((x>>22) & 0x00000001)
    301. 

  301. #define GET_WACS3_FIFO_FILLCNT(x)    ((x>>24) & 0x0000000f)
    302. 

  302. #define GET_WACS3_FIFO_FREECNT(x)    ((x>>28) & 0x0000000f)
    303. 

  303. #define GET_PWRAP_GPS_ACK(x)         ((x>>0)  & 0x00000001)
    304. 

  304. #define GET_GPS_PWRAP_REQ(x)         ((x>>1)  & 0x00000001)
    305. 

  305. #define GET_GPSINF_DLE_CNT(x)        ((x>>4)  & 0x00000003)
    306. 

  306. #define GET_GPSINF_ALE_CNT(x)        ((x>>6)  & 0x00000003)
    307. 

  307. #define GET_GPS_INF_FSM(x)           ((x>>8)  & 0x00000007)
    308. 

  308. #define GET_PWRAP_GPS_WDATA(x)       ((x>>17) & 0x00007fff)
    309. 

  309. #define GET_PWRAP_MD_ADC_NORM_DATA(x)  ((x>>0)  & 0x0000ffff)
    310. 

  310. #define GET_PWRAP_MD_ADC_INIT_DATA(x)  ((x>>16) & 0x0000ffff)
    311. 

  311. #define GET_BUF_MD_ADC_RDATA(x)      ((x>>0)  & 0x0000ffff)
    312. 

  312. #define GET_MD_ADC_BUF_WDATA(x)      ((x>>16) & 0x0000ffff)
    313. 

  313. #endif
    314. 

  314. /* Macros */
    315. 

  315. #define ENABLE	1
    316. 

  316. #define DISABLE 0
    317. 

  317. #define DISABLE_ALL 0
    318. 

  318. 

  319. /* #define PWRAP_ENABLE_DCM              WRAP_WR32(PMIC_WRAP_DCM_EN, ENABLE) */
    320. 

  320. /* #define PWRAP_DISABLE_DCM             WRAP_WR32(PMIC_WRAP_DCM_EN, DISABLE) */
    321. 

  321. /* #define PWRAP_DISABLE_DCM_DBC_PRD     WRAP_WR32(PMIC_WRAP_DCM_DBC_PRD, DISABLE) */
    322. 

  322. /* #define PWRAP_SET_DCM_DBC_PRD(x)      WRAP_WR32(PMIC_WRAP_DCM_DBC_PRD, x) */
    323. 

  323. /*  */
    324. 

  324. /* #define PWRAP_ENABLE                  WRAP_WR32(PMIC_WRAP_WRAP_EN,ENABLE) //enable wrap */
    325. 

  325. /* #define PWRAP_DISABLE                 WRAP_WR32(PMIC_WRAP_WRAP_EN,DISABLE) //disable wrap */
    326. 

  326. 

  327. /* HIPRIS_ARB */
    328. 

  328. #define MDINF		(1 << 0)
    329. 

  329. #define WACS0		(1 << 1)
    330. 

  330. #define WACS1		(1 << 2)
    331. 

  331. #if defined(CONFIG_ARCH_MT6735M)
    332. 

  332. #define WACS2		(1 << 4)
    333. 

  333. #else
    334. 

  334. #define WACS2		(1 << 5)
    335. 

  335. #endif
    336. 

  336. #define DVFSINF		(1 << 3)
    337. 

  337. #define STAUPD		(1 << 5)
    338. 

  338. #define GPSINF		(1 << 6)
    339. 

  339. /* #define PWRAP_HIPRIO_ARB_EN(x)        WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN,x)//need read back reg */
    340. 

  340. /* #define PWRAP_ENABLE_WACS2            WRAP_WR32(PMIC_WRAP_WACS2_EN,ENABLE) */
    341. 

  341. 

  342. /* MUX SEL */
    343. 

  343. #define	WRAPPER_MODE	0
    344. 

  344. #define	MANUAL_MODE		1
    345. 

  345. 

  346. /* OP TYPE */
    347. 

  347. #define OP_TYPE_CK	0	/* for MT6323 */
    348. 

  348. #define OP_TYPE_CSL	1	/* for MT6320 */
    349. 

  349. #define MSB		1	/* for MT6323 */
    350. 

  350. #define LSB		0	/* for MT6320 */
    351. 

  351. 

  352. /* SIG mode */
    353. 

  353. #define CHECK_CRC	0
    354. 

  354. #define CHECK_SIG	1
    355. 

  355. 

  356. 

  357. 

  358. /* macro for staupd sta fsm */
    359. 

  359. #define STAUPD_FSM_IDLE               (0x00)
    360. 

  360. #define STAUPD_FSM_REQ                (0x02)
    361. 

  361. #define STAUPD_FSM_WFDLE              (0x04)	/* wait for dle,wait for read data done, */
    362. 

  362. 

  363. /* macro for WRAP_STA  FSM */
    364. 

  364. /* #define WRAP_STA_FSM_IDLE               (0x00) */
    365. 

  365. /* #define WRAP_STA_IDLE               (0x00) */
    366. 

  366. 

  367. /* macro for MAN_RDATA  FSM */
    368. 

  368. #define MAN_FSM_NO_REQ             (0x00)
    369. 

  369. #define MAN_FSM_IDLE               (0x00)
    370. 

  370. #define MAN_FSM_REQ                (0x02)
    371. 

  371. #define MAN_FSM_WFDLE              (0x04)	/* wait for dle,wait for read data done, */
    372. 

  372. #define MAN_FSM_WFVLDCLR           (0x06)
    373. 

  373. 

  374. /* macro for WACS_FSM */
    375. 

  375. #define WACS_FSM_IDLE               (0x00)
    376. 

  376. #define WACS_FSM_REQ                (0x02)
    377. 

  377. #define WACS_FSM_WFDLE              (0x04)	/* wait for dle,wait for read data done, */
    378. 

  378. #define WACS_FSM_WFVLDCLR           (0x06)	/* finish read data , wait for valid flag clearing */
    379. 

  379. #define WACS_INIT_DONE              (0x01)
    380. 

  380. #define WACS_SYNC_IDLE              (0x01)
    381. 

  381. #define WACS_SYNC_BUSY              (0x00)
    382. 

  382. 

  383. 

  384. 

  385. /* -----macro for  regsister@PMIC ------------------------------------------------- */
    386. 

  386. #define SWCHR_REG_BASE (0x8000)
    387. 

  387. 

  388. #define MT6332_DEW_DIO_EN         ((SWCHR_REG_BASE+0x00F6))
    389. 

  389. #define MT6332_DEW_READ_TEST      ((SWCHR_REG_BASE+0x00F8))
    390. 

  390. #define MT6332_DEW_WRITE_TEST     ((SWCHR_REG_BASE+0x00FA))
    391. 

  391. #define MT6332_DEW_CRC_SWRST      ((SWCHR_REG_BASE+0x00FC))
    392. 

  392. #define MT6332_DEW_CRC_EN         ((SWCHR_REG_BASE+0x00FE))
    393. 

  393. #define MT6332_DEW_CRC_VAL        ((SWCHR_REG_BASE+0x0100))
    394. 

  394. #define MT6332_DEW_DBG_MON_SEL    ((SWCHR_REG_BASE+0x0102))
    395. 

  395. #define MT6332_DEW_CIPHER_KEY_SEL ((SWCHR_REG_BASE+0x0104))
    396. 

  396. #define MT6332_DEW_CIPHER_IV_SEL  ((SWCHR_REG_BASE+0x0106))
    397. 

  397. #define MT6332_DEW_CIPHER_EN      ((SWCHR_REG_BASE+0x0108))
    398. 

  398. #define MT6332_DEW_CIPHER_RDY     ((SWCHR_REG_BASE+0x010A))
    399. 

  399. #define MT6332_DEW_CIPHER_MODE    ((SWCHR_REG_BASE+0x010C))
    400. 

  400. #define MT6332_DEW_CIPHER_SWRST   ((SWCHR_REG_BASE+0x010E))
    401. 

  401. #define MT6332_DEW_RDDMY_NO       ((SWCHR_REG_BASE+0x0110))
    402. 

  402. 

  403. /*
    404. 

  404. #define MT6328_PMIC_REG_BASE (0x0000)
    405. 

  405. 

  406. #define MT6328_DEW_DIO_EN            ((unsigned int)(MT6328_PMIC_REG_BASE+0x02D4))
    407. 

  407. #define MT6328_DEW_READ_TEST         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02D6))
    408. 

  408. #define MT6328_DEW_WRITE_TEST        ((unsigned int)(MT6328_PMIC_REG_BASE+0x02D8))
    409. 

  409. #define MT6328_DEW_CRC_SWRST         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02DA))
    410. 

  410. #define MT6328_DEW_CRC_EN            ((unsigned int)(MT6328_PMIC_REG_BASE+0x02DC))
    411. 

  411. #define MT6328_DEW_CRC_VAL           ((unsigned int)(MT6328_PMIC_REG_BASE+0x02DE))
    412. 

  412. #define MT6328_DEW_DBG_MON_SEL       ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E0))
    413. 

  413. #define MT6328_DEW_CIPHER_KEY_SEL    ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E2))
    414. 

  414. #define MT6328_DEW_CIPHER_IV_SEL     ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E4))
    415. 

  415. #define MT6328_DEW_CIPHER_EN         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E6))
    416. 

  416. #define MT6328_DEW_CIPHER_RDY        ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E8))
    417. 

  417. #define MT6328_DEW_CIPHER_MODE       ((unsigned int)(MT6328_PMIC_REG_BASE+0x02EA))
    418. 

  418. #define MT6328_DEW_CIPHER_SWRST      ((unsigned int)(MT6328_PMIC_REG_BASE+0x02EC))
    419. 

  419. #define MT6328_DEW_RDDMY_NO          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02EE))
    420. 

  420. */
    421. 

  421. 

  422. #define MT6328_PMIC_REG_BASE (0x0000)
    423. 

  423. 

  424. #define MT6328_STRUP_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0000))
    425. 

  425. #define MT6328_STRUP_CON2            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0002))
    426. 

  426. #define MT6328_STRUP_CON3            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0004))
    427. 

  427. #define MT6328_STRUP_CON4            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0006))
    428. 

  428. #define MT6328_STRUP_CON5            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0008))
    429. 

  429. #define MT6328_STRUP_CON6            ((unsigned int)(MT6328_PMIC_REG_BASE+0x000A))
    430. 

  430. #define MT6328_STRUP_CON7            ((unsigned int)(MT6328_PMIC_REG_BASE+0x000C))
    431. 

  431. #define MT6328_STRUP_CON8            ((unsigned int)(MT6328_PMIC_REG_BASE+0x000E))
    432. 

  432. #define MT6328_STRUP_CON9            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0010))
    433. 

  433. #define MT6328_STRUP_CON10           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0012))
    434. 

  434. #define MT6328_STRUP_CON11           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0014))
    435. 

  435. #define MT6328_STRUP_CON12           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0016))
    436. 

  436. #define MT6328_STRUP_CON13           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0018))
    437. 

  437. #define MT6328_STRUP_CON14           ((unsigned int)(MT6328_PMIC_REG_BASE+0x001A))
    438. 

  438. #define MT6328_STRUP_CON15           ((unsigned int)(MT6328_PMIC_REG_BASE+0x001C))
    439. 

  439. #define MT6328_STRUP_CON16           ((unsigned int)(MT6328_PMIC_REG_BASE+0x001E))
    440. 

  440. #define MT6328_STRUP_CON17           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0020))
    441. 

  441. #define MT6328_STRUP_CON18           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0022))
    442. 

  442. #define MT6328_STRUP_CON19           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0024))
    443. 

  443. #define MT6328_STRUP_CON20           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0026))
    444. 

  444. #define MT6328_STRUP_CON21           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0028))
    445. 

  445. #define MT6328_STRUP_CON22           ((unsigned int)(MT6328_PMIC_REG_BASE+0x002A))
    446. 

  446. #define MT6328_STRUP_CON23           ((unsigned int)(MT6328_PMIC_REG_BASE+0x002C))
    447. 

  447. #define MT6328_STRUP_CON24           ((unsigned int)(MT6328_PMIC_REG_BASE+0x002E))
    448. 

  448. #define MT6328_STRUP_CON25           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0030))
    449. 

  449. #define MT6328_STRUP_CON26           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0032))
    450. 

  450. #define MT6328_STRUP_CON27           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0034))
    451. 

  451. #define MT6328_STRUP_CON28           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0036))
    452. 

  452. #define MT6328_STRUP_CON29           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0038))
    453. 

  453. #define MT6328_STRUP_CON30           ((unsigned int)(MT6328_PMIC_REG_BASE+0x003A))
    454. 

  454. #define MT6328_STRUP_CON31           ((unsigned int)(MT6328_PMIC_REG_BASE+0x003C))
    455. 

  455. #define MT6328_STRUP_CON32           ((unsigned int)(MT6328_PMIC_REG_BASE+0x003E))
    456. 

  456. #define MT6328_STRUP_ANA_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0040))
    457. 

  457. #define MT6328_HWCID                 ((unsigned int)(MT6328_PMIC_REG_BASE+0x0200))
    458. 

  458. #define MT6328_SWCID                 ((unsigned int)(MT6328_PMIC_REG_BASE+0x0202))
    459. 

  459. #define MT6328_TOP_CON               ((unsigned int)(MT6328_PMIC_REG_BASE+0x0204))
    460. 

  460. #define MT6328_TEST_OUT              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0206))
    461. 

  461. #define MT6328_TEST_CON0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0208))
    462. 

  462. #define MT6328_TEST_CON1             ((unsigned int)(MT6328_PMIC_REG_BASE+0x020A))
    463. 

  463. #define MT6328_TESTMODE_SW           ((unsigned int)(MT6328_PMIC_REG_BASE+0x020C))
    464. 

  464. #define MT6328_EN_STATUS0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x020E))
    465. 

  465. #define MT6328_EN_STATUS1            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0210))
    466. 

  466. #define MT6328_EN_STATUS2            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0212))
    467. 

  467. #define MT6328_OCSTATUS0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0214))
    468. 

  468. #define MT6328_OCSTATUS1             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0216))
    469. 

  469. #define MT6328_OCSTATUS2             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0218))
    470. 

  470. #define MT6328_PGDEBSTATUS           ((unsigned int)(MT6328_PMIC_REG_BASE+0x021A))
    471. 

  471. #define MT6328_PGSTATUS              ((unsigned int)(MT6328_PMIC_REG_BASE+0x021C))
    472. 

  472. #define MT6328_THERMALSTATUS         ((unsigned int)(MT6328_PMIC_REG_BASE+0x021E))
    473. 

  473. #define MT6328_TOPSTATUS             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0220))
    474. 

  474. #define MT6328_TDSEL_CON             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0222))
    475. 

  475. #define MT6328_RDSEL_CON             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0224))
    476. 

  476. #define MT6328_SMT_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0226))
    477. 

  477. #define MT6328_SMT_CON1              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0228))
    478. 

  478. #define MT6328_SMT_CON2              ((unsigned int)(MT6328_PMIC_REG_BASE+0x022A))
    479. 

  479. #define MT6328_DRV_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x022C))
    480. 

  480. #define MT6328_DRV_CON1              ((unsigned int)(MT6328_PMIC_REG_BASE+0x022E))
    481. 

  481. #define MT6328_DRV_CON2              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0230))
    482. 

  482. #define MT6328_DRV_CON3              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0232))
    483. 

  483. #define MT6328_TOP_STATUS            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0234))
    484. 

  484. #define MT6328_TOP_STATUS_SET        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0236))
    485. 

  485. #define MT6328_TOP_STATUS_CLR        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0238))
    486. 

  486. #define MT6328_RGS_ANA_MON           ((unsigned int)(MT6328_PMIC_REG_BASE+0x023A))
    487. 

  487. #define MT6328_TOP_CKPDN_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x023C))
    488. 

  488. #define MT6328_TOP_CKPDN_CON0_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x023E))
    489. 

  489. #define MT6328_TOP_CKPDN_CON0_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0240))
    490. 

  490. #define MT6328_TOP_CKPDN_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0242))
    491. 

  491. #define MT6328_TOP_CKPDN_CON1_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0244))
    492. 

  492. #define MT6328_TOP_CKPDN_CON1_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0246))
    493. 

  493. #define MT6328_TOP_CKPDN_CON2        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0248))
    494. 

  494. #define MT6328_TOP_CKPDN_CON2_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x024A))
    495. 

  495. #define MT6328_TOP_CKPDN_CON2_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x024C))
    496. 

  496. #define MT6328_TOP_CKPDN_CON3        ((unsigned int)(MT6328_PMIC_REG_BASE+0x024E))
    497. 

  497. #define MT6328_TOP_CKPDN_CON3_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0250))
    498. 

  498. #define MT6328_TOP_CKPDN_CON3_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0252))
    499. 

  499. #define MT6328_TOP_CKPDN_CON4        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0254))
    500. 

  500. #define MT6328_TOP_CKPDN_CON4_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0256))
    501. 

  501. #define MT6328_TOP_CKPDN_CON4_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0258))
    502. 

  502. #define MT6328_TOP_CKSEL_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x025A))
    503. 

  503. #define MT6328_TOP_CKSEL_CON0_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x025C))
    504. 

  504. #define MT6328_TOP_CKSEL_CON0_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x025E))
    505. 

  505. #define MT6328_TOP_CKSEL_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0260))
    506. 

  506. #define MT6328_TOP_CKSEL_CON1_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0262))
    507. 

  507. #define MT6328_TOP_CKSEL_CON1_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0264))
    508. 

  508. #define MT6328_TOP_CKSEL_CON2        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0266))
    509. 

  509. #define MT6328_TOP_CKSEL_CON2_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0268))
    510. 

  510. #define MT6328_TOP_CKSEL_CON2_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x026A))
    511. 

  511. #define MT6328_TOP_CKDIVSEL_CON0     ((unsigned int)(MT6328_PMIC_REG_BASE+0x026C))
    512. 

  512. #define MT6328_TOP_CKDIVSEL_CON0_SET ((unsigned int)(MT6328_PMIC_REG_BASE+0x026E))
    513. 

  513. #define MT6328_TOP_CKDIVSEL_CON0_CLR ((unsigned int)(MT6328_PMIC_REG_BASE+0x0270))
    514. 

  514. #define MT6328_TOP_CKDIVSEL_CON1     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0272))
    515. 

  515. #define MT6328_TOP_CKDIVSEL_CON1_SET ((unsigned int)(MT6328_PMIC_REG_BASE+0x0274))
    516. 

  516. #define MT6328_TOP_CKDIVSEL_CON1_CLR ((unsigned int)(MT6328_PMIC_REG_BASE+0x0276))
    517. 

  517. #define MT6328_TOP_CKHWEN_CON0       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0278))
    518. 

  518. #define MT6328_TOP_CKHWEN_CON0_SET   ((unsigned int)(MT6328_PMIC_REG_BASE+0x027A))
    519. 

  519. #define MT6328_TOP_CKHWEN_CON0_CLR   ((unsigned int)(MT6328_PMIC_REG_BASE+0x027C))
    520. 

  520. #define MT6328_TOP_CKHWEN_CON1       ((unsigned int)(MT6328_PMIC_REG_BASE+0x027E))
    521. 

  521. #define MT6328_TOP_CKHWEN_CON1_SET   ((unsigned int)(MT6328_PMIC_REG_BASE+0x0280))
    522. 

  522. #define MT6328_TOP_CKHWEN_CON1_CLR   ((unsigned int)(MT6328_PMIC_REG_BASE+0x0282))
    523. 

  523. #define MT6328_TOP_CKTST_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0284))
    524. 

  524. #define MT6328_TOP_CKTST_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0286))
    525. 

  525. #define MT6328_TOP_CKTST_CON2        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0288))
    526. 

  526. #define MT6328_TOP_CLKSQ             ((unsigned int)(MT6328_PMIC_REG_BASE+0x028A))
    527. 

  527. #define MT6328_TOP_CLKSQ_SET         ((unsigned int)(MT6328_PMIC_REG_BASE+0x028C))
    528. 

  528. #define MT6328_TOP_CLKSQ_CLR         ((unsigned int)(MT6328_PMIC_REG_BASE+0x028E))
    529. 

  529. #define MT6328_TOP_CLKSQ_RTC         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0290))
    530. 

  530. #define MT6328_TOP_CLKSQ_RTC_SET     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0292))
    531. 

  531. #define MT6328_TOP_CLKSQ_RTC_CLR     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0294))
    532. 

  532. #define MT6328_TOP_CLK_TRIM          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0296))
    533. 

  533. #define MT6328_TOP_RST_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0298))
    534. 

  534. #define MT6328_TOP_RST_CON0_SET      ((unsigned int)(MT6328_PMIC_REG_BASE+0x029A))
    535. 

  535. #define MT6328_TOP_RST_CON0_CLR      ((unsigned int)(MT6328_PMIC_REG_BASE+0x029C))
    536. 

  536. #define MT6328_TOP_RST_CON1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x029E))
    537. 

  537. #define MT6328_TOP_RST_MISC          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02A0))
    538. 

  538. #define MT6328_TOP_RST_MISC_SET      ((unsigned int)(MT6328_PMIC_REG_BASE+0x02A2))
    539. 

  539. #define MT6328_TOP_RST_MISC_CLR      ((unsigned int)(MT6328_PMIC_REG_BASE+0x02A4))
    540. 

  540. #define MT6328_TOP_RST_STATUS        ((unsigned int)(MT6328_PMIC_REG_BASE+0x02A6))
    541. 

  541. #define MT6328_TOP_RST_STATUS_SET    ((unsigned int)(MT6328_PMIC_REG_BASE+0x02A8))
    542. 

  542. #define MT6328_TOP_RST_STATUS_CLR    ((unsigned int)(MT6328_PMIC_REG_BASE+0x02AA))
    543. 

  543. #define MT6328_INT_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x02AC))
    544. 

  544. #define MT6328_INT_CON0_SET          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02AE))
    545. 

  545. #define MT6328_INT_CON0_CLR          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02B0))
    546. 

  546. #define MT6328_INT_CON1              ((unsigned int)(MT6328_PMIC_REG_BASE+0x02B2))
    547. 

  547. #define MT6328_INT_CON1_SET          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02B4))
    548. 

  548. #define MT6328_INT_CON1_CLR          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02B6))
    549. 

  549. #define MT6328_INT_CON2              ((unsigned int)(MT6328_PMIC_REG_BASE+0x02B8))
    550. 

  550. #define MT6328_INT_CON2_SET          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02BA))
    551. 

  551. #define MT6328_INT_CON2_CLR          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02BC))
    552. 

  552. #define MT6328_INT_MISC_CON          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02BE))
    553. 

  553. #define MT6328_INT_MISC_CON_SET      ((unsigned int)(MT6328_PMIC_REG_BASE+0x02C0))
    554. 

  554. #define MT6328_INT_MISC_CON_CLR      ((unsigned int)(MT6328_PMIC_REG_BASE+0x02C2))
    555. 

  555. #define MT6328_INT_STATUS0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x02C4))
    556. 

  556. #define MT6328_INT_STATUS1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x02C6))
    557. 

  557. #define MT6328_INT_STATUS2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x02C8))
    558. 

  558. #define MT6328_OC_GEAR_0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x02CA))
    559. 

  559. #define MT6328_FQMTR_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x02CC))
    560. 

  560. #define MT6328_FQMTR_CON1            ((unsigned int)(MT6328_PMIC_REG_BASE+0x02CE))
    561. 

  561. #define MT6328_FQMTR_CON2            ((unsigned int)(MT6328_PMIC_REG_BASE+0x02D0))
    562. 

  562. #define MT6328_RG_SPI_CON            ((unsigned int)(MT6328_PMIC_REG_BASE+0x02D2))
    563. 

  563. #define MT6328_DEW_DIO_EN            ((unsigned int)(MT6328_PMIC_REG_BASE+0x02D4))
    564. 

  564. #define MT6328_DEW_READ_TEST         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02D6))
    565. 

  565. #define MT6328_DEW_WRITE_TEST        ((unsigned int)(MT6328_PMIC_REG_BASE+0x02D8))
    566. 

  566. #define MT6328_DEW_CRC_SWRST         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02DA))
    567. 

  567. #define MT6328_DEW_CRC_EN            ((unsigned int)(MT6328_PMIC_REG_BASE+0x02DC))
    568. 

  568. #define MT6328_DEW_CRC_VAL           ((unsigned int)(MT6328_PMIC_REG_BASE+0x02DE))
    569. 

  569. #define MT6328_DEW_DBG_MON_SEL       ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E0))
    570. 

  570. #define MT6328_DEW_CIPHER_KEY_SEL    ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E2))
    571. 

  571. #define MT6328_DEW_CIPHER_IV_SEL     ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E4))
    572. 

  572. #define MT6328_DEW_CIPHER_EN         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E6))
    573. 

  573. #define MT6328_DEW_CIPHER_RDY        ((unsigned int)(MT6328_PMIC_REG_BASE+0x02E8))
    574. 

  574. #define MT6328_DEW_CIPHER_MODE       ((unsigned int)(MT6328_PMIC_REG_BASE+0x02EA))
    575. 

  575. #define MT6328_DEW_CIPHER_SWRST      ((unsigned int)(MT6328_PMIC_REG_BASE+0x02EC))
    576. 

  576. #define MT6328_DEW_RDDMY_NO          ((unsigned int)(MT6328_PMIC_REG_BASE+0x02EE))
    577. 

  577. #define MT6328_INT_TYPE_CON0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02F0))
    578. 

  578. #define MT6328_INT_TYPE_CON0_SET     ((unsigned int)(MT6328_PMIC_REG_BASE+0x02F2))
    579. 

  579. #define MT6328_INT_TYPE_CON0_CLR     ((unsigned int)(MT6328_PMIC_REG_BASE+0x02F4))
    580. 

  580. #define MT6328_INT_TYPE_CON1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02F6))
    581. 

  581. #define MT6328_INT_TYPE_CON1_SET     ((unsigned int)(MT6328_PMIC_REG_BASE+0x02F8))
    582. 

  582. #define MT6328_INT_TYPE_CON1_CLR     ((unsigned int)(MT6328_PMIC_REG_BASE+0x02FA))
    583. 

  583. #define MT6328_INT_TYPE_CON2         ((unsigned int)(MT6328_PMIC_REG_BASE+0x02FC))
    584. 

  584. #define MT6328_INT_TYPE_CON2_SET     ((unsigned int)(MT6328_PMIC_REG_BASE+0x02FE))
    585. 

  585. #define MT6328_INT_TYPE_CON2_CLR     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0300))
    586. 

  586. #define MT6328_INT_STA               ((unsigned int)(MT6328_PMIC_REG_BASE+0x0302))
    587. 

  587. #define MT6328_BUCK_ALL_CON0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0400))
    588. 

  588. #define MT6328_BUCK_ALL_CON1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0402))
    589. 

  589. #define MT6328_BUCK_ALL_CON2         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0404))
    590. 

  590. #define MT6328_BUCK_ALL_CON3         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0406))
    591. 

  591. #define MT6328_BUCK_ALL_CON4         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0408))
    592. 

  592. #define MT6328_BUCK_ALL_CON5         ((unsigned int)(MT6328_PMIC_REG_BASE+0x040A))
    593. 

  593. #define MT6328_BUCK_ALL_CON6         ((unsigned int)(MT6328_PMIC_REG_BASE+0x040C))
    594. 

  594. #define MT6328_BUCK_ALL_CON9         ((unsigned int)(MT6328_PMIC_REG_BASE+0x040E))
    595. 

  595. #define MT6328_BUCK_ALL_CON12        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0410))
    596. 

  596. #define MT6328_BUCK_ALL_CON13        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0412))
    597. 

  597. #define MT6328_BUCK_ALL_CON14        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0414))
    598. 

  598. #define MT6328_BUCK_ALL_CON16        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0416))
    599. 

  599. #define MT6328_BUCK_ALL_CON18        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0418))
    600. 

  600. #define MT6328_BUCK_ALL_CON19        ((unsigned int)(MT6328_PMIC_REG_BASE+0x041A))
    601. 

  601. #define MT6328_BUCK_ALL_CON20        ((unsigned int)(MT6328_PMIC_REG_BASE+0x041C))
    602. 

  602. #define MT6328_BUCK_ALL_CON21        ((unsigned int)(MT6328_PMIC_REG_BASE+0x041E))
    603. 

  603. #define MT6328_BUCK_ALL_CON22        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0420))
    604. 

  604. #define MT6328_BUCK_ALL_CON23        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0422))
    605. 

  605. #define MT6328_BUCK_ALL_CON24        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0424))
    606. 

  606. #define MT6328_BUCK_ALL_CON25        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0426))
    607. 

  607. #define MT6328_BUCK_ALL_CON26        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0428))
    608. 

  608. #define MT6328_BUCK_ALL_CON27        ((unsigned int)(MT6328_PMIC_REG_BASE+0x042A))
    609. 

  609. #define MT6328_BUCK_ALL_CON28        ((unsigned int)(MT6328_PMIC_REG_BASE+0x042C))
    610. 

  610. #define MT6328_SMPS_TOP_ANA_CON0     ((unsigned int)(MT6328_PMIC_REG_BASE+0x042E))
    611. 

  611. #define MT6328_SMPS_TOP_ANA_CON1     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0430))
    612. 

  612. #define MT6328_SMPS_TOP_ANA_CON2     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0432))
    613. 

  613. #define MT6328_SMPS_TOP_ANA_CON3     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0434))
    614. 

  614. #define MT6328_SMPS_TOP_ANA_CON4     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0436))
    615. 

  615. #define MT6328_SMPS_TOP_ANA_CON5     ((unsigned int)(MT6328_PMIC_REG_BASE+0x0438))
    616. 

  616. #define MT6328_SMPS_TOP_ANA_CON6     ((unsigned int)(MT6328_PMIC_REG_BASE+0x043A))
    617. 

  617. #define MT6328_SMPS_TOP_ANA_CON7     ((unsigned int)(MT6328_PMIC_REG_BASE+0x043C))
    618. 

  618. #define MT6328_SMPS_TOP_ANA_CON8     ((unsigned int)(MT6328_PMIC_REG_BASE+0x043E))
    619. 

  619. #define MT6328_VCORE_ANA_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0440))
    620. 

  620. #define MT6328_VCORE_ANA_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0442))
    621. 

  621. #define MT6328_VCORE_ANA_CON2        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0444))
    622. 

  622. #define MT6328_VCORE_ANA_CON3        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0446))
    623. 

  623. #define MT6328_VCORE_ANA_CON4        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0448))
    624. 

  624. #define MT6328_VSYS22_ANA_CON0       ((unsigned int)(MT6328_PMIC_REG_BASE+0x044A))
    625. 

  625. #define MT6328_VSYS22_ANA_CON1       ((unsigned int)(MT6328_PMIC_REG_BASE+0x044C))
    626. 

  626. #define MT6328_VSYS22_ANA_CON2       ((unsigned int)(MT6328_PMIC_REG_BASE+0x044E))
    627. 

  627. #define MT6328_VSYS22_ANA_CON3       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0450))
    628. 

  628. #define MT6328_VSYS22_ANA_CON4       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0452))
    629. 

  629. #define MT6328_VPROC_ANA_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0454))
    630. 

  630. #define MT6328_VPROC_ANA_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0456))
    631. 

  631. #define MT6328_VPROC_ANA_CON2        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0458))
    632. 

  632. #define MT6328_VPROC_ANA_CON3        ((unsigned int)(MT6328_PMIC_REG_BASE+0x045A))
    633. 

  633. #define MT6328_VPROC_ANA_CON4        ((unsigned int)(MT6328_PMIC_REG_BASE+0x045C))
    634. 

  634. #define MT6328_OSC32_ANA_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x045E))
    635. 

  635. #define MT6328_OSC32_ANA_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0460))
    636. 

  636. #define MT6328_VPA_ANA_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0462))
    637. 

  637. #define MT6328_VPA_ANA_CON1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0464))
    638. 

  638. #define MT6328_VPA_ANA_CON2          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0466))
    639. 

  639. #define MT6328_VPA_ANA_CON3          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0468))
    640. 

  640. #define MT6328_VLTE_ANA_CON0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x046A))
    641. 

  641. #define MT6328_VLTE_ANA_CON1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x046C))
    642. 

  642. #define MT6328_VLTE_ANA_CON2         ((unsigned int)(MT6328_PMIC_REG_BASE+0x046E))
    643. 

  643. #define MT6328_VLTE_ANA_CON3         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0470))
    644. 

  644. #define MT6328_VLTE_ANA_CON4         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0472))
    645. 

  645. #define MT6328_VPROC_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0474))
    646. 

  646. #define MT6328_VPROC_CON7            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0482))
    647. 

  647. #define MT6328_VPROC_CON8            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0484))
    648. 

  648. #define MT6328_VPROC_CON9            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0486))
    649. 

  649. #define MT6328_VPROC_CON10           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0488))
    650. 

  650. #define MT6328_VPROC_CON11           ((unsigned int)(MT6328_PMIC_REG_BASE+0x048A))
    651. 

  651. #define MT6328_VPROC_CON12           ((unsigned int)(MT6328_PMIC_REG_BASE+0x048C))
    652. 

  652. #define MT6328_VPROC_CON13           ((unsigned int)(MT6328_PMIC_REG_BASE+0x048E))
    653. 

  653. #define MT6328_VPROC_CON14           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0490))
    654. 

  654. #define MT6328_VPROC_CON15           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0492))
    655. 

  655. #define MT6328_VPROC_CON16           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0494))
    656. 

  656. #define MT6328_VPROC_CON17           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0496))
    657. 

  657. #define MT6328_VPROC_CON18           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0498))
    658. 

  658. #define MT6328_VPROC_CON19           ((unsigned int)(MT6328_PMIC_REG_BASE+0x049A))
    659. 

  659. #define MT6328_VSRAM_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x049C))
    660. 

  660. #define MT6328_VSRAM_CON7            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04AA))
    661. 

  661. #define MT6328_VSRAM_CON8            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04AC))
    662. 

  662. #define MT6328_VSRAM_CON9            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04AE))
    663. 

  663. #define MT6328_VSRAM_CON10           ((unsigned int)(MT6328_PMIC_REG_BASE+0x04B0))
    664. 

  664. #define MT6328_VSRAM_CON11           ((unsigned int)(MT6328_PMIC_REG_BASE+0x04B2))
    665. 

  665. #define MT6328_VSRAM_CON12           ((unsigned int)(MT6328_PMIC_REG_BASE+0x04B4))
    666. 

  666. #define MT6328_VSRAM_CON13           ((unsigned int)(MT6328_PMIC_REG_BASE+0x04B6))
    667. 

  667. #define MT6328_VSRAM_CON14           ((unsigned int)(MT6328_PMIC_REG_BASE+0x04B8))
    668. 

  668. #define MT6328_VSRAM_CON18           ((unsigned int)(MT6328_PMIC_REG_BASE+0x04C0))
    669. 

  669. #define MT6328_VSRAM_CON19           ((unsigned int)(MT6328_PMIC_REG_BASE+0x04C2))
    670. 

  670. #define MT6328_VLTE_CON0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x04C4))
    671. 

  671. #define MT6328_VLTE_CON7             ((unsigned int)(MT6328_PMIC_REG_BASE+0x04D2))
    672. 

  672. #define MT6328_VLTE_CON8             ((unsigned int)(MT6328_PMIC_REG_BASE+0x04D4))
    673. 

  673. #define MT6328_VLTE_CON9             ((unsigned int)(MT6328_PMIC_REG_BASE+0x04D6))
    674. 

  674. #define MT6328_VLTE_CON10            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04D8))
    675. 

  675. #define MT6328_VLTE_CON11            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04DA))
    676. 

  676. #define MT6328_VLTE_CON12            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04DC))
    677. 

  677. #define MT6328_VLTE_CON13            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04DE))
    678. 

  678. #define MT6328_VLTE_CON14            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04E0))
    679. 

  679. #define MT6328_VLTE_CON15            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04E2))
    680. 

  680. #define MT6328_VLTE_CON16            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04E4))
    681. 

  681. #define MT6328_VLTE_CON17            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04E6))
    682. 

  682. #define MT6328_VLTE_CON18            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04E8))
    683. 

  683. #define MT6328_VLTE_CON19            ((unsigned int)(MT6328_PMIC_REG_BASE+0x04EA))
    684. 

  684. #define MT6328_VCORE1_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0600))
    685. 

  685. #define MT6328_VCORE1_CON7           ((unsigned int)(MT6328_PMIC_REG_BASE+0x060E))
    686. 

  686. #define MT6328_VCORE1_CON8           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0610))
    687. 

  687. #define MT6328_VCORE1_CON9           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0612))
    688. 

  688. #define MT6328_VCORE1_CON10          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0614))
    689. 

  689. #define MT6328_VCORE1_CON11          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0616))
    690. 

  690. #define MT6328_VCORE1_CON12          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0618))
    691. 

  691. #define MT6328_VCORE1_CON13          ((unsigned int)(MT6328_PMIC_REG_BASE+0x061A))
    692. 

  692. #define MT6328_VCORE1_CON14          ((unsigned int)(MT6328_PMIC_REG_BASE+0x061C))
    693. 

  693. #define MT6328_VCORE1_CON15          ((unsigned int)(MT6328_PMIC_REG_BASE+0x061E))
    694. 

  694. #define MT6328_VCORE1_CON16          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0620))
    695. 

  695. #define MT6328_VCORE1_CON17          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0622))
    696. 

  696. #define MT6328_VCORE1_CON18          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0624))
    697. 

  697. #define MT6328_VCORE1_CON19          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0626))
    698. 

  698. #define MT6328_VSYS22_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0628))
    699. 

  699. #define MT6328_VSYS22_CON7           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0636))
    700. 

  700. #define MT6328_VSYS22_CON8           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0638))
    701. 

  701. #define MT6328_VSYS22_CON9           ((unsigned int)(MT6328_PMIC_REG_BASE+0x063A))
    702. 

  702. #define MT6328_VSYS22_CON10          ((unsigned int)(MT6328_PMIC_REG_BASE+0x063C))
    703. 

  703. #define MT6328_VSYS22_CON11          ((unsigned int)(MT6328_PMIC_REG_BASE+0x063E))
    704. 

  704. #define MT6328_VSYS22_CON12          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0640))
    705. 

  705. #define MT6328_VSYS22_CON13          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0642))
    706. 

  706. #define MT6328_VSYS22_CON14          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0644))
    707. 

  707. #define MT6328_VSYS22_CON15          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0646))
    708. 

  708. #define MT6328_VSYS22_CON16          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0648))
    709. 

  709. #define MT6328_VSYS22_CON17          ((unsigned int)(MT6328_PMIC_REG_BASE+0x064A))
    710. 

  710. #define MT6328_VSYS22_CON18          ((unsigned int)(MT6328_PMIC_REG_BASE+0x064C))
    711. 

  711. #define MT6328_VSYS22_CON19          ((unsigned int)(MT6328_PMIC_REG_BASE+0x064E))
    712. 

  712. #define MT6328_VPA_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0650))
    713. 

  713. #define MT6328_VPA_CON7              ((unsigned int)(MT6328_PMIC_REG_BASE+0x065E))
    714. 

  714. #define MT6328_VPA_CON8              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0660))
    715. 

  715. #define MT6328_VPA_CON9              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0662))
    716. 

  716. #define MT6328_VPA_CON10             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0664))
    717. 

  717. #define MT6328_VPA_CON11             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0666))
    718. 

  718. #define MT6328_VPA_CON12             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0668))
    719. 

  719. #define MT6328_VPA_CON13             ((unsigned int)(MT6328_PMIC_REG_BASE+0x066A))
    720. 

  720. #define MT6328_VPA_CON14             ((unsigned int)(MT6328_PMIC_REG_BASE+0x066C))
    721. 

  721. #define MT6328_VPA_CON15             ((unsigned int)(MT6328_PMIC_REG_BASE+0x066E))
    722. 

  722. #define MT6328_VPA_CON16             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0670))
    723. 

  723. #define MT6328_VPA_CON17             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0672))
    724. 

  724. #define MT6328_VPA_CON18             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0674))
    725. 

  725. #define MT6328_VPA_CON19             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0676))
    726. 

  726. #define MT6328_VPA_CON20             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0678))
    727. 

  727. #define MT6328_VPA_CON21             ((unsigned int)(MT6328_PMIC_REG_BASE+0x067A))
    728. 

  728. #define MT6328_VPA_CON22             ((unsigned int)(MT6328_PMIC_REG_BASE+0x067C))
    729. 

  729. #define MT6328_VPA_CON23             ((unsigned int)(MT6328_PMIC_REG_BASE+0x067E))
    730. 

  730. #define MT6328_VPA_CON24             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0680))
    731. 

  731. #define MT6328_BUCK_K_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0682))
    732. 

  732. #define MT6328_BUCK_K_CON1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0684))
    733. 

  733. #define MT6328_BUCK_K_CON2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0686))
    734. 

  734. #define MT6328_BUCK_K_CON3           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0688))
    735. 

  735. #define MT6328_ZCD_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0800))
    736. 

  736. #define MT6328_ZCD_CON1              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0802))
    737. 

  737. #define MT6328_ZCD_CON2              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0804))
    738. 

  738. #define MT6328_ZCD_CON3              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0806))
    739. 

  739. #define MT6328_ZCD_CON4              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0808))
    740. 

  740. #define MT6328_ZCD_CON5              ((unsigned int)(MT6328_PMIC_REG_BASE+0x080A))
    741. 

  741. #define MT6328_ISINK0_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x080C))
    742. 

  742. #define MT6328_ISINK0_CON1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x080E))
    743. 

  743. #define MT6328_ISINK0_CON2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0810))
    744. 

  744. #define MT6328_ISINK0_CON3           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0812))
    745. 

  745. #define MT6328_ISINK1_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0814))
    746. 

  746. #define MT6328_ISINK1_CON1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0816))
    747. 

  747. #define MT6328_ISINK1_CON2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0818))
    748. 

  748. #define MT6328_ISINK1_CON3           ((unsigned int)(MT6328_PMIC_REG_BASE+0x081A))
    749. 

  749. #define MT6328_ISINK2_CON1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x081C))
    750. 

  750. #define MT6328_ISINK3_CON1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x081E))
    751. 

  751. #define MT6328_ISINK_ANA0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0820))
    752. 

  752. #define MT6328_ISINK_ANA1            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0822))
    753. 

  753. #define MT6328_ISINK_PHASE_DLY       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0824))
    754. 

  754. #define MT6328_ISINK_SFSTR           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0826))
    755. 

  755. #define MT6328_ISINK_EN_CTRL         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0828))
    756. 

  756. #define MT6328_ISINK_MODE_CTRL       ((unsigned int)(MT6328_PMIC_REG_BASE+0x082A))
    757. 

  757. #define MT6328_VTCXO_0_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A00))
    758. 

  758. #define MT6328_VTCXO_1_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A02))
    759. 

  759. #define MT6328_VAUD28_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A04))
    760. 

  760. #define MT6328_VAUX18_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A06))
    761. 

  761. #define MT6328_VRF18_0_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A08))
    762. 

  762. #define MT6328_VRF18_0_CON1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A0A))
    763. 

  763. #define MT6328_VCAMA_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A0C))
    764. 

  764. #define MT6328_VCN28_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A0E))
    765. 

  765. #define MT6328_VCN33_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A10))
    766. 

  766. #define MT6328_VCN33_CON1            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A12))
    767. 

  767. #define MT6328_VCN33_CON2            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A14))
    768. 

  768. #define MT6328_VRF18_1_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A16))
    769. 

  769. #define MT6328_VRF18_1_CON1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A18))
    770. 

  770. #define MT6328_VUSB33_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A1A))
    771. 

  771. #define MT6328_VMCH_CON0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A1C))
    772. 

  772. #define MT6328_VMCH_CON1             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A1E))
    773. 

  773. #define MT6328_VMC_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A20))
    774. 

  774. #define MT6328_VMC_CON1              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A22))
    775. 

  775. #define MT6328_VEMC_3V3_CON0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A24))
    776. 

  776. #define MT6328_VEMC_3V3_CON1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A26))
    777. 

  777. #define MT6328_VIO28_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A28))
    778. 

  778. #define MT6328_VCAMAF_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A2A))
    779. 

  779. #define MT6328_VGP1_CON0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A2C))
    780. 

  780. #define MT6328_VGP1_CON1             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A2E))
    781. 

  781. #define MT6328_VEFUSE_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A30))
    782. 

  782. #define MT6328_VSIM1_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A32))
    783. 

  783. #define MT6328_VSIM2_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A34))
    784. 

  784. #define MT6328_VIO18_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A36))
    785. 

  785. #define MT6328_VIBR_CON0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A38))
    786. 

  786. #define MT6328_VCN18_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A3A))
    787. 

  787. #define MT6328_VCAM_CON0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A3C))
    788. 

  788. #define MT6328_VCAMIO_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A3E))
    789. 

  789. #define MT6328_LDO_VSRAM_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A40))
    790. 

  790. #define MT6328_LDO_VSRAM_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A42))
    791. 

  791. #define MT6328_VTREF_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A44))
    792. 

  792. #define MT6328_VM_CON0               ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A46))
    793. 

  793. #define MT6328_VM_CON1               ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A48))
    794. 

  794. #define MT6328_VRTC_CON0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A4A))
    795. 

  795. #define MT6328_LDO_OCFB0             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A4C))
    796. 

  796. #define MT6328_ALDO_ANA_CON0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A4E))
    797. 

  797. #define MT6328_ADLDO_ANA_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A50))
    798. 

  798. #define MT6328_ADLDO_ANA_CON2        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A52))
    799. 

  799. #define MT6328_ADLDO_ANA_CON3        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A54))
    800. 

  800. #define MT6328_ADLDO_ANA_CON4        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A56))
    801. 

  801. #define MT6328_ADLDO_ANA_CON5        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A58))
    802. 

  802. #define MT6328_ADLDO_ANA_CON6        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A5A))
    803. 

  803. #define MT6328_ADLDO_ANA_CON7        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A5C))
    804. 

  804. #define MT6328_ADLDO_ANA_CON8        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A5E))
    805. 

  805. #define MT6328_ADLDO_ANA_CON9        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A60))
    806. 

  806. #define MT6328_ADLDO_ANA_CON10       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A62))
    807. 

  807. #define MT6328_ADLDO_ANA_CON11       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A64))
    808. 

  808. #define MT6328_ADLDO_ANA_CON12       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A66))
    809. 

  809. #define MT6328_ADLDO_ANA_CON13       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A68))
    810. 

  810. #define MT6328_DLDO_ANA_CON0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A6A))
    811. 

  811. #define MT6328_DLDO_ANA_CON1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A6C))
    812. 

  812. #define MT6328_DLDO_ANA_CON2         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A6E))
    813. 

  813. #define MT6328_DLDO_ANA_CON3         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A70))
    814. 

  814. #define MT6328_DLDO_ANA_CON4         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A72))
    815. 

  815. #define MT6328_DLDO_ANA_CON5         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A74))
    816. 

  816. #define MT6328_SLDO_ANA_CON0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A76))
    817. 

  817. #define MT6328_SLDO_ANA_CON1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A78))
    818. 

  818. #define MT6328_SLDO_ANA_CON2         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A7A))
    819. 

  819. #define MT6328_SLDO_ANA_CON3         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A7C))
    820. 

  820. #define MT6328_SLDO_ANA_CON4         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A7E))
    821. 

  821. #define MT6328_SLDO_ANA_CON5         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A80))
    822. 

  822. #define MT6328_SLDO_ANA_CON6         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A82))
    823. 

  823. #define MT6328_SLDO_ANA_CON7         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A84))
    824. 

  824. #define MT6328_SLDO_ANA_CON8         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A86))
    825. 

  825. #define MT6328_SLDO_ANA_CON9         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A88))
    826. 

  826. #define MT6328_SLDO_ANA_CON10        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A8A))
    827. 

  827. #define MT6328_LDO_RSV_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A8C))
    828. 

  828. #define MT6328_LDO_RSV_CON1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A8E))
    829. 

  829. #define MT6328_SPK_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A90))
    830. 

  830. #define MT6328_SPK_CON1              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A92))
    831. 

  831. #define MT6328_SPK_CON2              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A94))
    832. 

  832. #define MT6328_SPK_CON3              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A96))
    833. 

  833. #define MT6328_SPK_CON4              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A98))
    834. 

  834. #define MT6328_SPK_CON5              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A9A))
    835. 

  835. #define MT6328_SPK_CON6              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A9C))
    836. 

  836. #define MT6328_SPK_CON7              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0A9E))
    837. 

  837. #define MT6328_SPK_CON8              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AA0))
    838. 

  838. #define MT6328_SPK_CON9              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AA2))
    839. 

  839. #define MT6328_SPK_CON10             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AA4))
    840. 

  840. #define MT6328_SPK_CON11             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AA6))
    841. 

  841. #define MT6328_SPK_CON12             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AA8))
    842. 

  842. #define MT6328_SPK_CON13             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AAA))
    843. 

  843. #define MT6328_SPK_CON14             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AAC))
    844. 

  844. #define MT6328_SPK_CON15             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AAE))
    845. 

  845. #define MT6328_SPK_CON16             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AB0))
    846. 

  846. #define MT6328_SPK_ANA_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AB2))
    847. 

  847. #define MT6328_SPK_ANA_CON1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AB4))
    848. 

  848. #define MT6328_SPK_ANA_CON3          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0AB6))
    849. 

  849. #define MT6328_OTP_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C00))
    850. 

  850. #define MT6328_OTP_CON1              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C02))
    851. 

  851. #define MT6328_OTP_CON2              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C04))
    852. 

  852. #define MT6328_OTP_CON3              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C06))
    853. 

  853. #define MT6328_OTP_CON4              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C08))
    854. 

  854. #define MT6328_OTP_CON5              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C0A))
    855. 

  855. #define MT6328_OTP_CON6              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C0C))
    856. 

  856. #define MT6328_OTP_CON7              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C0E))
    857. 

  857. #define MT6328_OTP_CON8              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C10))
    858. 

  858. #define MT6328_OTP_CON9              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C12))
    859. 

  859. #define MT6328_OTP_CON10             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C14))
    860. 

  860. #define MT6328_OTP_CON11             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C16))
    861. 

  861. #define MT6328_OTP_CON12             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C18))
    862. 

  862. #define MT6328_OTP_CON13             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C1A))
    863. 

  863. #define MT6328_OTP_CON14             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C1C))
    864. 

  864. #define MT6328_OTP_DOUT_0_15         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C1E))
    865. 

  865. #define MT6328_OTP_DOUT_16_31        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C20))
    866. 

  866. #define MT6328_OTP_DOUT_32_47        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C22))
    867. 

  867. #define MT6328_OTP_DOUT_48_63        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C24))
    868. 

  868. #define MT6328_OTP_DOUT_64_79        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C26))
    869. 

  869. #define MT6328_OTP_DOUT_80_95        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C28))
    870. 

  870. #define MT6328_OTP_DOUT_96_111       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C2A))
    871. 

  871. #define MT6328_OTP_DOUT_112_127      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C2C))
    872. 

  872. #define MT6328_OTP_DOUT_128_143      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C2E))
    873. 

  873. #define MT6328_OTP_DOUT_144_159      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C30))
    874. 

  874. #define MT6328_OTP_DOUT_160_175      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C32))
    875. 

  875. #define MT6328_OTP_DOUT_176_191      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C34))
    876. 

  876. #define MT6328_OTP_DOUT_192_207      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C36))
    877. 

  877. #define MT6328_OTP_DOUT_208_223      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C38))
    878. 

  878. #define MT6328_OTP_DOUT_224_239      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C3A))
    879. 

  879. #define MT6328_OTP_DOUT_240_255      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C3C))
    880. 

  880. #define MT6328_OTP_DOUT_256_271      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C3E))
    881. 

  881. #define MT6328_OTP_DOUT_272_287      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C40))
    882. 

  882. #define MT6328_OTP_DOUT_288_303      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C42))
    883. 

  883. #define MT6328_OTP_DOUT_304_319      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C44))
    884. 

  884. #define MT6328_OTP_DOUT_320_335      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C46))
    885. 

  885. #define MT6328_OTP_DOUT_336_351      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C48))
    886. 

  886. #define MT6328_OTP_DOUT_352_367      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C4A))
    887. 

  887. #define MT6328_OTP_DOUT_368_383      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C4C))
    888. 

  888. #define MT6328_OTP_DOUT_384_399      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C4E))
    889. 

  889. #define MT6328_OTP_DOUT_400_415      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C50))
    890. 

  890. #define MT6328_OTP_DOUT_416_431      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C52))
    891. 

  891. #define MT6328_OTP_DOUT_432_447      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C54))
    892. 

  892. #define MT6328_OTP_DOUT_448_463      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C56))
    893. 

  893. #define MT6328_OTP_DOUT_464_479      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C58))
    894. 

  894. #define MT6328_OTP_DOUT_480_495      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C5A))
    895. 

  895. #define MT6328_OTP_DOUT_496_511      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C5C))
    896. 

  896. #define MT6328_OTP_VAL_0_15          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C5E))
    897. 

  897. #define MT6328_OTP_VAL_16_31         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C60))
    898. 

  898. #define MT6328_OTP_VAL_32_47         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C62))
    899. 

  899. #define MT6328_OTP_VAL_48_63         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C64))
    900. 

  900. #define MT6328_OTP_VAL_64_79         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C66))
    901. 

  901. #define MT6328_OTP_VAL_80_95         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C68))
    902. 

  902. #define MT6328_OTP_VAL_96_111        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C6A))
    903. 

  903. #define MT6328_OTP_VAL_112_127       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C6C))
    904. 

  904. #define MT6328_OTP_VAL_128_143       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C6E))
    905. 

  905. #define MT6328_OTP_VAL_144_159       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C70))
    906. 

  906. #define MT6328_OTP_VAL_160_175       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C72))
    907. 

  907. #define MT6328_OTP_VAL_176_191       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C74))
    908. 

  908. #define MT6328_OTP_VAL_192_207       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C76))
    909. 

  909. #define MT6328_OTP_VAL_208_223       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C78))
    910. 

  910. #define MT6328_OTP_VAL_224_239       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C7A))
    911. 

  911. #define MT6328_OTP_VAL_240_255       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C7C))
    912. 

  912. #define MT6328_OTP_VAL_256_271       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C7E))
    913. 

  913. #define MT6328_OTP_VAL_272_287       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C80))
    914. 

  914. #define MT6328_OTP_VAL_288_303       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C82))
    915. 

  915. #define MT6328_OTP_VAL_304_319       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C84))
    916. 

  916. #define MT6328_OTP_VAL_320_335       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C86))
    917. 

  917. #define MT6328_OTP_VAL_336_351       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C88))
    918. 

  918. #define MT6328_OTP_VAL_352_367       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C8A))
    919. 

  919. #define MT6328_OTP_VAL_368_383       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C8C))
    920. 

  920. #define MT6328_OTP_VAL_384_399       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C8E))
    921. 

  921. #define MT6328_OTP_VAL_400_415       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C90))
    922. 

  922. #define MT6328_OTP_VAL_416_431       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C92))
    923. 

  923. #define MT6328_OTP_VAL_432_447       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C94))
    924. 

  924. #define MT6328_OTP_VAL_448_463       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C96))
    925. 

  925. #define MT6328_OTP_VAL_464_479       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C98))
    926. 

  926. #define MT6328_OTP_VAL_480_495       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C9A))
    927. 

  927. #define MT6328_OTP_VAL_496_511       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C9C))
    928. 

  928. #define MT6328_RTC_MIX_CON0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0C9E))
    929. 

  929. #define MT6328_RTC_MIX_CON1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CA0))
    930. 

  930. #define MT6328_RTC_MIX_CON2          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CA2))
    931. 

  931. #define MT6328_FGADC_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CA4))
    932. 

  932. #define MT6328_FGADC_CON1            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CA6))
    933. 

  933. #define MT6328_FGADC_CON2            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CA8))
    934. 

  934. #define MT6328_FGADC_CON3            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CAA))
    935. 

  935. #define MT6328_FGADC_CON4            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CAC))
    936. 

  936. #define MT6328_FGADC_CON5            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CAE))
    937. 

  937. #define MT6328_FGADC_CON6            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CB0))
    938. 

  938. #define MT6328_FGADC_CON7            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CB2))
    939. 

  939. #define MT6328_FGADC_CON8            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CB4))
    940. 

  940. #define MT6328_FGADC_CON9            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CB6))
    941. 

  941. #define MT6328_FGADC_CON10           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CB8))
    942. 

  942. #define MT6328_FGADC_CON11           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CBA))
    943. 

  943. #define MT6328_FGADC_CON12           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CBC))
    944. 

  944. #define MT6328_FGADC_CON13           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CBE))
    945. 

  945. #define MT6328_FGADC_CON14           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CC0))
    946. 

  946. #define MT6328_FGADC_CON15           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CC2))
    947. 

  947. #define MT6328_FGADC_CON16           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CC4))
    948. 

  948. #define MT6328_FGADC_CON17           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CC6))
    949. 

  949. #define MT6328_FGADC_CON18           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CC8))
    950. 

  950. #define MT6328_FGADC_CON19           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CCA))
    951. 

  951. #define MT6328_FGADC_CON20           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CCC))
    952. 

  952. #define MT6328_FGADC_CON21           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CCE))
    953. 

  953. #define MT6328_FGADC_CON22           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CD0))
    954. 

  954. #define MT6328_FGADC_CON23           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CD2))
    955. 

  955. #define MT6328_FGADC_CON24           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CD4))
    956. 

  956. #define MT6328_FGADC_CON25           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CD6))
    957. 

  957. #define MT6328_FGADC_CON26           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CD8))
    958. 

  958. #define MT6328_FGADC_CON27           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CDA))
    959. 

  959. #define MT6328_AUDDEC_ANA_CON0       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CDC))
    960. 

  960. #define MT6328_AUDDEC_ANA_CON1       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CDE))
    961. 

  961. #define MT6328_AUDDEC_ANA_CON2       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CE0))
    962. 

  962. #define MT6328_AUDDEC_ANA_CON3       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CE2))
    963. 

  963. #define MT6328_AUDDEC_ANA_CON4       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CE4))
    964. 

  964. #define MT6328_AUDDEC_ANA_CON5       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CE6))
    965. 

  965. #define MT6328_AUDDEC_ANA_CON6       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CE8))
    966. 

  966. #define MT6328_AUDDEC_ANA_CON7       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CEA))
    967. 

  967. #define MT6328_AUDDEC_ANA_CON8       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CEC))
    968. 

  968. #define MT6328_AUDENC_ANA_CON0       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CEE))
    969. 

  969. #define MT6328_AUDENC_ANA_CON1       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CF0))
    970. 

  970. #define MT6328_AUDENC_ANA_CON2       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CF2))
    971. 

  971. #define MT6328_AUDENC_ANA_CON3       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CF4))
    972. 

  972. #define MT6328_AUDENC_ANA_CON4       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CF6))
    973. 

  973. #define MT6328_AUDENC_ANA_CON5       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CF8))
    974. 

  974. #define MT6328_AUDENC_ANA_CON6       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CFA))
    975. 

  975. #define MT6328_AUDENC_ANA_CON7       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CFC))
    976. 

  976. #define MT6328_AUDENC_ANA_CON8       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0CFE))
    977. 

  977. #define MT6328_AUDENC_ANA_CON9       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0D00))
    978. 

  978. #define MT6328_AUDENC_ANA_CON10      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0D02))
    979. 

  979. #define MT6328_AUDNCP_CLKDIV_CON0    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0D04))
    980. 

  980. #define MT6328_AUDNCP_CLKDIV_CON1    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0D06))
    981. 

  981. #define MT6328_AUDNCP_CLKDIV_CON2    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0D08))
    982. 

  982. #define MT6328_AUDNCP_CLKDIV_CON3    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0D0A))
    983. 

  983. #define MT6328_AUDNCP_CLKDIV_CON4    ((unsigned int)(MT6328_PMIC_REG_BASE+0x0D0C))
    984. 

  984. #define MT6328_AUXADC_ADC0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E00))
    985. 

  985. #define MT6328_AUXADC_ADC1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E02))
    986. 

  986. #define MT6328_AUXADC_ADC2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E04))
    987. 

  987. #define MT6328_AUXADC_ADC3           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E06))
    988. 

  988. #define MT6328_AUXADC_ADC4           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E08))
    989. 

  989. #define MT6328_AUXADC_ADC5           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E0A))
    990. 

  990. #define MT6328_AUXADC_ADC6           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E0C))
    991. 

  991. #define MT6328_AUXADC_ADC7           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E0E))
    992. 

  992. #define MT6328_AUXADC_ADC8           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E10))
    993. 

  993. #define MT6328_AUXADC_ADC9           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E12))
    994. 

  994. #define MT6328_AUXADC_ADC10          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E14))
    995. 

  995. #define MT6328_AUXADC_ADC11          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E16))
    996. 

  996. #define MT6328_AUXADC_ADC12          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E18))
    997. 

  997. #define MT6328_AUXADC_ADC13          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E1A))
    998. 

  998. #define MT6328_AUXADC_ADC14          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E1C))
    999. 

  999. #define MT6328_AUXADC_ADC15          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E1E))
    1000. 

  1000. #define MT6328_AUXADC_ADC16          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E20))
    1001. 

  1001. #define MT6328_AUXADC_ADC17          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E22))
    1002. 

  1002. #define MT6328_AUXADC_ADC18          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E24))
    1003. 

  1003. #define MT6328_AUXADC_ADC19          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E26))
    1004. 

  1004. #define MT6328_AUXADC_ADC20          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E28))
    1005. 

  1005. #define MT6328_AUXADC_ADC21          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E2A))
    1006. 

  1006. #define MT6328_AUXADC_ADC22          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E2C))
    1007. 

  1007. #define MT6328_AUXADC_ADC23          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E2E))
    1008. 

  1008. #define MT6328_AUXADC_ADC24          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E30))
    1009. 

  1009. #define MT6328_AUXADC_ADC25          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E32))
    1010. 

  1010. #define MT6328_AUXADC_ADC26          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E34))
    1011. 

  1011. #define MT6328_AUXADC_ADC27          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E36))
    1012. 

  1012. #define MT6328_AUXADC_ADC28          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E38))
    1013. 

  1013. #define MT6328_AUXADC_ADC29          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E3A))
    1014. 

  1014. #define MT6328_AUXADC_ADC30          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E3C))
    1015. 

  1015. #define MT6328_AUXADC_ADC31          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E3E))
    1016. 

  1016. #define MT6328_AUXADC_ADC32          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E40))
    1017. 

  1017. #define MT6328_AUXADC_ADC33          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E42))
    1018. 

  1018. #define MT6328_AUXADC_BUF0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E44))
    1019. 

  1019. #define MT6328_AUXADC_BUF1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E46))
    1020. 

  1020. #define MT6328_AUXADC_BUF2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E48))
    1021. 

  1021. #define MT6328_AUXADC_BUF3           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E4A))
    1022. 

  1022. #define MT6328_AUXADC_BUF4           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E4C))
    1023. 

  1023. #define MT6328_AUXADC_BUF5           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E4E))
    1024. 

  1024. #define MT6328_AUXADC_BUF6           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E50))
    1025. 

  1025. #define MT6328_AUXADC_BUF7           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E52))
    1026. 

  1026. #define MT6328_AUXADC_BUF8           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E54))
    1027. 

  1027. #define MT6328_AUXADC_BUF9           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E56))
    1028. 

  1028. #define MT6328_AUXADC_BUF10          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E58))
    1029. 

  1029. #define MT6328_AUXADC_BUF11          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E5A))
    1030. 

  1030. #define MT6328_AUXADC_BUF12          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E5C))
    1031. 

  1031. #define MT6328_AUXADC_BUF13          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E5E))
    1032. 

  1032. #define MT6328_AUXADC_BUF14          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E60))
    1033. 

  1033. #define MT6328_AUXADC_BUF15          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E62))
    1034. 

  1034. #define MT6328_AUXADC_BUF16          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E64))
    1035. 

  1035. #define MT6328_AUXADC_BUF17          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E66))
    1036. 

  1036. #define MT6328_AUXADC_BUF18          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E68))
    1037. 

  1037. #define MT6328_AUXADC_BUF19          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E6A))
    1038. 

  1038. #define MT6328_AUXADC_BUF20          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E6C))
    1039. 

  1039. #define MT6328_AUXADC_BUF21          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E6E))
    1040. 

  1040. #define MT6328_AUXADC_BUF22          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E70))
    1041. 

  1041. #define MT6328_AUXADC_BUF23          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E72))
    1042. 

  1042. #define MT6328_AUXADC_BUF24          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E74))
    1043. 

  1043. #define MT6328_AUXADC_BUF25          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E76))
    1044. 

  1044. #define MT6328_AUXADC_BUF26          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E78))
    1045. 

  1045. #define MT6328_AUXADC_BUF27          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E7A))
    1046. 

  1046. #define MT6328_AUXADC_BUF28          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E7C))
    1047. 

  1047. #define MT6328_AUXADC_BUF29          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E7E))
    1048. 

  1048. #define MT6328_AUXADC_BUF30          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E80))
    1049. 

  1049. #define MT6328_AUXADC_BUF31          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E82))
    1050. 

  1050. #define MT6328_AUXADC_STA0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E84))
    1051. 

  1051. #define MT6328_AUXADC_STA1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E86))
    1052. 

  1052. #define MT6328_AUXADC_RQST0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E88))
    1053. 

  1053. #define MT6328_AUXADC_RQST0_SET      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E8A))
    1054. 

  1054. #define MT6328_AUXADC_RQST0_CLR      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E8C))
    1055. 

  1055. #define MT6328_AUXADC_RQST1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E8E))
    1056. 

  1056. #define MT6328_AUXADC_RQST1_SET      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E90))
    1057. 

  1057. #define MT6328_AUXADC_RQST1_CLR      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E92))
    1058. 

  1058. #define MT6328_AUXADC_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E94))
    1059. 

  1059. #define MT6328_AUXADC_CON0_SET       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E96))
    1060. 

  1060. #define MT6328_AUXADC_CON0_CLR       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E98))
    1061. 

  1061. #define MT6328_AUXADC_CON1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E9A))
    1062. 

  1062. #define MT6328_AUXADC_CON2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E9C))
    1063. 

  1063. #define MT6328_AUXADC_CON3           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0E9E))
    1064. 

  1064. #define MT6328_AUXADC_CON4           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EA0))
    1065. 

  1065. #define MT6328_AUXADC_CON5           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EA2))
    1066. 

  1066. #define MT6328_AUXADC_CON6           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EA4))
    1067. 

  1067. #define MT6328_AUXADC_CON7           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EA6))
    1068. 

  1068. #define MT6328_AUXADC_CON8           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EA8))
    1069. 

  1069. #define MT6328_AUXADC_CON9           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EAA))
    1070. 

  1070. #define MT6328_AUXADC_CON10          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EAC))
    1071. 

  1071. #define MT6328_AUXADC_CON11          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EAE))
    1072. 

  1072. #define MT6328_AUXADC_CON12          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EB0))
    1073. 

  1073. #define MT6328_AUXADC_CON13          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EB2))
    1074. 

  1074. #define MT6328_AUXADC_CON14          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EB4))
    1075. 

  1075. #define MT6328_AUXADC_CON15          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EB6))
    1076. 

  1076. #define MT6328_AUXADC_CON16          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EB8))
    1077. 

  1077. #define MT6328_AUXADC_AUTORPT0       ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EBA))
    1078. 

  1078. #define MT6328_AUXADC_LBAT0          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EBC))
    1079. 

  1079. #define MT6328_AUXADC_LBAT1          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EBE))
    1080. 

  1080. #define MT6328_AUXADC_LBAT2          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EC0))
    1081. 

  1081. #define MT6328_AUXADC_LBAT3          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EC2))
    1082. 

  1082. #define MT6328_AUXADC_LBAT4          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EC4))
    1083. 

  1083. #define MT6328_AUXADC_LBAT5          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EC6))
    1084. 

  1084. #define MT6328_AUXADC_LBAT6          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EC8))
    1085. 

  1085. #define MT6328_AUXADC_ACCDET         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0ECA))
    1086. 

  1086. #define MT6328_AUXADC_THR0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0ECC))
    1087. 

  1087. #define MT6328_AUXADC_THR1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0ECE))
    1088. 

  1088. #define MT6328_AUXADC_THR2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0ED0))
    1089. 

  1089. #define MT6328_AUXADC_THR3           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0ED2))
    1090. 

  1090. #define MT6328_AUXADC_THR4           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0ED4))
    1091. 

  1091. #define MT6328_AUXADC_THR5           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0ED6))
    1092. 

  1092. #define MT6328_AUXADC_THR6           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0ED8))
    1093. 

  1093. #define MT6328_AUXADC_EFUSE0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EDA))
    1094. 

  1094. #define MT6328_AUXADC_EFUSE1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EDC))
    1095. 

  1095. #define MT6328_AUXADC_EFUSE2         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EDE))
    1096. 

  1096. #define MT6328_AUXADC_EFUSE3         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EE0))
    1097. 

  1097. #define MT6328_AUXADC_EFUSE4         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EE2))
    1098. 

  1098. #define MT6328_AUXADC_EFUSE5         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EE4))
    1099. 

  1099. #define MT6328_AUXADC_DBG0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EE6))
    1100. 

  1100. #define MT6328_AUXADC_IMP0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EE8))
    1101. 

  1101. #define MT6328_AUXADC_IMP1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EEA))
    1102. 

  1102. #define MT6328_AUXADC_VISMPS0_1      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EEC))
    1103. 

  1103. #define MT6328_AUXADC_VISMPS0_2      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EEE))
    1104. 

  1104. #define MT6328_AUXADC_VISMPS0_3      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EF0))
    1105. 

  1105. #define MT6328_AUXADC_VISMPS0_4      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EF2))
    1106. 

  1106. #define MT6328_AUXADC_VISMPS0_5      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EF4))
    1107. 

  1107. #define MT6328_AUXADC_VISMPS0_6      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EF6))
    1108. 

  1108. #define MT6328_AUXADC_VISMPS0_7      ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EF8))
    1109. 

  1109. #define MT6328_AUXADC_LBAT2_1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EFA))
    1110. 

  1110. #define MT6328_AUXADC_LBAT2_2        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EFC))
    1111. 

  1111. #define MT6328_AUXADC_LBAT2_3        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0EFE))
    1112. 

  1112. #define MT6328_AUXADC_LBAT2_4        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F00))
    1113. 

  1113. #define MT6328_AUXADC_LBAT2_5        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F02))
    1114. 

  1114. #define MT6328_AUXADC_LBAT2_6        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F04))
    1115. 

  1115. #define MT6328_AUXADC_LBAT2_7        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F06))
    1116. 

  1116. #define MT6328_AUXADC_MDBG_0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F08))
    1117. 

  1117. #define MT6328_AUXADC_MDBG_1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F0A))
    1118. 

  1118. #define MT6328_AUXADC_MDBG_2         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F0C))
    1119. 

  1119. #define MT6328_AUXADC_MDRT_0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F0E))
    1120. 

  1120. #define MT6328_AUXADC_MDRT_1         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F10))
    1121. 

  1121. #define MT6328_AUXADC_MDRT_2         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F12))
    1122. 

  1122. #define MT6328_ACCDET_CON0           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F14))
    1123. 

  1123. #define MT6328_ACCDET_CON1           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F16))
    1124. 

  1124. #define MT6328_ACCDET_CON2           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F18))
    1125. 

  1125. #define MT6328_ACCDET_CON3           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F1A))
    1126. 

  1126. #define MT6328_ACCDET_CON4           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F1C))
    1127. 

  1127. #define MT6328_ACCDET_CON5           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F1E))
    1128. 

  1128. #define MT6328_ACCDET_CON6           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F20))
    1129. 

  1129. #define MT6328_ACCDET_CON7           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F22))
    1130. 

  1130. #define MT6328_ACCDET_CON8           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F24))
    1131. 

  1131. #define MT6328_ACCDET_CON9           ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F26))
    1132. 

  1132. #define MT6328_ACCDET_CON10          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F28))
    1133. 

  1133. #define MT6328_ACCDET_CON11          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F2A))
    1134. 

  1134. #define MT6328_ACCDET_CON12          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F2C))
    1135. 

  1135. #define MT6328_ACCDET_CON13          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F2E))
    1136. 

  1136. #define MT6328_ACCDET_CON14          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F30))
    1137. 

  1137. #define MT6328_ACCDET_CON15          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F32))
    1138. 

  1138. #define MT6328_ACCDET_CON16          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F34))
    1139. 

  1139. #define MT6328_ACCDET_CON17          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F36))
    1140. 

  1140. #define MT6328_ACCDET_CON18          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F38))
    1141. 

  1141. #define MT6328_ACCDET_CON19          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F3A))
    1142. 

  1142. #define MT6328_ACCDET_CON20          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F3C))
    1143. 

  1143. #define MT6328_ACCDET_CON21          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F3E))
    1144. 

  1144. #define MT6328_ACCDET_CON22          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F40))
    1145. 

  1145. #define MT6328_ACCDET_CON23          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F42))
    1146. 

  1146. #define MT6328_ACCDET_CON24          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F44))
    1147. 

  1147. #define MT6328_ACCDET_CON25          ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F46))
    1148. 

  1148. #define MT6328_CHR_CON0              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F48))
    1149. 

  1149. #define MT6328_CHR_CON1              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F4A))
    1150. 

  1150. #define MT6328_CHR_CON2              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F4C))
    1151. 

  1151. #define MT6328_CHR_CON3              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F4E))
    1152. 

  1152. #define MT6328_CHR_CON4              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F50))
    1153. 

  1153. #define MT6328_CHR_CON5              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F52))
    1154. 

  1154. #define MT6328_CHR_CON6              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F54))
    1155. 

  1155. #define MT6328_CHR_CON7              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F56))
    1156. 

  1156. #define MT6328_CHR_CON8              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F58))
    1157. 

  1157. #define MT6328_CHR_CON9              ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F5A))
    1158. 

  1158. #define MT6328_CHR_CON10             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F5C))
    1159. 

  1159. #define MT6328_CHR_CON11             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F5E))
    1160. 

  1160. #define MT6328_CHR_CON12             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F60))
    1161. 

  1161. #define MT6328_CHR_CON13             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F62))
    1162. 

  1162. #define MT6328_CHR_CON14             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F64))
    1163. 

  1163. #define MT6328_CHR_CON15             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F66))
    1164. 

  1164. #define MT6328_CHR_CON16             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F68))
    1165. 

  1165. #define MT6328_CHR_CON17             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F6A))
    1166. 

  1166. #define MT6328_CHR_CON18             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F6C))
    1167. 

  1167. #define MT6328_CHR_CON19             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F6E))
    1168. 

  1168. #define MT6328_CHR_CON20             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F70))
    1169. 

  1169. #define MT6328_CHR_CON21             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F72))
    1170. 

  1170. #define MT6328_CHR_CON22             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F74))
    1171. 

  1171. #define MT6328_CHR_CON23             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F76))
    1172. 

  1172. #define MT6328_CHR_CON24             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F78))
    1173. 

  1173. #define MT6328_CHR_CON25             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F7A))
    1174. 

  1174. #define MT6328_CHR_CON26             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F7C))
    1175. 

  1175. #define MT6328_CHR_CON27             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F7E))
    1176. 

  1176. #define MT6328_CHR_CON28             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F80))
    1177. 

  1177. #define MT6328_CHR_CON29             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F82))
    1178. 

  1178. #define MT6328_CHR_CON30             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F84))
    1179. 

  1179. #define MT6328_CHR_CON31             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F86))
    1180. 

  1180. #define MT6328_CHR_CON32             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F88))
    1181. 

  1181. #define MT6328_CHR_CON33             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F8A))
    1182. 

  1182. #define MT6328_CHR_CON34             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F8C))
    1183. 

  1183. #define MT6328_CHR_CON35             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F8E))
    1184. 

  1184. #define MT6328_CHR_CON36             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F90))
    1185. 

  1185. #define MT6328_CHR_CON37             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F92))
    1186. 

  1186. #define MT6328_CHR_CON38             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F94))
    1187. 

  1187. #define MT6328_CHR_CON39             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F96))
    1188. 

  1188. #define MT6328_CHR_CON40             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F98))
    1189. 

  1189. #define MT6328_CHR_CON41             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F9A))
    1190. 

  1190. #define MT6328_CHR_CON42             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F9C))
    1191. 

  1191. #define MT6328_BATON_CON0            ((unsigned int)(MT6328_PMIC_REG_BASE+0x0F9E))
    1192. 

  1192. #define MT6328_CHR_CON43             ((unsigned int)(MT6328_PMIC_REG_BASE+0x0FA0))
    1193. 

  1193. #define MT6328_EOSC_CALI_CON0        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0FAA))
    1194. 

  1194. #define MT6328_EOSC_CALI_CON1        ((unsigned int)(MT6328_PMIC_REG_BASE+0x0FAC))
    1195. 

  1195. #define MT6328_VRTC_PWM_CON0         ((unsigned int)(MT6328_PMIC_REG_BASE+0x0FAE))
    1196. 

  1196. 

  1197. 

  1198. 

  1199. /* -----PMIC_WRAP INT register for PMIC ------------------------------------------------- */
    1200. 

  1200. /* #define MT6328_INT_STA         (PMIC_REG_BASE+0x01B4) //0x01B4 */
    1201. 

  1201. #define MT6328_INT_STA               ((unsigned int)(MT6328_PMIC_REG_BASE+0x0302))
    1202. 

  1202. 

  1203. #define MT6332_INT_STA         (SWCHR_REG_BASE+0x0112)	/* 0x8112 */
    1204. 

  1204. /* ///////////////////////////////////////////////////////////////////////////////////////// */
    1205. 

  1205. 

  1206. /*
    1207. 

  1207. #define AUXADC_CON21       (PMIC_REG_BASE+0x076C)
    1208. 

  1208. #define AUXADC_ADC12       (PMIC_REG_BASE+0x072C)
    1209. 

  1209. #define AUXADC_ADC13       (PMIC_REG_BASE+0x072E)
    1210. 

  1210. #define AUXADC_ADC14       (PMIC_REG_BASE+0x0730)
    1211. 

  1211. #define AUXADC_CON2        (PMIC_REG_BASE+0x0746)
    1212. 

  1212. #define AUXADC_CON3        (PMIC_REG_BASE+0x0748)
    1213. 

  1213. 

  1214. #define EFUSE_VAL_0_15     (PMIC_REG_BASE+0x060E)
    1215. 

  1215. #define EFUSE_VAL_16_31    (PMIC_REG_BASE+0x0610)
    1216. 

  1216. #define EFUSE_VAL_32_47    (PMIC_REG_BASE+0x0612)
    1217. 

  1217. #define EFUSE_VAL_48_63    (PMIC_REG_BASE+0x0614)
    1218. 

  1218. #define EFUSE_VAL_64_79    (PMIC_REG_BASE+0x0616)
    1219. 

  1219. */
    1220. 

  1220. /* -----macro for dewrapper defaule value------------------------------------------------------- */
    1221. 

  1221. #define MT6328_DEFAULT_VALUE_READ_TEST      0x5aa5
    1222. 

  1222. #define WRITE_TEST_DEFAULT_VALUE		    0x0
    1223. 

  1223. #define WRITE_TEST_EXT_DEFAULT_VALUE	0x0
    1224. 

  1224. #define MT6332_DEFAULT_VALUE_READ_TEST     0xa55a
    1225. 

  1225. #define MT6328_WRITE_TEST_VALUE            0x1234
    1226. 

  1226. #define MT6332_WRITE_TEST_VALUE            0x4321
    1227. 

  1227. #define WRAP_ACCESS_TEST_REG			MT6328_DEW_WRITE_TEST
    1228. 

  1228. #define WRAP_ACCESS_TEST_EXT_REG		MT6332_DEW_WRITE_TEST
    1229. 

  1229. 

  1230. /* -----macro for manual commnd -------------------------------------------------------- */
    1231. 

  1231. #define OP_WR    (0x1)
    1232. 

  1232. #define OP_RD    (0x0)
    1233. 

  1233. 

  1234. #define OP_CSH   (0x0)
    1235. 

  1235. #define OP_CSL   (0x1)
    1236. 

  1236. #define OP_CK    (0x2)
    1237. 

  1237. 

  1238. #define OP_OUTS  (0x8)
    1239. 

  1239. #define OP_OUTD  (0x9)
    1240. 

  1240. #define OP_OUTQ  (0xA)
    1241. 

  1241. 

  1242. #define OP_INS   (0xC)
    1243. 

  1243. #define OP_INS0  (0xD)
    1244. 

  1244. #define OP_IND   (0xE)
    1245. 

  1245. #define OP_INQ   (0xF)
    1246. 

  1246. 

  1247. #define OP_OS2IS (0x10)
    1248. 

  1248. #define OP_OS2ID (0x11)
    1249. 

  1249. #define OP_OS2IQ (0x12)
    1250. 

  1250. #define OP_OD2IS (0x13)
    1251. 

  1251. #define OP_OD2ID (0x14)
    1252. 

  1252. #define OP_OD2IQ (0x15)
    1253. 

  1253. #define OP_OQ2IS (0x16)
    1254. 

  1254. #define OP_OQ2ID (0x17)
    1255. 

  1255. #define OP_OQ2IQ (0x18)
    1256. 

  1256. 

  1257. #define OP_OSNIS (0x19)
    1258. 

  1258. #define OP_ODNID (0x1A)
    1259. 

  1259. 

  1260. #define E_PWR_INVALID_ARG               1
    1261. 

  1261. #define E_PWR_INVALID_RW                2
    1262. 

  1262. #define E_PWR_INVALID_ADDR              3
    1263. 

  1263. #define E_PWR_INVALID_WDAT              4
    1264. 

  1264. #define E_PWR_INVALID_OP_MANUAL         5
    1265. 

  1265. #define E_PWR_NOT_IDLE_STATE            6
    1266. 

  1266. #define E_PWR_NOT_INIT_DONE             7
    1267. 

  1267. #define E_PWR_NOT_INIT_DONE_READ        8
    1268. 

  1268. #define E_PWR_WAIT_IDLE_TIMEOUT         9
    1269. 

  1269. #define E_PWR_WAIT_IDLE_TIMEOUT_READ    10
    1270. 

  1270. #define E_PWR_INIT_SIDLY_FAIL           11
    1271. 

  1271. #define E_PWR_RESET_TIMEOUT             12
    1272. 

  1272. #define E_PWR_TIMEOUT                   13
    1273. 

  1273. 

  1274. #define E_PWR_INIT_RESET_SPI            20
    1275. 

  1275. #define E_PWR_INIT_SIDLY                21
    1276. 

  1276. #define E_PWR_INIT_REG_CLOCK            22
    1277. 

  1277. #define E_PWR_INIT_ENABLE_PMIC          23
    1278. 

  1278. #define E_PWR_INIT_DIO                  24
    1279. 

  1279. #define E_PWR_INIT_CIPHER               25
    1280. 

  1280. #define E_PWR_INIT_WRITE_TEST           26
    1281. 

  1281. #define E_PWR_INIT_ENABLE_CRC           27
    1282. 

  1282. #define E_PWR_INIT_ENABLE_DEWRAP        28
    1283. 

  1283. 

  1284. #define E_PWR_READ_TEST_FAIL            30
    1285. 

  1285. #define E_PWR_WRITE_TEST_FAIL           31
    1286. 

  1286. #define E_PWR_SWITCH_DIO                32
    1287. 

  1287. 

  1288. /* -----macro for read/write register -------------------------------------------------------- */
    1289. 

  1289. 

  1290. /* #define WRAP_RD32(addr)            (*(volatile u32 *)(addr)) */
    1291. 

  1291. /* #define WRAP_WR32(addr,data)       ((*(volatile u32 *)(addr)) = (u32)data) */
    1292. 

  1292. 

  1293. /* #define WRAP_SET_BIT(BS,REG)       ((*(volatile u32*)(REG)) |= (u32)(BS)) */
    1294. 

  1294. /* #define WRAP_CLR_BIT(BS,REG)       ((*(volatile u32*)(REG)) &= ~((u32)(BS))) */
    1295. 

  1295. 

  1296. #define WRAP_RD32(addr)            __raw_readl((void *)addr)
    1297. 

  1297. #define WRAP_WR32(addr, val)        mt_reg_sync_writel((val), ((void *)addr))
    1298. 

  1298. 

  1299. #define WRAP_SET_BIT(BS, REG)       mt_reg_sync_writel((__raw_readl((void *)REG) | (u32)(BS)), ((void *)REG))
    1300. 

  1300. #define WRAP_CLR_BIT(BS, REG)       mt_reg_sync_writel((__raw_readl((void *)REG) & (~(u32)(BS))), ((void *)REG))
    1301. 

  1301. 

  1302. /* -----------------soft reset -------------------------------------------------------- */
    1303. 

  1303. #define INFRA_GLOBALCON_RST0               (INFRACFG_AO_REG_BASE+0x030)
    1304. 

  1304. #define INFRA_GLOBALCON_RST1               (INFRACFG_AO_REG_BASE+0x034)
    1305. 

  1305. 

  1306. 

  1307. #define PWRAP_SOFT_RESET                   WRAP_SET_BIT(1<<7, INFRA_GLOBALCON_RST0)
    1308. 

  1308. #define PWRAP_CLEAR_SOFT_RESET_BIT         WRAP_CLR_BIT(1<<7, INFRA_GLOBALCON_RST1)
    1309. 

  1309. #define PERI_GLOBALCON_RST1                (PERICFG_BASE+0x004)
    1310. 

  1310. 

  1311. #endif /* __PMIC_WRAP_REGS_H__ */
    1312.