bq24296.h 6.6 KB

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  1. /*****************************************************************************
  2. *
  3. * Filename:
  4. * ---------
  5. * bq24296.h
  6. *
  7. * Project:
  8. * --------
  9. * Android
  10. *
  11. * Description:
  12. * ------------
  13. * bq24296 header file
  14. *
  15. * Author:
  16. * -------
  17. *
  18. ****************************************************************************/
  19. #ifndef _bq24296_SW_H_
  20. #define _bq24296_SW_H_
  21. #define bq24296_CON0 0x00
  22. #define bq24296_CON1 0x01
  23. #define bq24296_CON2 0x02
  24. #define bq24296_CON3 0x03
  25. #define bq24296_CON4 0x04
  26. #define bq24296_CON5 0x05
  27. #define bq24296_CON6 0x06
  28. #define bq24296_CON7 0x07
  29. #define bq24296_CON8 0x08
  30. #define bq24296_CON9 0x09
  31. #define bq24296_CON10 0x0A
  32. #define bq24296_REG_NUM 11
  33. /**********************************************************
  34. *
  35. * [MASK/SHIFT]
  36. *
  37. *********************************************************/
  38. /* CON0 */
  39. #define CON0_EN_HIZ_MASK 0x01
  40. #define CON0_EN_HIZ_SHIFT 7
  41. #define CON0_VINDPM_MASK 0x0F
  42. #define CON0_VINDPM_SHIFT 3
  43. #define CON0_IINLIM_MASK 0x07
  44. #define CON0_IINLIM_SHIFT 0
  45. /* CON1 */
  46. #define CON1_REG_RST_MASK 0x01
  47. #define CON1_REG_RST_SHIFT 7
  48. #define CON1_WDT_RST_MASK 0x01
  49. #define CON1_WDT_RST_SHIFT 6
  50. #define CON1_OTG_CONFIG_MASK 0x01
  51. #define CON1_OTG_CONFIG_SHIFT 5
  52. #define CON1_CHG_CONFIG_MASK 0x01
  53. #define CON1_CHG_CONFIG_SHIFT 4
  54. #define CON1_SYS_MIN_MASK 0x07
  55. #define CON1_SYS_MIN_SHIFT 1
  56. #define CON1_BOOST_LIM_MASK 0x01
  57. #define CON1_BOOST_LIM_SHIFT 0
  58. /* CON2 */
  59. #define CON2_ICHG_MASK 0x3F
  60. #define CON2_ICHG_SHIFT 2
  61. #define CON2_BCOLD_MASK 0x1
  62. #define CON2_BCOLD_SHIFT 1
  63. #define CON2_FORCE_20PCT_MASK 0x1
  64. #define CON2_FORCE_20PCT_SHIFT 0
  65. /* CON3 */
  66. #define CON3_IPRECHG_MASK 0x0F
  67. #define CON3_IPRECHG_SHIFT 4
  68. #define CON3_ITERM_MASK 0x0F
  69. #define CON3_ITERM_SHIFT 0
  70. /* CON4 */
  71. #define CON4_VREG_MASK 0x3F
  72. #define CON4_VREG_SHIFT 2
  73. #define CON4_BATLOWV_MASK 0x01
  74. #define CON4_BATLOWV_SHIFT 1
  75. #define CON4_VRECHG_MASK 0x01
  76. #define CON4_VRECHG_SHIFT 0
  77. /* CON5 */
  78. #define CON5_EN_TERM_MASK 0x01
  79. #define CON5_EN_TERM_SHIFT 7
  80. #define CON5_WATCHDOG_MASK 0x03
  81. #define CON5_WATCHDOG_SHIFT 4
  82. #define CON5_EN_TIMER_MASK 0x01
  83. #define CON5_EN_TIMER_SHIFT 3
  84. #define CON5_CHG_TIMER_MASK 0x03
  85. #define CON5_CHG_TIMER_SHIFT 1
  86. /* CON6 */
  87. #define CON6_BOOSTV_MASK 0xF
  88. #define CON6_BOOSTV_SHIFT 4
  89. #define CON6_BHOT_MASK 0x3
  90. #define CON6_BHOT_SHIFT 2
  91. #define CON6_TREG_MASK 0x03
  92. #define CON6_TREG_SHIFT 0
  93. /* CON7 */
  94. #define CON7_TMR2X_EN_MASK 0x01
  95. #define CON7_TMR2X_EN_SHIFT 6
  96. #define CON7_BATFET_Disable_MASK 0x01
  97. #define CON7_BATFET_Disable_SHIFT 5
  98. #define CON7_INT_MASK_MASK 0x03
  99. #define CON7_INT_MASK_SHIFT 0
  100. /* CON8 */
  101. #define CON8_VBUS_STAT_MASK 0x03
  102. #define CON8_VBUS_STAT_SHIFT 6
  103. #define CON8_CHRG_STAT_MASK 0x03
  104. #define CON8_CHRG_STAT_SHIFT 4
  105. #define CON8_DPM_STAT_MASK 0x01
  106. #define CON8_DPM_STAT_SHIFT 3
  107. #define CON8_PG_STAT_MASK 0x01
  108. #define CON8_PG_STAT_SHIFT 2
  109. #define CON8_THERM_STAT_MASK 0x01
  110. #define CON8_THERM_STAT_SHIFT 1
  111. #define CON8_VSYS_STAT_MASK 0x01
  112. #define CON8_VSYS_STAT_SHIFT 0
  113. /* CON9 */
  114. #define CON9_WATCHDOG_FAULT_MASK 0x01
  115. #define CON9_WATCHDOG_FAULT_SHIFT 7
  116. #define CON9_OTG_FAULT_MASK 0x01
  117. #define CON9_OTG_FAULT_SHIFT 6
  118. #define CON9_CHRG_FAULT_MASK 0x03
  119. #define CON9_CHRG_FAULT_SHIFT 4
  120. #define CON9_BAT_FAULT_MASK 0x01
  121. #define CON9_BAT_FAULT_SHIFT 3
  122. #define CON9_NTC_FAULT_MASK 0x07
  123. #define CON9_NTC_FAULT_SHIFT 0
  124. /* CON10 */
  125. #define CON10_PN_MASK 0x07
  126. #define CON10_PN_SHIFT 3
  127. #define CON10_Rev_MASK 0x07
  128. #define CON10_Rev_SHIFT 0
  129. /**********************************************************
  130. *
  131. * [Extern Function]
  132. *
  133. *********************************************************/
  134. /* CON0---------------------------------------------------- */
  135. extern void bq24296_set_en_hiz(unsigned int val);
  136. extern void bq24296_set_vindpm(unsigned int val);
  137. extern void bq24296_set_iinlim(unsigned int val);
  138. /* CON1---------------------------------------------------- */
  139. extern void bq24296_set_reg_rst(unsigned int val);
  140. extern void bq24296_set_wdt_rst(unsigned int val);
  141. extern void bq24296_set_chg_config(unsigned int val);
  142. extern void bq24296_set_otg_config(unsigned int val);
  143. extern void bq24296_set_sys_min(unsigned int val);
  144. extern void bq24296_set_boost_lim(unsigned int val);
  145. /* CON2---------------------------------------------------- */
  146. extern void bq24296_set_ichg(unsigned int val);
  147. extern void bq24296_set_bcold(unsigned int val);
  148. extern void bq24296_set_force_20pct(unsigned int val);
  149. /* CON3---------------------------------------------------- */
  150. extern void bq24296_set_iprechg(unsigned int val);
  151. extern void bq24296_set_iterm(unsigned int val);
  152. /* CON4---------------------------------------------------- */
  153. extern void bq24296_set_vreg(unsigned int val);
  154. extern void bq24296_set_batlowv(unsigned int val);
  155. extern void bq24296_set_vrechg(unsigned int val);
  156. /* CON5---------------------------------------------------- */
  157. extern void bq24296_set_en_term(unsigned int val);
  158. extern void bq24296_set_watchdog(unsigned int val);
  159. extern void bq24296_set_en_timer(unsigned int val);
  160. extern void bq24296_set_chg_timer(unsigned int val);
  161. /* CON6---------------------------------------------------- */
  162. extern void bq24296_set_treg(unsigned int val);
  163. extern void bq24296_set_boostv(unsigned int val);
  164. extern void bq24296_set_bhot(unsigned int val);
  165. /* CON7---------------------------------------------------- */
  166. extern void bq24296_set_tmr2x_en(unsigned int val);
  167. extern void bq24296_set_batfet_disable(unsigned int val);
  168. extern void bq24296_set_int_mask(unsigned int val);
  169. /* CON8---------------------------------------------------- */
  170. extern unsigned int bq24296_get_system_status(void);
  171. extern unsigned int bq24296_get_vbus_stat(void);
  172. extern unsigned int bq24296_get_chrg_stat(void);
  173. extern unsigned int bq24296_get_vsys_stat(void);
  174. /* --------------------------------------------------------- */
  175. extern void bq24296_dump_register(void);
  176. extern unsigned int bq24296_reg_config_interface(unsigned char RegNum, unsigned char val);
  177. extern unsigned int bq24296_read_interface(unsigned char RegNum, unsigned char *val, unsigned char MASK,
  178. unsigned char SHIFT);
  179. extern unsigned int bq24296_config_interface(unsigned char RegNum, unsigned char val, unsigned char MASK,
  180. unsigned char SHIFT);
  181. #endif /* _bq24296_SW_H_ */