mmdvfs_mgr_v2.c 27 KB

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  1. #include <linux/uaccess.h>
  2. #include <linux/timer.h>
  3. #include <linux/jiffies.h>
  4. #include <linux/workqueue.h>
  5. #include <linux/mtk_gpu_utility.h>
  6. #include <aee.h>
  7. #include <mt_smi.h>
  8. #ifndef MMDVFS_STANDALONE
  9. #include <mt_vcorefs_manager.h>
  10. #endif
  11. #include <mach/mt_freqhopping.h>
  12. #include "mmdvfs_mgr.h"
  13. #undef pr_fmt
  14. #define pr_fmt(fmt) "[" MMDVFS_LOG_TAG "]" fmt
  15. /* MMDVFS SWITCH. NO MMDVFS for 6595 */
  16. #if IS_ENABLED(CONFIG_ARM64)
  17. /* 6795 */
  18. #define MMDVFS_ENABLE 1
  19. #else
  20. /* 6595 */
  21. #define MMDVFS_ENABLE 0
  22. #endif
  23. #if MMDVFS_ENABLE
  24. #ifndef MMDVFS_STANDALONE
  25. #include <mach/fliper.h>
  26. #endif
  27. #endif
  28. /* WQHD MMDVFS SWITCH */
  29. #define MMDVFS_ENABLE_WQHD 0
  30. #define MMDVFS_GPU_LOADING_NUM 30
  31. #define MMDVFS_GPU_LOADING_START_INDEX 10
  32. #define MMDVFS_GPU_LOADING_SAMPLE_DURATION_IN_MS 100
  33. #define MMDVFS_GPU_LOADING_THRESHOLD 18
  34. /* enable WQHD defalt 1.0v */
  35. /* #define MMDVFS_WQHD_1_0V */
  36. #if (MMDVFS_GPU_LOADING_START_INDEX >= MMDVFS_GPU_LOADING_NUM)
  37. #error "start index too large"
  38. #endif
  39. /* mmdvfs MM sizes */
  40. #define MMDVFS_PIXEL_NUM_720P (1280 * 720)
  41. #define MMDVFS_PIXEL_NUM_2160P (3840 * 2160)
  42. #define MMDVFS_PIXEL_NUM_1080P (2100 * 1300)
  43. #define MMDVFS_PIXEL_NUM_2M (2100 * 1300)
  44. #define MMDVFS_PIXEL_NUM_13M (13000000)
  45. /* 13M sensor */
  46. #define MMDVFS_PIXEL_NUM_SENSOR_FULL (13000000)
  47. /* mmdvfs display sizes */
  48. #define MMDVFS_DISPLAY_SIZE_FHD (1920 * 1216)
  49. #define MMDVFS_CLK_SWITCH_CB_MAX 16
  50. #define MMDVFS_CLK_SWITCH_CLIENT_MSG_MAX 20
  51. static int notify_cb_func_checked(clk_switch_cb func, int ori_mmsys_clk_mode,
  52. int update_mmsys_clk_mode, char *msg);
  53. static int mmdfvs_adjust_mmsys_clk_by_hopping(int clk_mode);
  54. static int mmdvfs_set_step_with_mmsys_clk(MTK_SMI_BWC_SCEN scenario, mmdvfs_voltage_enum step,
  55. int mmsys_clk_mode);
  56. static void notify_mmsys_clk_change(int ori_mmsys_clk_mode, int update_mmsys_clk_mode);
  57. static int mmsys_clk_change_notify_checked(clk_switch_cb func, int ori_mmsys_clk_mode,
  58. int update_mmsys_clk_mode, char *msg);
  59. static mmdvfs_voltage_enum determine_current_mmsys_clk(void);
  60. static int is_cam_monior_work;
  61. enum {
  62. MMDVFS_CAM_MON_SCEN = SMI_BWC_SCEN_CNT, MMDVFS_SCEN_MHL, MMDVFS_SCEN_COUNT
  63. };
  64. static clk_switch_cb quick_mmclk_cbs[MMDVFS_CLK_SWITCH_CB_MAX];
  65. static clk_switch_cb notify_cb_func;
  66. static clk_switch_cb notify_cb_func_nolock;
  67. static int current_mmsys_clk = MMSYS_CLK_MEDIUM;
  68. /* + 1 for MMDVFS_CAM_MON_SCEN */
  69. static mmdvfs_voltage_enum g_mmdvfs_scenario_voltage[MMDVFS_SCEN_COUNT] = {
  70. MMDVFS_VOLTAGE_DEFAULT};
  71. static mmdvfs_voltage_enum g_mmdvfs_current_step;
  72. static unsigned int g_mmdvfs_concurrency;
  73. static MTK_SMI_BWC_MM_INFO *g_mmdvfs_info;
  74. static MTK_MMDVFS_CMD g_mmdvfs_cmd;
  75. /* mmdvfs timer for monitor gpu loading */
  76. typedef struct {
  77. /* linux timer */
  78. struct timer_list timer;
  79. /* work q */
  80. struct workqueue_struct *work_queue;
  81. struct work_struct work;
  82. /* data payload */
  83. unsigned int gpu_loadings[MMDVFS_GPU_LOADING_NUM];
  84. int gpu_loading_index;
  85. } mmdvfs_gpu_monitor_struct;
  86. typedef struct {
  87. spinlock_t scen_lock;
  88. int is_mhl_enable;
  89. mmdvfs_gpu_monitor_struct gpu_monitor;
  90. } mmdvfs_context_struct;
  91. /* mmdvfs_query() return value, remember to sync with user space */
  92. typedef enum {
  93. MMDVFS_STEP_LOW = 0, MMDVFS_STEP_HIGH,
  94. MMDVFS_STEP_LOW2LOW, /* LOW */
  95. MMDVFS_STEP_HIGH2LOW, /* LOW */
  96. MMDVFS_STEP_LOW2HIGH, /* HIGH */
  97. MMDVFS_STEP_HIGH2HIGH,
  98. /* HIGH */
  99. } mmdvfs_step_enum;
  100. /* lcd size */
  101. typedef enum {
  102. MMDVFS_LCD_SIZE_FHD, MMDVFS_LCD_SIZE_WQHD, MMDVFS_LCD_SIZE_END_OF_ENUM
  103. } mmdvfs_lcd_size_enum;
  104. static mmdvfs_context_struct g_mmdvfs_mgr_cntx;
  105. static mmdvfs_context_struct * const g_mmdvfs_mgr = &g_mmdvfs_mgr_cntx;
  106. static mmdvfs_lcd_size_enum mmdvfs_get_lcd_resolution(void)
  107. {
  108. if (DISP_GetScreenWidth() * DISP_GetScreenHeight()
  109. <= MMDVFS_DISPLAY_SIZE_FHD) {
  110. return MMDVFS_LCD_SIZE_FHD;
  111. }
  112. return MMDVFS_LCD_SIZE_WQHD;
  113. }
  114. static mmdvfs_voltage_enum mmdvfs_get_default_step(void)
  115. {
  116. #ifdef MMDVFS_WQHD_1_0V
  117. return MMDVFS_VOLTAGE_LOW;
  118. #else
  119. if (mmdvfs_get_lcd_resolution() == MMDVFS_LCD_SIZE_FHD)
  120. return MMDVFS_VOLTAGE_LOW;
  121. else
  122. return MMDVFS_VOLTAGE_HIGH;
  123. #endif
  124. }
  125. static mmdvfs_voltage_enum mmdvfs_get_current_step(void)
  126. {
  127. return g_mmdvfs_current_step;
  128. }
  129. static int mmsys_clk_query(MTK_SMI_BWC_SCEN scenario,
  130. MTK_MMDVFS_CMD *cmd)
  131. {
  132. int step = MMSYS_CLK_MEDIUM;
  133. unsigned int venc_size;
  134. MTK_MMDVFS_CMD cmd_default;
  135. venc_size = g_mmdvfs_info->video_record_size[0]
  136. * g_mmdvfs_info->video_record_size[1];
  137. /* use default info */
  138. if (cmd == NULL) {
  139. memset(&cmd_default, 0, sizeof(MTK_MMDVFS_CMD));
  140. cmd_default.camera_mode = MMDVFS_CAMERA_MODE_FLAG_DEFAULT;
  141. cmd = &cmd_default;
  142. }
  143. /* collect the final information */
  144. if (cmd->sensor_size == 0)
  145. cmd->sensor_size = g_mmdvfs_cmd.sensor_size;
  146. if (cmd->sensor_fps == 0)
  147. cmd->sensor_fps = g_mmdvfs_cmd.sensor_fps;
  148. if (cmd->camera_mode == MMDVFS_CAMERA_MODE_FLAG_DEFAULT)
  149. cmd->camera_mode = g_mmdvfs_cmd.camera_mode;
  150. /* HIGH level scenarios */
  151. switch (scenario) {
  152. case SMI_BWC_SCEN_VR:
  153. if (is_force_max_mmsys_clk())
  154. step = MMSYS_CLK_HIGH;
  155. if (cmd->sensor_size >= MMDVFS_PIXEL_NUM_13M)
  156. /* 13M high */
  157. step = MMSYS_CLK_HIGH;
  158. else if (cmd->camera_mode & (MMDVFS_CAMERA_MODE_FLAG_PIP | MMDVFS_CAMERA_MODE_FLAG_STEREO))
  159. /* PIP for ISP clock */
  160. step = MMSYS_CLK_HIGH;
  161. break;
  162. case SMI_BWC_SCEN_VR_SLOW:
  163. case SMI_BWC_SCEN_ICFP:
  164. step = MMSYS_CLK_HIGH;
  165. break;
  166. default:
  167. break;
  168. }
  169. return step;
  170. }
  171. static mmdvfs_voltage_enum mmdvfs_query(MTK_SMI_BWC_SCEN scenario,
  172. MTK_MMDVFS_CMD *cmd)
  173. {
  174. mmdvfs_voltage_enum step = mmdvfs_get_default_step();
  175. unsigned int venc_size;
  176. MTK_MMDVFS_CMD cmd_default;
  177. venc_size = g_mmdvfs_info->video_record_size[0]
  178. * g_mmdvfs_info->video_record_size[1];
  179. /* use default info */
  180. if (cmd == NULL) {
  181. memset(&cmd_default, 0, sizeof(MTK_MMDVFS_CMD));
  182. cmd_default.camera_mode = MMDVFS_CAMERA_MODE_FLAG_DEFAULT;
  183. cmd = &cmd_default;
  184. }
  185. /* collect the final information */
  186. if (cmd->sensor_size == 0)
  187. cmd->sensor_size = g_mmdvfs_cmd.sensor_size;
  188. if (cmd->sensor_fps == 0)
  189. cmd->sensor_fps = g_mmdvfs_cmd.sensor_fps;
  190. if (cmd->camera_mode == MMDVFS_CAMERA_MODE_FLAG_DEFAULT)
  191. cmd->camera_mode = g_mmdvfs_cmd.camera_mode;
  192. /* HIGH level scenarios */
  193. switch (scenario) {
  194. case SMI_BWC_SCEN_VR:
  195. if (is_force_camera_hpm())
  196. step = MMDVFS_VOLTAGE_HIGH;
  197. if (cmd->sensor_size >= MMDVFS_PIXEL_NUM_13M)
  198. /* 13M high */
  199. step = MMDVFS_VOLTAGE_HIGH;
  200. else if (cmd->camera_mode & (MMDVFS_CAMERA_MODE_FLAG_PIP | MMDVFS_CAMERA_MODE_FLAG_STEREO |
  201. MMDVFS_CAMERA_MODE_FLAG_VFB | MMDVFS_CAMERA_MODE_FLAG_EIS_2_0))
  202. /* PIP for ISP clock */
  203. step = MMDVFS_VOLTAGE_HIGH;
  204. break;
  205. case SMI_BWC_SCEN_VR_SLOW:
  206. case SMI_BWC_SCEN_ICFP:
  207. step = MMDVFS_VOLTAGE_HIGH;
  208. break;
  209. default:
  210. break;
  211. }
  212. return step;
  213. }
  214. static mmdvfs_voltage_enum determine_current_mmsys_clk(void)
  215. {
  216. int i = 0;
  217. int final_clk = MMSYS_CLK_MEDIUM;
  218. for (i = 0; i < MMDVFS_SCEN_COUNT; i++) {
  219. if (g_mmdvfs_scenario_voltage[i] == MMDVFS_VOLTAGE_HIGH) {
  220. /* Check the mmsys clk */
  221. switch (i) {
  222. case SMI_BWC_SCEN_VR:
  223. case MMDVFS_CAM_MON_SCEN:
  224. if (is_force_max_mmsys_clk())
  225. final_clk = MMSYS_CLK_HIGH;
  226. else if (g_mmdvfs_cmd.sensor_size >= MMDVFS_PIXEL_NUM_13M)
  227. /* 13M high */
  228. final_clk = MMSYS_CLK_HIGH;
  229. else if (g_mmdvfs_cmd.camera_mode & (MMDVFS_CAMERA_MODE_FLAG_PIP |
  230. MMDVFS_CAMERA_MODE_FLAG_STEREO))
  231. /* PIP for ISP clock */
  232. final_clk = MMSYS_CLK_HIGH;
  233. break;
  234. case SMI_BWC_SCEN_VR_SLOW:
  235. case SMI_BWC_SCEN_ICFP:
  236. final_clk = MMSYS_CLK_HIGH;
  237. break;
  238. default:
  239. break;
  240. }
  241. }
  242. }
  243. return final_clk;
  244. }
  245. static void mmdvfs_update_cmd(MTK_MMDVFS_CMD *cmd)
  246. {
  247. if (cmd == NULL)
  248. return;
  249. if (cmd->sensor_size)
  250. g_mmdvfs_cmd.sensor_size = cmd->sensor_size;
  251. if (cmd->sensor_fps)
  252. g_mmdvfs_cmd.sensor_fps = cmd->sensor_fps;
  253. /* MMDVFSMSG("update cm %d\n", cmd->camera_mode); */
  254. /* if (cmd->camera_mode != MMDVFS_CAMERA_MODE_FLAG_DEFAULT) { */
  255. g_mmdvfs_cmd.camera_mode = cmd->camera_mode;
  256. /* } */
  257. }
  258. /* static void mmdvfs_dump_info(void)
  259. {
  260. MMDVFSMSG("CMD %d %d %d\n", g_mmdvfs_cmd.sensor_size,
  261. g_mmdvfs_cmd.sensor_fps, g_mmdvfs_cmd.camera_mode);
  262. MMDVFSMSG("INFO VR %d %d\n", g_mmdvfs_info->video_record_size[0],
  263. g_mmdvfs_info->video_record_size[1]);
  264. }
  265. */
  266. #ifdef MMDVFS_GPU_MONITOR_ENABLE
  267. static void mmdvfs_timer_callback(unsigned long data)
  268. {
  269. mmdvfs_gpu_monitor_struct *gpu_monitor =
  270. (mmdvfs_gpu_monitor_struct *)data;
  271. unsigned int gpu_loading = 0;
  272. /* if (mtk_get_gpu_loading(&gpu_loading)) {
  273. MMDVFSMSG("gpuload %d %ld\n", gpu_loading, jiffies_to_msecs(jiffies));
  274. */
  275. /* store gpu loading into the array */
  276. gpu_monitor->gpu_loadings[gpu_monitor->gpu_loading_index++]
  277. = gpu_loading;
  278. /* fire another timer until the end */
  279. if (gpu_monitor->gpu_loading_index < MMDVFS_GPU_LOADING_NUM - 1) {
  280. mod_timer(
  281. &gpu_monitor->timer,
  282. jiffies + msecs_to_jiffies(
  283. MMDVFS_GPU_LOADING_SAMPLE_DURATION_IN_MS));
  284. } else {
  285. /* the final timer */
  286. int i;
  287. int avg_loading;
  288. unsigned int sum = 0;
  289. for (i = MMDVFS_GPU_LOADING_START_INDEX; i
  290. < MMDVFS_GPU_LOADING_NUM; i++) {
  291. sum += gpu_monitor->gpu_loadings[i];
  292. }
  293. avg_loading = sum / MMDVFS_GPU_LOADING_NUM;
  294. MMDVFSMSG("gpuload %d AVG %d\n", jiffies_to_msecs(jiffies),
  295. avg_loading);
  296. /* drops to low step if the gpu loading is low */
  297. if (avg_loading <= MMDVFS_GPU_LOADING_THRESHOLD)
  298. queue_work(gpu_monitor->work_queue, &gpu_monitor->work);
  299. }
  300. }
  301. static void mmdvfs_gpu_monitor_work(struct work_struct *work)
  302. {
  303. MMDVFSMSG("WQ %d\n", jiffies_to_msecs(jiffies));
  304. }
  305. static void mmdvfs_init_gpu_monitor(mmdvfs_gpu_monitor_struct *gm)
  306. {
  307. struct timer_list *gpu_timer = &gm->timer;
  308. /* setup gpu monitor timer */
  309. setup_timer(gpu_timer, mmdvfs_timer_callback, (unsigned long)gm);
  310. gm->work_queue = create_singlethread_workqueue("mmdvfs_gpumon");
  311. INIT_WORK(&gm->work, mmdvfs_gpu_monitor_work);
  312. }
  313. #endif /* MMDVFS_GPU_MONITOR_ENABLE */
  314. /* delay 4 seconds to go LPM to workaround camera ZSD + PIP issue */
  315. static void mmdvfs_cam_work_handler(struct work_struct *work)
  316. {
  317. /* MMDVFSMSG("CAM handler %d\n", jiffies_to_msecs(jiffies)); */
  318. mmdvfs_set_step(MMDVFS_CAM_MON_SCEN, mmdvfs_get_default_step());
  319. spin_lock(&g_mmdvfs_mgr->scen_lock);
  320. is_cam_monior_work = 0;
  321. spin_unlock(&g_mmdvfs_mgr->scen_lock);
  322. }
  323. static DECLARE_DELAYED_WORK(g_mmdvfs_cam_work, mmdvfs_cam_work_handler);
  324. static void mmdvfs_stop_cam_monitor(void)
  325. {
  326. cancel_delayed_work_sync(&g_mmdvfs_cam_work);
  327. }
  328. #define MMDVFS_CAM_MON_DELAY (6 * HZ)
  329. static void mmdvfs_start_cam_monitor(int scen)
  330. {
  331. int delayed_mmsys_state = MMSYS_CLK_MEDIUM;
  332. mmdvfs_stop_cam_monitor();
  333. spin_lock(&g_mmdvfs_mgr->scen_lock);
  334. is_cam_monior_work = 1;
  335. spin_unlock(&g_mmdvfs_mgr->scen_lock);
  336. if (current_mmsys_clk == MMSYS_CLK_LOW) {
  337. MMDVFSMSG("Can't switch clk by hopping when CLK is low\n");
  338. delayed_mmsys_state = MMSYS_CLK_MEDIUM;
  339. } else {
  340. delayed_mmsys_state = current_mmsys_clk;
  341. }
  342. /* MMDVFSMSG("CAM start %d\n", jiffies_to_msecs(jiffies)); */
  343. if (is_force_max_mmsys_clk()) {
  344. mmdvfs_set_step_with_mmsys_clk(MMDVFS_CAM_MON_SCEN, MMDVFS_VOLTAGE_HIGH, MMSYS_CLK_HIGH);
  345. } else if (scen == SMI_BWC_SCEN_ICFP || scen == SMI_BWC_SCEN_VR_SLOW || scen == SMI_BWC_SCEN_VR) {
  346. if (g_mmdvfs_cmd.camera_mode & (MMDVFS_CAMERA_MODE_FLAG_PIP | MMDVFS_CAMERA_MODE_FLAG_STEREO))
  347. mmdvfs_set_step_with_mmsys_clk(MMDVFS_CAM_MON_SCEN, MMDVFS_VOLTAGE_HIGH, MMSYS_CLK_HIGH);
  348. /* MMDVFSMSG("CAM monitor keep MMSYS_CLK_HIGH\n"); */
  349. else if (g_mmdvfs_cmd.camera_mode & (MMDVFS_CAMERA_MODE_FLAG_VFB | MMDVFS_CAMERA_MODE_FLAG_EIS_2_0))
  350. mmdvfs_set_step_with_mmsys_clk(MMDVFS_CAM_MON_SCEN, MMDVFS_VOLTAGE_HIGH, delayed_mmsys_state);
  351. /*
  352. else {
  353. MMDVFSMSG("Keep cam monitor going so that DISP can't disable the vencpll\n");
  354. }
  355. */
  356. }
  357. /* 4 seconds for PIP switch preview aspect delays... */
  358. schedule_delayed_work(&g_mmdvfs_cam_work, MMDVFS_CAM_MON_DELAY);
  359. }
  360. #if MMDVFS_ENABLE_WQHD
  361. static void mmdvfs_start_gpu_monitor(mmdvfs_gpu_monitor_struct *gm)
  362. {
  363. struct timer_list *gpu_timer = &gm->timer;
  364. gm->gpu_loading_index = 0;
  365. memset(gm->gpu_loadings, 0, sizeof(unsigned int) * MMDVFS_GPU_LOADING_NUM);
  366. mod_timer(gpu_timer, jiffies + msecs_to_jiffies(MMDVFS_GPU_LOADING_SAMPLE_DURATION_IN_MS));
  367. }
  368. static void mmdvfs_stop_gpu_monitor(mmdvfs_gpu_monitor_struct *gm)
  369. {
  370. struct timer_list *gpu_timer = &gm->timer;
  371. /* flush workqueue */
  372. flush_workqueue(gm->work_queue);
  373. /* delete timer */
  374. del_timer(gpu_timer);
  375. }
  376. #endif /* MMDVFS_ENABLE_WQHD */
  377. static void mmdvfs_vcorefs_request_dvfs_opp(int mm_kicker, int mm_dvfs_opp)
  378. {
  379. int vcore_enable = 0;
  380. vcore_enable = is_vcorefs_can_work();
  381. if (vcore_enable != 1) {
  382. MMDVFSMSG("Vcore disable: is_vcorefs_can_work = %d, (%d, %d)\n", vcore_enable, mm_kicker, mm_dvfs_opp);
  383. } else {
  384. /* MMDVFSMSG("Vcore trigger: is_vcorefs_can_work = %d, (%d, %d)\n", vcore_enable,
  385. mm_kicker, mm_dvfs_opp); */
  386. vcorefs_request_dvfs_opp(mm_kicker, mm_dvfs_opp);
  387. }
  388. }
  389. int mmdvfs_set_step(MTK_SMI_BWC_SCEN scenario, mmdvfs_voltage_enum step)
  390. {
  391. return mmdvfs_set_step_with_mmsys_clk(scenario, step, MMSYS_CLK_MEDIUM);
  392. }
  393. int mmdvfs_set_step_with_mmsys_clk(MTK_SMI_BWC_SCEN smi_scenario, mmdvfs_voltage_enum step, int mmsys_clk_mode_request)
  394. {
  395. int i, scen_index;
  396. unsigned int concurrency;
  397. unsigned int scenario = smi_scenario;
  398. mmdvfs_voltage_enum final_step = mmdvfs_get_default_step();
  399. int mmsys_clk_step = MMSYS_CLK_MEDIUM;
  400. int mmsys_clk_mode = mmsys_clk_mode_request;
  401. /* workaround for WFD VENC scenario*/
  402. if (scenario == SMI_BWC_SCEN_VENC || scenario == SMI_BWC_SCEN_VP)
  403. return 0;
  404. if (step == MMDVFS_VOLTAGE_DEFAULT_STEP)
  405. step = final_step;
  406. #if !MMDVFS_ENABLE
  407. return 0;
  408. #endif
  409. /* MMDVFSMSG("MMDVFS set voltage scen %d step %d\n", scenario, step); */
  410. if ((scenario >= (MTK_SMI_BWC_SCEN)MMDVFS_SCEN_COUNT) || (scenario
  411. < SMI_BWC_SCEN_NORMAL)) {
  412. MMDVFSERR("invalid scenario\n");
  413. return -1;
  414. }
  415. /* dump information */
  416. /* mmdvfs_dump_info(); */
  417. /* go through all scenarios to decide the final step */
  418. scen_index = (int)scenario;
  419. spin_lock(&g_mmdvfs_mgr->scen_lock);
  420. g_mmdvfs_scenario_voltage[scen_index] = step;
  421. concurrency = 0;
  422. for (i = 0; i < MMDVFS_SCEN_COUNT; i++) {
  423. if (g_mmdvfs_scenario_voltage[i] == MMDVFS_VOLTAGE_HIGH)
  424. concurrency |= 1 << i;
  425. }
  426. /* one high = final high */
  427. for (i = 0; i < MMDVFS_SCEN_COUNT; i++) {
  428. if (g_mmdvfs_scenario_voltage[i] == MMDVFS_VOLTAGE_HIGH) {
  429. final_step = MMDVFS_VOLTAGE_HIGH;
  430. break;
  431. }
  432. }
  433. mmsys_clk_step = determine_current_mmsys_clk();
  434. if (mmsys_clk_mode_request == MMSYS_CLK_MEDIUM && mmsys_clk_step == MMSYS_CLK_HIGH)
  435. mmsys_clk_mode = MMSYS_CLK_HIGH;
  436. else
  437. mmsys_clk_mode = mmsys_clk_mode_request;
  438. g_mmdvfs_current_step = final_step;
  439. spin_unlock(&g_mmdvfs_mgr->scen_lock);
  440. #if MMDVFS_ENABLE
  441. /* call vcore dvfs API */
  442. /* MMDVFSMSG("FHD %d\n", final_step); */
  443. if (final_step == MMDVFS_VOLTAGE_HIGH) {
  444. if (scenario == MMDVFS_SCEN_MHL)
  445. mmdvfs_vcorefs_request_dvfs_opp(KIR_MM_MHL, OPPI_PERF);
  446. else if (scenario == SMI_BWC_SCEN_WFD)
  447. mmdvfs_vcorefs_request_dvfs_opp(KIR_MM_WFD, OPPI_PERF);
  448. else {
  449. mmdvfs_vcorefs_request_dvfs_opp(KIR_MM_16MCAM, OPPI_PERF);
  450. if (mmsys_clk_mode == MMSYS_CLK_HIGH)
  451. mmdfvs_adjust_mmsys_clk_by_hopping(MMSYS_CLK_HIGH);
  452. else
  453. mmdfvs_adjust_mmsys_clk_by_hopping(MMSYS_CLK_MEDIUM);
  454. }
  455. } else{
  456. if (scenario == MMDVFS_SCEN_MHL)
  457. mmdvfs_vcorefs_request_dvfs_opp(KIR_MM_MHL, OPPI_UNREQ);
  458. else if (scenario == SMI_BWC_SCEN_WFD)
  459. mmdvfs_vcorefs_request_dvfs_opp(KIR_MM_WFD, OPPI_UNREQ);
  460. else {
  461. /* must lower the mmsys clk before enter LPM mode */
  462. mmdfvs_adjust_mmsys_clk_by_hopping(MMSYS_CLK_MEDIUM);
  463. mmdvfs_vcorefs_request_dvfs_opp(KIR_MM_16MCAM, OPPI_UNREQ);
  464. }
  465. }
  466. #endif /* MMDVFS_ENABLE */
  467. MMDVFSMSG("Set vol scen:%d,step:%d,final:%d(0x%x),CMD(%d,%d,0x%x),INFO(%d,%d),CLK:%d\n",
  468. scenario, step, final_step, concurrency,
  469. g_mmdvfs_cmd.sensor_size, g_mmdvfs_cmd.sensor_fps, g_mmdvfs_cmd.camera_mode,
  470. g_mmdvfs_info->video_record_size[0], g_mmdvfs_info->video_record_size[1],
  471. current_mmsys_clk);
  472. return 0;
  473. }
  474. void mmdvfs_handle_cmd(MTK_MMDVFS_CMD *cmd)
  475. {
  476. #if !MMDVFS_ENABLE
  477. return;
  478. #endif
  479. /* MMDVFSMSG("MMDVFS handle cmd %u s %d\n", cmd->type, cmd->scen); */
  480. switch (cmd->type) {
  481. case MTK_MMDVFS_CMD_TYPE_SET:
  482. /* save cmd */
  483. mmdvfs_update_cmd(cmd);
  484. if (!(g_mmdvfs_concurrency & (1 << cmd->scen))) {
  485. MMDVFSMSG("invalid set scen %d\n", cmd->scen);
  486. cmd->ret = -1;
  487. } else {
  488. cmd->ret = mmdvfs_set_step_with_mmsys_clk(cmd->scen,
  489. mmdvfs_query(cmd->scen, cmd), mmsys_clk_query(cmd->scen, cmd));
  490. }
  491. break;
  492. case MTK_MMDVFS_CMD_TYPE_QUERY: { /* query with some parameters */
  493. #ifndef MMDVFS_WQHD_1_0V
  494. if (mmdvfs_get_lcd_resolution() == MMDVFS_LCD_SIZE_WQHD) {
  495. /* QUERY ALWAYS HIGH for WQHD */
  496. cmd->ret = (unsigned int)MMDVFS_STEP_HIGH2HIGH;
  497. } else
  498. #endif
  499. {
  500. mmdvfs_voltage_enum query_voltage = mmdvfs_query(cmd->scen, cmd);
  501. mmdvfs_voltage_enum current_voltage = mmdvfs_get_current_step();
  502. if (current_voltage < query_voltage) {
  503. cmd->ret = (unsigned int)MMDVFS_STEP_LOW2HIGH;
  504. } else if (current_voltage > query_voltage) {
  505. cmd->ret = (unsigned int)MMDVFS_STEP_HIGH2LOW;
  506. } else {
  507. cmd->ret
  508. = (unsigned int)(query_voltage
  509. == MMDVFS_VOLTAGE_HIGH
  510. ? MMDVFS_STEP_HIGH2HIGH
  511. : MMDVFS_STEP_LOW2LOW);
  512. }
  513. }
  514. /* MMDVFSMSG("query %d\n", cmd->ret); */
  515. /* cmd->ret = (unsigned int)query_voltage; */
  516. break;
  517. }
  518. default:
  519. MMDVFSMSG("invalid mmdvfs cmd\n");
  520. BUG();
  521. break;
  522. }
  523. }
  524. void mmdvfs_notify_scenario_exit(MTK_SMI_BWC_SCEN scen)
  525. {
  526. #if !MMDVFS_ENABLE
  527. return;
  528. #endif
  529. /* MMDVFSMSG("leave %d\n", scen); */
  530. if ((scen == SMI_BWC_SCEN_VR) || (scen == SMI_BWC_SCEN_VR_SLOW) || (scen == SMI_BWC_SCEN_ICFP))
  531. mmdvfs_start_cam_monitor(scen);
  532. /* reset scenario voltage to default when it exits */
  533. mmdvfs_set_step(scen, mmdvfs_get_default_step());
  534. }
  535. void mmdvfs_notify_scenario_enter(MTK_SMI_BWC_SCEN scen)
  536. {
  537. #if !MMDVFS_ENABLE
  538. return;
  539. #endif
  540. /* MMDVFSMSG("enter %d\n", scen); */
  541. switch (scen) {
  542. case SMI_BWC_SCEN_WFD:
  543. mmdvfs_set_step(scen, MMDVFS_VOLTAGE_HIGH);
  544. if (current_mmsys_clk == MMSYS_CLK_LOW)
  545. mmdvfs_raise_mmsys_by_mux();
  546. break;
  547. case SMI_BWC_SCEN_VR:
  548. if (current_mmsys_clk == MMSYS_CLK_LOW)
  549. mmdvfs_raise_mmsys_by_mux();
  550. if (is_force_camera_hpm()) {
  551. if (is_force_max_mmsys_clk())
  552. mmdvfs_set_step_with_mmsys_clk(scen, MMDVFS_VOLTAGE_HIGH, MMSYS_CLK_HIGH);
  553. else
  554. mmdvfs_set_step(scen, MMDVFS_VOLTAGE_HIGH);
  555. } else {
  556. if (g_mmdvfs_cmd.camera_mode & (MMDVFS_CAMERA_MODE_FLAG_PIP | MMDVFS_CAMERA_MODE_FLAG_STEREO)) {
  557. mmdvfs_set_step_with_mmsys_clk(scen, MMDVFS_VOLTAGE_HIGH, MMSYS_CLK_HIGH);
  558. } else if (g_mmdvfs_cmd.camera_mode & (MMDVFS_CAMERA_MODE_FLAG_VFB |
  559. MMDVFS_CAMERA_MODE_FLAG_EIS_2_0)){
  560. mmdvfs_set_step(scen, MMDVFS_VOLTAGE_HIGH);
  561. }
  562. }
  563. break;
  564. case SMI_BWC_SCEN_VR_SLOW:
  565. case SMI_BWC_SCEN_ICFP:
  566. if (current_mmsys_clk == MMSYS_CLK_LOW)
  567. mmdvfs_raise_mmsys_by_mux();
  568. mmdvfs_set_step_with_mmsys_clk(scen, MMDVFS_VOLTAGE_HIGH, MMSYS_CLK_HIGH);
  569. break;
  570. default:
  571. break;
  572. }
  573. }
  574. void mmdvfs_init(MTK_SMI_BWC_MM_INFO *info)
  575. {
  576. #if !MMDVFS_ENABLE
  577. return;
  578. #endif
  579. spin_lock_init(&g_mmdvfs_mgr->scen_lock);
  580. /* set current step as the default step */
  581. g_mmdvfs_current_step = mmdvfs_get_default_step();
  582. g_mmdvfs_info = info;
  583. #ifdef MMDVFS_GPU_MONITOR_ENABLE
  584. mmdvfs_init_gpu_monitor(&g_mmdvfs_mgr->gpu_monitor);
  585. #endif /* MMDVFS_GPU_MONITOR_ENABLE */
  586. }
  587. void mmdvfs_mhl_enable(int enable)
  588. {
  589. g_mmdvfs_mgr->is_mhl_enable = enable;
  590. if (enable)
  591. mmdvfs_set_step(MMDVFS_SCEN_MHL, MMDVFS_VOLTAGE_HIGH);
  592. else
  593. mmdvfs_set_step(MMDVFS_SCEN_MHL, MMDVFS_VOLTAGE_DEFAULT_STEP);
  594. }
  595. void mmdvfs_notify_scenario_concurrency(unsigned int u4Concurrency)
  596. {
  597. /*
  598. * DO NOT CALL VCORE DVFS API HERE. THIS FUNCTION IS IN SMI SPIN LOCK.
  599. */
  600. /* raise EMI monitor BW threshold in VP, VR, VR SLOW motion cases to
  601. make sure vcore stay MMDVFS level as long as possible */
  602. if (u4Concurrency & ((1 << SMI_BWC_SCEN_VP) | (1 << SMI_BWC_SCEN_VR)
  603. | (1 << SMI_BWC_SCEN_VR_SLOW))) {
  604. #if MMDVFS_ENABLE
  605. /* MMDVFSMSG("fliper high\n"); */
  606. /* fliper_set_bw(BW_THRESHOLD_HIGH); */
  607. #endif
  608. } else {
  609. #if MMDVFS_ENABLE
  610. /* MMDVFSMSG("fliper normal\n"); */
  611. /* fliper_restore_bw(); */
  612. #endif
  613. }
  614. g_mmdvfs_concurrency = u4Concurrency;
  615. }
  616. int mmdvfs_is_default_step_need_perf(void)
  617. {
  618. if (mmdvfs_get_default_step() == MMDVFS_VOLTAGE_LOW)
  619. return 0;
  620. else
  621. return 1;
  622. }
  623. /* switch MM CLK callback from VCORE DVFS driver */
  624. void mmdvfs_mm_clock_switch_notify(int is_before, int is_to_high)
  625. {
  626. /* for WQHD 1.0v, we have to dynamically switch DL/DC */
  627. #ifdef MMDVFS_WQHD_1_0V
  628. int session_id;
  629. if (mmdvfs_get_lcd_resolution() != MMDVFS_LCD_SIZE_WQHD)
  630. return;
  631. session_id = MAKE_DISP_SESSION(DISP_SESSION_PRIMARY, 0);
  632. if (!is_before && is_to_high) {
  633. MMDVFSMSG("DL\n");
  634. /* nonblocking switch to direct link after HPM */
  635. primary_display_switch_mode_for_mmdvfs(DISP_SESSION_DIRECT_LINK_MODE, session_id, 0);
  636. } else if (is_before && !is_to_high) {
  637. /* BLOCKING switch to decouple before switching to LPM */
  638. MMDVFSMSG("DC\n");
  639. primary_display_switch_mode_for_mmdvfs(DISP_SESSION_DECOUPLE_MODE, session_id, 1);
  640. }
  641. #endif /* MMDVFS_WQHD_1_0V */
  642. }
  643. static int mmdfvs_adjust_mmsys_clk_by_hopping(int clk_mode)
  644. {
  645. int freq_hopping_disable = is_mmdvfs_freq_hopping_disabled();
  646. int result = 0;
  647. if (clk_mode == MMSYS_CLK_HIGH) {
  648. if (current_mmsys_clk == MMSYS_CLK_LOW) {
  649. MMDVFSMSG("Doesn't allow mmsys clk adjust from low to high!\n");
  650. } else if (!freq_hopping_disable && current_mmsys_clk != MMSYS_CLK_HIGH) {
  651. /* MMDVFSMSG("Freq hopping: DSS: %d\n", 0xE0000);*/
  652. mt_dfs_vencpll(0xE0000);
  653. notify_cb_func_checked(notify_cb_func, current_mmsys_clk, MMSYS_CLK_HIGH,
  654. "notify_cb_func");
  655. /* For common clients */
  656. notify_mmsys_clk_change(current_mmsys_clk, MMSYS_CLK_HIGH);
  657. current_mmsys_clk = MMSYS_CLK_HIGH;
  658. } else {
  659. if (freq_hopping_disable)
  660. MMDVFSMSG("Freq hopping disable, not trigger: DSS: %d\n", 0xE0000);
  661. }
  662. result = 1;
  663. } else if (clk_mode == MMSYS_CLK_MEDIUM) {
  664. if (!freq_hopping_disable && current_mmsys_clk != MMSYS_CLK_MEDIUM) {
  665. /* MMDVFSMSG("Freq hopping: DSS: %d\n", 0xB0000); */
  666. mt_dfs_vencpll(0xB0000);
  667. notify_cb_func_checked(notify_cb_func, current_mmsys_clk, MMSYS_CLK_MEDIUM,
  668. "notify_cb_func");
  669. /* For common clients */
  670. notify_mmsys_clk_change(current_mmsys_clk, MMSYS_CLK_MEDIUM);
  671. current_mmsys_clk = MMSYS_CLK_MEDIUM;
  672. } else {
  673. if (freq_hopping_disable)
  674. MMDVFSMSG("Freq hopping disable, not trigger: DSS: %d\n", 0xB0000);
  675. }
  676. result = 1;
  677. } else if (clk_mode == MMSYS_CLK_LOW) {
  678. MMDVFSMSG("Doesn't support MMSYS_CLK_LOW with hopping in this platform\n");
  679. result = 1;
  680. } else {
  681. MMDVFSMSG("Don't change CLK: mode=%d\n", clk_mode);
  682. result = 0;
  683. }
  684. return result;
  685. }
  686. int mmdvfs_raise_mmsys_by_mux(void)
  687. {
  688. if (is_mmdvfs_freq_mux_disabled())
  689. return 0;
  690. notify_cb_func_checked(notify_cb_func, current_mmsys_clk, MMSYS_CLK_MEDIUM,
  691. "notify_cb_func");
  692. current_mmsys_clk = MMSYS_CLK_MEDIUM;
  693. return 1;
  694. }
  695. int mmdvfs_lower_mmsys_by_mux(void)
  696. {
  697. if (is_mmdvfs_freq_mux_disabled())
  698. return 0;
  699. if (notify_cb_func != NULL && current_mmsys_clk != MMSYS_CLK_HIGH) {
  700. notify_cb_func(current_mmsys_clk, MMSYS_CLK_LOW);
  701. current_mmsys_clk = MMSYS_CLK_LOW;
  702. } else{
  703. MMDVFSMSG("lower_cb_func has not been registered");
  704. return 0;
  705. }
  706. return 1;
  707. }
  708. int register_mmclk_switch_cb(clk_switch_cb notify_cb,
  709. clk_switch_cb notify_cb_nolock)
  710. {
  711. notify_cb_func = notify_cb;
  712. notify_cb_func_nolock = notify_cb_nolock;
  713. return 1;
  714. }
  715. static int notify_cb_func_checked(clk_switch_cb func, int ori_mmsys_clk_mode, int update_mmsys_clk_mode, char *msg)
  716. {
  717. if (is_mmdvfs_freq_mux_disabled()) {
  718. MMDVFSMSG("notify_cb_func is disabled, not invoked: %s, (%d,%d)\n", msg, ori_mmsys_clk_mode,
  719. update_mmsys_clk_mode);
  720. return 0;
  721. }
  722. if (func == NULL) {
  723. MMDVFSMSG("notify_cb_func is NULL, not invoked: %s, (%d,%d)\n", msg, ori_mmsys_clk_mode,
  724. update_mmsys_clk_mode);
  725. } else {
  726. if (ori_mmsys_clk_mode != update_mmsys_clk_mode)
  727. MMDVFSMSG("notify_cb_func: %s, (%d,%d)\n", msg, ori_mmsys_clk_mode, update_mmsys_clk_mode);
  728. func(ori_mmsys_clk_mode, update_mmsys_clk_mode);
  729. return 1;
  730. }
  731. return 0;
  732. }
  733. int mmdvfs_notify_mmclk_switch_request(int event)
  734. {
  735. int i = 0;
  736. MTK_SMI_BWC_SCEN current_smi_scenario = smi_get_current_profile();
  737. /* Don't get the lock since there is no need to synchronize the is_cam_monior_work here*/
  738. if (is_cam_monior_work != 0) {
  739. /* MMDVFSMSG("Doesn't handle disp request when cam monitor is active\n"); */
  740. return 0;
  741. }
  742. /* MMDVFSMSG("mmclk_switch_request: event=%d, current=%d", event, current_smi_scenario); */
  743. /* Only in UI idle modw or VP 1 layer scenario */
  744. /* we can lower the mmsys clock */
  745. if (event == MMDVFS_EVENT_UI_IDLE_ENTER && current_smi_scenario == SMI_BWC_SCEN_NORMAL) {
  746. for (i = 0; i < MMDVFS_SCEN_COUNT; i++) {
  747. if (g_mmdvfs_scenario_voltage[i] == MMDVFS_VOLTAGE_HIGH) {
  748. MMDVFSMSG("Doesn't switch to low mmsys clk; vore is still in HPM mode");
  749. return 0;
  750. }
  751. }
  752. /* call back from DISP so we don't need use DISP lock here */
  753. if (current_mmsys_clk != MMSYS_CLK_HIGH) {
  754. /* Only disable VENC pll when clock is in 286MHz */
  755. notify_cb_func_checked(notify_cb_func_nolock, current_mmsys_clk, MMSYS_CLK_LOW,
  756. "notify_cb_func_nolock");
  757. current_mmsys_clk = MMSYS_CLK_LOW;
  758. return 1;
  759. }
  760. } else if (event == MMDVFS_EVENT_OVL_SINGLE_LAYER_EXIT || event == MMDVFS_EVENT_UI_IDLE_EXIT) {
  761. if (current_mmsys_clk != MMSYS_CLK_HIGH) {
  762. /* call back from DISP so we don't need use DISP lock here */
  763. notify_cb_func_checked(notify_cb_func_nolock, current_mmsys_clk, MMSYS_CLK_MEDIUM,
  764. "notify_cb_func_nolock");
  765. current_mmsys_clk = MMSYS_CLK_MEDIUM;
  766. return 1;
  767. }
  768. } else if (event == MMDVFS_EVENT_OVL_SINGLE_LAYER_ENTER && SMI_BWC_SCEN_VP) {
  769. /* call back from DISP so we don't need use DISP lock here */
  770. if (current_mmsys_clk != MMSYS_CLK_HIGH) {
  771. notify_cb_func_checked(notify_cb_func_nolock, current_mmsys_clk, MMSYS_CLK_LOW,
  772. "notify_cb_func_nolock");
  773. current_mmsys_clk = MMSYS_CLK_LOW;
  774. return 1;
  775. }
  776. }
  777. return 0;
  778. }
  779. int mmdvfs_register_mmclk_switch_cb(clk_switch_cb notify_cb, int mmdvfs_client_id)
  780. {
  781. if (mmdvfs_client_id >= 0 && mmdvfs_client_id < MMDVFS_CLK_SWITCH_CB_MAX) {
  782. quick_mmclk_cbs[mmdvfs_client_id] = notify_cb;
  783. } else{
  784. MMDVFSMSG("clk_switch_cb register failed: id=%d\n", mmdvfs_client_id);
  785. return 1;
  786. }
  787. return 0;
  788. }
  789. static int mmsys_clk_change_notify_checked(clk_switch_cb func, int ori_mmsys_clk_mode,
  790. int update_mmsys_clk_mode, char *msg)
  791. {
  792. if (func == NULL) {
  793. MMDVFSMSG("notify_cb_func is NULL, not invoked: %s, (%d,%d)\n", msg, ori_mmsys_clk_mode,
  794. update_mmsys_clk_mode);
  795. } else {
  796. MMDVFSMSG("notify_cb_func: %s, (%d,%d)\n", msg, ori_mmsys_clk_mode, update_mmsys_clk_mode);
  797. func(ori_mmsys_clk_mode, update_mmsys_clk_mode);
  798. return 1;
  799. }
  800. return 0;
  801. }
  802. static void notify_mmsys_clk_change(int ori_mmsys_clk_mode, int update_mmsys_clk_mode)
  803. {
  804. int i = 0;
  805. char msg[MMDVFS_CLK_SWITCH_CLIENT_MSG_MAX] = "";
  806. for (i = 0; i < MMDVFS_CLK_SWITCH_CB_MAX; i++) {
  807. snprintf(msg, MMDVFS_CLK_SWITCH_CLIENT_MSG_MAX, "id=%d", i);
  808. if (quick_mmclk_cbs[i] != NULL)
  809. mmsys_clk_change_notify_checked(quick_mmclk_cbs[i], ori_mmsys_clk_mode,
  810. update_mmsys_clk_mode, msg);
  811. }
  812. }
  813. void dump_mmdvfs_info(void)
  814. {
  815. int i = 0;
  816. MMDVFSMSG("MMDVFS dump: CMD(%d,%d,0x%x),INFO VR(%d,%d),CLK: %d\n",
  817. g_mmdvfs_cmd.sensor_size, g_mmdvfs_cmd.sensor_fps, g_mmdvfs_cmd.camera_mode,
  818. g_mmdvfs_info->video_record_size[0], g_mmdvfs_info->video_record_size[1],
  819. current_mmsys_clk);
  820. for (i = 0; i < MMDVFS_SCEN_COUNT; i++)
  821. MMDVFSMSG("Secn:%d,vol-step:%d\n", i, g_mmdvfs_scenario_voltage[i]);
  822. }