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ssusb_dev_c_header.h

ssusb_dev_c_header.h 170 KB
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
  1. /* SSUSB_DEV REGISTER DEFINITION */
    2. 

  2. 

  3. #define U3D_LV1ISR                                (SSUSB_DEV_BASE+0x0000)
    4. 

  4. #define U3D_LV1IER                                (SSUSB_DEV_BASE+0x0004)
    5. 

  5. #define U3D_LV1IESR                               (SSUSB_DEV_BASE+0x0008)
    6. 

  6. #define U3D_LV1IECR                               (SSUSB_DEV_BASE+0x000C)
    7. 

  7. #define U3D_AXI_WR_DMA_CFG                        (SSUSB_DEV_BASE+0x0020)
    8. 

  8. #define U3D_AXI_RD_DMA_CFG                        (SSUSB_DEV_BASE+0x0024)
    9. 

  9. #define U3D_MAC_U1_EN_CTRL                        (SSUSB_DEV_BASE+0x0030)
    10. 

  10. #define U3D_MAC_U2_EN_CTRL                        (SSUSB_DEV_BASE+0x0034)
    11. 

  11. #define U3D_SRAM_DBG_CTRL                         (SSUSB_DEV_BASE+0x0040)
    12. 

  12. #define U3D_SRAM_DBG_CTRL_1                       (SSUSB_DEV_BASE+0x0044)
    13. 

  13. #define U3D_RISC_SIZE                             (SSUSB_DEV_BASE+0x0050)
    14. 

  14. #define U3D_WRBUF_ERR_STS                         (SSUSB_DEV_BASE+0x0070)
    15. 

  15. #define U3D_BUF_ERR_EN                            (SSUSB_DEV_BASE+0x0074)
    16. 

  16. #define U3D_EPISR                                 (SSUSB_DEV_BASE+0x0080)
    17. 

  17. #define U3D_EPIER                                 (SSUSB_DEV_BASE+0x0084)
    18. 

  18. #define U3D_EPIESR                                (SSUSB_DEV_BASE+0x0088)
    19. 

  19. #define U3D_EPIECR                                (SSUSB_DEV_BASE+0x008C)
    20. 

  20. #define U3D_DMAISR                                (SSUSB_DEV_BASE+0x0090)
    21. 

  21. #define U3D_DMAIER                                (SSUSB_DEV_BASE+0x0094)
    22. 

  22. #define U3D_DMAIESR                               (SSUSB_DEV_BASE+0x0098)
    23. 

  23. #define U3D_DMAIECR                               (SSUSB_DEV_BASE+0x009C)
    24. 

  24. #define U3D_EP0DMACTRL                            (SSUSB_DEV_BASE+0x00C0)
    25. 

  25. #define U3D_EP0DMASTRADDR                         (SSUSB_DEV_BASE+0x00C4)
    26. 

  26. #define U3D_EP0DMATFRCOUNT                        (SSUSB_DEV_BASE+0x00C8)
    27. 

  27. #define U3D_EP0DMARLCOUNT                         (SSUSB_DEV_BASE+0x00CC)
    28. 

  28. #define U3D_TXDMACTRL                             (SSUSB_DEV_BASE+0x00D0)
    29. 

  29. #define U3D_TXDMASTRADDR                          (SSUSB_DEV_BASE+0x00D4)
    30. 

  30. #define U3D_TXDMATRDCNT                           (SSUSB_DEV_BASE+0x00D8)
    31. 

  31. #define U3D_TXDMARLCOUNT                          (SSUSB_DEV_BASE+0x00DC)
    32. 

  32. #define U3D_RXDMACTRL                             (SSUSB_DEV_BASE+0x00E0)
    33. 

  33. #define U3D_RXDMASTRADDR                          (SSUSB_DEV_BASE+0x00E4)
    34. 

  34. #define U3D_RXDMATRDCNT                           (SSUSB_DEV_BASE+0x00E8)
    35. 

  35. #define U3D_RXDMARLCOUNT                          (SSUSB_DEV_BASE+0x00EC)
    36. 

  36. #define U3D_EP0CSR                                (SSUSB_DEV_BASE+0x0100)
    37. 

  37. #define U3D_RXCOUNT0                              (SSUSB_DEV_BASE+0x0108)
    38. 

  38. #define U3D_RESERVED                              (SSUSB_DEV_BASE+0x010C)
    39. 

  39. #define U3D_TX1CSR0                               (SSUSB_DEV_BASE+0x0110)
    40. 

  40. #define U3D_TX1CSR1                               (SSUSB_DEV_BASE+0x0114)
    41. 

  41. #define U3D_TX1CSR2                               (SSUSB_DEV_BASE+0x0118)
    42. 

  42. #define U3D_TX2CSR0                               (SSUSB_DEV_BASE+0x0120)
    43. 

  43. #define U3D_TX2CSR1                               (SSUSB_DEV_BASE+0x0124)
    44. 

  44. #define U3D_TX2CSR2                               (SSUSB_DEV_BASE+0x0128)
    45. 

  45. #define U3D_TX3CSR0                               (SSUSB_DEV_BASE+0x0130)
    46. 

  46. #define U3D_TX3CSR1                               (SSUSB_DEV_BASE+0x0134)
    47. 

  47. #define U3D_TX3CSR2                               (SSUSB_DEV_BASE+0x0138)
    48. 

  48. #define U3D_TX4CSR0                               (SSUSB_DEV_BASE+0x0140)
    49. 

  49. #define U3D_TX4CSR1                               (SSUSB_DEV_BASE+0x0144)
    50. 

  50. #define U3D_TX4CSR2                               (SSUSB_DEV_BASE+0x0148)
    51. 

  51. #define U3D_TX5CSR0                               (SSUSB_DEV_BASE+0x0150)
    52. 

  52. #define U3D_TX5CSR1                               (SSUSB_DEV_BASE+0x0154)
    53. 

  53. #define U3D_TX5CSR2                               (SSUSB_DEV_BASE+0x0158)
    54. 

  54. #define U3D_TX6CSR0                               (SSUSB_DEV_BASE+0x0160)
    55. 

  55. #define U3D_TX6CSR1                               (SSUSB_DEV_BASE+0x0164)
    56. 

  56. #define U3D_TX6CSR2                               (SSUSB_DEV_BASE+0x0168)
    57. 

  57. #define U3D_TX7CSR0                               (SSUSB_DEV_BASE+0x0170)
    58. 

  58. #define U3D_TX7CSR1                               (SSUSB_DEV_BASE+0x0174)
    59. 

  59. #define U3D_TX7CSR2                               (SSUSB_DEV_BASE+0x0178)
    60. 

  60. #define U3D_TX8CSR0                               (SSUSB_DEV_BASE+0x0180)
    61. 

  61. #define U3D_TX8CSR1                               (SSUSB_DEV_BASE+0x0184)
    62. 

  62. #define U3D_TX8CSR2                               (SSUSB_DEV_BASE+0x0188)
    63. 

  63. #define U3D_TX9CSR0                               (SSUSB_DEV_BASE+0x0190)
    64. 

  64. #define U3D_TX9CSR1                               (SSUSB_DEV_BASE+0x0194)
    65. 

  65. #define U3D_TX9CSR2                               (SSUSB_DEV_BASE+0x0198)
    66. 

  66. #define U3D_TX10CSR0                              (SSUSB_DEV_BASE+0x01A0)
    67. 

  67. #define U3D_TX10CSR1                              (SSUSB_DEV_BASE+0x01A4)
    68. 

  68. #define U3D_TX10CSR2                              (SSUSB_DEV_BASE+0x01A8)
    69. 

  69. #define U3D_TX11CSR0                              (SSUSB_DEV_BASE+0x01B0)
    70. 

  70. #define U3D_TX11CSR1                              (SSUSB_DEV_BASE+0x01B4)
    71. 

  71. #define U3D_TX11CSR2                              (SSUSB_DEV_BASE+0x01B8)
    72. 

  72. #define U3D_TX12CSR0                              (SSUSB_DEV_BASE+0x01C0)
    73. 

  73. #define U3D_TX12CSR1                              (SSUSB_DEV_BASE+0x01C4)
    74. 

  74. #define U3D_TX12CSR2                              (SSUSB_DEV_BASE+0x01C8)
    75. 

  75. #define U3D_TX13CSR0                              (SSUSB_DEV_BASE+0x01D0)
    76. 

  76. #define U3D_TX13CSR1                              (SSUSB_DEV_BASE+0x01D4)
    77. 

  77. #define U3D_TX13CSR2                              (SSUSB_DEV_BASE+0x01D8)
    78. 

  78. #define U3D_TX14CSR0                              (SSUSB_DEV_BASE+0x01E0)
    79. 

  79. #define U3D_TX14CSR1                              (SSUSB_DEV_BASE+0x01E4)
    80. 

  80. #define U3D_TX14CSR2                              (SSUSB_DEV_BASE+0x01E8)
    81. 

  81. #define U3D_TX15CSR0                              (SSUSB_DEV_BASE+0x01F0)
    82. 

  82. #define U3D_TX15CSR1                              (SSUSB_DEV_BASE+0x01F4)
    83. 

  83. #define U3D_TX15CSR2                              (SSUSB_DEV_BASE+0x01F8)
    84. 

  84. #define U3D_RX1CSR0                               (SSUSB_DEV_BASE+0x0210)
    85. 

  85. #define U3D_RX1CSR1                               (SSUSB_DEV_BASE+0x0214)
    86. 

  86. #define U3D_RX1CSR2                               (SSUSB_DEV_BASE+0x0218)
    87. 

  87. #define U3D_RX1CSR3                               (SSUSB_DEV_BASE+0x021C)
    88. 

  88. #define U3D_RX2CSR0                               (SSUSB_DEV_BASE+0x0220)
    89. 

  89. #define U3D_RX2CSR1                               (SSUSB_DEV_BASE+0x0224)
    90. 

  90. #define U3D_RX2CSR2                               (SSUSB_DEV_BASE+0x0228)
    91. 

  91. #define U3D_RX2CSR3                               (SSUSB_DEV_BASE+0x022C)
    92. 

  92. #define U3D_RX3CSR0                               (SSUSB_DEV_BASE+0x0230)
    93. 

  93. #define U3D_RX3CSR1                               (SSUSB_DEV_BASE+0x0234)
    94. 

  94. #define U3D_RX3CSR2                               (SSUSB_DEV_BASE+0x0238)
    95. 

  95. #define U3D_RX3CSR3                               (SSUSB_DEV_BASE+0x023C)
    96. 

  96. #define U3D_RX4CSR0                               (SSUSB_DEV_BASE+0x0240)
    97. 

  97. #define U3D_RX4CSR1                               (SSUSB_DEV_BASE+0x0244)
    98. 

  98. #define U3D_RX4CSR2                               (SSUSB_DEV_BASE+0x0248)
    99. 

  99. #define U3D_RX4CSR3                               (SSUSB_DEV_BASE+0x024C)
    100. 

  100. #define U3D_RX5CSR0                               (SSUSB_DEV_BASE+0x0250)
    101. 

  101. #define U3D_RX5CSR1                               (SSUSB_DEV_BASE+0x0254)
    102. 

  102. #define U3D_RX5CSR2                               (SSUSB_DEV_BASE+0x0258)
    103. 

  103. #define U3D_RX5CSR3                               (SSUSB_DEV_BASE+0x025C)
    104. 

  104. #define U3D_RX6CSR0                               (SSUSB_DEV_BASE+0x0260)
    105. 

  105. #define U3D_RX6CSR1                               (SSUSB_DEV_BASE+0x0264)
    106. 

  106. #define U3D_RX6CSR2                               (SSUSB_DEV_BASE+0x0268)
    107. 

  107. #define U3D_RX6CSR3                               (SSUSB_DEV_BASE+0x026C)
    108. 

  108. #define U3D_RX7CSR0                               (SSUSB_DEV_BASE+0x0270)
    109. 

  109. #define U3D_RX7CSR1                               (SSUSB_DEV_BASE+0x0274)
    110. 

  110. #define U3D_RX7CSR2                               (SSUSB_DEV_BASE+0x0278)
    111. 

  111. #define U3D_RX7CSR3                               (SSUSB_DEV_BASE+0x027C)
    112. 

  112. #define U3D_RX8CSR0                               (SSUSB_DEV_BASE+0x0280)
    113. 

  113. #define U3D_RX8CSR1                               (SSUSB_DEV_BASE+0x0284)
    114. 

  114. #define U3D_RX8CSR2                               (SSUSB_DEV_BASE+0x0288)
    115. 

  115. #define U3D_RX8CSR3                               (SSUSB_DEV_BASE+0x028C)
    116. 

  116. #define U3D_RX9CSR0                               (SSUSB_DEV_BASE+0x0290)
    117. 

  117. #define U3D_RX9CSR1                               (SSUSB_DEV_BASE+0x0294)
    118. 

  118. #define U3D_RX9CSR2                               (SSUSB_DEV_BASE+0x0298)
    119. 

  119. #define U3D_RX9CSR3                               (SSUSB_DEV_BASE+0x029C)
    120. 

  120. #define U3D_RX10CSR0                              (SSUSB_DEV_BASE+0x02A0)
    121. 

  121. #define U3D_RX10CSR1                              (SSUSB_DEV_BASE+0x02A4)
    122. 

  122. #define U3D_RX10CSR2                              (SSUSB_DEV_BASE+0x02A8)
    123. 

  123. #define U3D_RX10CSR3                              (SSUSB_DEV_BASE+0x02AC)
    124. 

  124. #define U3D_RX11CSR0                              (SSUSB_DEV_BASE+0x02B0)
    125. 

  125. #define U3D_RX11CSR1                              (SSUSB_DEV_BASE+0x02B4)
    126. 

  126. #define U3D_RX11CSR2                              (SSUSB_DEV_BASE+0x02B8)
    127. 

  127. #define U3D_RX11CSR3                              (SSUSB_DEV_BASE+0x02BC)
    128. 

  128. #define U3D_RX12CSR0                              (SSUSB_DEV_BASE+0x02C0)
    129. 

  129. #define U3D_RX12CSR1                              (SSUSB_DEV_BASE+0x02C4)
    130. 

  130. #define U3D_RX12CSR2                              (SSUSB_DEV_BASE+0x02C8)
    131. 

  131. #define U3D_RX12CSR3                              (SSUSB_DEV_BASE+0x02CC)
    132. 

  132. #define U3D_RX13CSR0                              (SSUSB_DEV_BASE+0x02D0)
    133. 

  133. #define U3D_RX13CSR1                              (SSUSB_DEV_BASE+0x02D4)
    134. 

  134. #define U3D_RX13CSR2                              (SSUSB_DEV_BASE+0x02D8)
    135. 

  135. #define U3D_RX13CSR3                              (SSUSB_DEV_BASE+0x02DC)
    136. 

  136. #define U3D_RX14CSR0                              (SSUSB_DEV_BASE+0x02E0)
    137. 

  137. #define U3D_RX14CSR1                              (SSUSB_DEV_BASE+0x02E4)
    138. 

  138. #define U3D_RX14CSR2                              (SSUSB_DEV_BASE+0x02E8)
    139. 

  139. #define U3D_RX14CSR3                              (SSUSB_DEV_BASE+0x02EC)
    140. 

  140. #define U3D_RX15CSR0                              (SSUSB_DEV_BASE+0x02F0)
    141. 

  141. #define U3D_RX15CSR1                              (SSUSB_DEV_BASE+0x02F4)
    142. 

  142. #define U3D_RX15CSR2                              (SSUSB_DEV_BASE+0x02F8)
    143. 

  143. #define U3D_RX15CSR3                              (SSUSB_DEV_BASE+0x02FC)
    144. 

  144. #define U3D_FIFO0                                 (SSUSB_DEV_BASE+0x0300)
    145. 

  145. #define U3D_FIFO1                                 (SSUSB_DEV_BASE+0x0310)
    146. 

  146. #define U3D_FIFO2                                 (SSUSB_DEV_BASE+0x0320)
    147. 

  147. #define U3D_FIFO3                                 (SSUSB_DEV_BASE+0x0330)
    148. 

  148. #define U3D_FIFO4                                 (SSUSB_DEV_BASE+0x0340)
    149. 

  149. #define U3D_FIFO5                                 (SSUSB_DEV_BASE+0x0350)
    150. 

  150. #define U3D_FIFO6                                 (SSUSB_DEV_BASE+0x0360)
    151. 

  151. #define U3D_FIFO7                                 (SSUSB_DEV_BASE+0x0370)
    152. 

  152. #define U3D_FIFO8                                 (SSUSB_DEV_BASE+0x0380)
    153. 

  153. #define U3D_FIFO9                                 (SSUSB_DEV_BASE+0x0390)
    154. 

  154. #define U3D_FIFO10                                (SSUSB_DEV_BASE+0x03A0)
    155. 

  155. #define U3D_FIFO11                                (SSUSB_DEV_BASE+0x03B0)
    156. 

  156. #define U3D_FIFO12                                (SSUSB_DEV_BASE+0x03C0)
    157. 

  157. #define U3D_FIFO13                                (SSUSB_DEV_BASE+0x03D0)
    158. 

  158. #define U3D_FIFO14                                (SSUSB_DEV_BASE+0x03E0)
    159. 

  159. #define U3D_FIFO15                                (SSUSB_DEV_BASE+0x03F0)
    160. 

  160. #define U3D_QCR0                                  (SSUSB_DEV_BASE+0x0400)
    161. 

  161. #define U3D_QCR1                                  (SSUSB_DEV_BASE+0x0404)
    162. 

  162. #define U3D_QCR2                                  (SSUSB_DEV_BASE+0x0408)
    163. 

  163. #define U3D_QCR3                                  (SSUSB_DEV_BASE+0x040C)
    164. 

  164. #define U3D_QGCSR                                 (SSUSB_DEV_BASE+0x0410)
    165. 

  165. #define U3D_TXQCSR1                               (SSUSB_DEV_BASE+0x0510)
    166. 

  166. #define U3D_TXQSAR1                               (SSUSB_DEV_BASE+0x0514)
    167. 

  167. #define U3D_TXQCPR1                               (SSUSB_DEV_BASE+0x0518)
    168. 

  168. #define U3D_TXQCSR2                               (SSUSB_DEV_BASE+0x0520)
    169. 

  169. #define U3D_TXQSAR2                               (SSUSB_DEV_BASE+0x0524)
    170. 

  170. #define U3D_TXQCPR2                               (SSUSB_DEV_BASE+0x0528)
    171. 

  171. #define U3D_TXQCSR3                               (SSUSB_DEV_BASE+0x0530)
    172. 

  172. #define U3D_TXQSAR3                               (SSUSB_DEV_BASE+0x0534)
    173. 

  173. #define U3D_TXQCPR3                               (SSUSB_DEV_BASE+0x0538)
    174. 

  174. #define U3D_TXQCSR4                               (SSUSB_DEV_BASE+0x0540)
    175. 

  175. #define U3D_TXQSAR4                               (SSUSB_DEV_BASE+0x0544)
    176. 

  176. #define U3D_TXQCPR4                               (SSUSB_DEV_BASE+0x0548)
    177. 

  177. #define U3D_TXQCSR5                               (SSUSB_DEV_BASE+0x0550)
    178. 

  178. #define U3D_TXQSAR5                               (SSUSB_DEV_BASE+0x0554)
    179. 

  179. #define U3D_TXQCPR5                               (SSUSB_DEV_BASE+0x0558)
    180. 

  180. #define U3D_TXQCSR6                               (SSUSB_DEV_BASE+0x0560)
    181. 

  181. #define U3D_TXQSAR6                               (SSUSB_DEV_BASE+0x0564)
    182. 

  182. #define U3D_TXQCPR6                               (SSUSB_DEV_BASE+0x0568)
    183. 

  183. #define U3D_TXQCSR7                               (SSUSB_DEV_BASE+0x0570)
    184. 

  184. #define U3D_TXQSAR7                               (SSUSB_DEV_BASE+0x0574)
    185. 

  185. #define U3D_TXQCPR7                               (SSUSB_DEV_BASE+0x0578)
    186. 

  186. #define U3D_TXQCSR8                               (SSUSB_DEV_BASE+0x0580)
    187. 

  187. #define U3D_TXQSAR8                               (SSUSB_DEV_BASE+0x0584)
    188. 

  188. #define U3D_TXQCPR8                               (SSUSB_DEV_BASE+0x0588)
    189. 

  189. #define U3D_TXQCSR9                               (SSUSB_DEV_BASE+0x0590)
    190. 

  190. #define U3D_TXQSAR9                               (SSUSB_DEV_BASE+0x0594)
    191. 

  191. #define U3D_TXQCPR9                               (SSUSB_DEV_BASE+0x0598)
    192. 

  192. #define U3D_TXQCSR10                              (SSUSB_DEV_BASE+0x05A0)
    193. 

  193. #define U3D_TXQSAR10                              (SSUSB_DEV_BASE+0x05A4)
    194. 

  194. #define U3D_TXQCPR10                              (SSUSB_DEV_BASE+0x05A8)
    195. 

  195. #define U3D_TXQCSR11                              (SSUSB_DEV_BASE+0x05B0)
    196. 

  196. #define U3D_TXQSAR11                              (SSUSB_DEV_BASE+0x05B4)
    197. 

  197. #define U3D_TXQCPR11                              (SSUSB_DEV_BASE+0x05B8)
    198. 

  198. #define U3D_TXQCSR12                              (SSUSB_DEV_BASE+0x05C0)
    199. 

  199. #define U3D_TXQSAR12                              (SSUSB_DEV_BASE+0x05C4)
    200. 

  200. #define U3D_TXQCPR12                              (SSUSB_DEV_BASE+0x05C8)
    201. 

  201. #define U3D_TXQCSR13                              (SSUSB_DEV_BASE+0x05D0)
    202. 

  202. #define U3D_TXQSAR13                              (SSUSB_DEV_BASE+0x05D4)
    203. 

  203. #define U3D_TXQCPR13                              (SSUSB_DEV_BASE+0x05D8)
    204. 

  204. #define U3D_TXQCSR14                              (SSUSB_DEV_BASE+0x05E0)
    205. 

  205. #define U3D_TXQSAR14                              (SSUSB_DEV_BASE+0x05E4)
    206. 

  206. #define U3D_TXQCPR14                              (SSUSB_DEV_BASE+0x05E8)
    207. 

  207. #define U3D_TXQCSR15                              (SSUSB_DEV_BASE+0x05F0)
    208. 

  208. #define U3D_TXQSAR15                              (SSUSB_DEV_BASE+0x05F4)
    209. 

  209. #define U3D_TXQCPR15                              (SSUSB_DEV_BASE+0x05F8)
    210. 

  210. #define U3D_RXQCSR1                               (SSUSB_DEV_BASE+0x0610)
    211. 

  211. #define U3D_RXQSAR1                               (SSUSB_DEV_BASE+0x0614)
    212. 

  212. #define U3D_RXQCPR1                               (SSUSB_DEV_BASE+0x0618)
    213. 

  213. #define U3D_RXQLDPR1                              (SSUSB_DEV_BASE+0x061C)
    214. 

  214. #define U3D_RXQCSR2                               (SSUSB_DEV_BASE+0x0620)
    215. 

  215. #define U3D_RXQSAR2                               (SSUSB_DEV_BASE+0x0624)
    216. 

  216. #define U3D_RXQCPR2                               (SSUSB_DEV_BASE+0x0628)
    217. 

  217. #define U3D_RXQLDPR2                              (SSUSB_DEV_BASE+0x062C)
    218. 

  218. #define U3D_RXQCSR3                               (SSUSB_DEV_BASE+0x0630)
    219. 

  219. #define U3D_RXQSAR3                               (SSUSB_DEV_BASE+0x0634)
    220. 

  220. #define U3D_RXQCPR3                               (SSUSB_DEV_BASE+0x0638)
    221. 

  221. #define U3D_RXQLDPR3                              (SSUSB_DEV_BASE+0x063C)
    222. 

  222. #define U3D_RXQCSR4                               (SSUSB_DEV_BASE+0x0640)
    223. 

  223. #define U3D_RXQSAR4                               (SSUSB_DEV_BASE+0x0644)
    224. 

  224. #define U3D_RXQCPR4                               (SSUSB_DEV_BASE+0x0648)
    225. 

  225. #define U3D_RXQLDPR4                              (SSUSB_DEV_BASE+0x064C)
    226. 

  226. #define U3D_RXQCSR5                               (SSUSB_DEV_BASE+0x0650)
    227. 

  227. #define U3D_RXQSAR5                               (SSUSB_DEV_BASE+0x0654)
    228. 

  228. #define U3D_RXQCPR5                               (SSUSB_DEV_BASE+0x0658)
    229. 

  229. #define U3D_RXQLDPR5                              (SSUSB_DEV_BASE+0x065C)
    230. 

  230. #define U3D_RXQCSR6                               (SSUSB_DEV_BASE+0x0660)
    231. 

  231. #define U3D_RXQSAR6                               (SSUSB_DEV_BASE+0x0664)
    232. 

  232. #define U3D_RXQCPR6                               (SSUSB_DEV_BASE+0x0668)
    233. 

  233. #define U3D_RXQLDPR6                              (SSUSB_DEV_BASE+0x066C)
    234. 

  234. #define U3D_RXQCSR7                               (SSUSB_DEV_BASE+0x0670)
    235. 

  235. #define U3D_RXQSAR7                               (SSUSB_DEV_BASE+0x0674)
    236. 

  236. #define U3D_RXQCPR7                               (SSUSB_DEV_BASE+0x0678)
    237. 

  237. #define U3D_RXQLDPR7                              (SSUSB_DEV_BASE+0x067C)
    238. 

  238. #define U3D_RXQCSR8                               (SSUSB_DEV_BASE+0x0680)
    239. 

  239. #define U3D_RXQSAR8                               (SSUSB_DEV_BASE+0x0684)
    240. 

  240. #define U3D_RXQCPR8                               (SSUSB_DEV_BASE+0x0688)
    241. 

  241. #define U3D_RXQLDPR8                              (SSUSB_DEV_BASE+0x068C)
    242. 

  242. #define U3D_RXQCSR9                               (SSUSB_DEV_BASE+0x0690)
    243. 

  243. #define U3D_RXQSAR9                               (SSUSB_DEV_BASE+0x0694)
    244. 

  244. #define U3D_RXQCPR9                               (SSUSB_DEV_BASE+0x0698)
    245. 

  245. #define U3D_RXQLDPR9                              (SSUSB_DEV_BASE+0x069C)
    246. 

  246. #define U3D_RXQCSR10                              (SSUSB_DEV_BASE+0x06A0)
    247. 

  247. #define U3D_RXQSAR10                              (SSUSB_DEV_BASE+0x06A4)
    248. 

  248. #define U3D_RXQCPR10                              (SSUSB_DEV_BASE+0x06A8)
    249. 

  249. #define U3D_RXQLDPR10                             (SSUSB_DEV_BASE+0x06AC)
    250. 

  250. #define U3D_RXQCSR11                              (SSUSB_DEV_BASE+0x06B0)
    251. 

  251. #define U3D_RXQSAR11                              (SSUSB_DEV_BASE+0x06B4)
    252. 

  252. #define U3D_RXQCPR11                              (SSUSB_DEV_BASE+0x06B8)
    253. 

  253. #define U3D_RXQLDPR11                             (SSUSB_DEV_BASE+0x06BC)
    254. 

  254. #define U3D_RXQCSR12                              (SSUSB_DEV_BASE+0x06C0)
    255. 

  255. #define U3D_RXQSAR12                              (SSUSB_DEV_BASE+0x06C4)
    256. 

  256. #define U3D_RXQCPR12                              (SSUSB_DEV_BASE+0x06C8)
    257. 

  257. #define U3D_RXQLDPR12                             (SSUSB_DEV_BASE+0x06CC)
    258. 

  258. #define U3D_RXQCSR13                              (SSUSB_DEV_BASE+0x06D0)
    259. 

  259. #define U3D_RXQSAR13                              (SSUSB_DEV_BASE+0x06D4)
    260. 

  260. #define U3D_RXQCPR13                              (SSUSB_DEV_BASE+0x06D8)
    261. 

  261. #define U3D_RXQLDPR13                             (SSUSB_DEV_BASE+0x06DC)
    262. 

  262. #define U3D_RXQCSR14                              (SSUSB_DEV_BASE+0x06E0)
    263. 

  263. #define U3D_RXQSAR14                              (SSUSB_DEV_BASE+0x06E4)
    264. 

  264. #define U3D_RXQCPR14                              (SSUSB_DEV_BASE+0x06E8)
    265. 

  265. #define U3D_RXQLDPR14                             (SSUSB_DEV_BASE+0x06EC)
    266. 

  266. #define U3D_RXQCSR15                              (SSUSB_DEV_BASE+0x06F0)
    267. 

  267. #define U3D_RXQSAR15                              (SSUSB_DEV_BASE+0x06F4)
    268. 

  268. #define U3D_RXQCPR15                              (SSUSB_DEV_BASE+0x06F8)
    269. 

  269. #define U3D_RXQLDPR15                             (SSUSB_DEV_BASE+0x06FC)
    270. 

  270. #define U3D_QISAR0                                (SSUSB_DEV_BASE+0x0700)
    271. 

  271. #define U3D_QIER0                                 (SSUSB_DEV_BASE+0x0704)
    272. 

  272. #define U3D_QIESR0                                (SSUSB_DEV_BASE+0x0708)
    273. 

  273. #define U3D_QIECR0                                (SSUSB_DEV_BASE+0x070C)
    274. 

  274. #define U3D_QISAR1                                (SSUSB_DEV_BASE+0x0710)
    275. 

  275. #define U3D_QIER1                                 (SSUSB_DEV_BASE+0x0714)
    276. 

  276. #define U3D_QIESR1                                (SSUSB_DEV_BASE+0x0718)
    277. 

  277. #define U3D_QIECR1                                (SSUSB_DEV_BASE+0x071C)
    278. 

  278. #define U3D_QEMIR                                 (SSUSB_DEV_BASE+0x0740)
    279. 

  279. #define U3D_QEMIER                                (SSUSB_DEV_BASE+0x0744)
    280. 

  280. #define U3D_QEMIESR                               (SSUSB_DEV_BASE+0x0748)
    281. 

  281. #define U3D_QEMIECR                               (SSUSB_DEV_BASE+0x074C)
    282. 

  282. #define U3D_TQERRIR0                              (SSUSB_DEV_BASE+0x0780)
    283. 

  283. #define U3D_TQERRIER0                             (SSUSB_DEV_BASE+0x0784)
    284. 

  284. #define U3D_TQERRIESR0                            (SSUSB_DEV_BASE+0x0788)
    285. 

  285. #define U3D_TQERRIECR0                            (SSUSB_DEV_BASE+0x078C)
    286. 

  286. #define U3D_RQERRIR0                              (SSUSB_DEV_BASE+0x07C0)
    287. 

  287. #define U3D_RQERRIER0                             (SSUSB_DEV_BASE+0x07C4)
    288. 

  288. #define U3D_RQERRIESR0                            (SSUSB_DEV_BASE+0x07C8)
    289. 

  289. #define U3D_RQERRIECR0                            (SSUSB_DEV_BASE+0x07CC)
    290. 

  290. #define U3D_RQERRIR1                              (SSUSB_DEV_BASE+0x07D0)
    291. 

  291. #define U3D_RQERRIER1                             (SSUSB_DEV_BASE+0x07D4)
    292. 

  292. #define U3D_RQERRIESR1                            (SSUSB_DEV_BASE+0x07D8)
    293. 

  293. #define U3D_RQERRIECR1                            (SSUSB_DEV_BASE+0x07DC)
    294. 

  294. #define U3D_CAP_EP0FFSZ                           (SSUSB_DEV_BASE+0x0C04)
    295. 

  295. #define U3D_CAP_EPNTXFFSZ                         (SSUSB_DEV_BASE+0x0C08)
    296. 

  296. #define U3D_CAP_EPNRXFFSZ                         (SSUSB_DEV_BASE+0x0C0C)
    297. 

  297. #define U3D_CAP_EPINFO                            (SSUSB_DEV_BASE+0x0C10)
    298. 

  298. #define U3D_CAP_TX_SLOT1                          (SSUSB_DEV_BASE+0x0C20)
    299. 

  299. #define U3D_CAP_TX_SLOT2                          (SSUSB_DEV_BASE+0x0C24)
    300. 

  300. #define U3D_CAP_TX_SLOT3                          (SSUSB_DEV_BASE+0x0C28)
    301. 

  301. #define U3D_CAP_TX_SLOT4                          (SSUSB_DEV_BASE+0x0C2C)
    302. 

  302. #define U3D_CAP_RX_SLOT1                          (SSUSB_DEV_BASE+0x0C30)
    303. 

  303. #define U3D_CAP_RX_SLOT2                          (SSUSB_DEV_BASE+0x0C34)
    304. 

  304. #define U3D_CAP_RX_SLOT3                          (SSUSB_DEV_BASE+0x0C38)
    305. 

  305. #define U3D_CAP_RX_SLOT4                          (SSUSB_DEV_BASE+0x0C3C)
    306. 

  306. #define U3D_MISC_CTRL                             (SSUSB_DEV_BASE+0x0C84)
    307. 

  307. 

  308. /* SSUSB_DEV FIELD DEFINITION */
    309. 

  309. 

  310. /* U3D_LV1ISR */
    311. 

  311. #define EP_CTRL_INTR                              (0x1<<5)	/* 5:5 */
    312. 

  312. #define MAC2_INTR                                 (0x1<<4)	/* 4:4 */
    313. 

  313. #define DMA_INTR                                  (0x1<<3)	/* 3:3 */
    314. 

  314. #define MAC3_INTR                                 (0x1<<2)	/* 2:2 */
    315. 

  315. #define QMU_INTR                                  (0x1<<1)	/* 1:1 */
    316. 

  316. #define BMU_INTR                                  (0x1<<0)	/* 0:0 */
    317. 

  317. 

  318. /* U3D_LV1IER */
    319. 

  319. #define LV1IER                                    (0xffffffff<<0)	/* 31:0 */
    320. 

  320. 

  321. /* U3D_LV1IESR */
    322. 

  322. #define LV1IESR                                   (0xffffffff<<0)	/* 31:0 */
    323. 

  323. 

  324. /* U3D_LV1IECR */
    325. 

  325. #define LV1IECR                                   (0xffffffff<<0)	/* 31:0 */
    326. 

  326. 

  327. /* U3D_AXI_WR_DMA_CFG */
    328. 

  328. #define AXI_WR_ULTRA_NUM                          (0xff<<24)	/* 31:24 */
    329. 

  329. #define AXI_WR_PRE_ULTRA_NUM                      (0xff<<16)	/* 23:16 */
    330. 

  330. #define AXI_WR_ULTRA_EN                           (0x1<<0)	/* 0:0 */
    331. 

  331. 

  332. /* U3D_AXI_RD_DMA_CFG */
    333. 

  333. #define AXI_RD_ULTRA_NUM                          (0xff<<24)	/* 31:24 */
    334. 

  334. #define AXI_RD_PRE_ULTRA_NUM                      (0xff<<16)	/* 23:16 */
    335. 

  335. #define AXI_RD_ULTRA_EN                           (0x1<<0)	/* 0:0 */
    336. 

  336. 

  337. /* U3D_MAC_U1_EN_CTRL */
    338. 

  338. #define EXIT_BY_ERDY_DIS                          (0x1<<31)	/* 31:31 */
    339. 

  339. #define ACCEPT_BMU_RX_EMPTY_CHK                   (0x1<<20)	/* 20:20 */
    340. 

  340. #define ACCEPT_BMU_TX_EMPTY_CHK                   (0x1<<19)	/* 19:19 */
    341. 

  341. #define ACCEPT_RXQ_INACTIVE_CHK                   (0x1<<18)	/* 18:18 */
    342. 

  342. #define ACCEPT_TXQ_INACTIVE_CHK                   (0x1<<17)	/* 17:17 */
    343. 

  343. #define ACCEPT_EP0_INACTIVE_CHK                   (0x1<<16)	/* 16:16 */
    344. 

  344. #define REQUEST_BMU_RX_EMPTY_CHK                  (0x1<<4)	/* 4:4 */
    345. 

  345. #define REQUEST_BMU_TX_EMPTY_CHK                  (0x1<<3)	/* 3:3 */
    346. 

  346. #define REQUEST_RXQ_INACTIVE_CHK                  (0x1<<2)	/* 2:2 */
    347. 

  347. #define REQUEST_TXQ_INACTIVE_CHK                  (0x1<<1)	/* 1:1 */
    348. 

  348. #define REQUEST_EP0_INACTIVE_CHK                  (0x1<<0)	/* 0:0 */
    349. 

  349. 

  350. /* U3D_MAC_U2_EN_CTRL */
    351. 

  351. #define EXIT_BY_ERDY_DIS                          (0x1<<31)	/* 31:31 */
    352. 

  352. #define ACCEPT_BMU_RX_EMPTY_CHK                   (0x1<<20)	/* 20:20 */
    353. 

  353. #define ACCEPT_BMU_TX_EMPTY_CHK                   (0x1<<19)	/* 19:19 */
    354. 

  354. #define ACCEPT_RXQ_INACTIVE_CHK                   (0x1<<18)	/* 18:18 */
    355. 

  355. #define ACCEPT_TXQ_INACTIVE_CHK                   (0x1<<17)	/* 17:17 */
    356. 

  356. #define ACCEPT_EP0_INACTIVE_CHK                   (0x1<<16)	/* 16:16 */
    357. 

  357. #define REQUEST_BMU_RX_EMPTY_CHK                  (0x1<<4)	/* 4:4 */
    358. 

  358. #define REQUEST_BMU_TX_EMPTY_CHK                  (0x1<<3)	/* 3:3 */
    359. 

  359. #define REQUEST_RXQ_INACTIVE_CHK                  (0x1<<2)	/* 2:2 */
    360. 

  360. #define REQUEST_TXQ_INACTIVE_CHK                  (0x1<<1)	/* 1:1 */
    361. 

  361. #define REQUEST_EP0_INACTIVE_CHK                  (0x1<<0)	/* 0:0 */
    362. 

  362. 

  363. /* U3D_SRAM_DBG_CTRL */
    364. 

  364. #define EPNRX_SRAM_DEBUG_MODE                     (0x1<<2)	/* 2:2 */
    365. 

  365. #define EPNTX_SRAM_DEBUG_MODE                     (0x1<<1)	/* 1:1 */
    366. 

  366. #define EP0_SRAM_DEBUG_MODE                       (0x1<<0)	/* 0:0 */
    367. 

  367. 

  368. /* U3D_SRAM_DBG_CTRL_1 */
    369. 

  369. #define SRAM_DEBUG_FIFOSEGSIZE                    (0xf<<24)	/* 27:24 */
    370. 

  370. #define SRAM_DEBUG_SLOT                           (0x3f<<16)	/* 21:16 */
    371. 

  371. #define SRAM_DEBUG_DP_COUNT                       (0x7ff<<0)	/* 10:0 */
    372. 

  372. 

  373. /* U3D_RISC_SIZE */
    374. 

  374. #define RISC_SIZE                                 (0x3<<0)	/* 1:0 */
    375. 

  375. 

  376. /* U3D_WRBUF_ERR_STS */
    377. 

  377. #define RX_RDBUF_ERR_STS                          (0x7fff<<17)	/* 31:17 */
    378. 

  378. #define TX_WRBUF_ERR_STS                          (0x7fff<<1)	/* 15:1 */
    379. 

  379. 

  380. /* U3D_BUF_ERR_EN */
    381. 

  381. #define RX_RDBUF_ERR_EN                           (0x7fff<<17)	/* 31:17 */
    382. 

  382. #define TX_WRBUF_ERR_EN                           (0x7fff<<1)	/* 15:1 */
    383. 

  383. 

  384. /* U3D_EPISR */
    385. 

  385. #define EPRISR                                    (0x7fff<<17)	/* 31:17 */
    386. 

  386. #define SETUPENDISR                               (0x1<<16)	/* 16:16 */
    387. 

  387. #define EPTISR                                    (0x7fff<<1)	/* 15:1 */
    388. 

  388. #define EP0ISR                                    (0x1<<0)	/* 0:0 */
    389. 

  389. 

  390. /* U3D_EPIER */
    391. 

  391. #define EPRIER                                    (0x7fff<<17)	/* 31:17 */
    392. 

  392. #define SETUPENDIER                               (0x1<<16)	/* 16:16 */
    393. 

  393. #define EPTIER                                    (0x7fff<<1)	/* 15:1 */
    394. 

  394. #define EP0IER                                    (0x1<<0)	/* 0:0 */
    395. 

  395. 

  396. /* U3D_EPIESR */
    397. 

  397. #define EPRIESR                                   (0x7fff<<17)	/* 31:17 */
    398. 

  398. #define SETUPENDIESR                              (0x1<<16)	/* 16:16 */
    399. 

  399. #define EPTIESR                                   (0x7fff<<1)	/* 15:1 */
    400. 

  400. #define EP0IESR                                   (0x1<<0)	/* 0:0 */
    401. 

  401. 

  402. /* U3D_EPIECR */
    403. 

  403. #define EPRISR                                    (0x7fff<<17)	/* 31:17 */
    404. 

  404. #define SETUPENDIECR                              (0x1<<16)	/* 16:16 */
    405. 

  405. #define EPTIECR                                   (0x7fff<<1)	/* 15:1 */
    406. 

  406. #define EP0IECR                                   (0x1<<0)	/* 0:0 */
    407. 

  407. 

  408. /* U3D_DMAISR */
    409. 

  409. #define RXDMAISR                                  (0x1<<2)	/* 2:2 */
    410. 

  410. #define TXDMAISR                                  (0x1<<1)	/* 1:1 */
    411. 

  411. #define EP0DMAISR                                 (0x1<<0)	/* 0:0 */
    412. 

  412. 

  413. /* U3D_DMAIER */
    414. 

  414. #define RXDMAIER                                  (0x1<<2)	/* 2:2 */
    415. 

  415. #define TXDMAIER                                  (0x1<<1)	/* 1:1 */
    416. 

  416. #define EP0DMAER                                  (0x1<<0)	/* 0:0 */
    417. 

  417. 

  418. /* U3D_DMAIESR */
    419. 

  419. #define RXDMAIESR                                 (0x1<<2)	/* 2:2 */
    420. 

  420. #define TXDMAIESR                                 (0x1<<1)	/* 1:1 */
    421. 

  421. #define EP0DMAIESR                                (0x1<<0)	/* 0:0 */
    422. 

  422. 

  423. /* U3D_DMAIECR */
    424. 

  424. #define RXDMAIECR                                 (0x1<<2)	/* 2:2 */
    425. 

  425. #define TXDMAIECR                                 (0x1<<1)	/* 1:1 */
    426. 

  426. #define EP0DMAIECR                                (0x1<<0)	/* 0:0 */
    427. 

  427. 

  428. /* U3D_EP0DMACTRL */
    429. 

  429. #define FFSTRADDR0                                (0xffff<<16)	/* 31:16 */
    430. 

  430. #define ENDPNT                                    (0xf<<4)	/* 7:4 */
    431. 

  431. #define INTEN                                     (0x1<<3)	/* 3:3 */
    432. 

  432. #define DMA_DIR                                   (0x1<<1)	/* 1:1 */
    433. 

  433. #define DMA_EN                                    (0x1<<0)	/* 0:0 */
    434. 

  434. 

  435. /* U3D_EP0DMASTRADDR */
    436. 

  436. #define DMASTRADDR0                               (0xffffffff<<0)	/* 31:0 */
    437. 

  437. 

  438. /* U3D_EP0DMATFRCOUNT */
    439. 

  439. #define DMATFRCNT0                                (0x7ff<<0)	/* 10:0 */
    440. 

  440. 

  441. /* U3D_EP0DMARLCOUNT */
    442. 

  442. #define EP0_DMALIMITER                            (0x7<<28)	/* 30:28 */
    443. 

  443. #define DMA_FAKE                                  (0x1<<27)	/* 27:27 */
    444. 

  444. #define DMA_BURST                                 (0x3<<24)	/* 25:24 */
    445. 

  445. #define AXI_DMA_OUTSTAND_NUM                      (0xf<<20)	/* 23:20 */
    446. 

  446. #define AXI_DMA_COHERENCE                         (0x1<<19)	/* 19:19 */
    447. 

  447. #define AXI_DMA_IOMMU                             (0x1<<18)	/* 18:18 */
    448. 

  448. #define AXI_DMA_CACHEABLE                         (0x1<<17)	/* 17:17 */
    449. 

  449. #define AXI_DMA_ULTRA_EN                          (0x1<<16)	/* 16:16 */
    450. 

  450. #define AXI_DMA_ULTRA_NUM                         (0xff<<8)	/* 15:8 */
    451. 

  451. #define AXI_DMA_PRE_ULTRA_NUM                     (0xff<<0)	/* 7:0 */
    452. 

  452. 

  453. /* U3D_TXDMACTRL */
    454. 

  454. #define FFSTRADDR                                 (0xffff<<16)	/* 31:16 */
    455. 

  455. #define ENDPNT                                    (0xf<<4)	/* 7:4 */
    456. 

  456. #define INTEN                                     (0x1<<3)	/* 3:3 */
    457. 

  457. #define DMA_DIR                                   (0x1<<1)	/* 1:1 */
    458. 

  458. #define DMA_EN                                    (0x1<<0)	/* 0:0 */
    459. 

  459. 

  460. /* U3D_TXDMASTRADDR */
    461. 

  461. #define DMASTRADDR                                (0xffffffff<<0)	/* 31:0 */
    462. 

  462. 

  463. /* U3D_TXDMATRDCNT */
    464. 

  464. #define DMATFRCNT                                 (0x7ff<<0)	/* 10:0 */
    465. 

  465. 

  466. /* U3D_TXDMARLCOUNT */
    467. 

  467. #define DMALIMITER                                (0x7<<28)	/* 30:28 */
    468. 

  468. #define DMA_FAKE                                  (0x1<<27)	/* 27:27 */
    469. 

  469. #define DMA_BURST                                 (0x3<<24)	/* 25:24 */
    470. 

  470. #define AXI_DMA_OUTSTAND_NUM                      (0xf<<20)	/* 23:20 */
    471. 

  471. #define AXI_DMA_COHERENCE                         (0x1<<19)	/* 19:19 */
    472. 

  472. #define AXI_DMA_IOMMU                             (0x1<<18)	/* 18:18 */
    473. 

  473. #define AXI_DMA_CACHEABLE                         (0x1<<17)	/* 17:17 */
    474. 

  474. #define AXI_DMA_ULTRA_EN                          (0x1<<16)	/* 16:16 */
    475. 

  475. #define AXI_DMA_ULTRA_NUM                         (0xff<<8)	/* 15:8 */
    476. 

  476. #define AXI_DMA_PRE_ULTRA_NUM                     (0xff<<0)	/* 7:0 */
    477. 

  477. 

  478. /* U3D_RXDMACTRL */
    479. 

  479. #define FFSTRADDR                                 (0xffff<<16)	/* 31:16 */
    480. 

  480. #define ENDPNT                                    (0xf<<4)	/* 7:4 */
    481. 

  481. #define INTEN                                     (0x1<<3)	/* 3:3 */
    482. 

  482. #define DMA_DIR                                   (0x1<<1)	/* 1:1 */
    483. 

  483. #define DMA_EN                                    (0x1<<0)	/* 0:0 */
    484. 

  484. 

  485. /* U3D_RXDMASTRADDR */
    486. 

  486. #define DMASTRADDR                                (0xffffffff<<0)	/* 31:0 */
    487. 

  487. 

  488. /* U3D_RXDMATRDCNT */
    489. 

  489. #define DMATFRCNT                                 (0x7ff<<0)	/* 10:0 */
    490. 

  490. 

  491. /* U3D_RXDMARLCOUNT */
    492. 

  492. #define DMA_NON_BUF                               (0x1<<31)	/* 31:31 */
    493. 

  493. #define DMALIMITER                                (0x7<<28)	/* 30:28 */
    494. 

  494. #define DMA_FAKE                                  (0x1<<27)	/* 27:27 */
    495. 

  495. #define DMA_BURST                                 (0x3<<24)	/* 25:24 */
    496. 

  496. #define AXI_DMA_OUTSTAND_NUM                      (0xf<<20)	/* 23:20 */
    497. 

  497. #define AXI_DMA_COHERENCE                         (0x1<<19)	/* 19:19 */
    498. 

  498. #define AXI_DMA_IOMMU                             (0x1<<18)	/* 18:18 */
    499. 

  499. #define AXI_DMA_CACHEABLE                         (0x1<<17)	/* 17:17 */
    500. 

  500. #define AXI_DMA_ULTRA_EN                          (0x1<<16)	/* 16:16 */
    501. 

  501. #define AXI_DMA_ULTRA_NUM                         (0xff<<8)	/* 15:8 */
    502. 

  502. #define AXI_DMA_PRE_ULTRA_NUM                     (0xff<<0)	/* 7:0 */
    503. 

  503. 

  504. /* U3D_EP0CSR */
    505. 

  505. #define EP0_EP_RESET                              (0x1<<31)	/* 31:31 */
    506. 

  506. #define EP0_AUTOCLEAR                             (0x1<<30)	/* 30:30 */
    507. 

  507. #define EP0_AUTOSET                               (0x1<<29)	/* 29:29 */
    508. 

  508. #define EP0_DMAREQEN                              (0x1<<28)	/* 28:28 */
    509. 

  509. #define EP0_SENDSTALL                             (0x1<<25)	/* 25:25 */
    510. 

  510. #define EP0_FIFOFULL                              (0x1<<23)	/* 23:23 */
    511. 

  511. #define EP0_SENTSTALL                             (0x1<<22)	/* 22:22 */
    512. 

  512. #define EP0_DPHTX                                 (0x1<<20)	/* 20:20 */
    513. 

  513. #define EP0_DATAEND                               (0x1<<19)	/* 19:19 */
    514. 

  514. #define EP0_TXPKTRDY                              (0x1<<18)	/* 18:18 */
    515. 

  515. #define EP0_SETUPPKTRDY                           (0x1<<17)	/* 17:17 */
    516. 

  516. #define EP0_RXPKTRDY                              (0x1<<16)	/* 16:16 */
    517. 

  517. #define EP0_MAXPKTSZ0                             (0x3ff<<0)	/* 9:0 */
    518. 

  518. 

  519. /* U3D_RXCOUNT0 */
    520. 

  520. #define EP0_RX_COUNT                              (0x3ff<<0)	/* 9:0 */
    521. 

  521. 

  522. /* U3D_RESERVED */
    523. 

  523. 

  524. /* U3D_TX1CSR0 */
    525. 

  525. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    526. 

  526. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    527. 

  527. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    528. 

  528. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    529. 

  529. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    530. 

  530. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    531. 

  531. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    532. 

  532. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    533. 

  533. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    534. 

  534. 

  535. /* U3D_TX1CSR1 */
    536. 

  536. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    537. 

  537. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    538. 

  538. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    539. 

  539. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    540. 

  540. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    541. 

  541. 

  542. /* U3D_TX1CSR2 */
    543. 

  543. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    544. 

  544. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    545. 

  545. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    546. 

  546. 

  547. /* U3D_TX2CSR0 */
    548. 

  548. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    549. 

  549. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    550. 

  550. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    551. 

  551. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    552. 

  552. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    553. 

  553. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    554. 

  554. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    555. 

  555. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    556. 

  556. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    557. 

  557. 

  558. /* U3D_TX2CSR1 */
    559. 

  559. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    560. 

  560. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    561. 

  561. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    562. 

  562. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    563. 

  563. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    564. 

  564. 

  565. /* U3D_TX2CSR2 */
    566. 

  566. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    567. 

  567. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    568. 

  568. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    569. 

  569. 

  570. /* U3D_TX3CSR0 */
    571. 

  571. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    572. 

  572. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    573. 

  573. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    574. 

  574. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    575. 

  575. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    576. 

  576. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    577. 

  577. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    578. 

  578. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    579. 

  579. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    580. 

  580. 

  581. /* U3D_TX3CSR1 */
    582. 

  582. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    583. 

  583. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    584. 

  584. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    585. 

  585. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    586. 

  586. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    587. 

  587. 

  588. /* U3D_TX3CSR2 */
    589. 

  589. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    590. 

  590. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    591. 

  591. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    592. 

  592. 

  593. /* U3D_TX4CSR0 */
    594. 

  594. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    595. 

  595. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    596. 

  596. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    597. 

  597. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    598. 

  598. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    599. 

  599. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    600. 

  600. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    601. 

  601. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    602. 

  602. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    603. 

  603. 

  604. /* U3D_TX4CSR1 */
    605. 

  605. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    606. 

  606. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    607. 

  607. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    608. 

  608. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    609. 

  609. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    610. 

  610. 

  611. /* U3D_TX4CSR2 */
    612. 

  612. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    613. 

  613. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    614. 

  614. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    615. 

  615. 

  616. /* U3D_TX5CSR0 */
    617. 

  617. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    618. 

  618. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    619. 

  619. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    620. 

  620. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    621. 

  621. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    622. 

  622. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    623. 

  623. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    624. 

  624. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    625. 

  625. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    626. 

  626. 

  627. /* U3D_TX5CSR1 */
    628. 

  628. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    629. 

  629. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    630. 

  630. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    631. 

  631. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    632. 

  632. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    633. 

  633. 

  634. /* U3D_TX5CSR2 */
    635. 

  635. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    636. 

  636. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    637. 

  637. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    638. 

  638. 

  639. /* U3D_TX6CSR0 */
    640. 

  640. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    641. 

  641. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    642. 

  642. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    643. 

  643. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    644. 

  644. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    645. 

  645. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    646. 

  646. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    647. 

  647. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    648. 

  648. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    649. 

  649. 

  650. /* U3D_TX6CSR1 */
    651. 

  651. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    652. 

  652. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    653. 

  653. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    654. 

  654. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    655. 

  655. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    656. 

  656. 

  657. /* U3D_TX6CSR2 */
    658. 

  658. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    659. 

  659. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    660. 

  660. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    661. 

  661. 

  662. /* U3D_TX7CSR0 */
    663. 

  663. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    664. 

  664. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    665. 

  665. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    666. 

  666. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    667. 

  667. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    668. 

  668. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    669. 

  669. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    670. 

  670. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    671. 

  671. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    672. 

  672. 

  673. /* U3D_TX7CSR1 */
    674. 

  674. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    675. 

  675. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    676. 

  676. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    677. 

  677. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    678. 

  678. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    679. 

  679. 

  680. /* U3D_TX7CSR2 */
    681. 

  681. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    682. 

  682. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    683. 

  683. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    684. 

  684. 

  685. /* U3D_TX8CSR0 */
    686. 

  686. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    687. 

  687. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    688. 

  688. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    689. 

  689. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    690. 

  690. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    691. 

  691. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    692. 

  692. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    693. 

  693. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    694. 

  694. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    695. 

  695. 

  696. /* U3D_TX8CSR1 */
    697. 

  697. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    698. 

  698. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    699. 

  699. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    700. 

  700. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    701. 

  701. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    702. 

  702. 

  703. /* U3D_TX8CSR2 */
    704. 

  704. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    705. 

  705. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    706. 

  706. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    707. 

  707. 

  708. /* U3D_TX9CSR0 */
    709. 

  709. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    710. 

  710. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    711. 

  711. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    712. 

  712. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    713. 

  713. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    714. 

  714. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    715. 

  715. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    716. 

  716. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    717. 

  717. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    718. 

  718. 

  719. /* U3D_TX9CSR1 */
    720. 

  720. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    721. 

  721. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    722. 

  722. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    723. 

  723. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    724. 

  724. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    725. 

  725. 

  726. /* U3D_TX9CSR2 */
    727. 

  727. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    728. 

  728. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    729. 

  729. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    730. 

  730. 

  731. /* U3D_TX10CSR0 */
    732. 

  732. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    733. 

  733. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    734. 

  734. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    735. 

  735. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    736. 

  736. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    737. 

  737. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    738. 

  738. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    739. 

  739. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    740. 

  740. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    741. 

  741. 

  742. /* U3D_TX10CSR1 */
    743. 

  743. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    744. 

  744. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    745. 

  745. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    746. 

  746. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    747. 

  747. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    748. 

  748. 

  749. /* U3D_TX10CSR2 */
    750. 

  750. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    751. 

  751. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    752. 

  752. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    753. 

  753. 

  754. /* U3D_TX11CSR0 */
    755. 

  755. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    756. 

  756. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    757. 

  757. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    758. 

  758. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    759. 

  759. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    760. 

  760. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    761. 

  761. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    762. 

  762. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    763. 

  763. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    764. 

  764. 

  765. /* U3D_TX11CSR1 */
    766. 

  766. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    767. 

  767. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    768. 

  768. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    769. 

  769. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    770. 

  770. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    771. 

  771. 

  772. /* U3D_TX11CSR2 */
    773. 

  773. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    774. 

  774. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    775. 

  775. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    776. 

  776. 

  777. /* U3D_TX12CSR0 */
    778. 

  778. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    779. 

  779. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    780. 

  780. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    781. 

  781. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    782. 

  782. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    783. 

  783. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    784. 

  784. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    785. 

  785. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    786. 

  786. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    787. 

  787. 

  788. /* U3D_TX12CSR1 */
    789. 

  789. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    790. 

  790. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    791. 

  791. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    792. 

  792. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    793. 

  793. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    794. 

  794. 

  795. /* U3D_TX12CSR2 */
    796. 

  796. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    797. 

  797. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    798. 

  798. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    799. 

  799. 

  800. /* U3D_TX13CSR0 */
    801. 

  801. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    802. 

  802. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    803. 

  803. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    804. 

  804. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    805. 

  805. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    806. 

  806. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    807. 

  807. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    808. 

  808. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    809. 

  809. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    810. 

  810. 

  811. /* U3D_TX13CSR1 */
    812. 

  812. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    813. 

  813. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    814. 

  814. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    815. 

  815. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    816. 

  816. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    817. 

  817. 

  818. /* U3D_TX13CSR2 */
    819. 

  819. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    820. 

  820. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    821. 

  821. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    822. 

  822. 

  823. /* U3D_TX14CSR0 */
    824. 

  824. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    825. 

  825. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    826. 

  826. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    827. 

  827. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    828. 

  828. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    829. 

  829. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    830. 

  830. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    831. 

  831. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    832. 

  832. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    833. 

  833. 

  834. /* U3D_TX14CSR1 */
    835. 

  835. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    836. 

  836. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    837. 

  837. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    838. 

  838. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    839. 

  839. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    840. 

  840. 

  841. /* U3D_TX14CSR2 */
    842. 

  842. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    843. 

  843. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    844. 

  844. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    845. 

  845. 

  846. /* U3D_TX15CSR0 */
    847. 

  847. #define TX_EP_RESET                               (0x1<<31)	/* 31:31 */
    848. 

  848. #define TX_AUTOSET                                (0x1<<30)	/* 30:30 */
    849. 

  849. #define TX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    850. 

  850. #define TX_FIFOFULL                               (0x1<<25)	/* 25:25 */
    851. 

  851. #define TX_FIFOEMPTY                              (0x1<<24)	/* 24:24 */
    852. 

  852. #define TX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    853. 

  853. #define TX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    854. 

  854. #define TX_TXPKTRDY                               (0x1<<16)	/* 16:16 */
    855. 

  855. #define TX_TXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    856. 

  856. 

  857. /* U3D_TX15CSR1 */
    858. 

  858. #define TX_MULT                                   (0x3<<22)	/* 23:22 */
    859. 

  859. #define TX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    860. 

  860. #define TX_SLOT                                   (0x3f<<8)	/* 13:8 */
    861. 

  861. #define TXTYPE                                    (0x3<<4)	/* 5:4 */
    862. 

  862. #define SS_TX_BURST                               (0xf<<0)	/* 3:0 */
    863. 

  863. 

  864. /* U3D_TX15CSR2 */
    865. 

  865. #define TXBINTERVAL                               (0xff<<24)	/* 31:24 */
    866. 

  866. #define TXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    867. 

  867. #define TXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    868. 

  868. 

  869. /* U3D_RX1CSR0 */
    870. 

  870. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    871. 

  871. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    872. 

  872. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    873. 

  873. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    874. 

  874. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    875. 

  875. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    876. 

  876. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    877. 

  877. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    878. 

  878. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    879. 

  879. 

  880. /* U3D_RX1CSR1 */
    881. 

  881. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    882. 

  882. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    883. 

  883. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    884. 

  884. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    885. 

  885. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    886. 

  886. 

  887. /* U3D_RX1CSR2 */
    888. 

  888. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    889. 

  889. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    890. 

  890. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    891. 

  891. 

  892. /* U3D_RX1CSR3 */
    893. 

  893. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    894. 

  894. 

  895. /* U3D_RX2CSR0 */
    896. 

  896. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    897. 

  897. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    898. 

  898. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    899. 

  899. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    900. 

  900. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    901. 

  901. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    902. 

  902. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    903. 

  903. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    904. 

  904. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    905. 

  905. 

  906. /* U3D_RX2CSR1 */
    907. 

  907. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    908. 

  908. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    909. 

  909. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    910. 

  910. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    911. 

  911. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    912. 

  912. 

  913. /* U3D_RX2CSR2 */
    914. 

  914. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    915. 

  915. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    916. 

  916. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    917. 

  917. 

  918. /* U3D_RX2CSR3 */
    919. 

  919. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    920. 

  920. 

  921. /* U3D_RX3CSR0 */
    922. 

  922. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    923. 

  923. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    924. 

  924. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    925. 

  925. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    926. 

  926. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    927. 

  927. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    928. 

  928. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    929. 

  929. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    930. 

  930. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    931. 

  931. 

  932. /* U3D_RX3CSR1 */
    933. 

  933. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    934. 

  934. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    935. 

  935. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    936. 

  936. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    937. 

  937. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    938. 

  938. 

  939. /* U3D_RX3CSR2 */
    940. 

  940. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    941. 

  941. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    942. 

  942. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    943. 

  943. 

  944. /* U3D_RX3CSR3 */
    945. 

  945. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    946. 

  946. 

  947. /* U3D_RX4CSR0 */
    948. 

  948. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    949. 

  949. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    950. 

  950. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    951. 

  951. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    952. 

  952. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    953. 

  953. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    954. 

  954. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    955. 

  955. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    956. 

  956. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    957. 

  957. 

  958. /* U3D_RX4CSR1 */
    959. 

  959. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    960. 

  960. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    961. 

  961. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    962. 

  962. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    963. 

  963. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    964. 

  964. 

  965. /* U3D_RX4CSR2 */
    966. 

  966. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    967. 

  967. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    968. 

  968. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    969. 

  969. 

  970. /* U3D_RX4CSR3 */
    971. 

  971. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    972. 

  972. 

  973. /* U3D_RX5CSR0 */
    974. 

  974. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    975. 

  975. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    976. 

  976. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    977. 

  977. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    978. 

  978. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    979. 

  979. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    980. 

  980. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    981. 

  981. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    982. 

  982. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    983. 

  983. 

  984. /* U3D_RX5CSR1 */
    985. 

  985. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    986. 

  986. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    987. 

  987. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    988. 

  988. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    989. 

  989. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    990. 

  990. 

  991. /* U3D_RX5CSR2 */
    992. 

  992. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    993. 

  993. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    994. 

  994. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    995. 

  995. 

  996. /* U3D_RX5CSR3 */
    997. 

  997. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    998. 

  998. 

  999. /* U3D_RX6CSR0 */
    1000. 

  1000. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1001. 

  1001. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1002. 

  1002. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1003. 

  1003. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1004. 

  1004. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1005. 

  1005. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1006. 

  1006. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1007. 

  1007. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1008. 

  1008. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1009. 

  1009. 

  1010. /* U3D_RX6CSR1 */
    1011. 

  1011. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1012. 

  1012. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1013. 

  1013. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1014. 

  1014. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1015. 

  1015. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1016. 

  1016. 

  1017. /* U3D_RX6CSR2 */
    1018. 

  1018. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1019. 

  1019. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1020. 

  1020. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1021. 

  1021. 

  1022. /* U3D_RX6CSR3 */
    1023. 

  1023. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1024. 

  1024. 

  1025. /* U3D_RX7CSR0 */
    1026. 

  1026. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1027. 

  1027. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1028. 

  1028. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1029. 

  1029. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1030. 

  1030. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1031. 

  1031. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1032. 

  1032. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1033. 

  1033. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1034. 

  1034. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1035. 

  1035. 

  1036. /* U3D_RX7CSR1 */
    1037. 

  1037. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1038. 

  1038. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1039. 

  1039. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1040. 

  1040. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1041. 

  1041. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1042. 

  1042. 

  1043. /* U3D_RX7CSR2 */
    1044. 

  1044. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1045. 

  1045. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1046. 

  1046. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1047. 

  1047. 

  1048. /* U3D_RX7CSR3 */
    1049. 

  1049. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1050. 

  1050. 

  1051. /* U3D_RX8CSR0 */
    1052. 

  1052. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1053. 

  1053. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1054. 

  1054. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1055. 

  1055. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1056. 

  1056. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1057. 

  1057. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1058. 

  1058. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1059. 

  1059. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1060. 

  1060. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1061. 

  1061. 

  1062. /* U3D_RX8CSR1 */
    1063. 

  1063. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1064. 

  1064. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1065. 

  1065. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1066. 

  1066. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1067. 

  1067. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1068. 

  1068. 

  1069. /* U3D_RX8CSR2 */
    1070. 

  1070. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1071. 

  1071. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1072. 

  1072. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1073. 

  1073. 

  1074. /* U3D_RX8CSR3 */
    1075. 

  1075. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1076. 

  1076. 

  1077. /* U3D_RX9CSR0 */
    1078. 

  1078. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1079. 

  1079. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1080. 

  1080. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1081. 

  1081. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1082. 

  1082. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1083. 

  1083. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1084. 

  1084. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1085. 

  1085. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1086. 

  1086. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1087. 

  1087. 

  1088. /* U3D_RX9CSR1 */
    1089. 

  1089. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1090. 

  1090. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1091. 

  1091. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1092. 

  1092. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1093. 

  1093. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1094. 

  1094. 

  1095. /* U3D_RX9CSR2 */
    1096. 

  1096. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1097. 

  1097. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1098. 

  1098. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1099. 

  1099. 

  1100. /* U3D_RX9CSR3 */
    1101. 

  1101. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1102. 

  1102. 

  1103. /* U3D_RX10CSR0 */
    1104. 

  1104. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1105. 

  1105. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1106. 

  1106. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1107. 

  1107. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1108. 

  1108. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1109. 

  1109. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1110. 

  1110. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1111. 

  1111. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1112. 

  1112. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1113. 

  1113. 

  1114. /* U3D_RX10CSR1 */
    1115. 

  1115. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1116. 

  1116. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1117. 

  1117. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1118. 

  1118. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1119. 

  1119. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1120. 

  1120. 

  1121. /* U3D_RX10CSR2 */
    1122. 

  1122. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1123. 

  1123. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1124. 

  1124. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1125. 

  1125. 

  1126. /* U3D_RX10CSR3 */
    1127. 

  1127. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1128. 

  1128. 

  1129. /* U3D_RX11CSR0 */
    1130. 

  1130. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1131. 

  1131. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1132. 

  1132. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1133. 

  1133. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1134. 

  1134. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1135. 

  1135. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1136. 

  1136. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1137. 

  1137. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1138. 

  1138. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1139. 

  1139. 

  1140. /* U3D_RX11CSR1 */
    1141. 

  1141. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1142. 

  1142. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1143. 

  1143. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1144. 

  1144. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1145. 

  1145. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1146. 

  1146. 

  1147. /* U3D_RX11CSR2 */
    1148. 

  1148. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1149. 

  1149. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1150. 

  1150. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1151. 

  1151. 

  1152. /* U3D_RX11CSR3 */
    1153. 

  1153. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1154. 

  1154. 

  1155. /* U3D_RX12CSR0 */
    1156. 

  1156. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1157. 

  1157. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1158. 

  1158. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1159. 

  1159. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1160. 

  1160. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1161. 

  1161. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1162. 

  1162. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1163. 

  1163. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1164. 

  1164. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1165. 

  1165. 

  1166. /* U3D_RX12CSR1 */
    1167. 

  1167. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1168. 

  1168. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1169. 

  1169. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1170. 

  1170. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1171. 

  1171. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1172. 

  1172. 

  1173. /* U3D_RX12CSR2 */
    1174. 

  1174. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1175. 

  1175. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1176. 

  1176. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1177. 

  1177. 

  1178. /* U3D_RX12CSR3 */
    1179. 

  1179. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1180. 

  1180. 

  1181. /* U3D_RX13CSR0 */
    1182. 

  1182. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1183. 

  1183. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1184. 

  1184. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1185. 

  1185. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1186. 

  1186. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1187. 

  1187. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1188. 

  1188. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1189. 

  1189. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1190. 

  1190. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1191. 

  1191. 

  1192. /* U3D_RX13CSR1 */
    1193. 

  1193. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1194. 

  1194. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1195. 

  1195. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1196. 

  1196. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1197. 

  1197. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1198. 

  1198. 

  1199. /* U3D_RX13CSR2 */
    1200. 

  1200. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1201. 

  1201. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1202. 

  1202. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1203. 

  1203. 

  1204. /* U3D_RX13CSR3 */
    1205. 

  1205. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1206. 

  1206. 

  1207. /* U3D_RX14CSR0 */
    1208. 

  1208. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1209. 

  1209. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1210. 

  1210. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1211. 

  1211. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1212. 

  1212. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1213. 

  1213. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1214. 

  1214. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1215. 

  1215. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1216. 

  1216. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1217. 

  1217. 

  1218. /* U3D_RX14CSR1 */
    1219. 

  1219. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1220. 

  1220. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1221. 

  1221. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1222. 

  1222. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1223. 

  1223. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1224. 

  1224. 

  1225. /* U3D_RX14CSR2 */
    1226. 

  1226. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1227. 

  1227. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1228. 

  1228. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1229. 

  1229. 

  1230. /* U3D_RX14CSR3 */
    1231. 

  1231. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1232. 

  1232. 

  1233. /* U3D_RX15CSR0 */
    1234. 

  1234. #define RX_EP_RESET                               (0x1<<31)	/* 31:31 */
    1235. 

  1235. #define RX_AUTOCLEAR                              (0x1<<30)	/* 30:30 */
    1236. 

  1236. #define RX_DMAREQEN                               (0x1<<29)	/* 29:29 */
    1237. 

  1237. #define RX_SENTSTALL                              (0x1<<22)	/* 22:22 */
    1238. 

  1238. #define RX_SENDSTALL                              (0x1<<21)	/* 21:21 */
    1239. 

  1239. #define RX_FIFOFULL                               (0x1<<18)	/* 18:18 */
    1240. 

  1240. #define RX_FIFOEMPTY                              (0x1<<17)	/* 17:17 */
    1241. 

  1241. #define RX_RXPKTRDY                               (0x1<<16)	/* 16:16 */
    1242. 

  1242. #define RX_RXMAXPKTSZ                             (0x7ff<<0)	/* 10:0 */
    1243. 

  1243. 

  1244. /* U3D_RX15CSR1 */
    1245. 

  1245. #define RX_MULT                                   (0x3<<22)	/* 23:22 */
    1246. 

  1246. #define RX_MAX_PKT                                (0x3f<<16)	/* 21:16 */
    1247. 

  1247. #define RX_SLOT                                   (0x3f<<8)	/* 13:8 */
    1248. 

  1248. #define RX_TYPE                                   (0x3<<4)	/* 5:4 */
    1249. 

  1249. #define SS_RX_BURST                               (0xf<<0)	/* 3:0 */
    1250. 

  1250. 

  1251. /* U3D_RX15CSR2 */
    1252. 

  1252. #define RXBINTERVAL                               (0xff<<24)	/* 31:24 */
    1253. 

  1253. #define RXFIFOSEGSIZE                             (0xf<<16)	/* 19:16 */
    1254. 

  1254. #define RXFIFOADDR                                (0x1fff<<0)	/* 12:0 */
    1255. 

  1255. 

  1256. /* U3D_RX15CSR3 */
    1257. 

  1257. #define EP_RX_COUNT                               (0x7ff<<16)	/* 26:16 */
    1258. 

  1258. 

  1259. /* U3D_FIFO0 */
    1260. 

  1260. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1261. 

  1261. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1262. 

  1262. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1263. 

  1263. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1264. 

  1264. 

  1265. /* U3D_FIFO1 */
    1266. 

  1266. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1267. 

  1267. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1268. 

  1268. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1269. 

  1269. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1270. 

  1270. 

  1271. /* U3D_FIFO2 */
    1272. 

  1272. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1273. 

  1273. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1274. 

  1274. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1275. 

  1275. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1276. 

  1276. 

  1277. /* U3D_FIFO3 */
    1278. 

  1278. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1279. 

  1279. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1280. 

  1280. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1281. 

  1281. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1282. 

  1282. 

  1283. /* U3D_FIFO4 */
    1284. 

  1284. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1285. 

  1285. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1286. 

  1286. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1287. 

  1287. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1288. 

  1288. 

  1289. /* U3D_FIFO5 */
    1290. 

  1290. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1291. 

  1291. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1292. 

  1292. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1293. 

  1293. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1294. 

  1294. 

  1295. /* U3D_FIFO6 */
    1296. 

  1296. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1297. 

  1297. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1298. 

  1298. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1299. 

  1299. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1300. 

  1300. 

  1301. /* U3D_FIFO7 */
    1302. 

  1302. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1303. 

  1303. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1304. 

  1304. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1305. 

  1305. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1306. 

  1306. 

  1307. /* U3D_FIFO8 */
    1308. 

  1308. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1309. 

  1309. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1310. 

  1310. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1311. 

  1311. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1312. 

  1312. 

  1313. /* U3D_FIFO9 */
    1314. 

  1314. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1315. 

  1315. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1316. 

  1316. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1317. 

  1317. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1318. 

  1318. 

  1319. /* U3D_FIFO10 */
    1320. 

  1320. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1321. 

  1321. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1322. 

  1322. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1323. 

  1323. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1324. 

  1324. 

  1325. /* U3D_FIFO11 */
    1326. 

  1326. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1327. 

  1327. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1328. 

  1328. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1329. 

  1329. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1330. 

  1330. 

  1331. /* U3D_FIFO12 */
    1332. 

  1332. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1333. 

  1333. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1334. 

  1334. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1335. 

  1335. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1336. 

  1336. 

  1337. /* U3D_FIFO13 */
    1338. 

  1338. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1339. 

  1339. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1340. 

  1340. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1341. 

  1341. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1342. 

  1342. 

  1343. /* U3D_FIFO14 */
    1344. 

  1344. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1345. 

  1345. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1346. 

  1346. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1347. 

  1347. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1348. 

  1348. 

  1349. /* U3D_FIFO15 */
    1350. 

  1350. #define BYTE3                                     (0xff<<24)	/* 31:24 */
    1351. 

  1351. #define BYTE2                                     (0xff<<16)	/* 23:16 */
    1352. 

  1352. #define BYTE1                                     (0xff<<8)	/* 15:8 */
    1353. 

  1353. #define BYTE0                                     (0xff<<0)	/* 7:0 */
    1354. 

  1354. 

  1355. /* U3D_QCR0 */
    1356. 

  1356. #define RXQ_CS_EN                                 (0x7fff<<17)	/* 31:17 */
    1357. 

  1357. #define TXQ_CS_EN                                 (0x7fff<<1)	/* 15:1 */
    1358. 

  1358. #define CS16B_EN                                  (0x1<<0)	/* 0:0 */
    1359. 

  1359. 

  1360. /* U3D_QCR1 */
    1361. 

  1361. #define CFG_TX_ZLP_GPD                            (0x7fff<<1)	/* 15:1 */
    1362. 

  1362. 

  1363. /* U3D_QCR2 */
    1364. 

  1364. #define CFG_TX_ZLP                                (0x7fff<<1)	/* 15:1 */
    1365. 

  1365. 

  1366. /* U3D_QCR3 */
    1367. 

  1367. #define CFG_RX_COZ                                (0x7fff<<17)	/* 31:17 */
    1368. 

  1368. #define CFG_RX_ZLP                                (0x7fff<<1)	/* 15:1 */
    1369. 

  1369. 

  1370. /* U3D_QGCSR */
    1371. 

  1371. #define RXQ_EN                                    (0x7fff<<17)	/* 31:17 */
    1372. 

  1372. #define TXQ_EN                                    (0x7fff<<1)	/* 15:1 */
    1373. 

  1373. 

  1374. /* U3D_TXQCSR1 */
    1375. 

  1375. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1376. 

  1376. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1377. 

  1377. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1378. 

  1378. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1379. 

  1379. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1380. 

  1380. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1381. 

  1381. 

  1382. /* U3D_TXQSAR1 */
    1383. 

  1383. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1384. 

  1384. 

  1385. /* U3D_TXQCPR1 */
    1386. 

  1386. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1387. 

  1387. 

  1388. /* U3D_TXQCSR2 */
    1389. 

  1389. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1390. 

  1390. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1391. 

  1391. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1392. 

  1392. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1393. 

  1393. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1394. 

  1394. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1395. 

  1395. 

  1396. /* U3D_TXQSAR2 */
    1397. 

  1397. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1398. 

  1398. 

  1399. /* U3D_TXQCPR2 */
    1400. 

  1400. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1401. 

  1401. 

  1402. /* U3D_TXQCSR3 */
    1403. 

  1403. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1404. 

  1404. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1405. 

  1405. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1406. 

  1406. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1407. 

  1407. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1408. 

  1408. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1409. 

  1409. 

  1410. /* U3D_TXQSAR3 */
    1411. 

  1411. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1412. 

  1412. 

  1413. /* U3D_TXQCPR3 */
    1414. 

  1414. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1415. 

  1415. 

  1416. /* U3D_TXQCSR4 */
    1417. 

  1417. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1418. 

  1418. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1419. 

  1419. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1420. 

  1420. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1421. 

  1421. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1422. 

  1422. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1423. 

  1423. 

  1424. /* U3D_TXQSAR4 */
    1425. 

  1425. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1426. 

  1426. 

  1427. /* U3D_TXQCPR4 */
    1428. 

  1428. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1429. 

  1429. 

  1430. /* U3D_TXQCSR5 */
    1431. 

  1431. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1432. 

  1432. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1433. 

  1433. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1434. 

  1434. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1435. 

  1435. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1436. 

  1436. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1437. 

  1437. 

  1438. /* U3D_TXQSAR5 */
    1439. 

  1439. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1440. 

  1440. 

  1441. /* U3D_TXQCPR5 */
    1442. 

  1442. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1443. 

  1443. 

  1444. /* U3D_TXQCSR6 */
    1445. 

  1445. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1446. 

  1446. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1447. 

  1447. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1448. 

  1448. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1449. 

  1449. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1450. 

  1450. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1451. 

  1451. 

  1452. /* U3D_TXQSAR6 */
    1453. 

  1453. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1454. 

  1454. 

  1455. /* U3D_TXQCPR6 */
    1456. 

  1456. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1457. 

  1457. 

  1458. /* U3D_TXQCSR7 */
    1459. 

  1459. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1460. 

  1460. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1461. 

  1461. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1462. 

  1462. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1463. 

  1463. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1464. 

  1464. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1465. 

  1465. 

  1466. /* U3D_TXQSAR7 */
    1467. 

  1467. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1468. 

  1468. 

  1469. /* U3D_TXQCPR7 */
    1470. 

  1470. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1471. 

  1471. 

  1472. /* U3D_TXQCSR8 */
    1473. 

  1473. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1474. 

  1474. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1475. 

  1475. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1476. 

  1476. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1477. 

  1477. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1478. 

  1478. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1479. 

  1479. 

  1480. /* U3D_TXQSAR8 */
    1481. 

  1481. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1482. 

  1482. 

  1483. /* U3D_TXQCPR8 */
    1484. 

  1484. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1485. 

  1485. 

  1486. /* U3D_TXQCSR9 */
    1487. 

  1487. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1488. 

  1488. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1489. 

  1489. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1490. 

  1490. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1491. 

  1491. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1492. 

  1492. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1493. 

  1493. 

  1494. /* U3D_TXQSAR9 */
    1495. 

  1495. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1496. 

  1496. 

  1497. /* U3D_TXQCPR9 */
    1498. 

  1498. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1499. 

  1499. 

  1500. /* U3D_TXQCSR10 */
    1501. 

  1501. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1502. 

  1502. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1503. 

  1503. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1504. 

  1504. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1505. 

  1505. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1506. 

  1506. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1507. 

  1507. 

  1508. /* U3D_TXQSAR10 */
    1509. 

  1509. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1510. 

  1510. 

  1511. /* U3D_TXQCPR10 */
    1512. 

  1512. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1513. 

  1513. 

  1514. /* U3D_TXQCSR11 */
    1515. 

  1515. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1516. 

  1516. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1517. 

  1517. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1518. 

  1518. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1519. 

  1519. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1520. 

  1520. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1521. 

  1521. 

  1522. /* U3D_TXQSAR11 */
    1523. 

  1523. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1524. 

  1524. 

  1525. /* U3D_TXQCPR11 */
    1526. 

  1526. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1527. 

  1527. 

  1528. /* U3D_TXQCSR12 */
    1529. 

  1529. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1530. 

  1530. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1531. 

  1531. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1532. 

  1532. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1533. 

  1533. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1534. 

  1534. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1535. 

  1535. 

  1536. /* U3D_TXQSAR12 */
    1537. 

  1537. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1538. 

  1538. 

  1539. /* U3D_TXQCPR12 */
    1540. 

  1540. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1541. 

  1541. 

  1542. /* U3D_TXQCSR13 */
    1543. 

  1543. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1544. 

  1544. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1545. 

  1545. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1546. 

  1546. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1547. 

  1547. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1548. 

  1548. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1549. 

  1549. 

  1550. /* U3D_TXQSAR13 */
    1551. 

  1551. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1552. 

  1552. 

  1553. /* U3D_TXQCPR13 */
    1554. 

  1554. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1555. 

  1555. 

  1556. /* U3D_TXQCSR14 */
    1557. 

  1557. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1558. 

  1558. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1559. 

  1559. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1560. 

  1560. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1561. 

  1561. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1562. 

  1562. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1563. 

  1563. 

  1564. /* U3D_TXQSAR14 */
    1565. 

  1565. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1566. 

  1566. 

  1567. /* U3D_TXQCPR14 */
    1568. 

  1568. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1569. 

  1569. 

  1570. /* U3D_TXQCSR15 */
    1571. 

  1571. #define TXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1572. 

  1572. #define TXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1573. 

  1573. #define TXQ_EPQ_STATE                             (0xf<<8)	/* 11:8 */
    1574. 

  1574. #define TXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1575. 

  1575. #define TXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1576. 

  1576. #define TXQ_START                                 (0x1<<0)	/* 0:0 */
    1577. 

  1577. 

  1578. /* U3D_TXQSAR15 */
    1579. 

  1579. #define TXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1580. 

  1580. 

  1581. /* U3D_TXQCPR15 */
    1582. 

  1582. #define TXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1583. 

  1583. 

  1584. /* U3D_RXQCSR1 */
    1585. 

  1585. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1586. 

  1586. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1587. 

  1587. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1588. 

  1588. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1589. 

  1589. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1590. 

  1590. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1591. 

  1591. 

  1592. /* U3D_RXQSAR1 */
    1593. 

  1593. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1594. 

  1594. 

  1595. /* U3D_RXQCPR1 */
    1596. 

  1596. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1597. 

  1597. 

  1598. /* U3D_RXQLDPR1 */
    1599. 

  1599. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1600. 

  1600. 

  1601. /* U3D_RXQCSR2 */
    1602. 

  1602. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1603. 

  1603. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1604. 

  1604. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1605. 

  1605. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1606. 

  1606. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1607. 

  1607. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1608. 

  1608. 

  1609. /* U3D_RXQSAR2 */
    1610. 

  1610. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1611. 

  1611. 

  1612. /* U3D_RXQCPR2 */
    1613. 

  1613. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1614. 

  1614. 

  1615. /* U3D_RXQLDPR2 */
    1616. 

  1616. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1617. 

  1617. 

  1618. /* U3D_RXQCSR3 */
    1619. 

  1619. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1620. 

  1620. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1621. 

  1621. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1622. 

  1622. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1623. 

  1623. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1624. 

  1624. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1625. 

  1625. 

  1626. /* U3D_RXQSAR3 */
    1627. 

  1627. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1628. 

  1628. 

  1629. /* U3D_RXQCPR3 */
    1630. 

  1630. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1631. 

  1631. 

  1632. /* U3D_RXQLDPR3 */
    1633. 

  1633. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1634. 

  1634. 

  1635. /* U3D_RXQCSR4 */
    1636. 

  1636. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1637. 

  1637. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1638. 

  1638. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1639. 

  1639. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1640. 

  1640. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1641. 

  1641. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1642. 

  1642. 

  1643. /* U3D_RXQSAR4 */
    1644. 

  1644. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1645. 

  1645. 

  1646. /* U3D_RXQCPR4 */
    1647. 

  1647. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1648. 

  1648. 

  1649. /* U3D_RXQLDPR4 */
    1650. 

  1650. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1651. 

  1651. 

  1652. /* U3D_RXQCSR5 */
    1653. 

  1653. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1654. 

  1654. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1655. 

  1655. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1656. 

  1656. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1657. 

  1657. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1658. 

  1658. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1659. 

  1659. 

  1660. /* U3D_RXQSAR5 */
    1661. 

  1661. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1662. 

  1662. 

  1663. /* U3D_RXQCPR5 */
    1664. 

  1664. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1665. 

  1665. 

  1666. /* U3D_RXQLDPR5 */
    1667. 

  1667. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1668. 

  1668. 

  1669. /* U3D_RXQCSR6 */
    1670. 

  1670. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1671. 

  1671. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1672. 

  1672. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1673. 

  1673. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1674. 

  1674. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1675. 

  1675. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1676. 

  1676. 

  1677. /* U3D_RXQSAR6 */
    1678. 

  1678. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1679. 

  1679. 

  1680. /* U3D_RXQCPR6 */
    1681. 

  1681. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1682. 

  1682. 

  1683. /* U3D_RXQLDPR6 */
    1684. 

  1684. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1685. 

  1685. 

  1686. /* U3D_RXQCSR7 */
    1687. 

  1687. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1688. 

  1688. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1689. 

  1689. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1690. 

  1690. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1691. 

  1691. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1692. 

  1692. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1693. 

  1693. 

  1694. /* U3D_RXQSAR7 */
    1695. 

  1695. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1696. 

  1696. 

  1697. /* U3D_RXQCPR7 */
    1698. 

  1698. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1699. 

  1699. 

  1700. /* U3D_RXQLDPR7 */
    1701. 

  1701. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1702. 

  1702. 

  1703. /* U3D_RXQCSR8 */
    1704. 

  1704. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1705. 

  1705. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1706. 

  1706. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1707. 

  1707. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1708. 

  1708. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1709. 

  1709. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1710. 

  1710. 

  1711. /* U3D_RXQSAR8 */
    1712. 

  1712. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1713. 

  1713. 

  1714. /* U3D_RXQCPR8 */
    1715. 

  1715. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1716. 

  1716. 

  1717. /* U3D_RXQLDPR8 */
    1718. 

  1718. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1719. 

  1719. 

  1720. /* U3D_RXQCSR9 */
    1721. 

  1721. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1722. 

  1722. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1723. 

  1723. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1724. 

  1724. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1725. 

  1725. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1726. 

  1726. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1727. 

  1727. 

  1728. /* U3D_RXQSAR9 */
    1729. 

  1729. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1730. 

  1730. 

  1731. /* U3D_RXQCPR9 */
    1732. 

  1732. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1733. 

  1733. 

  1734. /* U3D_RXQLDPR9 */
    1735. 

  1735. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1736. 

  1736. 

  1737. /* U3D_RXQCSR10 */
    1738. 

  1738. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1739. 

  1739. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1740. 

  1740. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1741. 

  1741. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1742. 

  1742. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1743. 

  1743. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1744. 

  1744. 

  1745. /* U3D_RXQSAR10 */
    1746. 

  1746. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1747. 

  1747. 

  1748. /* U3D_RXQCPR10 */
    1749. 

  1749. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1750. 

  1750. 

  1751. /* U3D_RXQLDPR10 */
    1752. 

  1752. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1753. 

  1753. 

  1754. /* U3D_RXQCSR11 */
    1755. 

  1755. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1756. 

  1756. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1757. 

  1757. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1758. 

  1758. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1759. 

  1759. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1760. 

  1760. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1761. 

  1761. 

  1762. /* U3D_RXQSAR11 */
    1763. 

  1763. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1764. 

  1764. 

  1765. /* U3D_RXQCPR11 */
    1766. 

  1766. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1767. 

  1767. 

  1768. /* U3D_RXQLDPR11 */
    1769. 

  1769. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1770. 

  1770. 

  1771. /* U3D_RXQCSR12 */
    1772. 

  1772. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1773. 

  1773. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1774. 

  1774. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1775. 

  1775. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1776. 

  1776. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1777. 

  1777. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1778. 

  1778. 

  1779. /* U3D_RXQSAR12 */
    1780. 

  1780. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1781. 

  1781. 

  1782. /* U3D_RXQCPR12 */
    1783. 

  1783. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1784. 

  1784. 

  1785. /* U3D_RXQLDPR12 */
    1786. 

  1786. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1787. 

  1787. 

  1788. /* U3D_RXQCSR13 */
    1789. 

  1789. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1790. 

  1790. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1791. 

  1791. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1792. 

  1792. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1793. 

  1793. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1794. 

  1794. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1795. 

  1795. 

  1796. /* U3D_RXQSAR13 */
    1797. 

  1797. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1798. 

  1798. 

  1799. /* U3D_RXQCPR13 */
    1800. 

  1800. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1801. 

  1801. 

  1802. /* U3D_RXQLDPR13 */
    1803. 

  1803. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1804. 

  1804. 

  1805. /* U3D_RXQCSR14 */
    1806. 

  1806. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1807. 

  1807. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1808. 

  1808. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1809. 

  1809. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1810. 

  1810. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1811. 

  1811. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1812. 

  1812. 

  1813. /* U3D_RXQSAR14 */
    1814. 

  1814. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1815. 

  1815. 

  1816. /* U3D_RXQCPR14 */
    1817. 

  1817. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1818. 

  1818. 

  1819. /* U3D_RXQLDPR14 */
    1820. 

  1820. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1821. 

  1821. 

  1822. /* U3D_RXQCSR15 */
    1823. 

  1823. #define RXQ_DMGR_DMSM_CS                          (0xf<<16)	/* 19:16 */
    1824. 

  1824. #define RXQ_ACTIVE                                (0x1<<15)	/* 15:15 */
    1825. 

  1825. #define RXQ_EPQ_STATE                             (0x1f<<8)	/* 12:8 */
    1826. 

  1826. #define RXQ_STOP                                  (0x1<<2)	/* 2:2 */
    1827. 

  1827. #define RXQ_RESUME                                (0x1<<1)	/* 1:1 */
    1828. 

  1828. #define RXQ_START                                 (0x1<<0)	/* 0:0 */
    1829. 

  1829. 

  1830. /* U3D_RXQSAR15 */
    1831. 

  1831. #define RXQ_START_ADDR                            (0x3fffffff<<2)	/* 31:2 */
    1832. 

  1832. 

  1833. /* U3D_RXQCPR15 */
    1834. 

  1834. #define RXQ_CUR_GPD_ADDR                          (0x3fffffff<<2)	/* 31:2 */
    1835. 

  1835. 

  1836. /* U3D_RXQLDPR15 */
    1837. 

  1837. #define RXQ_LAST_DONE_PTR                         (0x3fffffff<<2)	/* 31:2 */
    1838. 

  1838. 

  1839. /* U3D_QISAR0 */
    1840. 

  1840. #define RXQ_DONE_INT                              (0x7fff<<17)	/* 31:17 */
    1841. 

  1841. #define TXQ_DONE_INT                              (0x7fff<<1)	/* 15:1 */
    1842. 

  1842. 

  1843. /* U3D_QIER0 */
    1844. 

  1844. #define RXQ_DONE_IER                              (0x7fff<<17)	/* 31:17 */
    1845. 

  1845. #define TXQ_DONE_IER                              (0x7fff<<1)	/* 15:1 */
    1846. 

  1846. 

  1847. /* U3D_QIESR0 */
    1848. 

  1848. #define RXQ_DONE_IESR                             (0x7fff<<17)	/* 31:17 */
    1849. 

  1849. #define TXQ_DONE_IESR                             (0x7fff<<1)	/* 15:1 */
    1850. 

  1850. 

  1851. /* U3D_QIECR0 */
    1852. 

  1852. #define RXQ_DONE_IECR                             (0x7fff<<17)	/* 31:17 */
    1853. 

  1853. #define TXQ_DONE_IECR                             (0x7fff<<1)	/* 15:1 */
    1854. 

  1854. 

  1855. /* U3D_QISAR1 */
    1856. 

  1856. #define RXQ_ZLPERR_INT                            (0x1<<20)	/* 20:20 */
    1857. 

  1857. #define RXQ_LENERR_INT                            (0x1<<18)	/* 18:18 */
    1858. 

  1858. #define RXQ_CSERR_INT                             (0x1<<17)	/* 17:17 */
    1859. 

  1859. #define RXQ_EMPTY_INT                             (0x1<<16)	/* 16:16 */
    1860. 

  1860. #define TXQ_LENERR_INT                            (0x1<<2)	/* 2:2 */
    1861. 

  1861. #define TXQ_CSERR_INT                             (0x1<<1)	/* 1:1 */
    1862. 

  1862. #define TXQ_EMPTY_INT                             (0x1<<0)	/* 0:0 */
    1863. 

  1863. 

  1864. /* U3D_QIER1 */
    1865. 

  1865. #define RXQ_ZLPERR_IER                            (0x1<<20)	/* 20:20 */
    1866. 

  1866. #define RXQ_LENERR_IER                            (0x1<<18)	/* 18:18 */
    1867. 

  1867. #define RXQ_CSERR_IER                             (0x1<<17)	/* 17:17 */
    1868. 

  1868. #define RXQ_EMPTY_IER                             (0x1<<16)	/* 16:16 */
    1869. 

  1869. #define TXQ_LENERR_IER                            (0x1<<2)	/* 2:2 */
    1870. 

  1870. #define TXQ_CSERR_IER                             (0x1<<1)	/* 1:1 */
    1871. 

  1871. #define TXQ_EMPTY_IER                             (0x1<<0)	/* 0:0 */
    1872. 

  1872. 

  1873. /* U3D_QIESR1 */
    1874. 

  1874. #define RXQ_ZLPERR_IESR                           (0x1<<20)	/* 20:20 */
    1875. 

  1875. #define RXQ_LENERR_IESR                           (0x1<<18)	/* 18:18 */
    1876. 

  1876. #define RXQ_CSERR_IESR                            (0x1<<17)	/* 17:17 */
    1877. 

  1877. #define RXQ_EMPTY_IESR                            (0x1<<16)	/* 16:16 */
    1878. 

  1878. #define TXQ_LENERR_IESR                           (0x1<<2)	/* 2:2 */
    1879. 

  1879. #define TXQ_CSERR_IESR                            (0x1<<1)	/* 1:1 */
    1880. 

  1880. #define TXQ_EMPTY_IESR                            (0x1<<0)	/* 0:0 */
    1881. 

  1881. 

  1882. /* U3D_QIECR1 */
    1883. 

  1883. #define RXQ_ZLPERR_IECR                           (0x1<<20)	/* 20:20 */
    1884. 

  1884. #define RXQ_LENERR_IECR                           (0x1<<18)	/* 18:18 */
    1885. 

  1885. #define RXQ_CSERR_IECR                            (0x1<<17)	/* 17:17 */
    1886. 

  1886. #define RXQ_EMPTY_IECR                            (0x1<<16)	/* 16:16 */
    1887. 

  1887. #define TXQ_LENERR_IECR                           (0x1<<2)	/* 2:2 */
    1888. 

  1888. #define TXQ_CSERR_IECR                            (0x1<<1)	/* 1:1 */
    1889. 

  1889. #define TXQ_EMPTY_IECR                            (0x1<<0)	/* 0:0 */
    1890. 

  1890. 

  1891. /* U3D_QEMIR */
    1892. 

  1892. #define RXQ_EMPTY_MASK                            (0x7fff<<17)	/* 31:17 */
    1893. 

  1893. #define TXQ_EMPTY_MASK                            (0x7fff<<1)	/* 15:1 */
    1894. 

  1894. 

  1895. /* U3D_QEMIER */
    1896. 

  1896. #define RXQ_EMPTY_IER_MASK                        (0x7fff<<17)	/* 31:17 */
    1897. 

  1897. #define TXQ_EMPTY_IER_MASK                        (0x7fff<<1)	/* 15:1 */
    1898. 

  1898. 

  1899. /* U3D_QEMIESR */
    1900. 

  1900. #define RXQ_EMPTY_IESR_MASK                       (0x7fff<<17)	/* 31:17 */
    1901. 

  1901. #define TXQ_EMPTY_IESR_MASK                       (0x7fff<<1)	/* 15:1 */
    1902. 

  1902. 

  1903. /* U3D_QEMIECR */
    1904. 

  1904. #define RXQ_EMPTY_IECR_MASK                       (0x7fff<<17)	/* 31:17 */
    1905. 

  1905. #define TXQ_EMPTY_IECR_MASK                       (0x7fff<<1)	/* 15:1 */
    1906. 

  1906. 

  1907. /* U3D_TQERRIR0 */
    1908. 

  1908. #define TXQ_LENERR_MASK                           (0x7fff<<17)	/* 31:17 */
    1909. 

  1909. #define TXQ_CSERR_MASK                            (0x7fff<<1)	/* 15:1 */
    1910. 

  1910. 

  1911. /* U3D_TQERRIER0 */
    1912. 

  1912. #define TXQ_LENERR_IER_MASK                       (0x7fff<<17)	/* 31:17 */
    1913. 

  1913. #define TXQ_CSERR_IER_MASK                        (0x7fff<<1)	/* 15:1 */
    1914. 

  1914. 

  1915. /* U3D_TQERRIESR0 */
    1916. 

  1916. #define TXQ_LENERR_IESR_MASK                      (0x7fff<<17)	/* 31:17 */
    1917. 

  1917. #define TXQ_CSERR_IESR_MASK                       (0x7fff<<1)	/* 15:1 */
    1918. 

  1918. 

  1919. /* U3D_TQERRIECR0 */
    1920. 

  1920. #define TXQ_LENERR_IECR_MASK                      (0x7fff<<17)	/* 31:17 */
    1921. 

  1921. #define TXQ_CSERR_IECR_MASK                       (0x7fff<<1)	/* 15:1 */
    1922. 

  1922. 

  1923. /* U3D_RQERRIR0 */
    1924. 

  1924. #define RXQ_LENERR_MASK                           (0x7fff<<17)	/* 31:17 */
    1925. 

  1925. #define RXQ_CSERR_MASK                            (0x7fff<<1)	/* 15:1 */
    1926. 

  1926. 

  1927. /* U3D_RQERRIER0 */
    1928. 

  1928. #define RXQ_LENERR_IER_MASK                       (0x7fff<<17)	/* 31:17 */
    1929. 

  1929. #define RXQ_CSERR_IER_MASK                        (0x7fff<<1)	/* 15:1 */
    1930. 

  1930. 

  1931. /* U3D_RQERRIESR0 */
    1932. 

  1932. #define RXQ_LENERR_IESR_MASK                      (0x7fff<<17)	/* 31:17 */
    1933. 

  1933. #define RXQ_CSERR_IESR_MASK                       (0x7fff<<1)	/* 15:1 */
    1934. 

  1934. 

  1935. /* U3D_RQERRIECR0 */
    1936. 

  1936. #define RXQ_LENERR_IECR_MASK                      (0x7fff<<17)	/* 31:17 */
    1937. 

  1937. #define RXQ_CSERR_IECR_MASK                       (0x7fff<<1)	/* 15:1 */
    1938. 

  1938. 

  1939. /* U3D_RQERRIR1 */
    1940. 

  1940. #define RXQ_ZLPERR_MASK                           (0x7fff<<17)	/* 31:17 */
    1941. 

  1941. 

  1942. /* U3D_RQERRIER1 */
    1943. 

  1943. #define RXQ_ZLPERR_IER_MASK                       (0x7fff<<17)	/* 31:17 */
    1944. 

  1944. 

  1945. /* U3D_RQERRIESR1 */
    1946. 

  1946. #define RXQ_ZLPERR_IESR_MASK                      (0x7fff<<17)	/* 31:17 */
    1947. 

  1947. 

  1948. /* U3D_RQERRIECR1 */
    1949. 

  1949. #define RXQ_ZLPERR_IECR_MASK                      (0x7fff<<17)	/* 31:17 */
    1950. 

  1950. 

  1951. /* U3D_CAP_EP0FFSZ */
    1952. 

  1952. #define CAP_EP0FFSZ                               (0xffffffff<<0)	/* 31:0 */
    1953. 

  1953. 

  1954. /* U3D_CAP_EPNTXFFSZ */
    1955. 

  1955. #define CAP_EPNTXFFSZ                             (0xffffffff<<0)	/* 31:0 */
    1956. 

  1956. 

  1957. /* U3D_CAP_EPNRXFFSZ */
    1958. 

  1958. #define CAP_EPNRXFFSZ                             (0xffffffff<<0)	/* 31:0 */
    1959. 

  1959. 

  1960. /* U3D_CAP_EPINFO */
    1961. 

  1961. #define CAP_RX_EP_NUM                             (0x1f<<8)	/* 12:8 */
    1962. 

  1962. #define CAP_TX_EP_NUM                             (0x1f<<0)	/* 4:0 */
    1963. 

  1963. 

  1964. /* U3D_CAP_TX_SLOT1 */
    1965. 

  1965. #define CAP_TX_SLOT3                              (0x3f<<24)	/* 29:24 */
    1966. 

  1966. #define CAP_TX_SLOT2                              (0x3f<<16)	/* 21:16 */
    1967. 

  1967. #define CAP_TX_SLOT1                              (0x3f<<8)	/* 13:8 */
    1968. 

  1968. #define RSV                                       (0x3f<<0)	/* 5:0 */
    1969. 

  1969. 

  1970. /* U3D_CAP_TX_SLOT2 */
    1971. 

  1971. #define CAP_TX_SLOT7                              (0x3f<<24)	/* 29:24 */
    1972. 

  1972. #define CAP_TX_SLOT6                              (0x3f<<16)	/* 21:16 */
    1973. 

  1973. #define CAP_TX_SLOT5                              (0x3f<<8)	/* 13:8 */
    1974. 

  1974. #define CAP_TX_SLOT4                              (0x3f<<0)	/* 5:0 */
    1975. 

  1975. 

  1976. /* U3D_CAP_TX_SLOT3 */
    1977. 

  1977. #define CAP_TX_SLOT11                             (0x3f<<24)	/* 29:24 */
    1978. 

  1978. #define CAP_TX_SLOT10                             (0x3f<<16)	/* 21:16 */
    1979. 

  1979. #define CAP_TX_SLOT9                              (0x3f<<8)	/* 13:8 */
    1980. 

  1980. #define CAP_TX_SLOT8                              (0x3f<<0)	/* 5:0 */
    1981. 

  1981. 

  1982. /* U3D_CAP_TX_SLOT4 */
    1983. 

  1983. #define CAP_TX_SLOT15                             (0x3f<<24)	/* 29:24 */
    1984. 

  1984. #define CAP_TX_SLOT14                             (0x3f<<16)	/* 21:16 */
    1985. 

  1985. #define CAP_TX_SLOT13                             (0x3f<<8)	/* 13:8 */
    1986. 

  1986. #define CAP_TX_SLOT12                             (0x3f<<0)	/* 5:0 */
    1987. 

  1987. 

  1988. /* U3D_CAP_RX_SLOT1 */
    1989. 

  1989. #define CAP_RX_SLOT3                              (0x3f<<24)	/* 29:24 */
    1990. 

  1990. #define CAP_RX_SLOT2                              (0x3f<<16)	/* 21:16 */
    1991. 

  1991. #define CAP_RX_SLOT1                              (0x3f<<8)	/* 13:8 */
    1992. 

  1992. #define RSV                                       (0x3f<<0)	/* 5:0 */
    1993. 

  1993. 

  1994. /* U3D_CAP_RX_SLOT2 */
    1995. 

  1995. #define CAP_RX_SLOT7                              (0x3f<<24)	/* 29:24 */
    1996. 

  1996. #define CAP_RX_SLOT6                              (0x3f<<16)	/* 21:16 */
    1997. 

  1997. #define CAP_RX_SLOT5                              (0x3f<<8)	/* 13:8 */
    1998. 

  1998. #define CAP_RX_SLOT4                              (0x3f<<0)	/* 5:0 */
    1999. 

  1999. 

  2000. /* U3D_CAP_RX_SLOT3 */
    2001. 

  2001. #define CAP_RX_SLOT11                             (0x3f<<24)	/* 29:24 */
    2002. 

  2002. #define CAP_RX_SLOT10                             (0x3f<<16)	/* 21:16 */
    2003. 

  2003. #define CAP_RX_SLOT9                              (0x3f<<8)	/* 13:8 */
    2004. 

  2004. #define CAP_RX_SLOT8                              (0x3f<<0)	/* 5:0 */
    2005. 

  2005. 

  2006. /* U3D_CAP_RX_SLOT4 */
    2007. 

  2007. #define CAP_RX_SLOT15                             (0x3f<<24)	/* 29:24 */
    2008. 

  2008. #define CAP_RX_SLOT14                             (0x3f<<16)	/* 21:16 */
    2009. 

  2009. #define CAP_RX_SLOT13                             (0x3f<<8)	/* 13:8 */
    2010. 

  2010. #define CAP_RX_SLOT12                             (0x3f<<0)	/* 5:0 */
    2011. 

  2011. 

  2012. /* U3D_MISC_CTRL */
    2013. 

  2013. #define DMA_BUS_CK_GATE_DIS                       (0x1<<2)	/* 2:2 */
    2014. 

  2014. #define VBUS_ON                                   (0x1<<1)	/* 1:1 */
    2015. 

  2015. #define VBUS_FRC_EN                               (0x1<<0)	/* 0:0 */
    2016. 

  2016. 

  2017. 

  2018. /* SSUSB_DEV FIELD OFFSET DEFINITION */
    2019. 

  2019. 

  2020. /* U3D_LV1ISR */
    2021. 

  2021. #define EP_CTRL_INTR_OFST                         (5)
    2022. 

  2022. #define MAC2_INTR_OFST                            (4)
    2023. 

  2023. #define DMA_INTR_OFST                             (3)
    2024. 

  2024. #define MAC3_INTR_OFST                            (2)
    2025. 

  2025. #define QMU_INTR_OFST                             (1)
    2026. 

  2026. #define BMU_INTR_OFST                             (0)
    2027. 

  2027. 

  2028. /* U3D_LV1IER */
    2029. 

  2029. #define LV1IER_OFST                               (0)
    2030. 

  2030. 

  2031. /* U3D_LV1IESR */
    2032. 

  2032. #define LV1IESR_OFST                              (0)
    2033. 

  2033. 

  2034. /* U3D_LV1IECR */
    2035. 

  2035. #define LV1IECR_OFST                              (0)
    2036. 

  2036. 

  2037. /* U3D_AXI_WR_DMA_CFG */
    2038. 

  2038. #define AXI_WR_ULTRA_NUM_OFST                     (24)
    2039. 

  2039. #define AXI_WR_PRE_ULTRA_NUM_OFST                 (16)
    2040. 

  2040. #define AXI_WR_ULTRA_EN_OFST                      (0)
    2041. 

  2041. 

  2042. /* U3D_AXI_RD_DMA_CFG */
    2043. 

  2043. #define AXI_RD_ULTRA_NUM_OFST                     (24)
    2044. 

  2044. #define AXI_RD_PRE_ULTRA_NUM_OFST                 (16)
    2045. 

  2045. #define AXI_RD_ULTRA_EN_OFST                      (0)
    2046. 

  2046. 

  2047. /* U3D_MAC_U1_EN_CTRL */
    2048. 

  2048. #define EXIT_BY_ERDY_DIS_OFST                     (31)
    2049. 

  2049. #define ACCEPT_BMU_RX_EMPTY_CHK_OFST              (20)
    2050. 

  2050. #define ACCEPT_BMU_TX_EMPTY_CHK_OFST              (19)
    2051. 

  2051. #define ACCEPT_RXQ_INACTIVE_CHK_OFST              (18)
    2052. 

  2052. #define ACCEPT_TXQ_INACTIVE_CHK_OFST              (17)
    2053. 

  2053. #define ACCEPT_EP0_INACTIVE_CHK_OFST              (16)
    2054. 

  2054. #define REQUEST_BMU_RX_EMPTY_CHK_OFST             (4)
    2055. 

  2055. #define REQUEST_BMU_TX_EMPTY_CHK_OFST             (3)
    2056. 

  2056. #define REQUEST_RXQ_INACTIVE_CHK_OFST             (2)
    2057. 

  2057. #define REQUEST_TXQ_INACTIVE_CHK_OFST             (1)
    2058. 

  2058. #define REQUEST_EP0_INACTIVE_CHK_OFST             (0)
    2059. 

  2059. 

  2060. /* U3D_MAC_U2_EN_CTRL */
    2061. 

  2061. #define EXIT_BY_ERDY_DIS_OFST                     (31)
    2062. 

  2062. #define ACCEPT_BMU_RX_EMPTY_CHK_OFST              (20)
    2063. 

  2063. #define ACCEPT_BMU_TX_EMPTY_CHK_OFST              (19)
    2064. 

  2064. #define ACCEPT_RXQ_INACTIVE_CHK_OFST              (18)
    2065. 

  2065. #define ACCEPT_TXQ_INACTIVE_CHK_OFST              (17)
    2066. 

  2066. #define ACCEPT_EP0_INACTIVE_CHK_OFST              (16)
    2067. 

  2067. #define REQUEST_BMU_RX_EMPTY_CHK_OFST             (4)
    2068. 

  2068. #define REQUEST_BMU_TX_EMPTY_CHK_OFST             (3)
    2069. 

  2069. #define REQUEST_RXQ_INACTIVE_CHK_OFST             (2)
    2070. 

  2070. #define REQUEST_TXQ_INACTIVE_CHK_OFST             (1)
    2071. 

  2071. #define REQUEST_EP0_INACTIVE_CHK_OFST             (0)
    2072. 

  2072. 

  2073. /* U3D_SRAM_DBG_CTRL */
    2074. 

  2074. #define EPNRX_SRAM_DEBUG_MODE_OFST                (2)
    2075. 

  2075. #define EPNTX_SRAM_DEBUG_MODE_OFST                (1)
    2076. 

  2076. #define EP0_SRAM_DEBUG_MODE_OFST                  (0)
    2077. 

  2077. 

  2078. /* U3D_SRAM_DBG_CTRL_1 */
    2079. 

  2079. #define SRAM_DEBUG_FIFOSEGSIZE_OFST               (24)
    2080. 

  2080. #define SRAM_DEBUG_SLOT_OFST                      (16)
    2081. 

  2081. #define SRAM_DEBUG_DP_COUNT_OFST                  (0)
    2082. 

  2082. 

  2083. /* U3D_RISC_SIZE */
    2084. 

  2084. #define RISC_SIZE_OFST                            (0)
    2085. 

  2085. 

  2086. /* U3D_WRBUF_ERR_STS */
    2087. 

  2087. #define RX_RDBUF_ERR_STS_OFST                     (17)
    2088. 

  2088. #define TX_WRBUF_ERR_STS_OFST                     (1)
    2089. 

  2089. 

  2090. /* U3D_BUF_ERR_EN */
    2091. 

  2091. #define RX_RDBUF_ERR_EN_OFST                      (17)
    2092. 

  2092. #define TX_WRBUF_ERR_EN_OFST                      (1)
    2093. 

  2093. 

  2094. /* U3D_EPISR */
    2095. 

  2095. #define EPRISR_OFST                               (17)
    2096. 

  2096. #define SETUPENDISR_OFST                          (16)
    2097. 

  2097. #define EPTISR_OFST                               (1)
    2098. 

  2098. #define EP0ISR_OFST                               (0)
    2099. 

  2099. 

  2100. /* U3D_EPIER */
    2101. 

  2101. #define EPRIER_OFST                               (17)
    2102. 

  2102. #define SETUPENDIER_OFST                          (16)
    2103. 

  2103. #define EPTIER_OFST                               (1)
    2104. 

  2104. #define EP0IER_OFST                               (0)
    2105. 

  2105. 

  2106. /* U3D_EPIESR */
    2107. 

  2107. #define EPRIESR_OFST                              (17)
    2108. 

  2108. #define SETUPENDIESR_OFST                         (16)
    2109. 

  2109. #define EPTIESR_OFST                              (1)
    2110. 

  2110. #define EP0IESR_OFST                              (0)
    2111. 

  2111. 

  2112. /* U3D_EPIECR */
    2113. 

  2113. #define EPRISR_OFST                               (17)
    2114. 

  2114. #define SETUPENDIECR_OFST                         (16)
    2115. 

  2115. #define EPTIECR_OFST                              (1)
    2116. 

  2116. #define EP0IECR_OFST                              (0)
    2117. 

  2117. 

  2118. /* U3D_DMAISR */
    2119. 

  2119. #define RXDMAISR_OFST                             (2)
    2120. 

  2120. #define TXDMAISR_OFST                             (1)
    2121. 

  2121. #define EP0DMAISR_OFST                            (0)
    2122. 

  2122. 

  2123. /* U3D_DMAIER */
    2124. 

  2124. #define RXDMAIER_OFST                             (2)
    2125. 

  2125. #define TXDMAIER_OFST                             (1)
    2126. 

  2126. #define EP0DMAER_OFST                             (0)
    2127. 

  2127. 

  2128. /* U3D_DMAIESR */
    2129. 

  2129. #define RXDMAIESR_OFST                            (2)
    2130. 

  2130. #define TXDMAIESR_OFST                            (1)
    2131. 

  2131. #define EP0DMAIESR_OFST                           (0)
    2132. 

  2132. 

  2133. /* U3D_DMAIECR */
    2134. 

  2134. #define RXDMAIECR_OFST                            (2)
    2135. 

  2135. #define TXDMAIECR_OFST                            (1)
    2136. 

  2136. #define EP0DMAIECR_OFST                           (0)
    2137. 

  2137. 

  2138. /* U3D_EP0DMACTRL */
    2139. 

  2139. #define FFSTRADDR0_OFST                           (16)
    2140. 

  2140. #define ENDPNT_OFST                               (4)
    2141. 

  2141. #define INTEN_OFST                                (3)
    2142. 

  2142. #define DMA_DIR_OFST                              (1)
    2143. 

  2143. #define DMA_EN_OFST                               (0)
    2144. 

  2144. 

  2145. /* U3D_EP0DMASTRADDR */
    2146. 

  2146. #define DMASTRADDR0_OFST                          (0)
    2147. 

  2147. 

  2148. /* U3D_EP0DMATFRCOUNT */
    2149. 

  2149. #define DMATFRCNT0_OFST                           (0)
    2150. 

  2150. 

  2151. /* U3D_EP0DMARLCOUNT */
    2152. 

  2152. #define EP0_DMALIMITER_OFST                       (28)
    2153. 

  2153. #define DMA_FAKE_OFST                             (27)
    2154. 

  2154. #define DMA_BURST_OFST                            (24)
    2155. 

  2155. #define AXI_DMA_OUTSTAND_NUM_OFST                 (20)
    2156. 

  2156. #define AXI_DMA_COHERENCE_OFST                    (19)
    2157. 

  2157. #define AXI_DMA_IOMMU_OFST                        (18)
    2158. 

  2158. #define AXI_DMA_CACHEABLE_OFST                    (17)
    2159. 

  2159. #define AXI_DMA_ULTRA_EN_OFST                     (16)
    2160. 

  2160. #define AXI_DMA_ULTRA_NUM_OFST                    (8)
    2161. 

  2161. #define AXI_DMA_PRE_ULTRA_NUM_OFST                (0)
    2162. 

  2162. 

  2163. /* U3D_TXDMACTRL */
    2164. 

  2164. #define FFSTRADDR_OFST                            (16)
    2165. 

  2165. #define ENDPNT_OFST                               (4)
    2166. 

  2166. #define INTEN_OFST                                (3)
    2167. 

  2167. #define DMA_DIR_OFST                              (1)
    2168. 

  2168. #define DMA_EN_OFST                               (0)
    2169. 

  2169. 

  2170. /* U3D_TXDMASTRADDR */
    2171. 

  2171. #define DMASTRADDR_OFST                           (0)
    2172. 

  2172. 

  2173. /* U3D_TXDMATRDCNT */
    2174. 

  2174. #define DMATFRCNT_OFST                            (0)
    2175. 

  2175. 

  2176. /* U3D_TXDMARLCOUNT */
    2177. 

  2177. #define DMALIMITER_OFST                           (28)
    2178. 

  2178. #define DMA_FAKE_OFST                             (27)
    2179. 

  2179. #define DMA_BURST_OFST                            (24)
    2180. 

  2180. #define AXI_DMA_OUTSTAND_NUM_OFST                 (20)
    2181. 

  2181. #define AXI_DMA_COHERENCE_OFST                    (19)
    2182. 

  2182. #define AXI_DMA_IOMMU_OFST                        (18)
    2183. 

  2183. #define AXI_DMA_CACHEABLE_OFST                    (17)
    2184. 

  2184. #define AXI_DMA_ULTRA_EN_OFST                     (16)
    2185. 

  2185. #define AXI_DMA_ULTRA_NUM_OFST                    (8)
    2186. 

  2186. #define AXI_DMA_PRE_ULTRA_NUM_OFST                (0)
    2187. 

  2187. 

  2188. /* U3D_RXDMACTRL */
    2189. 

  2189. #define FFSTRADDR_OFST                            (16)
    2190. 

  2190. #define ENDPNT_OFST                               (4)
    2191. 

  2191. #define INTEN_OFST                                (3)
    2192. 

  2192. #define DMA_DIR_OFST                              (1)
    2193. 

  2193. #define DMA_EN_OFST                               (0)
    2194. 

  2194. 

  2195. /* U3D_RXDMASTRADDR */
    2196. 

  2196. #define DMASTRADDR_OFST                           (0)
    2197. 

  2197. 

  2198. /* U3D_RXDMATRDCNT */
    2199. 

  2199. #define DMATFRCNT_OFST                            (0)
    2200. 

  2200. 

  2201. /* U3D_RXDMARLCOUNT */
    2202. 

  2202. #define DMA_NON_BUF_OFST                          (31)
    2203. 

  2203. #define DMALIMITER_OFST                           (28)
    2204. 

  2204. #define DMA_FAKE_OFST                             (27)
    2205. 

  2205. #define DMA_BURST_OFST                            (24)
    2206. 

  2206. #define AXI_DMA_OUTSTAND_NUM_OFST                 (20)
    2207. 

  2207. #define AXI_DMA_COHERENCE_OFST                    (19)
    2208. 

  2208. #define AXI_DMA_IOMMU_OFST                        (18)
    2209. 

  2209. #define AXI_DMA_CACHEABLE_OFST                    (17)
    2210. 

  2210. #define AXI_DMA_ULTRA_EN_OFST                     (16)
    2211. 

  2211. #define AXI_DMA_ULTRA_NUM_OFST                    (8)
    2212. 

  2212. #define AXI_DMA_PRE_ULTRA_NUM_OFST                (0)
    2213. 

  2213. 

  2214. /* U3D_EP0CSR */
    2215. 

  2215. #define EP0_EP_RESET_OFST                         (31)
    2216. 

  2216. #define EP0_AUTOCLEAR_OFST                        (30)
    2217. 

  2217. #define EP0_AUTOSET_OFST                          (29)
    2218. 

  2218. #define EP0_DMAREQEN_OFST                         (28)
    2219. 

  2219. #define EP0_SENDSTALL_OFST                        (25)
    2220. 

  2220. #define EP0_FIFOFULL_OFST                         (23)
    2221. 

  2221. #define EP0_SENTSTALL_OFST                        (22)
    2222. 

  2222. #define EP0_DPHTX_OFST                            (20)
    2223. 

  2223. #define EP0_DATAEND_OFST                          (19)
    2224. 

  2224. #define EP0_TXPKTRDY_OFST                         (18)
    2225. 

  2225. #define EP0_SETUPPKTRDY_OFST                      (17)
    2226. 

  2226. #define EP0_RXPKTRDY_OFST                         (16)
    2227. 

  2227. #define EP0_MAXPKTSZ0_OFST                        (0)
    2228. 

  2228. 

  2229. /* U3D_RXCOUNT0 */
    2230. 

  2230. #define EP0_RX_COUNT_OFST                         (0)
    2231. 

  2231. 

  2232. /* U3D_RESERVED */
    2233. 

  2233. 

  2234. /* U3D_TX1CSR0 */
    2235. 

  2235. #define TX_EP_RESET_OFST                          (31)
    2236. 

  2236. #define TX_AUTOSET_OFST                           (30)
    2237. 

  2237. #define TX_DMAREQEN_OFST                          (29)
    2238. 

  2238. #define TX_FIFOFULL_OFST                          (25)
    2239. 

  2239. #define TX_FIFOEMPTY_OFST                         (24)
    2240. 

  2240. #define TX_SENTSTALL_OFST                         (22)
    2241. 

  2241. #define TX_SENDSTALL_OFST                         (21)
    2242. 

  2242. #define TX_TXPKTRDY_OFST                          (16)
    2243. 

  2243. #define TX_TXMAXPKTSZ_OFST                        (0)
    2244. 

  2244. 

  2245. /* U3D_TX1CSR1 */
    2246. 

  2246. #define TX_MULT_OFST                              (22)
    2247. 

  2247. #define TX_MAX_PKT_OFST                           (16)
    2248. 

  2248. #define TX_SLOT_OFST                              (8)
    2249. 

  2249. #define TXTYPE_OFST                               (4)
    2250. 

  2250. #define SS_TX_BURST_OFST                          (0)
    2251. 

  2251. 

  2252. /* U3D_TX1CSR2 */
    2253. 

  2253. #define TXBINTERVAL_OFST                          (24)
    2254. 

  2254. #define TXFIFOSEGSIZE_OFST                        (16)
    2255. 

  2255. #define TXFIFOADDR_OFST                           (0)
    2256. 

  2256. 

  2257. /* U3D_TX2CSR0 */
    2258. 

  2258. #define TX_EP_RESET_OFST                          (31)
    2259. 

  2259. #define TX_AUTOSET_OFST                           (30)
    2260. 

  2260. #define TX_DMAREQEN_OFST                          (29)
    2261. 

  2261. #define TX_FIFOFULL_OFST                          (25)
    2262. 

  2262. #define TX_FIFOEMPTY_OFST                         (24)
    2263. 

  2263. #define TX_SENTSTALL_OFST                         (22)
    2264. 

  2264. #define TX_SENDSTALL_OFST                         (21)
    2265. 

  2265. #define TX_TXPKTRDY_OFST                          (16)
    2266. 

  2266. #define TX_TXMAXPKTSZ_OFST                        (0)
    2267. 

  2267. 

  2268. /* U3D_TX2CSR1 */
    2269. 

  2269. #define TX_MULT_OFST                              (22)
    2270. 

  2270. #define TX_MAX_PKT_OFST                           (16)
    2271. 

  2271. #define TX_SLOT_OFST                              (8)
    2272. 

  2272. #define TXTYPE_OFST                               (4)
    2273. 

  2273. #define SS_TX_BURST_OFST                          (0)
    2274. 

  2274. 

  2275. /* U3D_TX2CSR2 */
    2276. 

  2276. #define TXBINTERVAL_OFST                          (24)
    2277. 

  2277. #define TXFIFOSEGSIZE_OFST                        (16)
    2278. 

  2278. #define TXFIFOADDR_OFST                           (0)
    2279. 

  2279. 

  2280. /* U3D_TX3CSR0 */
    2281. 

  2281. #define TX_EP_RESET_OFST                          (31)
    2282. 

  2282. #define TX_AUTOSET_OFST                           (30)
    2283. 

  2283. #define TX_DMAREQEN_OFST                          (29)
    2284. 

  2284. #define TX_FIFOFULL_OFST                          (25)
    2285. 

  2285. #define TX_FIFOEMPTY_OFST                         (24)
    2286. 

  2286. #define TX_SENTSTALL_OFST                         (22)
    2287. 

  2287. #define TX_SENDSTALL_OFST                         (21)
    2288. 

  2288. #define TX_TXPKTRDY_OFST                          (16)
    2289. 

  2289. #define TX_TXMAXPKTSZ_OFST                        (0)
    2290. 

  2290. 

  2291. /* U3D_TX3CSR1 */
    2292. 

  2292. #define TX_MULT_OFST                              (22)
    2293. 

  2293. #define TX_MAX_PKT_OFST                           (16)
    2294. 

  2294. #define TX_SLOT_OFST                              (8)
    2295. 

  2295. #define TXTYPE_OFST                               (4)
    2296. 

  2296. #define SS_TX_BURST_OFST                          (0)
    2297. 

  2297. 

  2298. /* U3D_TX3CSR2 */
    2299. 

  2299. #define TXBINTERVAL_OFST                          (24)
    2300. 

  2300. #define TXFIFOSEGSIZE_OFST                        (16)
    2301. 

  2301. #define TXFIFOADDR_OFST                           (0)
    2302. 

  2302. 

  2303. /* U3D_TX4CSR0 */
    2304. 

  2304. #define TX_EP_RESET_OFST                          (31)
    2305. 

  2305. #define TX_AUTOSET_OFST                           (30)
    2306. 

  2306. #define TX_DMAREQEN_OFST                          (29)
    2307. 

  2307. #define TX_FIFOFULL_OFST                          (25)
    2308. 

  2308. #define TX_FIFOEMPTY_OFST                         (24)
    2309. 

  2309. #define TX_SENTSTALL_OFST                         (22)
    2310. 

  2310. #define TX_SENDSTALL_OFST                         (21)
    2311. 

  2311. #define TX_TXPKTRDY_OFST                          (16)
    2312. 

  2312. #define TX_TXMAXPKTSZ_OFST                        (0)
    2313. 

  2313. 

  2314. /* U3D_TX4CSR1 */
    2315. 

  2315. #define TX_MULT_OFST                              (22)
    2316. 

  2316. #define TX_MAX_PKT_OFST                           (16)
    2317. 

  2317. #define TX_SLOT_OFST                              (8)
    2318. 

  2318. #define TXTYPE_OFST                               (4)
    2319. 

  2319. #define SS_TX_BURST_OFST                          (0)
    2320. 

  2320. 

  2321. /* U3D_TX4CSR2 */
    2322. 

  2322. #define TXBINTERVAL_OFST                          (24)
    2323. 

  2323. #define TXFIFOSEGSIZE_OFST                        (16)
    2324. 

  2324. #define TXFIFOADDR_OFST                           (0)
    2325. 

  2325. 

  2326. /* U3D_TX5CSR0 */
    2327. 

  2327. #define TX_EP_RESET_OFST                          (31)
    2328. 

  2328. #define TX_AUTOSET_OFST                           (30)
    2329. 

  2329. #define TX_DMAREQEN_OFST                          (29)
    2330. 

  2330. #define TX_FIFOFULL_OFST                          (25)
    2331. 

  2331. #define TX_FIFOEMPTY_OFST                         (24)
    2332. 

  2332. #define TX_SENTSTALL_OFST                         (22)
    2333. 

  2333. #define TX_SENDSTALL_OFST                         (21)
    2334. 

  2334. #define TX_TXPKTRDY_OFST                          (16)
    2335. 

  2335. #define TX_TXMAXPKTSZ_OFST                        (0)
    2336. 

  2336. 

  2337. /* U3D_TX5CSR1 */
    2338. 

  2338. #define TX_MULT_OFST                              (22)
    2339. 

  2339. #define TX_MAX_PKT_OFST                           (16)
    2340. 

  2340. #define TX_SLOT_OFST                              (8)
    2341. 

  2341. #define TXTYPE_OFST                               (4)
    2342. 

  2342. #define SS_TX_BURST_OFST                          (0)
    2343. 

  2343. 

  2344. /* U3D_TX5CSR2 */
    2345. 

  2345. #define TXBINTERVAL_OFST                          (24)
    2346. 

  2346. #define TXFIFOSEGSIZE_OFST                        (16)
    2347. 

  2347. #define TXFIFOADDR_OFST                           (0)
    2348. 

  2348. 

  2349. /* U3D_TX6CSR0 */
    2350. 

  2350. #define TX_EP_RESET_OFST                          (31)
    2351. 

  2351. #define TX_AUTOSET_OFST                           (30)
    2352. 

  2352. #define TX_DMAREQEN_OFST                          (29)
    2353. 

  2353. #define TX_FIFOFULL_OFST                          (25)
    2354. 

  2354. #define TX_FIFOEMPTY_OFST                         (24)
    2355. 

  2355. #define TX_SENTSTALL_OFST                         (22)
    2356. 

  2356. #define TX_SENDSTALL_OFST                         (21)
    2357. 

  2357. #define TX_TXPKTRDY_OFST                          (16)
    2358. 

  2358. #define TX_TXMAXPKTSZ_OFST                        (0)
    2359. 

  2359. 

  2360. /* U3D_TX6CSR1 */
    2361. 

  2361. #define TX_MULT_OFST                              (22)
    2362. 

  2362. #define TX_MAX_PKT_OFST                           (16)
    2363. 

  2363. #define TX_SLOT_OFST                              (8)
    2364. 

  2364. #define TXTYPE_OFST                               (4)
    2365. 

  2365. #define SS_TX_BURST_OFST                          (0)
    2366. 

  2366. 

  2367. /* U3D_TX6CSR2 */
    2368. 

  2368. #define TXBINTERVAL_OFST                          (24)
    2369. 

  2369. #define TXFIFOSEGSIZE_OFST                        (16)
    2370. 

  2370. #define TXFIFOADDR_OFST                           (0)
    2371. 

  2371. 

  2372. /* U3D_TX7CSR0 */
    2373. 

  2373. #define TX_EP_RESET_OFST                          (31)
    2374. 

  2374. #define TX_AUTOSET_OFST                           (30)
    2375. 

  2375. #define TX_DMAREQEN_OFST                          (29)
    2376. 

  2376. #define TX_FIFOFULL_OFST                          (25)
    2377. 

  2377. #define TX_FIFOEMPTY_OFST                         (24)
    2378. 

  2378. #define TX_SENTSTALL_OFST                         (22)
    2379. 

  2379. #define TX_SENDSTALL_OFST                         (21)
    2380. 

  2380. #define TX_TXPKTRDY_OFST                          (16)
    2381. 

  2381. #define TX_TXMAXPKTSZ_OFST                        (0)
    2382. 

  2382. 

  2383. /* U3D_TX7CSR1 */
    2384. 

  2384. #define TX_MULT_OFST                              (22)
    2385. 

  2385. #define TX_MAX_PKT_OFST                           (16)
    2386. 

  2386. #define TX_SLOT_OFST                              (8)
    2387. 

  2387. #define TXTYPE_OFST                               (4)
    2388. 

  2388. #define SS_TX_BURST_OFST                          (0)
    2389. 

  2389. 

  2390. /* U3D_TX7CSR2 */
    2391. 

  2391. #define TXBINTERVAL_OFST                          (24)
    2392. 

  2392. #define TXFIFOSEGSIZE_OFST                        (16)
    2393. 

  2393. #define TXFIFOADDR_OFST                           (0)
    2394. 

  2394. 

  2395. /* U3D_TX8CSR0 */
    2396. 

  2396. #define TX_EP_RESET_OFST                          (31)
    2397. 

  2397. #define TX_AUTOSET_OFST                           (30)
    2398. 

  2398. #define TX_DMAREQEN_OFST                          (29)
    2399. 

  2399. #define TX_FIFOFULL_OFST                          (25)
    2400. 

  2400. #define TX_FIFOEMPTY_OFST                         (24)
    2401. 

  2401. #define TX_SENTSTALL_OFST                         (22)
    2402. 

  2402. #define TX_SENDSTALL_OFST                         (21)
    2403. 

  2403. #define TX_TXPKTRDY_OFST                          (16)
    2404. 

  2404. #define TX_TXMAXPKTSZ_OFST                        (0)
    2405. 

  2405. 

  2406. /* U3D_TX8CSR1 */
    2407. 

  2407. #define TX_MULT_OFST                              (22)
    2408. 

  2408. #define TX_MAX_PKT_OFST                           (16)
    2409. 

  2409. #define TX_SLOT_OFST                              (8)
    2410. 

  2410. #define TXTYPE_OFST                               (4)
    2411. 

  2411. #define SS_TX_BURST_OFST                          (0)
    2412. 

  2412. 

  2413. /* U3D_TX8CSR2 */
    2414. 

  2414. #define TXBINTERVAL_OFST                          (24)
    2415. 

  2415. #define TXFIFOSEGSIZE_OFST                        (16)
    2416. 

  2416. #define TXFIFOADDR_OFST                           (0)
    2417. 

  2417. 

  2418. /* U3D_TX9CSR0 */
    2419. 

  2419. #define TX_EP_RESET_OFST                          (31)
    2420. 

  2420. #define TX_AUTOSET_OFST                           (30)
    2421. 

  2421. #define TX_DMAREQEN_OFST                          (29)
    2422. 

  2422. #define TX_FIFOFULL_OFST                          (25)
    2423. 

  2423. #define TX_FIFOEMPTY_OFST                         (24)
    2424. 

  2424. #define TX_SENTSTALL_OFST                         (22)
    2425. 

  2425. #define TX_SENDSTALL_OFST                         (21)
    2426. 

  2426. #define TX_TXPKTRDY_OFST                          (16)
    2427. 

  2427. #define TX_TXMAXPKTSZ_OFST                        (0)
    2428. 

  2428. 

  2429. /* U3D_TX9CSR1 */
    2430. 

  2430. #define TX_MULT_OFST                              (22)
    2431. 

  2431. #define TX_MAX_PKT_OFST                           (16)
    2432. 

  2432. #define TX_SLOT_OFST                              (8)
    2433. 

  2433. #define TXTYPE_OFST                               (4)
    2434. 

  2434. #define SS_TX_BURST_OFST                          (0)
    2435. 

  2435. 

  2436. /* U3D_TX9CSR2 */
    2437. 

  2437. #define TXBINTERVAL_OFST                          (24)
    2438. 

  2438. #define TXFIFOSEGSIZE_OFST                        (16)
    2439. 

  2439. #define TXFIFOADDR_OFST                           (0)
    2440. 

  2440. 

  2441. /* U3D_TX10CSR0 */
    2442. 

  2442. #define TX_EP_RESET_OFST                          (31)
    2443. 

  2443. #define TX_AUTOSET_OFST                           (30)
    2444. 

  2444. #define TX_DMAREQEN_OFST                          (29)
    2445. 

  2445. #define TX_FIFOFULL_OFST                          (25)
    2446. 

  2446. #define TX_FIFOEMPTY_OFST                         (24)
    2447. 

  2447. #define TX_SENTSTALL_OFST                         (22)
    2448. 

  2448. #define TX_SENDSTALL_OFST                         (21)
    2449. 

  2449. #define TX_TXPKTRDY_OFST                          (16)
    2450. 

  2450. #define TX_TXMAXPKTSZ_OFST                        (0)
    2451. 

  2451. 

  2452. /* U3D_TX10CSR1 */
    2453. 

  2453. #define TX_MULT_OFST                              (22)
    2454. 

  2454. #define TX_MAX_PKT_OFST                           (16)
    2455. 

  2455. #define TX_SLOT_OFST                              (8)
    2456. 

  2456. #define TXTYPE_OFST                               (4)
    2457. 

  2457. #define SS_TX_BURST_OFST                          (0)
    2458. 

  2458. 

  2459. /* U3D_TX10CSR2 */
    2460. 

  2460. #define TXBINTERVAL_OFST                          (24)
    2461. 

  2461. #define TXFIFOSEGSIZE_OFST                        (16)
    2462. 

  2462. #define TXFIFOADDR_OFST                           (0)
    2463. 

  2463. 

  2464. /* U3D_TX11CSR0 */
    2465. 

  2465. #define TX_EP_RESET_OFST                          (31)
    2466. 

  2466. #define TX_AUTOSET_OFST                           (30)
    2467. 

  2467. #define TX_DMAREQEN_OFST                          (29)
    2468. 

  2468. #define TX_FIFOFULL_OFST                          (25)
    2469. 

  2469. #define TX_FIFOEMPTY_OFST                         (24)
    2470. 

  2470. #define TX_SENTSTALL_OFST                         (22)
    2471. 

  2471. #define TX_SENDSTALL_OFST                         (21)
    2472. 

  2472. #define TX_TXPKTRDY_OFST                          (16)
    2473. 

  2473. #define TX_TXMAXPKTSZ_OFST                        (0)
    2474. 

  2474. 

  2475. /* U3D_TX11CSR1 */
    2476. 

  2476. #define TX_MULT_OFST                              (22)
    2477. 

  2477. #define TX_MAX_PKT_OFST                           (16)
    2478. 

  2478. #define TX_SLOT_OFST                              (8)
    2479. 

  2479. #define TXTYPE_OFST                               (4)
    2480. 

  2480. #define SS_TX_BURST_OFST                          (0)
    2481. 

  2481. 

  2482. /* U3D_TX11CSR2 */
    2483. 

  2483. #define TXBINTERVAL_OFST                          (24)
    2484. 

  2484. #define TXFIFOSEGSIZE_OFST                        (16)
    2485. 

  2485. #define TXFIFOADDR_OFST                           (0)
    2486. 

  2486. 

  2487. /* U3D_TX12CSR0 */
    2488. 

  2488. #define TX_EP_RESET_OFST                          (31)
    2489. 

  2489. #define TX_AUTOSET_OFST                           (30)
    2490. 

  2490. #define TX_DMAREQEN_OFST                          (29)
    2491. 

  2491. #define TX_FIFOFULL_OFST                          (25)
    2492. 

  2492. #define TX_FIFOEMPTY_OFST                         (24)
    2493. 

  2493. #define TX_SENTSTALL_OFST                         (22)
    2494. 

  2494. #define TX_SENDSTALL_OFST                         (21)
    2495. 

  2495. #define TX_TXPKTRDY_OFST                          (16)
    2496. 

  2496. #define TX_TXMAXPKTSZ_OFST                        (0)
    2497. 

  2497. 

  2498. /* U3D_TX12CSR1 */
    2499. 

  2499. #define TX_MULT_OFST                              (22)
    2500. 

  2500. #define TX_MAX_PKT_OFST                           (16)
    2501. 

  2501. #define TX_SLOT_OFST                              (8)
    2502. 

  2502. #define TXTYPE_OFST                               (4)
    2503. 

  2503. #define SS_TX_BURST_OFST                          (0)
    2504. 

  2504. 

  2505. /* U3D_TX12CSR2 */
    2506. 

  2506. #define TXBINTERVAL_OFST                          (24)
    2507. 

  2507. #define TXFIFOSEGSIZE_OFST                        (16)
    2508. 

  2508. #define TXFIFOADDR_OFST                           (0)
    2509. 

  2509. 

  2510. /* U3D_TX13CSR0 */
    2511. 

  2511. #define TX_EP_RESET_OFST                          (31)
    2512. 

  2512. #define TX_AUTOSET_OFST                           (30)
    2513. 

  2513. #define TX_DMAREQEN_OFST                          (29)
    2514. 

  2514. #define TX_FIFOFULL_OFST                          (25)
    2515. 

  2515. #define TX_FIFOEMPTY_OFST                         (24)
    2516. 

  2516. #define TX_SENTSTALL_OFST                         (22)
    2517. 

  2517. #define TX_SENDSTALL_OFST                         (21)
    2518. 

  2518. #define TX_TXPKTRDY_OFST                          (16)
    2519. 

  2519. #define TX_TXMAXPKTSZ_OFST                        (0)
    2520. 

  2520. 

  2521. /* U3D_TX13CSR1 */
    2522. 

  2522. #define TX_MULT_OFST                              (22)
    2523. 

  2523. #define TX_MAX_PKT_OFST                           (16)
    2524. 

  2524. #define TX_SLOT_OFST                              (8)
    2525. 

  2525. #define TXTYPE_OFST                               (4)
    2526. 

  2526. #define SS_TX_BURST_OFST                          (0)
    2527. 

  2527. 

  2528. /* U3D_TX13CSR2 */
    2529. 

  2529. #define TXBINTERVAL_OFST                          (24)
    2530. 

  2530. #define TXFIFOSEGSIZE_OFST                        (16)
    2531. 

  2531. #define TXFIFOADDR_OFST                           (0)
    2532. 

  2532. 

  2533. /* U3D_TX14CSR0 */
    2534. 

  2534. #define TX_EP_RESET_OFST                          (31)
    2535. 

  2535. #define TX_AUTOSET_OFST                           (30)
    2536. 

  2536. #define TX_DMAREQEN_OFST                          (29)
    2537. 

  2537. #define TX_FIFOFULL_OFST                          (25)
    2538. 

  2538. #define TX_FIFOEMPTY_OFST                         (24)
    2539. 

  2539. #define TX_SENTSTALL_OFST                         (22)
    2540. 

  2540. #define TX_SENDSTALL_OFST                         (21)
    2541. 

  2541. #define TX_TXPKTRDY_OFST                          (16)
    2542. 

  2542. #define TX_TXMAXPKTSZ_OFST                        (0)
    2543. 

  2543. 

  2544. /* U3D_TX14CSR1 */
    2545. 

  2545. #define TX_MULT_OFST                              (22)
    2546. 

  2546. #define TX_MAX_PKT_OFST                           (16)
    2547. 

  2547. #define TX_SLOT_OFST                              (8)
    2548. 

  2548. #define TXTYPE_OFST                               (4)
    2549. 

  2549. #define SS_TX_BURST_OFST                          (0)
    2550. 

  2550. 

  2551. /* U3D_TX14CSR2 */
    2552. 

  2552. #define TXBINTERVAL_OFST                          (24)
    2553. 

  2553. #define TXFIFOSEGSIZE_OFST                        (16)
    2554. 

  2554. #define TXFIFOADDR_OFST                           (0)
    2555. 

  2555. 

  2556. /* U3D_TX15CSR0 */
    2557. 

  2557. #define TX_EP_RESET_OFST                          (31)
    2558. 

  2558. #define TX_AUTOSET_OFST                           (30)
    2559. 

  2559. #define TX_DMAREQEN_OFST                          (29)
    2560. 

  2560. #define TX_FIFOFULL_OFST                          (25)
    2561. 

  2561. #define TX_FIFOEMPTY_OFST                         (24)
    2562. 

  2562. #define TX_SENTSTALL_OFST                         (22)
    2563. 

  2563. #define TX_SENDSTALL_OFST                         (21)
    2564. 

  2564. #define TX_TXPKTRDY_OFST                          (16)
    2565. 

  2565. #define TX_TXMAXPKTSZ_OFST                        (0)
    2566. 

  2566. 

  2567. /* U3D_TX15CSR1 */
    2568. 

  2568. #define TX_MULT_OFST                              (22)
    2569. 

  2569. #define TX_MAX_PKT_OFST                           (16)
    2570. 

  2570. #define TX_SLOT_OFST                              (8)
    2571. 

  2571. #define TXTYPE_OFST                               (4)
    2572. 

  2572. #define SS_TX_BURST_OFST                          (0)
    2573. 

  2573. 

  2574. /* U3D_TX15CSR2 */
    2575. 

  2575. #define TXBINTERVAL_OFST                          (24)
    2576. 

  2576. #define TXFIFOSEGSIZE_OFST                        (16)
    2577. 

  2577. #define TXFIFOADDR_OFST                           (0)
    2578. 

  2578. 

  2579. /* U3D_RX1CSR0 */
    2580. 

  2580. #define RX_EP_RESET_OFST                          (31)
    2581. 

  2581. #define RX_AUTOCLEAR_OFST                         (30)
    2582. 

  2582. #define RX_DMAREQEN_OFST                          (29)
    2583. 

  2583. #define RX_SENTSTALL_OFST                         (22)
    2584. 

  2584. #define RX_SENDSTALL_OFST                         (21)
    2585. 

  2585. #define RX_FIFOFULL_OFST                          (18)
    2586. 

  2586. #define RX_FIFOEMPTY_OFST                         (17)
    2587. 

  2587. #define RX_RXPKTRDY_OFST                          (16)
    2588. 

  2588. #define RX_RXMAXPKTSZ_OFST                        (0)
    2589. 

  2589. 

  2590. /* U3D_RX1CSR1 */
    2591. 

  2591. #define RX_MULT_OFST                              (22)
    2592. 

  2592. #define RX_MAX_PKT_OFST                           (16)
    2593. 

  2593. #define RX_SLOT_OFST                              (8)
    2594. 

  2594. #define RX_TYPE_OFST                              (4)
    2595. 

  2595. #define SS_RX_BURST_OFST                          (0)
    2596. 

  2596. 

  2597. /* U3D_RX1CSR2 */
    2598. 

  2598. #define RXBINTERVAL_OFST                          (24)
    2599. 

  2599. #define RXFIFOSEGSIZE_OFST                        (16)
    2600. 

  2600. #define RXFIFOADDR_OFST                           (0)
    2601. 

  2601. 

  2602. /* U3D_RX1CSR3 */
    2603. 

  2603. #define EP_RX_COUNT_OFST                          (16)
    2604. 

  2604. 

  2605. /* U3D_RX2CSR0 */
    2606. 

  2606. #define RX_EP_RESET_OFST                          (31)
    2607. 

  2607. #define RX_AUTOCLEAR_OFST                         (30)
    2608. 

  2608. #define RX_DMAREQEN_OFST                          (29)
    2609. 

  2609. #define RX_SENTSTALL_OFST                         (22)
    2610. 

  2610. #define RX_SENDSTALL_OFST                         (21)
    2611. 

  2611. #define RX_FIFOFULL_OFST                          (18)
    2612. 

  2612. #define RX_FIFOEMPTY_OFST                         (17)
    2613. 

  2613. #define RX_RXPKTRDY_OFST                          (16)
    2614. 

  2614. #define RX_RXMAXPKTSZ_OFST                        (0)
    2615. 

  2615. 

  2616. /* U3D_RX2CSR1 */
    2617. 

  2617. #define RX_MULT_OFST                              (22)
    2618. 

  2618. #define RX_MAX_PKT_OFST                           (16)
    2619. 

  2619. #define RX_SLOT_OFST                              (8)
    2620. 

  2620. #define RX_TYPE_OFST                              (4)
    2621. 

  2621. #define SS_RX_BURST_OFST                          (0)
    2622. 

  2622. 

  2623. /* U3D_RX2CSR2 */
    2624. 

  2624. #define RXBINTERVAL_OFST                          (24)
    2625. 

  2625. #define RXFIFOSEGSIZE_OFST                        (16)
    2626. 

  2626. #define RXFIFOADDR_OFST                           (0)
    2627. 

  2627. 

  2628. /* U3D_RX2CSR3 */
    2629. 

  2629. #define EP_RX_COUNT_OFST                          (16)
    2630. 

  2630. 

  2631. /* U3D_RX3CSR0 */
    2632. 

  2632. #define RX_EP_RESET_OFST                          (31)
    2633. 

  2633. #define RX_AUTOCLEAR_OFST                         (30)
    2634. 

  2634. #define RX_DMAREQEN_OFST                          (29)
    2635. 

  2635. #define RX_SENTSTALL_OFST                         (22)
    2636. 

  2636. #define RX_SENDSTALL_OFST                         (21)
    2637. 

  2637. #define RX_FIFOFULL_OFST                          (18)
    2638. 

  2638. #define RX_FIFOEMPTY_OFST                         (17)
    2639. 

  2639. #define RX_RXPKTRDY_OFST                          (16)
    2640. 

  2640. #define RX_RXMAXPKTSZ_OFST                        (0)
    2641. 

  2641. 

  2642. /* U3D_RX3CSR1 */
    2643. 

  2643. #define RX_MULT_OFST                              (22)
    2644. 

  2644. #define RX_MAX_PKT_OFST                           (16)
    2645. 

  2645. #define RX_SLOT_OFST                              (8)
    2646. 

  2646. #define RX_TYPE_OFST                              (4)
    2647. 

  2647. #define SS_RX_BURST_OFST                          (0)
    2648. 

  2648. 

  2649. /* U3D_RX3CSR2 */
    2650. 

  2650. #define RXBINTERVAL_OFST                          (24)
    2651. 

  2651. #define RXFIFOSEGSIZE_OFST                        (16)
    2652. 

  2652. #define RXFIFOADDR_OFST                           (0)
    2653. 

  2653. 

  2654. /* U3D_RX3CSR3 */
    2655. 

  2655. #define EP_RX_COUNT_OFST                          (16)
    2656. 

  2656. 

  2657. /* U3D_RX4CSR0 */
    2658. 

  2658. #define RX_EP_RESET_OFST                          (31)
    2659. 

  2659. #define RX_AUTOCLEAR_OFST                         (30)
    2660. 

  2660. #define RX_DMAREQEN_OFST                          (29)
    2661. 

  2661. #define RX_SENTSTALL_OFST                         (22)
    2662. 

  2662. #define RX_SENDSTALL_OFST                         (21)
    2663. 

  2663. #define RX_FIFOFULL_OFST                          (18)
    2664. 

  2664. #define RX_FIFOEMPTY_OFST                         (17)
    2665. 

  2665. #define RX_RXPKTRDY_OFST                          (16)
    2666. 

  2666. #define RX_RXMAXPKTSZ_OFST                        (0)
    2667. 

  2667. 

  2668. /* U3D_RX4CSR1 */
    2669. 

  2669. #define RX_MULT_OFST                              (22)
    2670. 

  2670. #define RX_MAX_PKT_OFST                           (16)
    2671. 

  2671. #define RX_SLOT_OFST                              (8)
    2672. 

  2672. #define RX_TYPE_OFST                              (4)
    2673. 

  2673. #define SS_RX_BURST_OFST                          (0)
    2674. 

  2674. 

  2675. /* U3D_RX4CSR2 */
    2676. 

  2676. #define RXBINTERVAL_OFST                          (24)
    2677. 

  2677. #define RXFIFOSEGSIZE_OFST                        (16)
    2678. 

  2678. #define RXFIFOADDR_OFST                           (0)
    2679. 

  2679. 

  2680. /* U3D_RX4CSR3 */
    2681. 

  2681. #define EP_RX_COUNT_OFST                          (16)
    2682. 

  2682. 

  2683. /* U3D_RX5CSR0 */
    2684. 

  2684. #define RX_EP_RESET_OFST                          (31)
    2685. 

  2685. #define RX_AUTOCLEAR_OFST                         (30)
    2686. 

  2686. #define RX_DMAREQEN_OFST                          (29)
    2687. 

  2687. #define RX_SENTSTALL_OFST                         (22)
    2688. 

  2688. #define RX_SENDSTALL_OFST                         (21)
    2689. 

  2689. #define RX_FIFOFULL_OFST                          (18)
    2690. 

  2690. #define RX_FIFOEMPTY_OFST                         (17)
    2691. 

  2691. #define RX_RXPKTRDY_OFST                          (16)
    2692. 

  2692. #define RX_RXMAXPKTSZ_OFST                        (0)
    2693. 

  2693. 

  2694. /* U3D_RX5CSR1 */
    2695. 

  2695. #define RX_MULT_OFST                              (22)
    2696. 

  2696. #define RX_MAX_PKT_OFST                           (16)
    2697. 

  2697. #define RX_SLOT_OFST                              (8)
    2698. 

  2698. #define RX_TYPE_OFST                              (4)
    2699. 

  2699. #define SS_RX_BURST_OFST                          (0)
    2700. 

  2700. 

  2701. /* U3D_RX5CSR2 */
    2702. 

  2702. #define RXBINTERVAL_OFST                          (24)
    2703. 

  2703. #define RXFIFOSEGSIZE_OFST                        (16)
    2704. 

  2704. #define RXFIFOADDR_OFST                           (0)
    2705. 

  2705. 

  2706. /* U3D_RX5CSR3 */
    2707. 

  2707. #define EP_RX_COUNT_OFST                          (16)
    2708. 

  2708. 

  2709. /* U3D_RX6CSR0 */
    2710. 

  2710. #define RX_EP_RESET_OFST                          (31)
    2711. 

  2711. #define RX_AUTOCLEAR_OFST                         (30)
    2712. 

  2712. #define RX_DMAREQEN_OFST                          (29)
    2713. 

  2713. #define RX_SENTSTALL_OFST                         (22)
    2714. 

  2714. #define RX_SENDSTALL_OFST                         (21)
    2715. 

  2715. #define RX_FIFOFULL_OFST                          (18)
    2716. 

  2716. #define RX_FIFOEMPTY_OFST                         (17)
    2717. 

  2717. #define RX_RXPKTRDY_OFST                          (16)
    2718. 

  2718. #define RX_RXMAXPKTSZ_OFST                        (0)
    2719. 

  2719. 

  2720. /* U3D_RX6CSR1 */
    2721. 

  2721. #define RX_MULT_OFST                              (22)
    2722. 

  2722. #define RX_MAX_PKT_OFST                           (16)
    2723. 

  2723. #define RX_SLOT_OFST                              (8)
    2724. 

  2724. #define RX_TYPE_OFST                              (4)
    2725. 

  2725. #define SS_RX_BURST_OFST                          (0)
    2726. 

  2726. 

  2727. /* U3D_RX6CSR2 */
    2728. 

  2728. #define RXBINTERVAL_OFST                          (24)
    2729. 

  2729. #define RXFIFOSEGSIZE_OFST                        (16)
    2730. 

  2730. #define RXFIFOADDR_OFST                           (0)
    2731. 

  2731. 

  2732. /* U3D_RX6CSR3 */
    2733. 

  2733. #define EP_RX_COUNT_OFST                          (16)
    2734. 

  2734. 

  2735. /* U3D_RX7CSR0 */
    2736. 

  2736. #define RX_EP_RESET_OFST                          (31)
    2737. 

  2737. #define RX_AUTOCLEAR_OFST                         (30)
    2738. 

  2738. #define RX_DMAREQEN_OFST                          (29)
    2739. 

  2739. #define RX_SENTSTALL_OFST                         (22)
    2740. 

  2740. #define RX_SENDSTALL_OFST                         (21)
    2741. 

  2741. #define RX_FIFOFULL_OFST                          (18)
    2742. 

  2742. #define RX_FIFOEMPTY_OFST                         (17)
    2743. 

  2743. #define RX_RXPKTRDY_OFST                          (16)
    2744. 

  2744. #define RX_RXMAXPKTSZ_OFST                        (0)
    2745. 

  2745. 

  2746. /* U3D_RX7CSR1 */
    2747. 

  2747. #define RX_MULT_OFST                              (22)
    2748. 

  2748. #define RX_MAX_PKT_OFST                           (16)
    2749. 

  2749. #define RX_SLOT_OFST                              (8)
    2750. 

  2750. #define RX_TYPE_OFST                              (4)
    2751. 

  2751. #define SS_RX_BURST_OFST                          (0)
    2752. 

  2752. 

  2753. /* U3D_RX7CSR2 */
    2754. 

  2754. #define RXBINTERVAL_OFST                          (24)
    2755. 

  2755. #define RXFIFOSEGSIZE_OFST                        (16)
    2756. 

  2756. #define RXFIFOADDR_OFST                           (0)
    2757. 

  2757. 

  2758. /* U3D_RX7CSR3 */
    2759. 

  2759. #define EP_RX_COUNT_OFST                          (16)
    2760. 

  2760. 

  2761. /* U3D_RX8CSR0 */
    2762. 

  2762. #define RX_EP_RESET_OFST                          (31)
    2763. 

  2763. #define RX_AUTOCLEAR_OFST                         (30)
    2764. 

  2764. #define RX_DMAREQEN_OFST                          (29)
    2765. 

  2765. #define RX_SENTSTALL_OFST                         (22)
    2766. 

  2766. #define RX_SENDSTALL_OFST                         (21)
    2767. 

  2767. #define RX_FIFOFULL_OFST                          (18)
    2768. 

  2768. #define RX_FIFOEMPTY_OFST                         (17)
    2769. 

  2769. #define RX_RXPKTRDY_OFST                          (16)
    2770. 

  2770. #define RX_RXMAXPKTSZ_OFST                        (0)
    2771. 

  2771. 

  2772. /* U3D_RX8CSR1 */
    2773. 

  2773. #define RX_MULT_OFST                              (22)
    2774. 

  2774. #define RX_MAX_PKT_OFST                           (16)
    2775. 

  2775. #define RX_SLOT_OFST                              (8)
    2776. 

  2776. #define RX_TYPE_OFST                              (4)
    2777. 

  2777. #define SS_RX_BURST_OFST                          (0)
    2778. 

  2778. 

  2779. /* U3D_RX8CSR2 */
    2780. 

  2780. #define RXBINTERVAL_OFST                          (24)
    2781. 

  2781. #define RXFIFOSEGSIZE_OFST                        (16)
    2782. 

  2782. #define RXFIFOADDR_OFST                           (0)
    2783. 

  2783. 

  2784. /* U3D_RX8CSR3 */
    2785. 

  2785. #define EP_RX_COUNT_OFST                          (16)
    2786. 

  2786. 

  2787. /* U3D_RX9CSR0 */
    2788. 

  2788. #define RX_EP_RESET_OFST                          (31)
    2789. 

  2789. #define RX_AUTOCLEAR_OFST                         (30)
    2790. 

  2790. #define RX_DMAREQEN_OFST                          (29)
    2791. 

  2791. #define RX_SENTSTALL_OFST                         (22)
    2792. 

  2792. #define RX_SENDSTALL_OFST                         (21)
    2793. 

  2793. #define RX_FIFOFULL_OFST                          (18)
    2794. 

  2794. #define RX_FIFOEMPTY_OFST                         (17)
    2795. 

  2795. #define RX_RXPKTRDY_OFST                          (16)
    2796. 

  2796. #define RX_RXMAXPKTSZ_OFST                        (0)
    2797. 

  2797. 

  2798. /* U3D_RX9CSR1 */
    2799. 

  2799. #define RX_MULT_OFST                              (22)
    2800. 

  2800. #define RX_MAX_PKT_OFST                           (16)
    2801. 

  2801. #define RX_SLOT_OFST                              (8)
    2802. 

  2802. #define RX_TYPE_OFST                              (4)
    2803. 

  2803. #define SS_RX_BURST_OFST                          (0)
    2804. 

  2804. 

  2805. /* U3D_RX9CSR2 */
    2806. 

  2806. #define RXBINTERVAL_OFST                          (24)
    2807. 

  2807. #define RXFIFOSEGSIZE_OFST                        (16)
    2808. 

  2808. #define RXFIFOADDR_OFST                           (0)
    2809. 

  2809. 

  2810. /* U3D_RX9CSR3 */
    2811. 

  2811. #define EP_RX_COUNT_OFST                          (16)
    2812. 

  2812. 

  2813. /* U3D_RX10CSR0 */
    2814. 

  2814. #define RX_EP_RESET_OFST                          (31)
    2815. 

  2815. #define RX_AUTOCLEAR_OFST                         (30)
    2816. 

  2816. #define RX_DMAREQEN_OFST                          (29)
    2817. 

  2817. #define RX_SENTSTALL_OFST                         (22)
    2818. 

  2818. #define RX_SENDSTALL_OFST                         (21)
    2819. 

  2819. #define RX_FIFOFULL_OFST                          (18)
    2820. 

  2820. #define RX_FIFOEMPTY_OFST                         (17)
    2821. 

  2821. #define RX_RXPKTRDY_OFST                          (16)
    2822. 

  2822. #define RX_RXMAXPKTSZ_OFST                        (0)
    2823. 

  2823. 

  2824. /* U3D_RX10CSR1 */
    2825. 

  2825. #define RX_MULT_OFST                              (22)
    2826. 

  2826. #define RX_MAX_PKT_OFST                           (16)
    2827. 

  2827. #define RX_SLOT_OFST                              (8)
    2828. 

  2828. #define RX_TYPE_OFST                              (4)
    2829. 

  2829. #define SS_RX_BURST_OFST                          (0)
    2830. 

  2830. 

  2831. /* U3D_RX10CSR2 */
    2832. 

  2832. #define RXBINTERVAL_OFST                          (24)
    2833. 

  2833. #define RXFIFOSEGSIZE_OFST                        (16)
    2834. 

  2834. #define RXFIFOADDR_OFST                           (0)
    2835. 

  2835. 

  2836. /* U3D_RX10CSR3 */
    2837. 

  2837. #define EP_RX_COUNT_OFST                          (16)
    2838. 

  2838. 

  2839. /* U3D_RX11CSR0 */
    2840. 

  2840. #define RX_EP_RESET_OFST                          (31)
    2841. 

  2841. #define RX_AUTOCLEAR_OFST                         (30)
    2842. 

  2842. #define RX_DMAREQEN_OFST                          (29)
    2843. 

  2843. #define RX_SENTSTALL_OFST                         (22)
    2844. 

  2844. #define RX_SENDSTALL_OFST                         (21)
    2845. 

  2845. #define RX_FIFOFULL_OFST                          (18)
    2846. 

  2846. #define RX_FIFOEMPTY_OFST                         (17)
    2847. 

  2847. #define RX_RXPKTRDY_OFST                          (16)
    2848. 

  2848. #define RX_RXMAXPKTSZ_OFST                        (0)
    2849. 

  2849. 

  2850. /* U3D_RX11CSR1 */
    2851. 

  2851. #define RX_MULT_OFST                              (22)
    2852. 

  2852. #define RX_MAX_PKT_OFST                           (16)
    2853. 

  2853. #define RX_SLOT_OFST                              (8)
    2854. 

  2854. #define RX_TYPE_OFST                              (4)
    2855. 

  2855. #define SS_RX_BURST_OFST                          (0)
    2856. 

  2856. 

  2857. /* U3D_RX11CSR2 */
    2858. 

  2858. #define RXBINTERVAL_OFST                          (24)
    2859. 

  2859. #define RXFIFOSEGSIZE_OFST                        (16)
    2860. 

  2860. #define RXFIFOADDR_OFST                           (0)
    2861. 

  2861. 

  2862. /* U3D_RX11CSR3 */
    2863. 

  2863. #define EP_RX_COUNT_OFST                          (16)
    2864. 

  2864. 

  2865. /* U3D_RX12CSR0 */
    2866. 

  2866. #define RX_EP_RESET_OFST                          (31)
    2867. 

  2867. #define RX_AUTOCLEAR_OFST                         (30)
    2868. 

  2868. #define RX_DMAREQEN_OFST                          (29)
    2869. 

  2869. #define RX_SENTSTALL_OFST                         (22)
    2870. 

  2870. #define RX_SENDSTALL_OFST                         (21)
    2871. 

  2871. #define RX_FIFOFULL_OFST                          (18)
    2872. 

  2872. #define RX_FIFOEMPTY_OFST                         (17)
    2873. 

  2873. #define RX_RXPKTRDY_OFST                          (16)
    2874. 

  2874. #define RX_RXMAXPKTSZ_OFST                        (0)
    2875. 

  2875. 

  2876. /* U3D_RX12CSR1 */
    2877. 

  2877. #define RX_MULT_OFST                              (22)
    2878. 

  2878. #define RX_MAX_PKT_OFST                           (16)
    2879. 

  2879. #define RX_SLOT_OFST                              (8)
    2880. 

  2880. #define RX_TYPE_OFST                              (4)
    2881. 

  2881. #define SS_RX_BURST_OFST                          (0)
    2882. 

  2882. 

  2883. /* U3D_RX12CSR2 */
    2884. 

  2884. #define RXBINTERVAL_OFST                          (24)
    2885. 

  2885. #define RXFIFOSEGSIZE_OFST                        (16)
    2886. 

  2886. #define RXFIFOADDR_OFST                           (0)
    2887. 

  2887. 

  2888. /* U3D_RX12CSR3 */
    2889. 

  2889. #define EP_RX_COUNT_OFST                          (16)
    2890. 

  2890. 

  2891. /* U3D_RX13CSR0 */
    2892. 

  2892. #define RX_EP_RESET_OFST                          (31)
    2893. 

  2893. #define RX_AUTOCLEAR_OFST                         (30)
    2894. 

  2894. #define RX_DMAREQEN_OFST                          (29)
    2895. 

  2895. #define RX_SENTSTALL_OFST                         (22)
    2896. 

  2896. #define RX_SENDSTALL_OFST                         (21)
    2897. 

  2897. #define RX_FIFOFULL_OFST                          (18)
    2898. 

  2898. #define RX_FIFOEMPTY_OFST                         (17)
    2899. 

  2899. #define RX_RXPKTRDY_OFST                          (16)
    2900. 

  2900. #define RX_RXMAXPKTSZ_OFST                        (0)
    2901. 

  2901. 

  2902. /* U3D_RX13CSR1 */
    2903. 

  2903. #define RX_MULT_OFST                              (22)
    2904. 

  2904. #define RX_MAX_PKT_OFST                           (16)
    2905. 

  2905. #define RX_SLOT_OFST                              (8)
    2906. 

  2906. #define RX_TYPE_OFST                              (4)
    2907. 

  2907. #define SS_RX_BURST_OFST                          (0)
    2908. 

  2908. 

  2909. /* U3D_RX13CSR2 */
    2910. 

  2910. #define RXBINTERVAL_OFST                          (24)
    2911. 

  2911. #define RXFIFOSEGSIZE_OFST                        (16)
    2912. 

  2912. #define RXFIFOADDR_OFST                           (0)
    2913. 

  2913. 

  2914. /* U3D_RX13CSR3 */
    2915. 

  2915. #define EP_RX_COUNT_OFST                          (16)
    2916. 

  2916. 

  2917. /* U3D_RX14CSR0 */
    2918. 

  2918. #define RX_EP_RESET_OFST                          (31)
    2919. 

  2919. #define RX_AUTOCLEAR_OFST                         (30)
    2920. 

  2920. #define RX_DMAREQEN_OFST                          (29)
    2921. 

  2921. #define RX_SENTSTALL_OFST                         (22)
    2922. 

  2922. #define RX_SENDSTALL_OFST                         (21)
    2923. 

  2923. #define RX_FIFOFULL_OFST                          (18)
    2924. 

  2924. #define RX_FIFOEMPTY_OFST                         (17)
    2925. 

  2925. #define RX_RXPKTRDY_OFST                          (16)
    2926. 

  2926. #define RX_RXMAXPKTSZ_OFST                        (0)
    2927. 

  2927. 

  2928. /* U3D_RX14CSR1 */
    2929. 

  2929. #define RX_MULT_OFST                              (22)
    2930. 

  2930. #define RX_MAX_PKT_OFST                           (16)
    2931. 

  2931. #define RX_SLOT_OFST                              (8)
    2932. 

  2932. #define RX_TYPE_OFST                              (4)
    2933. 

  2933. #define SS_RX_BURST_OFST                          (0)
    2934. 

  2934. 

  2935. /* U3D_RX14CSR2 */
    2936. 

  2936. #define RXBINTERVAL_OFST                          (24)
    2937. 

  2937. #define RXFIFOSEGSIZE_OFST                        (16)
    2938. 

  2938. #define RXFIFOADDR_OFST                           (0)
    2939. 

  2939. 

  2940. /* U3D_RX14CSR3 */
    2941. 

  2941. #define EP_RX_COUNT_OFST                          (16)
    2942. 

  2942. 

  2943. /* U3D_RX15CSR0 */
    2944. 

  2944. #define RX_EP_RESET_OFST                          (31)
    2945. 

  2945. #define RX_AUTOCLEAR_OFST                         (30)
    2946. 

  2946. #define RX_DMAREQEN_OFST                          (29)
    2947. 

  2947. #define RX_SENTSTALL_OFST                         (22)
    2948. 

  2948. #define RX_SENDSTALL_OFST                         (21)
    2949. 

  2949. #define RX_FIFOFULL_OFST                          (18)
    2950. 

  2950. #define RX_FIFOEMPTY_OFST                         (17)
    2951. 

  2951. #define RX_RXPKTRDY_OFST                          (16)
    2952. 

  2952. #define RX_RXMAXPKTSZ_OFST                        (0)
    2953. 

  2953. 

  2954. /* U3D_RX15CSR1 */
    2955. 

  2955. #define RX_MULT_OFST                              (22)
    2956. 

  2956. #define RX_MAX_PKT_OFST                           (16)
    2957. 

  2957. #define RX_SLOT_OFST                              (8)
    2958. 

  2958. #define RX_TYPE_OFST                              (4)
    2959. 

  2959. #define SS_RX_BURST_OFST                          (0)
    2960. 

  2960. 

  2961. /* U3D_RX15CSR2 */
    2962. 

  2962. #define RXBINTERVAL_OFST                          (24)
    2963. 

  2963. #define RXFIFOSEGSIZE_OFST                        (16)
    2964. 

  2964. #define RXFIFOADDR_OFST                           (0)
    2965. 

  2965. 

  2966. /* U3D_RX15CSR3 */
    2967. 

  2967. #define EP_RX_COUNT_OFST                          (16)
    2968. 

  2968. 

  2969. /* U3D_FIFO0 */
    2970. 

  2970. #define BYTE3_OFST                                (24)
    2971. 

  2971. #define BYTE2_OFST                                (16)
    2972. 

  2972. #define BYTE1_OFST                                (8)
    2973. 

  2973. #define BYTE0_OFST                                (0)
    2974. 

  2974. 

  2975. /* U3D_FIFO1 */
    2976. 

  2976. #define BYTE3_OFST                                (24)
    2977. 

  2977. #define BYTE2_OFST                                (16)
    2978. 

  2978. #define BYTE1_OFST                                (8)
    2979. 

  2979. #define BYTE0_OFST                                (0)
    2980. 

  2980. 

  2981. /* U3D_FIFO2 */
    2982. 

  2982. #define BYTE3_OFST                                (24)
    2983. 

  2983. #define BYTE2_OFST                                (16)
    2984. 

  2984. #define BYTE1_OFST                                (8)
    2985. 

  2985. #define BYTE0_OFST                                (0)
    2986. 

  2986. 

  2987. /* U3D_FIFO3 */
    2988. 

  2988. #define BYTE3_OFST                                (24)
    2989. 

  2989. #define BYTE2_OFST                                (16)
    2990. 

  2990. #define BYTE1_OFST                                (8)
    2991. 

  2991. #define BYTE0_OFST                                (0)
    2992. 

  2992. 

  2993. /* U3D_FIFO4 */
    2994. 

  2994. #define BYTE3_OFST                                (24)
    2995. 

  2995. #define BYTE2_OFST                                (16)
    2996. 

  2996. #define BYTE1_OFST                                (8)
    2997. 

  2997. #define BYTE0_OFST                                (0)
    2998. 

  2998. 

  2999. /* U3D_FIFO5 */
    3000. 

  3000. #define BYTE3_OFST                                (24)
    3001. 

  3001. #define BYTE2_OFST                                (16)
    3002. 

  3002. #define BYTE1_OFST                                (8)
    3003. 

  3003. #define BYTE0_OFST                                (0)
    3004. 

  3004. 

  3005. /* U3D_FIFO6 */
    3006. 

  3006. #define BYTE3_OFST                                (24)
    3007. 

  3007. #define BYTE2_OFST                                (16)
    3008. 

  3008. #define BYTE1_OFST                                (8)
    3009. 

  3009. #define BYTE0_OFST                                (0)
    3010. 

  3010. 

  3011. /* U3D_FIFO7 */
    3012. 

  3012. #define BYTE3_OFST                                (24)
    3013. 

  3013. #define BYTE2_OFST                                (16)
    3014. 

  3014. #define BYTE1_OFST                                (8)
    3015. 

  3015. #define BYTE0_OFST                                (0)
    3016. 

  3016. 

  3017. /* U3D_FIFO8 */
    3018. 

  3018. #define BYTE3_OFST                                (24)
    3019. 

  3019. #define BYTE2_OFST                                (16)
    3020. 

  3020. #define BYTE1_OFST                                (8)
    3021. 

  3021. #define BYTE0_OFST                                (0)
    3022. 

  3022. 

  3023. /* U3D_FIFO9 */
    3024. 

  3024. #define BYTE3_OFST                                (24)
    3025. 

  3025. #define BYTE2_OFST                                (16)
    3026. 

  3026. #define BYTE1_OFST                                (8)
    3027. 

  3027. #define BYTE0_OFST                                (0)
    3028. 

  3028. 

  3029. /* U3D_FIFO10 */
    3030. 

  3030. #define BYTE3_OFST                                (24)
    3031. 

  3031. #define BYTE2_OFST                                (16)
    3032. 

  3032. #define BYTE1_OFST                                (8)
    3033. 

  3033. #define BYTE0_OFST                                (0)
    3034. 

  3034. 

  3035. /* U3D_FIFO11 */
    3036. 

  3036. #define BYTE3_OFST                                (24)
    3037. 

  3037. #define BYTE2_OFST                                (16)
    3038. 

  3038. #define BYTE1_OFST                                (8)
    3039. 

  3039. #define BYTE0_OFST                                (0)
    3040. 

  3040. 

  3041. /* U3D_FIFO12 */
    3042. 

  3042. #define BYTE3_OFST                                (24)
    3043. 

  3043. #define BYTE2_OFST                                (16)
    3044. 

  3044. #define BYTE1_OFST                                (8)
    3045. 

  3045. #define BYTE0_OFST                                (0)
    3046. 

  3046. 

  3047. /* U3D_FIFO13 */
    3048. 

  3048. #define BYTE3_OFST                                (24)
    3049. 

  3049. #define BYTE2_OFST                                (16)
    3050. 

  3050. #define BYTE1_OFST                                (8)
    3051. 

  3051. #define BYTE0_OFST                                (0)
    3052. 

  3052. 

  3053. /* U3D_FIFO14 */
    3054. 

  3054. #define BYTE3_OFST                                (24)
    3055. 

  3055. #define BYTE2_OFST                                (16)
    3056. 

  3056. #define BYTE1_OFST                                (8)
    3057. 

  3057. #define BYTE0_OFST                                (0)
    3058. 

  3058. 

  3059. /* U3D_FIFO15 */
    3060. 

  3060. #define BYTE3_OFST                                (24)
    3061. 

  3061. #define BYTE2_OFST                                (16)
    3062. 

  3062. #define BYTE1_OFST                                (8)
    3063. 

  3063. #define BYTE0_OFST                                (0)
    3064. 

  3064. 

  3065. /* U3D_QCR0 */
    3066. 

  3066. #define RXQ_CS_EN_OFST                            (17)
    3067. 

  3067. #define TXQ_CS_EN_OFST                            (1)
    3068. 

  3068. #define CS16B_EN_OFST                             (0)
    3069. 

  3069. 

  3070. /* U3D_QCR1 */
    3071. 

  3071. #define CFG_TX_ZLP_GPD_OFST                       (1)
    3072. 

  3072. 

  3073. /* U3D_QCR2 */
    3074. 

  3074. #define CFG_TX_ZLP_OFST                           (1)
    3075. 

  3075. 

  3076. /* U3D_QCR3 */
    3077. 

  3077. #define CFG_RX_COZ_OFST                           (17)
    3078. 

  3078. #define CFG_RX_ZLP_OFST                           (1)
    3079. 

  3079. 

  3080. /* U3D_QGCSR */
    3081. 

  3081. #define RXQ_EN_OFST                               (17)
    3082. 

  3082. #define TXQ_EN_OFST                               (1)
    3083. 

  3083. 

  3084. /* U3D_TXQCSR1 */
    3085. 

  3085. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3086. 

  3086. #define TXQ_ACTIVE_OFST                           (15)
    3087. 

  3087. #define TXQ_EPQ_STATE_OFST                        (8)
    3088. 

  3088. #define TXQ_STOP_OFST                             (2)
    3089. 

  3089. #define TXQ_RESUME_OFST                           (1)
    3090. 

  3090. #define TXQ_START_OFST                            (0)
    3091. 

  3091. 

  3092. /* U3D_TXQSAR1 */
    3093. 

  3093. #define TXQ_START_ADDR_OFST                       (2)
    3094. 

  3094. 

  3095. /* U3D_TXQCPR1 */
    3096. 

  3096. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3097. 

  3097. 

  3098. /* U3D_TXQCSR2 */
    3099. 

  3099. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3100. 

  3100. #define TXQ_ACTIVE_OFST                           (15)
    3101. 

  3101. #define TXQ_EPQ_STATE_OFST                        (8)
    3102. 

  3102. #define TXQ_STOP_OFST                             (2)
    3103. 

  3103. #define TXQ_RESUME_OFST                           (1)
    3104. 

  3104. #define TXQ_START_OFST                            (0)
    3105. 

  3105. 

  3106. /* U3D_TXQSAR2 */
    3107. 

  3107. #define TXQ_START_ADDR_OFST                       (2)
    3108. 

  3108. 

  3109. /* U3D_TXQCPR2 */
    3110. 

  3110. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3111. 

  3111. 

  3112. /* U3D_TXQCSR3 */
    3113. 

  3113. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3114. 

  3114. #define TXQ_ACTIVE_OFST                           (15)
    3115. 

  3115. #define TXQ_EPQ_STATE_OFST                        (8)
    3116. 

  3116. #define TXQ_STOP_OFST                             (2)
    3117. 

  3117. #define TXQ_RESUME_OFST                           (1)
    3118. 

  3118. #define TXQ_START_OFST                            (0)
    3119. 

  3119. 

  3120. /* U3D_TXQSAR3 */
    3121. 

  3121. #define TXQ_START_ADDR_OFST                       (2)
    3122. 

  3122. 

  3123. /* U3D_TXQCPR3 */
    3124. 

  3124. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3125. 

  3125. 

  3126. /* U3D_TXQCSR4 */
    3127. 

  3127. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3128. 

  3128. #define TXQ_ACTIVE_OFST                           (15)
    3129. 

  3129. #define TXQ_EPQ_STATE_OFST                        (8)
    3130. 

  3130. #define TXQ_STOP_OFST                             (2)
    3131. 

  3131. #define TXQ_RESUME_OFST                           (1)
    3132. 

  3132. #define TXQ_START_OFST                            (0)
    3133. 

  3133. 

  3134. /* U3D_TXQSAR4 */
    3135. 

  3135. #define TXQ_START_ADDR_OFST                       (2)
    3136. 

  3136. 

  3137. /* U3D_TXQCPR4 */
    3138. 

  3138. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3139. 

  3139. 

  3140. /* U3D_TXQCSR5 */
    3141. 

  3141. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3142. 

  3142. #define TXQ_ACTIVE_OFST                           (15)
    3143. 

  3143. #define TXQ_EPQ_STATE_OFST                        (8)
    3144. 

  3144. #define TXQ_STOP_OFST                             (2)
    3145. 

  3145. #define TXQ_RESUME_OFST                           (1)
    3146. 

  3146. #define TXQ_START_OFST                            (0)
    3147. 

  3147. 

  3148. /* U3D_TXQSAR5 */
    3149. 

  3149. #define TXQ_START_ADDR_OFST                       (2)
    3150. 

  3150. 

  3151. /* U3D_TXQCPR5 */
    3152. 

  3152. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3153. 

  3153. 

  3154. /* U3D_TXQCSR6 */
    3155. 

  3155. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3156. 

  3156. #define TXQ_ACTIVE_OFST                           (15)
    3157. 

  3157. #define TXQ_EPQ_STATE_OFST                        (8)
    3158. 

  3158. #define TXQ_STOP_OFST                             (2)
    3159. 

  3159. #define TXQ_RESUME_OFST                           (1)
    3160. 

  3160. #define TXQ_START_OFST                            (0)
    3161. 

  3161. 

  3162. /* U3D_TXQSAR6 */
    3163. 

  3163. #define TXQ_START_ADDR_OFST                       (2)
    3164. 

  3164. 

  3165. /* U3D_TXQCPR6 */
    3166. 

  3166. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3167. 

  3167. 

  3168. /* U3D_TXQCSR7 */
    3169. 

  3169. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3170. 

  3170. #define TXQ_ACTIVE_OFST                           (15)
    3171. 

  3171. #define TXQ_EPQ_STATE_OFST                        (8)
    3172. 

  3172. #define TXQ_STOP_OFST                             (2)
    3173. 

  3173. #define TXQ_RESUME_OFST                           (1)
    3174. 

  3174. #define TXQ_START_OFST                            (0)
    3175. 

  3175. 

  3176. /* U3D_TXQSAR7 */
    3177. 

  3177. #define TXQ_START_ADDR_OFST                       (2)
    3178. 

  3178. 

  3179. /* U3D_TXQCPR7 */
    3180. 

  3180. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3181. 

  3181. 

  3182. /* U3D_TXQCSR8 */
    3183. 

  3183. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3184. 

  3184. #define TXQ_ACTIVE_OFST                           (15)
    3185. 

  3185. #define TXQ_EPQ_STATE_OFST                        (8)
    3186. 

  3186. #define TXQ_STOP_OFST                             (2)
    3187. 

  3187. #define TXQ_RESUME_OFST                           (1)
    3188. 

  3188. #define TXQ_START_OFST                            (0)
    3189. 

  3189. 

  3190. /* U3D_TXQSAR8 */
    3191. 

  3191. #define TXQ_START_ADDR_OFST                       (2)
    3192. 

  3192. 

  3193. /* U3D_TXQCPR8 */
    3194. 

  3194. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3195. 

  3195. 

  3196. /* U3D_TXQCSR9 */
    3197. 

  3197. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3198. 

  3198. #define TXQ_ACTIVE_OFST                           (15)
    3199. 

  3199. #define TXQ_EPQ_STATE_OFST                        (8)
    3200. 

  3200. #define TXQ_STOP_OFST                             (2)
    3201. 

  3201. #define TXQ_RESUME_OFST                           (1)
    3202. 

  3202. #define TXQ_START_OFST                            (0)
    3203. 

  3203. 

  3204. /* U3D_TXQSAR9 */
    3205. 

  3205. #define TXQ_START_ADDR_OFST                       (2)
    3206. 

  3206. 

  3207. /* U3D_TXQCPR9 */
    3208. 

  3208. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3209. 

  3209. 

  3210. /* U3D_TXQCSR10 */
    3211. 

  3211. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3212. 

  3212. #define TXQ_ACTIVE_OFST                           (15)
    3213. 

  3213. #define TXQ_EPQ_STATE_OFST                        (8)
    3214. 

  3214. #define TXQ_STOP_OFST                             (2)
    3215. 

  3215. #define TXQ_RESUME_OFST                           (1)
    3216. 

  3216. #define TXQ_START_OFST                            (0)
    3217. 

  3217. 

  3218. /* U3D_TXQSAR10 */
    3219. 

  3219. #define TXQ_START_ADDR_OFST                       (2)
    3220. 

  3220. 

  3221. /* U3D_TXQCPR10 */
    3222. 

  3222. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3223. 

  3223. 

  3224. /* U3D_TXQCSR11 */
    3225. 

  3225. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3226. 

  3226. #define TXQ_ACTIVE_OFST                           (15)
    3227. 

  3227. #define TXQ_EPQ_STATE_OFST                        (8)
    3228. 

  3228. #define TXQ_STOP_OFST                             (2)
    3229. 

  3229. #define TXQ_RESUME_OFST                           (1)
    3230. 

  3230. #define TXQ_START_OFST                            (0)
    3231. 

  3231. 

  3232. /* U3D_TXQSAR11 */
    3233. 

  3233. #define TXQ_START_ADDR_OFST                       (2)
    3234. 

  3234. 

  3235. /* U3D_TXQCPR11 */
    3236. 

  3236. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3237. 

  3237. 

  3238. /* U3D_TXQCSR12 */
    3239. 

  3239. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3240. 

  3240. #define TXQ_ACTIVE_OFST                           (15)
    3241. 

  3241. #define TXQ_EPQ_STATE_OFST                        (8)
    3242. 

  3242. #define TXQ_STOP_OFST                             (2)
    3243. 

  3243. #define TXQ_RESUME_OFST                           (1)
    3244. 

  3244. #define TXQ_START_OFST                            (0)
    3245. 

  3245. 

  3246. /* U3D_TXQSAR12 */
    3247. 

  3247. #define TXQ_START_ADDR_OFST                       (2)
    3248. 

  3248. 

  3249. /* U3D_TXQCPR12 */
    3250. 

  3250. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3251. 

  3251. 

  3252. /* U3D_TXQCSR13 */
    3253. 

  3253. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3254. 

  3254. #define TXQ_ACTIVE_OFST                           (15)
    3255. 

  3255. #define TXQ_EPQ_STATE_OFST                        (8)
    3256. 

  3256. #define TXQ_STOP_OFST                             (2)
    3257. 

  3257. #define TXQ_RESUME_OFST                           (1)
    3258. 

  3258. #define TXQ_START_OFST                            (0)
    3259. 

  3259. 

  3260. /* U3D_TXQSAR13 */
    3261. 

  3261. #define TXQ_START_ADDR_OFST                       (2)
    3262. 

  3262. 

  3263. /* U3D_TXQCPR13 */
    3264. 

  3264. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3265. 

  3265. 

  3266. /* U3D_TXQCSR14 */
    3267. 

  3267. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3268. 

  3268. #define TXQ_ACTIVE_OFST                           (15)
    3269. 

  3269. #define TXQ_EPQ_STATE_OFST                        (8)
    3270. 

  3270. #define TXQ_STOP_OFST                             (2)
    3271. 

  3271. #define TXQ_RESUME_OFST                           (1)
    3272. 

  3272. #define TXQ_START_OFST                            (0)
    3273. 

  3273. 

  3274. /* U3D_TXQSAR14 */
    3275. 

  3275. #define TXQ_START_ADDR_OFST                       (2)
    3276. 

  3276. 

  3277. /* U3D_TXQCPR14 */
    3278. 

  3278. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3279. 

  3279. 

  3280. /* U3D_TXQCSR15 */
    3281. 

  3281. #define TXQ_DMGR_DMSM_CS_OFST                     (16)
    3282. 

  3282. #define TXQ_ACTIVE_OFST                           (15)
    3283. 

  3283. #define TXQ_EPQ_STATE_OFST                        (8)
    3284. 

  3284. #define TXQ_STOP_OFST                             (2)
    3285. 

  3285. #define TXQ_RESUME_OFST                           (1)
    3286. 

  3286. #define TXQ_START_OFST                            (0)
    3287. 

  3287. 

  3288. /* U3D_TXQSAR15 */
    3289. 

  3289. #define TXQ_START_ADDR_OFST                       (2)
    3290. 

  3290. 

  3291. /* U3D_TXQCPR15 */
    3292. 

  3292. #define TXQ_CUR_GPD_ADDR_OFST                     (2)
    3293. 

  3293. 

  3294. /* U3D_RXQCSR1 */
    3295. 

  3295. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3296. 

  3296. #define RXQ_ACTIVE_OFST                           (15)
    3297. 

  3297. #define RXQ_EPQ_STATE_OFST                        (8)
    3298. 

  3298. #define RXQ_STOP_OFST                             (2)
    3299. 

  3299. #define RXQ_RESUME_OFST                           (1)
    3300. 

  3300. #define RXQ_START_OFST                            (0)
    3301. 

  3301. 

  3302. /* U3D_RXQSAR1 */
    3303. 

  3303. #define RXQ_START_ADDR_OFST                       (2)
    3304. 

  3304. 

  3305. /* U3D_RXQCPR1 */
    3306. 

  3306. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3307. 

  3307. 

  3308. /* U3D_RXQLDPR1 */
    3309. 

  3309. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3310. 

  3310. 

  3311. /* U3D_RXQCSR2 */
    3312. 

  3312. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3313. 

  3313. #define RXQ_ACTIVE_OFST                           (15)
    3314. 

  3314. #define RXQ_EPQ_STATE_OFST                        (8)
    3315. 

  3315. #define RXQ_STOP_OFST                             (2)
    3316. 

  3316. #define RXQ_RESUME_OFST                           (1)
    3317. 

  3317. #define RXQ_START_OFST                            (0)
    3318. 

  3318. 

  3319. /* U3D_RXQSAR2 */
    3320. 

  3320. #define RXQ_START_ADDR_OFST                       (2)
    3321. 

  3321. 

  3322. /* U3D_RXQCPR2 */
    3323. 

  3323. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3324. 

  3324. 

  3325. /* U3D_RXQLDPR2 */
    3326. 

  3326. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3327. 

  3327. 

  3328. /* U3D_RXQCSR3 */
    3329. 

  3329. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3330. 

  3330. #define RXQ_ACTIVE_OFST                           (15)
    3331. 

  3331. #define RXQ_EPQ_STATE_OFST                        (8)
    3332. 

  3332. #define RXQ_STOP_OFST                             (2)
    3333. 

  3333. #define RXQ_RESUME_OFST                           (1)
    3334. 

  3334. #define RXQ_START_OFST                            (0)
    3335. 

  3335. 

  3336. /* U3D_RXQSAR3 */
    3337. 

  3337. #define RXQ_START_ADDR_OFST                       (2)
    3338. 

  3338. 

  3339. /* U3D_RXQCPR3 */
    3340. 

  3340. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3341. 

  3341. 

  3342. /* U3D_RXQLDPR3 */
    3343. 

  3343. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3344. 

  3344. 

  3345. /* U3D_RXQCSR4 */
    3346. 

  3346. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3347. 

  3347. #define RXQ_ACTIVE_OFST                           (15)
    3348. 

  3348. #define RXQ_EPQ_STATE_OFST                        (8)
    3349. 

  3349. #define RXQ_STOP_OFST                             (2)
    3350. 

  3350. #define RXQ_RESUME_OFST                           (1)
    3351. 

  3351. #define RXQ_START_OFST                            (0)
    3352. 

  3352. 

  3353. /* U3D_RXQSAR4 */
    3354. 

  3354. #define RXQ_START_ADDR_OFST                       (2)
    3355. 

  3355. 

  3356. /* U3D_RXQCPR4 */
    3357. 

  3357. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3358. 

  3358. 

  3359. /* U3D_RXQLDPR4 */
    3360. 

  3360. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3361. 

  3361. 

  3362. /* U3D_RXQCSR5 */
    3363. 

  3363. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3364. 

  3364. #define RXQ_ACTIVE_OFST                           (15)
    3365. 

  3365. #define RXQ_EPQ_STATE_OFST                        (8)
    3366. 

  3366. #define RXQ_STOP_OFST                             (2)
    3367. 

  3367. #define RXQ_RESUME_OFST                           (1)
    3368. 

  3368. #define RXQ_START_OFST                            (0)
    3369. 

  3369. 

  3370. /* U3D_RXQSAR5 */
    3371. 

  3371. #define RXQ_START_ADDR_OFST                       (2)
    3372. 

  3372. 

  3373. /* U3D_RXQCPR5 */
    3374. 

  3374. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3375. 

  3375. 

  3376. /* U3D_RXQLDPR5 */
    3377. 

  3377. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3378. 

  3378. 

  3379. /* U3D_RXQCSR6 */
    3380. 

  3380. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3381. 

  3381. #define RXQ_ACTIVE_OFST                           (15)
    3382. 

  3382. #define RXQ_EPQ_STATE_OFST                        (8)
    3383. 

  3383. #define RXQ_STOP_OFST                             (2)
    3384. 

  3384. #define RXQ_RESUME_OFST                           (1)
    3385. 

  3385. #define RXQ_START_OFST                            (0)
    3386. 

  3386. 

  3387. /* U3D_RXQSAR6 */
    3388. 

  3388. #define RXQ_START_ADDR_OFST                       (2)
    3389. 

  3389. 

  3390. /* U3D_RXQCPR6 */
    3391. 

  3391. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3392. 

  3392. 

  3393. /* U3D_RXQLDPR6 */
    3394. 

  3394. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3395. 

  3395. 

  3396. /* U3D_RXQCSR7 */
    3397. 

  3397. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3398. 

  3398. #define RXQ_ACTIVE_OFST                           (15)
    3399. 

  3399. #define RXQ_EPQ_STATE_OFST                        (8)
    3400. 

  3400. #define RXQ_STOP_OFST                             (2)
    3401. 

  3401. #define RXQ_RESUME_OFST                           (1)
    3402. 

  3402. #define RXQ_START_OFST                            (0)
    3403. 

  3403. 

  3404. /* U3D_RXQSAR7 */
    3405. 

  3405. #define RXQ_START_ADDR_OFST                       (2)
    3406. 

  3406. 

  3407. /* U3D_RXQCPR7 */
    3408. 

  3408. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3409. 

  3409. 

  3410. /* U3D_RXQLDPR7 */
    3411. 

  3411. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3412. 

  3412. 

  3413. /* U3D_RXQCSR8 */
    3414. 

  3414. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3415. 

  3415. #define RXQ_ACTIVE_OFST                           (15)
    3416. 

  3416. #define RXQ_EPQ_STATE_OFST                        (8)
    3417. 

  3417. #define RXQ_STOP_OFST                             (2)
    3418. 

  3418. #define RXQ_RESUME_OFST                           (1)
    3419. 

  3419. #define RXQ_START_OFST                            (0)
    3420. 

  3420. 

  3421. /* U3D_RXQSAR8 */
    3422. 

  3422. #define RXQ_START_ADDR_OFST                       (2)
    3423. 

  3423. 

  3424. /* U3D_RXQCPR8 */
    3425. 

  3425. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3426. 

  3426. 

  3427. /* U3D_RXQLDPR8 */
    3428. 

  3428. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3429. 

  3429. 

  3430. /* U3D_RXQCSR9 */
    3431. 

  3431. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3432. 

  3432. #define RXQ_ACTIVE_OFST                           (15)
    3433. 

  3433. #define RXQ_EPQ_STATE_OFST                        (8)
    3434. 

  3434. #define RXQ_STOP_OFST                             (2)
    3435. 

  3435. #define RXQ_RESUME_OFST                           (1)
    3436. 

  3436. #define RXQ_START_OFST                            (0)
    3437. 

  3437. 

  3438. /* U3D_RXQSAR9 */
    3439. 

  3439. #define RXQ_START_ADDR_OFST                       (2)
    3440. 

  3440. 

  3441. /* U3D_RXQCPR9 */
    3442. 

  3442. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3443. 

  3443. 

  3444. /* U3D_RXQLDPR9 */
    3445. 

  3445. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3446. 

  3446. 

  3447. /* U3D_RXQCSR10 */
    3448. 

  3448. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3449. 

  3449. #define RXQ_ACTIVE_OFST                           (15)
    3450. 

  3450. #define RXQ_EPQ_STATE_OFST                        (8)
    3451. 

  3451. #define RXQ_STOP_OFST                             (2)
    3452. 

  3452. #define RXQ_RESUME_OFST                           (1)
    3453. 

  3453. #define RXQ_START_OFST                            (0)
    3454. 

  3454. 

  3455. /* U3D_RXQSAR10 */
    3456. 

  3456. #define RXQ_START_ADDR_OFST                       (2)
    3457. 

  3457. 

  3458. /* U3D_RXQCPR10 */
    3459. 

  3459. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3460. 

  3460. 

  3461. /* U3D_RXQLDPR10 */
    3462. 

  3462. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3463. 

  3463. 

  3464. /* U3D_RXQCSR11 */
    3465. 

  3465. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3466. 

  3466. #define RXQ_ACTIVE_OFST                           (15)
    3467. 

  3467. #define RXQ_EPQ_STATE_OFST                        (8)
    3468. 

  3468. #define RXQ_STOP_OFST                             (2)
    3469. 

  3469. #define RXQ_RESUME_OFST                           (1)
    3470. 

  3470. #define RXQ_START_OFST                            (0)
    3471. 

  3471. 

  3472. /* U3D_RXQSAR11 */
    3473. 

  3473. #define RXQ_START_ADDR_OFST                       (2)
    3474. 

  3474. 

  3475. /* U3D_RXQCPR11 */
    3476. 

  3476. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3477. 

  3477. 

  3478. /* U3D_RXQLDPR11 */
    3479. 

  3479. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3480. 

  3480. 

  3481. /* U3D_RXQCSR12 */
    3482. 

  3482. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3483. 

  3483. #define RXQ_ACTIVE_OFST                           (15)
    3484. 

  3484. #define RXQ_EPQ_STATE_OFST                        (8)
    3485. 

  3485. #define RXQ_STOP_OFST                             (2)
    3486. 

  3486. #define RXQ_RESUME_OFST                           (1)
    3487. 

  3487. #define RXQ_START_OFST                            (0)
    3488. 

  3488. 

  3489. /* U3D_RXQSAR12 */
    3490. 

  3490. #define RXQ_START_ADDR_OFST                       (2)
    3491. 

  3491. 

  3492. /* U3D_RXQCPR12 */
    3493. 

  3493. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3494. 

  3494. 

  3495. /* U3D_RXQLDPR12 */
    3496. 

  3496. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3497. 

  3497. 

  3498. /* U3D_RXQCSR13 */
    3499. 

  3499. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3500. 

  3500. #define RXQ_ACTIVE_OFST                           (15)
    3501. 

  3501. #define RXQ_EPQ_STATE_OFST                        (8)
    3502. 

  3502. #define RXQ_STOP_OFST                             (2)
    3503. 

  3503. #define RXQ_RESUME_OFST                           (1)
    3504. 

  3504. #define RXQ_START_OFST                            (0)
    3505. 

  3505. 

  3506. /* U3D_RXQSAR13 */
    3507. 

  3507. #define RXQ_START_ADDR_OFST                       (2)
    3508. 

  3508. 

  3509. /* U3D_RXQCPR13 */
    3510. 

  3510. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3511. 

  3511. 

  3512. /* U3D_RXQLDPR13 */
    3513. 

  3513. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3514. 

  3514. 

  3515. /* U3D_RXQCSR14 */
    3516. 

  3516. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3517. 

  3517. #define RXQ_ACTIVE_OFST                           (15)
    3518. 

  3518. #define RXQ_EPQ_STATE_OFST                        (8)
    3519. 

  3519. #define RXQ_STOP_OFST                             (2)
    3520. 

  3520. #define RXQ_RESUME_OFST                           (1)
    3521. 

  3521. #define RXQ_START_OFST                            (0)
    3522. 

  3522. 

  3523. /* U3D_RXQSAR14 */
    3524. 

  3524. #define RXQ_START_ADDR_OFST                       (2)
    3525. 

  3525. 

  3526. /* U3D_RXQCPR14 */
    3527. 

  3527. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3528. 

  3528. 

  3529. /* U3D_RXQLDPR14 */
    3530. 

  3530. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3531. 

  3531. 

  3532. /* U3D_RXQCSR15 */
    3533. 

  3533. #define RXQ_DMGR_DMSM_CS_OFST                     (16)
    3534. 

  3534. #define RXQ_ACTIVE_OFST                           (15)
    3535. 

  3535. #define RXQ_EPQ_STATE_OFST                        (8)
    3536. 

  3536. #define RXQ_STOP_OFST                             (2)
    3537. 

  3537. #define RXQ_RESUME_OFST                           (1)
    3538. 

  3538. #define RXQ_START_OFST                            (0)
    3539. 

  3539. 

  3540. /* U3D_RXQSAR15 */
    3541. 

  3541. #define RXQ_START_ADDR_OFST                       (2)
    3542. 

  3542. 

  3543. /* U3D_RXQCPR15 */
    3544. 

  3544. #define RXQ_CUR_GPD_ADDR_OFST                     (2)
    3545. 

  3545. 

  3546. /* U3D_RXQLDPR15 */
    3547. 

  3547. #define RXQ_LAST_DONE_PTR_OFST                    (2)
    3548. 

  3548. 

  3549. /* U3D_QISAR0 */
    3550. 

  3550. #define RXQ_DONE_INT_OFST                         (17)
    3551. 

  3551. #define TXQ_DONE_INT_OFST                         (1)
    3552. 

  3552. 

  3553. /* U3D_QIER0 */
    3554. 

  3554. #define RXQ_DONE_IER_OFST                         (17)
    3555. 

  3555. #define TXQ_DONE_IER_OFST                         (1)
    3556. 

  3556. 

  3557. /* U3D_QIESR0 */
    3558. 

  3558. #define RXQ_DONE_IESR_OFST                        (17)
    3559. 

  3559. #define TXQ_DONE_IESR_OFST                        (1)
    3560. 

  3560. 

  3561. /* U3D_QIECR0 */
    3562. 

  3562. #define RXQ_DONE_IECR_OFST                        (17)
    3563. 

  3563. #define TXQ_DONE_IECR_OFST                        (1)
    3564. 

  3564. 

  3565. /* U3D_QISAR1 */
    3566. 

  3566. #define RXQ_ZLPERR_INT_OFST                       (20)
    3567. 

  3567. #define RXQ_LENERR_INT_OFST                       (18)
    3568. 

  3568. #define RXQ_CSERR_INT_OFST                        (17)
    3569. 

  3569. #define RXQ_EMPTY_INT_OFST                        (16)
    3570. 

  3570. #define TXQ_LENERR_INT_OFST                       (2)
    3571. 

  3571. #define TXQ_CSERR_INT_OFST                        (1)
    3572. 

  3572. #define TXQ_EMPTY_INT_OFST                        (0)
    3573. 

  3573. 

  3574. /* U3D_QIER1 */
    3575. 

  3575. #define RXQ_ZLPERR_IER_OFST                       (20)
    3576. 

  3576. #define RXQ_LENERR_IER_OFST                       (18)
    3577. 

  3577. #define RXQ_CSERR_IER_OFST                        (17)
    3578. 

  3578. #define RXQ_EMPTY_IER_OFST                        (16)
    3579. 

  3579. #define TXQ_LENERR_IER_OFST                       (2)
    3580. 

  3580. #define TXQ_CSERR_IER_OFST                        (1)
    3581. 

  3581. #define TXQ_EMPTY_IER_OFST                        (0)
    3582. 

  3582. 

  3583. /* U3D_QIESR1 */
    3584. 

  3584. #define RXQ_ZLPERR_IESR_OFST                      (20)
    3585. 

  3585. #define RXQ_LENERR_IESR_OFST                      (18)
    3586. 

  3586. #define RXQ_CSERR_IESR_OFST                       (17)
    3587. 

  3587. #define RXQ_EMPTY_IESR_OFST                       (16)
    3588. 

  3588. #define TXQ_LENERR_IESR_OFST                      (2)
    3589. 

  3589. #define TXQ_CSERR_IESR_OFST                       (1)
    3590. 

  3590. #define TXQ_EMPTY_IESR_OFST                       (0)
    3591. 

  3591. 

  3592. /* U3D_QIECR1 */
    3593. 

  3593. #define RXQ_ZLPERR_IECR_OFST                      (20)
    3594. 

  3594. #define RXQ_LENERR_IECR_OFST                      (18)
    3595. 

  3595. #define RXQ_CSERR_IECR_OFST                       (17)
    3596. 

  3596. #define RXQ_EMPTY_IECR_OFST                       (16)
    3597. 

  3597. #define TXQ_LENERR_IECR_OFST                      (2)
    3598. 

  3598. #define TXQ_CSERR_IECR_OFST                       (1)
    3599. 

  3599. #define TXQ_EMPTY_IECR_OFST                       (0)
    3600. 

  3600. 

  3601. /* U3D_QEMIR */
    3602. 

  3602. #define RXQ_EMPTY_MASK_OFST                       (17)
    3603. 

  3603. #define TXQ_EMPTY_MASK_OFST                       (1)
    3604. 

  3604. 

  3605. /* U3D_QEMIER */
    3606. 

  3606. #define RXQ_EMPTY_IER_MASK_OFST                   (17)
    3607. 

  3607. #define TXQ_EMPTY_IER_MASK_OFST                   (1)
    3608. 

  3608. 

  3609. /* U3D_QEMIESR */
    3610. 

  3610. #define RXQ_EMPTY_IESR_MASK_OFST                  (17)
    3611. 

  3611. #define TXQ_EMPTY_IESR_MASK_OFST                  (1)
    3612. 

  3612. 

  3613. /* U3D_QEMIECR */
    3614. 

  3614. #define RXQ_EMPTY_IECR_MASK_OFST                  (17)
    3615. 

  3615. #define TXQ_EMPTY_IECR_MASK_OFST                  (1)
    3616. 

  3616. 

  3617. /* U3D_TQERRIR0 */
    3618. 

  3618. #define TXQ_LENERR_MASK_OFST                      (17)
    3619. 

  3619. #define TXQ_CSERR_MASK_OFST                       (1)
    3620. 

  3620. 

  3621. /* U3D_TQERRIER0 */
    3622. 

  3622. #define TXQ_LENERR_IER_MASK_OFST                  (17)
    3623. 

  3623. #define TXQ_CSERR_IER_MASK_OFST                   (1)
    3624. 

  3624. 

  3625. /* U3D_TQERRIESR0 */
    3626. 

  3626. #define TXQ_LENERR_IESR_MASK_OFST                 (17)
    3627. 

  3627. #define TXQ_CSERR_IESR_MASK_OFST                  (1)
    3628. 

  3628. 

  3629. /* U3D_TQERRIECR0 */
    3630. 

  3630. #define TXQ_LENERR_IECR_MASK_OFST                 (17)
    3631. 

  3631. #define TXQ_CSERR_IECR_MASK_OFST                  (1)
    3632. 

  3632. 

  3633. /* U3D_RQERRIR0 */
    3634. 

  3634. #define RXQ_LENERR_MASK_OFST                      (17)
    3635. 

  3635. #define RXQ_CSERR_MASK_OFST                       (1)
    3636. 

  3636. 

  3637. /* U3D_RQERRIER0 */
    3638. 

  3638. #define RXQ_LENERR_IER_MASK_OFST                  (17)
    3639. 

  3639. #define RXQ_CSERR_IER_MASK_OFST                   (1)
    3640. 

  3640. 

  3641. /* U3D_RQERRIESR0 */
    3642. 

  3642. #define RXQ_LENERR_IESR_MASK_OFST                 (17)
    3643. 

  3643. #define RXQ_CSERR_IESR_MASK_OFST                  (1)
    3644. 

  3644. 

  3645. /* U3D_RQERRIECR0 */
    3646. 

  3646. #define RXQ_LENERR_IECR_MASK_OFST                 (17)
    3647. 

  3647. #define RXQ_CSERR_IECR_MASK_OFST                  (1)
    3648. 

  3648. 

  3649. /* U3D_RQERRIR1 */
    3650. 

  3650. #define RXQ_ZLPERR_MASK_OFST                      (17)
    3651. 

  3651. 

  3652. /* U3D_RQERRIER1 */
    3653. 

  3653. #define RXQ_ZLPERR_IER_MASK_OFST                  (17)
    3654. 

  3654. 

  3655. /* U3D_RQERRIESR1 */
    3656. 

  3656. #define RXQ_ZLPERR_IESR_MASK_OFST                 (17)
    3657. 

  3657. 

  3658. /* U3D_RQERRIECR1 */
    3659. 

  3659. #define RXQ_ZLPERR_IECR_MASK_OFST                 (17)
    3660. 

  3660. 

  3661. /* U3D_CAP_EP0FFSZ */
    3662. 

  3662. #define CAP_EP0FFSZ_OFST                          (0)
    3663. 

  3663. 

  3664. /* U3D_CAP_EPNTXFFSZ */
    3665. 

  3665. #define CAP_EPNTXFFSZ_OFST                        (0)
    3666. 

  3666. 

  3667. /* U3D_CAP_EPNRXFFSZ */
    3668. 

  3668. #define CAP_EPNRXFFSZ_OFST                        (0)
    3669. 

  3669. 

  3670. /* U3D_CAP_EPINFO */
    3671. 

  3671. #define CAP_RX_EP_NUM_OFST                        (8)
    3672. 

  3672. #define CAP_TX_EP_NUM_OFST                        (0)
    3673. 

  3673. 

  3674. /* U3D_CAP_TX_SLOT1 */
    3675. 

  3675. #define CAP_TX_SLOT3_OFST                         (24)
    3676. 

  3676. #define CAP_TX_SLOT2_OFST                         (16)
    3677. 

  3677. #define CAP_TX_SLOT1_OFST                         (8)
    3678. 

  3678. #define RSV_OFST                                  (0)
    3679. 

  3679. 

  3680. /* U3D_CAP_TX_SLOT2 */
    3681. 

  3681. #define CAP_TX_SLOT7_OFST                         (24)
    3682. 

  3682. #define CAP_TX_SLOT6_OFST                         (16)
    3683. 

  3683. #define CAP_TX_SLOT5_OFST                         (8)
    3684. 

  3684. #define CAP_TX_SLOT4_OFST                         (0)
    3685. 

  3685. 

  3686. /* U3D_CAP_TX_SLOT3 */
    3687. 

  3687. #define CAP_TX_SLOT11_OFST                        (24)
    3688. 

  3688. #define CAP_TX_SLOT10_OFST                        (16)
    3689. 

  3689. #define CAP_TX_SLOT9_OFST                         (8)
    3690. 

  3690. #define CAP_TX_SLOT8_OFST                         (0)
    3691. 

  3691. 

  3692. /* U3D_CAP_TX_SLOT4 */
    3693. 

  3693. #define CAP_TX_SLOT15_OFST                        (24)
    3694. 

  3694. #define CAP_TX_SLOT14_OFST                        (16)
    3695. 

  3695. #define CAP_TX_SLOT13_OFST                        (8)
    3696. 

  3696. #define CAP_TX_SLOT12_OFST                        (0)
    3697. 

  3697. 

  3698. /* U3D_CAP_RX_SLOT1 */
    3699. 

  3699. #define CAP_RX_SLOT3_OFST                         (24)
    3700. 

  3700. #define CAP_RX_SLOT2_OFST                         (16)
    3701. 

  3701. #define CAP_RX_SLOT1_OFST                         (8)
    3702. 

  3702. #define RSV_OFST                                  (0)
    3703. 

  3703. 

  3704. /* U3D_CAP_RX_SLOT2 */
    3705. 

  3705. #define CAP_RX_SLOT7_OFST                         (24)
    3706. 

  3706. #define CAP_RX_SLOT6_OFST                         (16)
    3707. 

  3707. #define CAP_RX_SLOT5_OFST                         (8)
    3708. 

  3708. #define CAP_RX_SLOT4_OFST                         (0)
    3709. 

  3709. 

  3710. /* U3D_CAP_RX_SLOT3 */
    3711. 

  3711. #define CAP_RX_SLOT11_OFST                        (24)
    3712. 

  3712. #define CAP_RX_SLOT10_OFST                        (16)
    3713. 

  3713. #define CAP_RX_SLOT9_OFST                         (8)
    3714. 

  3714. #define CAP_RX_SLOT8_OFST                         (0)
    3715. 

  3715. 

  3716. /* U3D_CAP_RX_SLOT4 */
    3717. 

  3717. #define CAP_RX_SLOT15_OFST                        (24)
    3718. 

  3718. #define CAP_RX_SLOT14_OFST                        (16)
    3719. 

  3719. #define CAP_RX_SLOT13_OFST                        (8)
    3720. 

  3720. #define CAP_RX_SLOT12_OFST                        (0)
    3721. 

  3721. 

  3722. /* U3D_MISC_CTRL */
    3723. 

  3723. #define DMA_BUS_CK_GATE_DIS_OFST                  (2)
    3724. 

  3724. #define VBUS_ON_OFST                              (1)
    3725. 

  3725. #define VBUS_FRC_EN_OFST                          (0)
    3726. 

  3726. 

  3727. /* //////////////////////////////////////////////////////////////////// */
    3728.