qla_isr.c 85 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199
  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  15. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  16. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  17. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  18. sts_entry_t *);
  19. /**
  20. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  21. * @irq:
  22. * @dev_id: SCSI driver HA context
  23. *
  24. * Called by system whenever the host adapter generates an interrupt.
  25. *
  26. * Returns handled flag.
  27. */
  28. irqreturn_t
  29. qla2100_intr_handler(int irq, void *dev_id)
  30. {
  31. scsi_qla_host_t *vha;
  32. struct qla_hw_data *ha;
  33. struct device_reg_2xxx __iomem *reg;
  34. int status;
  35. unsigned long iter;
  36. uint16_t hccr;
  37. uint16_t mb[4];
  38. struct rsp_que *rsp;
  39. unsigned long flags;
  40. rsp = (struct rsp_que *) dev_id;
  41. if (!rsp) {
  42. ql_log(ql_log_info, NULL, 0x505d,
  43. "%s: NULL response queue pointer.\n", __func__);
  44. return (IRQ_NONE);
  45. }
  46. ha = rsp->hw;
  47. reg = &ha->iobase->isp;
  48. status = 0;
  49. spin_lock_irqsave(&ha->hardware_lock, flags);
  50. vha = pci_get_drvdata(ha->pdev);
  51. for (iter = 50; iter--; ) {
  52. hccr = RD_REG_WORD(&reg->hccr);
  53. if (qla2x00_check_reg16_for_disconnect(vha, hccr))
  54. break;
  55. if (hccr & HCCR_RISC_PAUSE) {
  56. if (pci_channel_offline(ha->pdev))
  57. break;
  58. /*
  59. * Issue a "HARD" reset in order for the RISC interrupt
  60. * bit to be cleared. Schedule a big hammer to get
  61. * out of the RISC PAUSED state.
  62. */
  63. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  64. RD_REG_WORD(&reg->hccr);
  65. ha->isp_ops->fw_dump(vha, 1);
  66. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  67. break;
  68. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  69. break;
  70. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  71. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  72. RD_REG_WORD(&reg->hccr);
  73. /* Get mailbox data. */
  74. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  75. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  76. qla2x00_mbx_completion(vha, mb[0]);
  77. status |= MBX_INTERRUPT;
  78. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  79. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  80. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  81. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  82. qla2x00_async_event(vha, rsp, mb);
  83. } else {
  84. /*EMPTY*/
  85. ql_dbg(ql_dbg_async, vha, 0x5025,
  86. "Unrecognized interrupt type (%d).\n",
  87. mb[0]);
  88. }
  89. /* Release mailbox registers. */
  90. WRT_REG_WORD(&reg->semaphore, 0);
  91. RD_REG_WORD(&reg->semaphore);
  92. } else {
  93. qla2x00_process_response_queue(rsp);
  94. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  95. RD_REG_WORD(&reg->hccr);
  96. }
  97. }
  98. qla2x00_handle_mbx_completion(ha, status);
  99. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  100. return (IRQ_HANDLED);
  101. }
  102. bool
  103. qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *vha, uint32_t reg)
  104. {
  105. /* Check for PCI disconnection */
  106. if (reg == 0xffffffff) {
  107. if (!test_and_set_bit(PFLG_DISCONNECTED, &vha->pci_flags) &&
  108. !test_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags) &&
  109. !test_bit(PFLG_DRIVER_PROBING, &vha->pci_flags)) {
  110. /*
  111. * Schedule this (only once) on the default system
  112. * workqueue so that all the adapter workqueues and the
  113. * DPC thread can be shutdown cleanly.
  114. */
  115. schedule_work(&vha->hw->board_disable);
  116. }
  117. return true;
  118. } else
  119. return false;
  120. }
  121. bool
  122. qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *vha, uint16_t reg)
  123. {
  124. return qla2x00_check_reg32_for_disconnect(vha, 0xffff0000 | reg);
  125. }
  126. /**
  127. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  128. * @irq:
  129. * @dev_id: SCSI driver HA context
  130. *
  131. * Called by system whenever the host adapter generates an interrupt.
  132. *
  133. * Returns handled flag.
  134. */
  135. irqreturn_t
  136. qla2300_intr_handler(int irq, void *dev_id)
  137. {
  138. scsi_qla_host_t *vha;
  139. struct device_reg_2xxx __iomem *reg;
  140. int status;
  141. unsigned long iter;
  142. uint32_t stat;
  143. uint16_t hccr;
  144. uint16_t mb[4];
  145. struct rsp_que *rsp;
  146. struct qla_hw_data *ha;
  147. unsigned long flags;
  148. rsp = (struct rsp_que *) dev_id;
  149. if (!rsp) {
  150. ql_log(ql_log_info, NULL, 0x5058,
  151. "%s: NULL response queue pointer.\n", __func__);
  152. return (IRQ_NONE);
  153. }
  154. ha = rsp->hw;
  155. reg = &ha->iobase->isp;
  156. status = 0;
  157. spin_lock_irqsave(&ha->hardware_lock, flags);
  158. vha = pci_get_drvdata(ha->pdev);
  159. for (iter = 50; iter--; ) {
  160. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  161. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  162. break;
  163. if (stat & HSR_RISC_PAUSED) {
  164. if (unlikely(pci_channel_offline(ha->pdev)))
  165. break;
  166. hccr = RD_REG_WORD(&reg->hccr);
  167. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  168. ql_log(ql_log_warn, vha, 0x5026,
  169. "Parity error -- HCCR=%x, Dumping "
  170. "firmware.\n", hccr);
  171. else
  172. ql_log(ql_log_warn, vha, 0x5027,
  173. "RISC paused -- HCCR=%x, Dumping "
  174. "firmware.\n", hccr);
  175. /*
  176. * Issue a "HARD" reset in order for the RISC
  177. * interrupt bit to be cleared. Schedule a big
  178. * hammer to get out of the RISC PAUSED state.
  179. */
  180. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  181. RD_REG_WORD(&reg->hccr);
  182. ha->isp_ops->fw_dump(vha, 1);
  183. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  184. break;
  185. } else if ((stat & HSR_RISC_INT) == 0)
  186. break;
  187. switch (stat & 0xff) {
  188. case 0x1:
  189. case 0x2:
  190. case 0x10:
  191. case 0x11:
  192. qla2x00_mbx_completion(vha, MSW(stat));
  193. status |= MBX_INTERRUPT;
  194. /* Release mailbox registers. */
  195. WRT_REG_WORD(&reg->semaphore, 0);
  196. break;
  197. case 0x12:
  198. mb[0] = MSW(stat);
  199. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  200. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  201. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  202. qla2x00_async_event(vha, rsp, mb);
  203. break;
  204. case 0x13:
  205. qla2x00_process_response_queue(rsp);
  206. break;
  207. case 0x15:
  208. mb[0] = MBA_CMPLT_1_16BIT;
  209. mb[1] = MSW(stat);
  210. qla2x00_async_event(vha, rsp, mb);
  211. break;
  212. case 0x16:
  213. mb[0] = MBA_SCSI_COMPLETION;
  214. mb[1] = MSW(stat);
  215. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  216. qla2x00_async_event(vha, rsp, mb);
  217. break;
  218. default:
  219. ql_dbg(ql_dbg_async, vha, 0x5028,
  220. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  221. break;
  222. }
  223. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  224. RD_REG_WORD_RELAXED(&reg->hccr);
  225. }
  226. qla2x00_handle_mbx_completion(ha, status);
  227. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  228. return (IRQ_HANDLED);
  229. }
  230. /**
  231. * qla2x00_mbx_completion() - Process mailbox command completions.
  232. * @ha: SCSI driver HA context
  233. * @mb0: Mailbox0 register
  234. */
  235. static void
  236. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  237. {
  238. uint16_t cnt;
  239. uint32_t mboxes;
  240. uint16_t __iomem *wptr;
  241. struct qla_hw_data *ha = vha->hw;
  242. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  243. /* Read all mbox registers? */
  244. mboxes = (1 << ha->mbx_count) - 1;
  245. if (!ha->mcp)
  246. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  247. else
  248. mboxes = ha->mcp->in_mb;
  249. /* Load return mailbox registers. */
  250. ha->flags.mbox_int = 1;
  251. ha->mailbox_out[0] = mb0;
  252. mboxes >>= 1;
  253. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  254. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  255. if (IS_QLA2200(ha) && cnt == 8)
  256. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  257. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  258. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  259. else if (mboxes & BIT_0)
  260. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  261. wptr++;
  262. mboxes >>= 1;
  263. }
  264. }
  265. static void
  266. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  267. {
  268. static char *event[] =
  269. { "Complete", "Request Notification", "Time Extension" };
  270. int rval;
  271. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  272. struct device_reg_82xx __iomem *reg82 = &vha->hw->iobase->isp82;
  273. uint16_t __iomem *wptr;
  274. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  275. /* Seed data -- mailbox1 -> mailbox7. */
  276. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  277. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  278. else if (IS_QLA8044(vha->hw))
  279. wptr = (uint16_t __iomem *)&reg82->mailbox_out[1];
  280. else
  281. return;
  282. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  283. mb[cnt] = RD_REG_WORD(wptr);
  284. ql_dbg(ql_dbg_async, vha, 0x5021,
  285. "Inter-Driver Communication %s -- "
  286. "%04x %04x %04x %04x %04x %04x %04x.\n",
  287. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  288. mb[4], mb[5], mb[6]);
  289. switch (aen) {
  290. /* Handle IDC Error completion case. */
  291. case MBA_IDC_COMPLETE:
  292. if (mb[1] >> 15) {
  293. vha->hw->flags.idc_compl_status = 1;
  294. if (vha->hw->notify_dcbx_comp && !vha->vp_idx)
  295. complete(&vha->hw->dcbx_comp);
  296. }
  297. break;
  298. case MBA_IDC_NOTIFY:
  299. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  300. timeout = (descr >> 8) & 0xf;
  301. ql_dbg(ql_dbg_async, vha, 0x5022,
  302. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  303. vha->host_no, event[aen & 0xff], timeout);
  304. if (!timeout)
  305. return;
  306. rval = qla2x00_post_idc_ack_work(vha, mb);
  307. if (rval != QLA_SUCCESS)
  308. ql_log(ql_log_warn, vha, 0x5023,
  309. "IDC failed to post ACK.\n");
  310. break;
  311. case MBA_IDC_TIME_EXT:
  312. vha->hw->idc_extend_tmo = descr;
  313. ql_dbg(ql_dbg_async, vha, 0x5087,
  314. "%lu Inter-Driver Communication %s -- "
  315. "Extend timeout by=%d.\n",
  316. vha->host_no, event[aen & 0xff], vha->hw->idc_extend_tmo);
  317. break;
  318. }
  319. }
  320. #define LS_UNKNOWN 2
  321. const char *
  322. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  323. {
  324. static const char *const link_speeds[] = {
  325. "1", "2", "?", "4", "8", "16", "32", "10"
  326. };
  327. #define QLA_LAST_SPEED 7
  328. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  329. return link_speeds[0];
  330. else if (speed == 0x13)
  331. return link_speeds[QLA_LAST_SPEED];
  332. else if (speed < QLA_LAST_SPEED)
  333. return link_speeds[speed];
  334. else
  335. return link_speeds[LS_UNKNOWN];
  336. }
  337. static void
  338. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  339. {
  340. struct qla_hw_data *ha = vha->hw;
  341. /*
  342. * 8200 AEN Interpretation:
  343. * mb[0] = AEN code
  344. * mb[1] = AEN Reason code
  345. * mb[2] = LSW of Peg-Halt Status-1 Register
  346. * mb[6] = MSW of Peg-Halt Status-1 Register
  347. * mb[3] = LSW of Peg-Halt Status-2 register
  348. * mb[7] = MSW of Peg-Halt Status-2 register
  349. * mb[4] = IDC Device-State Register value
  350. * mb[5] = IDC Driver-Presence Register value
  351. */
  352. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  353. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  354. mb[0], mb[1], mb[2], mb[6]);
  355. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  356. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  357. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  358. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  359. IDC_HEARTBEAT_FAILURE)) {
  360. ha->flags.nic_core_hung = 1;
  361. ql_log(ql_log_warn, vha, 0x5060,
  362. "83XX: F/W Error Reported: Check if reset required.\n");
  363. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  364. uint32_t protocol_engine_id, fw_err_code, err_level;
  365. /*
  366. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  367. * - PEG-Halt Status-1 Register:
  368. * (LSW = mb[2], MSW = mb[6])
  369. * Bits 0-7 = protocol-engine ID
  370. * Bits 8-28 = f/w error code
  371. * Bits 29-31 = Error-level
  372. * Error-level 0x1 = Non-Fatal error
  373. * Error-level 0x2 = Recoverable Fatal error
  374. * Error-level 0x4 = UnRecoverable Fatal error
  375. * - PEG-Halt Status-2 Register:
  376. * (LSW = mb[3], MSW = mb[7])
  377. */
  378. protocol_engine_id = (mb[2] & 0xff);
  379. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  380. ((mb[6] & 0x1fff) << 8));
  381. err_level = ((mb[6] & 0xe000) >> 13);
  382. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  383. "Register: protocol_engine_id=0x%x "
  384. "fw_err_code=0x%x err_level=0x%x.\n",
  385. protocol_engine_id, fw_err_code, err_level);
  386. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  387. "Register: 0x%x%x.\n", mb[7], mb[3]);
  388. if (err_level == ERR_LEVEL_NON_FATAL) {
  389. ql_log(ql_log_warn, vha, 0x5063,
  390. "Not a fatal error, f/w has recovered "
  391. "iteself.\n");
  392. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  393. ql_log(ql_log_fatal, vha, 0x5064,
  394. "Recoverable Fatal error: Chip reset "
  395. "required.\n");
  396. qla83xx_schedule_work(vha,
  397. QLA83XX_NIC_CORE_RESET);
  398. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  399. ql_log(ql_log_fatal, vha, 0x5065,
  400. "Unrecoverable Fatal error: Set FAILED "
  401. "state, reboot required.\n");
  402. qla83xx_schedule_work(vha,
  403. QLA83XX_NIC_CORE_UNRECOVERABLE);
  404. }
  405. }
  406. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  407. uint16_t peg_fw_state, nw_interface_link_up;
  408. uint16_t nw_interface_signal_detect, sfp_status;
  409. uint16_t htbt_counter, htbt_monitor_enable;
  410. uint16_t sfp_additonal_info, sfp_multirate;
  411. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  412. /*
  413. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  414. * - PEG-to-FC Status Register:
  415. * (LSW = mb[2], MSW = mb[6])
  416. * Bits 0-7 = Peg-Firmware state
  417. * Bit 8 = N/W Interface Link-up
  418. * Bit 9 = N/W Interface signal detected
  419. * Bits 10-11 = SFP Status
  420. * SFP Status 0x0 = SFP+ transceiver not expected
  421. * SFP Status 0x1 = SFP+ transceiver not present
  422. * SFP Status 0x2 = SFP+ transceiver invalid
  423. * SFP Status 0x3 = SFP+ transceiver present and
  424. * valid
  425. * Bits 12-14 = Heartbeat Counter
  426. * Bit 15 = Heartbeat Monitor Enable
  427. * Bits 16-17 = SFP Additional Info
  428. * SFP info 0x0 = Unregocnized transceiver for
  429. * Ethernet
  430. * SFP info 0x1 = SFP+ brand validation failed
  431. * SFP info 0x2 = SFP+ speed validation failed
  432. * SFP info 0x3 = SFP+ access error
  433. * Bit 18 = SFP Multirate
  434. * Bit 19 = SFP Tx Fault
  435. * Bits 20-22 = Link Speed
  436. * Bits 23-27 = Reserved
  437. * Bits 28-30 = DCBX Status
  438. * DCBX Status 0x0 = DCBX Disabled
  439. * DCBX Status 0x1 = DCBX Enabled
  440. * DCBX Status 0x2 = DCBX Exchange error
  441. * Bit 31 = Reserved
  442. */
  443. peg_fw_state = (mb[2] & 0x00ff);
  444. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  445. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  446. sfp_status = ((mb[2] & 0x0c00) >> 10);
  447. htbt_counter = ((mb[2] & 0x7000) >> 12);
  448. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  449. sfp_additonal_info = (mb[6] & 0x0003);
  450. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  451. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  452. link_speed = ((mb[6] & 0x0070) >> 4);
  453. dcbx_status = ((mb[6] & 0x7000) >> 12);
  454. ql_log(ql_log_warn, vha, 0x5066,
  455. "Peg-to-Fc Status Register:\n"
  456. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  457. "nw_interface_signal_detect=0x%x"
  458. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  459. nw_interface_link_up, nw_interface_signal_detect,
  460. sfp_status);
  461. ql_log(ql_log_warn, vha, 0x5067,
  462. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  463. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  464. htbt_counter, htbt_monitor_enable,
  465. sfp_additonal_info, sfp_multirate);
  466. ql_log(ql_log_warn, vha, 0x5068,
  467. "sfp_tx_fault=0x%x, link_state=0x%x, "
  468. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  469. dcbx_status);
  470. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  471. }
  472. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  473. ql_log(ql_log_warn, vha, 0x5069,
  474. "Heartbeat Failure encountered, chip reset "
  475. "required.\n");
  476. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  477. }
  478. }
  479. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  480. ql_log(ql_log_info, vha, 0x506a,
  481. "IDC Device-State changed = 0x%x.\n", mb[4]);
  482. if (ha->flags.nic_core_reset_owner)
  483. return;
  484. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  485. }
  486. }
  487. int
  488. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  489. {
  490. struct qla_hw_data *ha = vha->hw;
  491. scsi_qla_host_t *vp;
  492. uint32_t vp_did;
  493. unsigned long flags;
  494. int ret = 0;
  495. if (!ha->num_vhosts)
  496. return ret;
  497. spin_lock_irqsave(&ha->vport_slock, flags);
  498. list_for_each_entry(vp, &ha->vp_list, list) {
  499. vp_did = vp->d_id.b24;
  500. if (vp_did == rscn_entry) {
  501. ret = 1;
  502. break;
  503. }
  504. }
  505. spin_unlock_irqrestore(&ha->vport_slock, flags);
  506. return ret;
  507. }
  508. /**
  509. * qla2x00_async_event() - Process aynchronous events.
  510. * @ha: SCSI driver HA context
  511. * @mb: Mailbox registers (0 - 3)
  512. */
  513. void
  514. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  515. {
  516. uint16_t handle_cnt;
  517. uint16_t cnt, mbx;
  518. uint32_t handles[5];
  519. struct qla_hw_data *ha = vha->hw;
  520. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  521. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  522. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  523. uint32_t rscn_entry, host_pid, tmp_pid;
  524. unsigned long flags;
  525. fc_port_t *fcport = NULL;
  526. /* Setup to process RIO completion. */
  527. handle_cnt = 0;
  528. if (IS_CNA_CAPABLE(ha))
  529. goto skip_rio;
  530. switch (mb[0]) {
  531. case MBA_SCSI_COMPLETION:
  532. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  533. handle_cnt = 1;
  534. break;
  535. case MBA_CMPLT_1_16BIT:
  536. handles[0] = mb[1];
  537. handle_cnt = 1;
  538. mb[0] = MBA_SCSI_COMPLETION;
  539. break;
  540. case MBA_CMPLT_2_16BIT:
  541. handles[0] = mb[1];
  542. handles[1] = mb[2];
  543. handle_cnt = 2;
  544. mb[0] = MBA_SCSI_COMPLETION;
  545. break;
  546. case MBA_CMPLT_3_16BIT:
  547. handles[0] = mb[1];
  548. handles[1] = mb[2];
  549. handles[2] = mb[3];
  550. handle_cnt = 3;
  551. mb[0] = MBA_SCSI_COMPLETION;
  552. break;
  553. case MBA_CMPLT_4_16BIT:
  554. handles[0] = mb[1];
  555. handles[1] = mb[2];
  556. handles[2] = mb[3];
  557. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  558. handle_cnt = 4;
  559. mb[0] = MBA_SCSI_COMPLETION;
  560. break;
  561. case MBA_CMPLT_5_16BIT:
  562. handles[0] = mb[1];
  563. handles[1] = mb[2];
  564. handles[2] = mb[3];
  565. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  566. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  567. handle_cnt = 5;
  568. mb[0] = MBA_SCSI_COMPLETION;
  569. break;
  570. case MBA_CMPLT_2_32BIT:
  571. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  572. handles[1] = le32_to_cpu(
  573. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  574. RD_MAILBOX_REG(ha, reg, 6));
  575. handle_cnt = 2;
  576. mb[0] = MBA_SCSI_COMPLETION;
  577. break;
  578. default:
  579. break;
  580. }
  581. skip_rio:
  582. switch (mb[0]) {
  583. case MBA_SCSI_COMPLETION: /* Fast Post */
  584. if (!vha->flags.online)
  585. break;
  586. for (cnt = 0; cnt < handle_cnt; cnt++)
  587. qla2x00_process_completed_request(vha, rsp->req,
  588. handles[cnt]);
  589. break;
  590. case MBA_RESET: /* Reset */
  591. ql_dbg(ql_dbg_async, vha, 0x5002,
  592. "Asynchronous RESET.\n");
  593. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  594. break;
  595. case MBA_SYSTEM_ERR: /* System Error */
  596. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ?
  597. RD_REG_WORD(&reg24->mailbox7) : 0;
  598. ql_log(ql_log_warn, vha, 0x5003,
  599. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  600. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  601. ha->isp_ops->fw_dump(vha, 1);
  602. if (IS_FWI2_CAPABLE(ha)) {
  603. if (mb[1] == 0 && mb[2] == 0) {
  604. ql_log(ql_log_fatal, vha, 0x5004,
  605. "Unrecoverable Hardware Error: adapter "
  606. "marked OFFLINE!\n");
  607. vha->flags.online = 0;
  608. vha->device_flags |= DFLG_DEV_FAILED;
  609. } else {
  610. /* Check to see if MPI timeout occurred */
  611. if ((mbx & MBX_3) && (ha->port_no == 0))
  612. set_bit(MPI_RESET_NEEDED,
  613. &vha->dpc_flags);
  614. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  615. }
  616. } else if (mb[1] == 0) {
  617. ql_log(ql_log_fatal, vha, 0x5005,
  618. "Unrecoverable Hardware Error: adapter marked "
  619. "OFFLINE!\n");
  620. vha->flags.online = 0;
  621. vha->device_flags |= DFLG_DEV_FAILED;
  622. } else
  623. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  624. break;
  625. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  626. ql_log(ql_log_warn, vha, 0x5006,
  627. "ISP Request Transfer Error (%x).\n", mb[1]);
  628. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  629. break;
  630. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  631. ql_log(ql_log_warn, vha, 0x5007,
  632. "ISP Response Transfer Error.\n");
  633. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  634. break;
  635. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  636. ql_dbg(ql_dbg_async, vha, 0x5008,
  637. "Asynchronous WAKEUP_THRES.\n");
  638. break;
  639. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  640. ql_dbg(ql_dbg_async, vha, 0x5009,
  641. "LIP occurred (%x).\n", mb[1]);
  642. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  643. atomic_set(&vha->loop_state, LOOP_DOWN);
  644. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  645. qla2x00_mark_all_devices_lost(vha, 1);
  646. }
  647. if (vha->vp_idx) {
  648. atomic_set(&vha->vp_state, VP_FAILED);
  649. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  650. }
  651. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  652. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  653. vha->flags.management_server_logged_in = 0;
  654. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  655. break;
  656. case MBA_LOOP_UP: /* Loop Up Event */
  657. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  658. ha->link_data_rate = PORT_SPEED_1GB;
  659. else
  660. ha->link_data_rate = mb[1];
  661. ql_log(ql_log_info, vha, 0x500a,
  662. "LOOP UP detected (%s Gbps).\n",
  663. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  664. vha->flags.management_server_logged_in = 0;
  665. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  666. break;
  667. case MBA_LOOP_DOWN: /* Loop Down Event */
  668. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  669. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  670. mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(&reg82->mailbox_out[4])
  671. : mbx;
  672. ql_log(ql_log_info, vha, 0x500b,
  673. "LOOP DOWN detected (%x %x %x %x).\n",
  674. mb[1], mb[2], mb[3], mbx);
  675. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  676. atomic_set(&vha->loop_state, LOOP_DOWN);
  677. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  678. /*
  679. * In case of loop down, restore WWPN from
  680. * NVRAM in case of FA-WWPN capable ISP
  681. */
  682. if (ha->flags.fawwpn_enabled) {
  683. void *wwpn = ha->init_cb->port_name;
  684. memcpy(vha->port_name, wwpn, WWN_SIZE);
  685. }
  686. vha->device_flags |= DFLG_NO_CABLE;
  687. qla2x00_mark_all_devices_lost(vha, 1);
  688. }
  689. if (vha->vp_idx) {
  690. atomic_set(&vha->vp_state, VP_FAILED);
  691. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  692. }
  693. vha->flags.management_server_logged_in = 0;
  694. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  695. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  696. break;
  697. case MBA_LIP_RESET: /* LIP reset occurred */
  698. ql_dbg(ql_dbg_async, vha, 0x500c,
  699. "LIP reset occurred (%x).\n", mb[1]);
  700. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  701. atomic_set(&vha->loop_state, LOOP_DOWN);
  702. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  703. qla2x00_mark_all_devices_lost(vha, 1);
  704. }
  705. if (vha->vp_idx) {
  706. atomic_set(&vha->vp_state, VP_FAILED);
  707. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  708. }
  709. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  710. ha->operating_mode = LOOP;
  711. vha->flags.management_server_logged_in = 0;
  712. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  713. break;
  714. /* case MBA_DCBX_COMPLETE: */
  715. case MBA_POINT_TO_POINT: /* Point-to-Point */
  716. if (IS_QLA2100(ha))
  717. break;
  718. if (IS_CNA_CAPABLE(ha)) {
  719. ql_dbg(ql_dbg_async, vha, 0x500d,
  720. "DCBX Completed -- %04x %04x %04x.\n",
  721. mb[1], mb[2], mb[3]);
  722. if (ha->notify_dcbx_comp && !vha->vp_idx)
  723. complete(&ha->dcbx_comp);
  724. } else
  725. ql_dbg(ql_dbg_async, vha, 0x500e,
  726. "Asynchronous P2P MODE received.\n");
  727. /*
  728. * Until there's a transition from loop down to loop up, treat
  729. * this as loop down only.
  730. */
  731. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  732. atomic_set(&vha->loop_state, LOOP_DOWN);
  733. if (!atomic_read(&vha->loop_down_timer))
  734. atomic_set(&vha->loop_down_timer,
  735. LOOP_DOWN_TIME);
  736. qla2x00_mark_all_devices_lost(vha, 1);
  737. }
  738. if (vha->vp_idx) {
  739. atomic_set(&vha->vp_state, VP_FAILED);
  740. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  741. }
  742. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  743. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  744. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  745. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  746. ha->flags.gpsc_supported = 1;
  747. vha->flags.management_server_logged_in = 0;
  748. break;
  749. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  750. if (IS_QLA2100(ha))
  751. break;
  752. ql_dbg(ql_dbg_async, vha, 0x500f,
  753. "Configuration change detected: value=%x.\n", mb[1]);
  754. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  755. atomic_set(&vha->loop_state, LOOP_DOWN);
  756. if (!atomic_read(&vha->loop_down_timer))
  757. atomic_set(&vha->loop_down_timer,
  758. LOOP_DOWN_TIME);
  759. qla2x00_mark_all_devices_lost(vha, 1);
  760. }
  761. if (vha->vp_idx) {
  762. atomic_set(&vha->vp_state, VP_FAILED);
  763. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  764. }
  765. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  766. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  767. break;
  768. case MBA_PORT_UPDATE: /* Port database update */
  769. /*
  770. * Handle only global and vn-port update events
  771. *
  772. * Relevant inputs:
  773. * mb[1] = N_Port handle of changed port
  774. * OR 0xffff for global event
  775. * mb[2] = New login state
  776. * 7 = Port logged out
  777. * mb[3] = LSB is vp_idx, 0xff = all vps
  778. *
  779. * Skip processing if:
  780. * Event is global, vp_idx is NOT all vps,
  781. * vp_idx does not match
  782. * Event is not global, vp_idx does not match
  783. */
  784. if (IS_QLA2XXX_MIDTYPE(ha) &&
  785. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  786. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  787. break;
  788. /* Global event -- port logout or port unavailable. */
  789. if (mb[1] == 0xffff && mb[2] == 0x7) {
  790. ql_dbg(ql_dbg_async, vha, 0x5010,
  791. "Port unavailable %04x %04x %04x.\n",
  792. mb[1], mb[2], mb[3]);
  793. ql_log(ql_log_warn, vha, 0x505e,
  794. "Link is offline.\n");
  795. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  796. atomic_set(&vha->loop_state, LOOP_DOWN);
  797. atomic_set(&vha->loop_down_timer,
  798. LOOP_DOWN_TIME);
  799. vha->device_flags |= DFLG_NO_CABLE;
  800. qla2x00_mark_all_devices_lost(vha, 1);
  801. }
  802. if (vha->vp_idx) {
  803. atomic_set(&vha->vp_state, VP_FAILED);
  804. fc_vport_set_state(vha->fc_vport,
  805. FC_VPORT_FAILED);
  806. qla2x00_mark_all_devices_lost(vha, 1);
  807. }
  808. vha->flags.management_server_logged_in = 0;
  809. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  810. break;
  811. }
  812. /*
  813. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  814. * event etc. earlier indicating loop is down) then process
  815. * it. Otherwise ignore it and Wait for RSCN to come in.
  816. */
  817. atomic_set(&vha->loop_down_timer, 0);
  818. if (atomic_read(&vha->loop_state) != LOOP_DOWN &&
  819. atomic_read(&vha->loop_state) != LOOP_DEAD) {
  820. ql_dbg(ql_dbg_async, vha, 0x5011,
  821. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  822. mb[1], mb[2], mb[3]);
  823. qlt_async_event(mb[0], vha, mb);
  824. break;
  825. }
  826. ql_dbg(ql_dbg_async, vha, 0x5012,
  827. "Port database changed %04x %04x %04x.\n",
  828. mb[1], mb[2], mb[3]);
  829. /*
  830. * Mark all devices as missing so we will login again.
  831. */
  832. atomic_set(&vha->loop_state, LOOP_UP);
  833. qla2x00_mark_all_devices_lost(vha, 1);
  834. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  835. set_bit(SCR_PENDING, &vha->dpc_flags);
  836. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  837. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  838. qlt_async_event(mb[0], vha, mb);
  839. break;
  840. case MBA_RSCN_UPDATE: /* State Change Registration */
  841. /* Check if the Vport has issued a SCR */
  842. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  843. break;
  844. /* Only handle SCNs for our Vport index. */
  845. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  846. break;
  847. ql_dbg(ql_dbg_async, vha, 0x5013,
  848. "RSCN database changed -- %04x %04x %04x.\n",
  849. mb[1], mb[2], mb[3]);
  850. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  851. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  852. | vha->d_id.b.al_pa;
  853. if (rscn_entry == host_pid) {
  854. ql_dbg(ql_dbg_async, vha, 0x5014,
  855. "Ignoring RSCN update to local host "
  856. "port ID (%06x).\n", host_pid);
  857. break;
  858. }
  859. /* Ignore reserved bits from RSCN-payload. */
  860. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  861. /* Skip RSCNs for virtual ports on the same physical port */
  862. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  863. break;
  864. /*
  865. * Search for the rport related to this RSCN entry and mark it
  866. * as lost.
  867. */
  868. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  869. if (atomic_read(&fcport->state) != FCS_ONLINE)
  870. continue;
  871. tmp_pid = fcport->d_id.b24;
  872. if (fcport->d_id.b24 == rscn_entry) {
  873. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  874. break;
  875. }
  876. }
  877. atomic_set(&vha->loop_down_timer, 0);
  878. vha->flags.management_server_logged_in = 0;
  879. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  880. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  881. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  882. break;
  883. /* case MBA_RIO_RESPONSE: */
  884. case MBA_ZIO_RESPONSE:
  885. ql_dbg(ql_dbg_async, vha, 0x5015,
  886. "[R|Z]IO update completion.\n");
  887. if (IS_FWI2_CAPABLE(ha))
  888. qla24xx_process_response_queue(vha, rsp);
  889. else
  890. qla2x00_process_response_queue(rsp);
  891. break;
  892. case MBA_DISCARD_RND_FRAME:
  893. ql_dbg(ql_dbg_async, vha, 0x5016,
  894. "Discard RND Frame -- %04x %04x %04x.\n",
  895. mb[1], mb[2], mb[3]);
  896. break;
  897. case MBA_TRACE_NOTIFICATION:
  898. ql_dbg(ql_dbg_async, vha, 0x5017,
  899. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  900. break;
  901. case MBA_ISP84XX_ALERT:
  902. ql_dbg(ql_dbg_async, vha, 0x5018,
  903. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  904. mb[1], mb[2], mb[3]);
  905. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  906. switch (mb[1]) {
  907. case A84_PANIC_RECOVERY:
  908. ql_log(ql_log_info, vha, 0x5019,
  909. "Alert 84XX: panic recovery %04x %04x.\n",
  910. mb[2], mb[3]);
  911. break;
  912. case A84_OP_LOGIN_COMPLETE:
  913. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  914. ql_log(ql_log_info, vha, 0x501a,
  915. "Alert 84XX: firmware version %x.\n",
  916. ha->cs84xx->op_fw_version);
  917. break;
  918. case A84_DIAG_LOGIN_COMPLETE:
  919. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  920. ql_log(ql_log_info, vha, 0x501b,
  921. "Alert 84XX: diagnostic firmware version %x.\n",
  922. ha->cs84xx->diag_fw_version);
  923. break;
  924. case A84_GOLD_LOGIN_COMPLETE:
  925. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  926. ha->cs84xx->fw_update = 1;
  927. ql_log(ql_log_info, vha, 0x501c,
  928. "Alert 84XX: gold firmware version %x.\n",
  929. ha->cs84xx->gold_fw_version);
  930. break;
  931. default:
  932. ql_log(ql_log_warn, vha, 0x501d,
  933. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  934. mb[1], mb[2], mb[3]);
  935. }
  936. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  937. break;
  938. case MBA_DCBX_START:
  939. ql_dbg(ql_dbg_async, vha, 0x501e,
  940. "DCBX Started -- %04x %04x %04x.\n",
  941. mb[1], mb[2], mb[3]);
  942. break;
  943. case MBA_DCBX_PARAM_UPDATE:
  944. ql_dbg(ql_dbg_async, vha, 0x501f,
  945. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  946. mb[1], mb[2], mb[3]);
  947. break;
  948. case MBA_FCF_CONF_ERR:
  949. ql_dbg(ql_dbg_async, vha, 0x5020,
  950. "FCF Configuration Error -- %04x %04x %04x.\n",
  951. mb[1], mb[2], mb[3]);
  952. break;
  953. case MBA_IDC_NOTIFY:
  954. if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  955. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  956. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  957. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  958. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  959. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  960. /*
  961. * Extend loop down timer since port is active.
  962. */
  963. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  964. atomic_set(&vha->loop_down_timer,
  965. LOOP_DOWN_TIME);
  966. qla2xxx_wake_dpc(vha);
  967. }
  968. }
  969. case MBA_IDC_COMPLETE:
  970. if (ha->notify_lb_portup_comp && !vha->vp_idx)
  971. complete(&ha->lb_portup_comp);
  972. /* Fallthru */
  973. case MBA_IDC_TIME_EXT:
  974. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) ||
  975. IS_QLA8044(ha))
  976. qla81xx_idc_event(vha, mb[0], mb[1]);
  977. break;
  978. case MBA_IDC_AEN:
  979. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  980. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  981. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  982. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  983. qla83xx_handle_8200_aen(vha, mb);
  984. break;
  985. case MBA_DPORT_DIAGNOSTICS:
  986. ql_dbg(ql_dbg_async, vha, 0x5052,
  987. "D-Port Diagnostics: %04x %04x=%s\n", mb[0], mb[1],
  988. mb[1] == 0 ? "start" :
  989. mb[1] == 1 ? "done (ok)" :
  990. mb[1] == 2 ? "done (error)" : "other");
  991. break;
  992. default:
  993. ql_dbg(ql_dbg_async, vha, 0x5057,
  994. "Unknown AEN:%04x %04x %04x %04x\n",
  995. mb[0], mb[1], mb[2], mb[3]);
  996. }
  997. qlt_async_event(mb[0], vha, mb);
  998. if (!vha->vp_idx && ha->num_vhosts)
  999. qla2x00_alert_all_vps(rsp, mb);
  1000. }
  1001. /**
  1002. * qla2x00_process_completed_request() - Process a Fast Post response.
  1003. * @ha: SCSI driver HA context
  1004. * @index: SRB index
  1005. */
  1006. void
  1007. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  1008. struct req_que *req, uint32_t index)
  1009. {
  1010. srb_t *sp;
  1011. struct qla_hw_data *ha = vha->hw;
  1012. /* Validate handle. */
  1013. if (index >= req->num_outstanding_cmds) {
  1014. ql_log(ql_log_warn, vha, 0x3014,
  1015. "Invalid SCSI command index (%x).\n", index);
  1016. if (IS_P3P_TYPE(ha))
  1017. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1018. else
  1019. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1020. return;
  1021. }
  1022. sp = req->outstanding_cmds[index];
  1023. if (sp) {
  1024. /* Free outstanding command slot. */
  1025. req->outstanding_cmds[index] = NULL;
  1026. /* Save ISP completion status */
  1027. sp->done(ha, sp, DID_OK << 16);
  1028. } else {
  1029. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  1030. if (IS_P3P_TYPE(ha))
  1031. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1032. else
  1033. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1034. }
  1035. }
  1036. srb_t *
  1037. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  1038. struct req_que *req, void *iocb)
  1039. {
  1040. struct qla_hw_data *ha = vha->hw;
  1041. sts_entry_t *pkt = iocb;
  1042. srb_t *sp = NULL;
  1043. uint16_t index;
  1044. index = LSW(pkt->handle);
  1045. if (index >= req->num_outstanding_cmds) {
  1046. ql_log(ql_log_warn, vha, 0x5031,
  1047. "Invalid command index (%x).\n", index);
  1048. if (IS_P3P_TYPE(ha))
  1049. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1050. else
  1051. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1052. goto done;
  1053. }
  1054. sp = req->outstanding_cmds[index];
  1055. if (!sp) {
  1056. ql_log(ql_log_warn, vha, 0x5032,
  1057. "Invalid completion handle (%x) -- timed-out.\n", index);
  1058. return sp;
  1059. }
  1060. if (sp->handle != index) {
  1061. ql_log(ql_log_warn, vha, 0x5033,
  1062. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  1063. return NULL;
  1064. }
  1065. req->outstanding_cmds[index] = NULL;
  1066. done:
  1067. return sp;
  1068. }
  1069. static void
  1070. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1071. struct mbx_entry *mbx)
  1072. {
  1073. const char func[] = "MBX-IOCB";
  1074. const char *type;
  1075. fc_port_t *fcport;
  1076. srb_t *sp;
  1077. struct srb_iocb *lio;
  1078. uint16_t *data;
  1079. uint16_t status;
  1080. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1081. if (!sp)
  1082. return;
  1083. lio = &sp->u.iocb_cmd;
  1084. type = sp->name;
  1085. fcport = sp->fcport;
  1086. data = lio->u.logio.data;
  1087. data[0] = MBS_COMMAND_ERROR;
  1088. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1089. QLA_LOGIO_LOGIN_RETRIED : 0;
  1090. if (mbx->entry_status) {
  1091. ql_dbg(ql_dbg_async, vha, 0x5043,
  1092. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1093. "entry-status=%x status=%x state-flag=%x "
  1094. "status-flags=%x.\n", type, sp->handle,
  1095. fcport->d_id.b.domain, fcport->d_id.b.area,
  1096. fcport->d_id.b.al_pa, mbx->entry_status,
  1097. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1098. le16_to_cpu(mbx->status_flags));
  1099. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1100. (uint8_t *)mbx, sizeof(*mbx));
  1101. goto logio_done;
  1102. }
  1103. status = le16_to_cpu(mbx->status);
  1104. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1105. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1106. status = 0;
  1107. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1108. ql_dbg(ql_dbg_async, vha, 0x5045,
  1109. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1110. type, sp->handle, fcport->d_id.b.domain,
  1111. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1112. le16_to_cpu(mbx->mb1));
  1113. data[0] = MBS_COMMAND_COMPLETE;
  1114. if (sp->type == SRB_LOGIN_CMD) {
  1115. fcport->port_type = FCT_TARGET;
  1116. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1117. fcport->port_type = FCT_INITIATOR;
  1118. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1119. fcport->flags |= FCF_FCP2_DEVICE;
  1120. }
  1121. goto logio_done;
  1122. }
  1123. data[0] = le16_to_cpu(mbx->mb0);
  1124. switch (data[0]) {
  1125. case MBS_PORT_ID_USED:
  1126. data[1] = le16_to_cpu(mbx->mb1);
  1127. break;
  1128. case MBS_LOOP_ID_USED:
  1129. break;
  1130. default:
  1131. data[0] = MBS_COMMAND_ERROR;
  1132. break;
  1133. }
  1134. ql_log(ql_log_warn, vha, 0x5046,
  1135. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1136. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1137. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1138. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1139. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1140. le16_to_cpu(mbx->mb7));
  1141. logio_done:
  1142. sp->done(vha, sp, 0);
  1143. }
  1144. static void
  1145. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1146. sts_entry_t *pkt, int iocb_type)
  1147. {
  1148. const char func[] = "CT_IOCB";
  1149. const char *type;
  1150. srb_t *sp;
  1151. struct fc_bsg_job *bsg_job;
  1152. uint16_t comp_status;
  1153. int res;
  1154. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1155. if (!sp)
  1156. return;
  1157. bsg_job = sp->u.bsg_job;
  1158. type = "ct pass-through";
  1159. comp_status = le16_to_cpu(pkt->comp_status);
  1160. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1161. * fc payload to the caller
  1162. */
  1163. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1164. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1165. if (comp_status != CS_COMPLETE) {
  1166. if (comp_status == CS_DATA_UNDERRUN) {
  1167. res = DID_OK << 16;
  1168. bsg_job->reply->reply_payload_rcv_len =
  1169. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1170. ql_log(ql_log_warn, vha, 0x5048,
  1171. "CT pass-through-%s error "
  1172. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1173. type, comp_status,
  1174. bsg_job->reply->reply_payload_rcv_len);
  1175. } else {
  1176. ql_log(ql_log_warn, vha, 0x5049,
  1177. "CT pass-through-%s error "
  1178. "comp_status-status=0x%x.\n", type, comp_status);
  1179. res = DID_ERROR << 16;
  1180. bsg_job->reply->reply_payload_rcv_len = 0;
  1181. }
  1182. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1183. (uint8_t *)pkt, sizeof(*pkt));
  1184. } else {
  1185. res = DID_OK << 16;
  1186. bsg_job->reply->reply_payload_rcv_len =
  1187. bsg_job->reply_payload.payload_len;
  1188. bsg_job->reply_len = 0;
  1189. }
  1190. sp->done(vha, sp, res);
  1191. }
  1192. static void
  1193. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1194. struct sts_entry_24xx *pkt, int iocb_type)
  1195. {
  1196. const char func[] = "ELS_CT_IOCB";
  1197. const char *type;
  1198. srb_t *sp;
  1199. struct fc_bsg_job *bsg_job;
  1200. uint16_t comp_status;
  1201. uint32_t fw_status[3];
  1202. uint8_t* fw_sts_ptr;
  1203. int res;
  1204. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1205. if (!sp)
  1206. return;
  1207. bsg_job = sp->u.bsg_job;
  1208. type = NULL;
  1209. switch (sp->type) {
  1210. case SRB_ELS_CMD_RPT:
  1211. case SRB_ELS_CMD_HST:
  1212. type = "els";
  1213. break;
  1214. case SRB_CT_CMD:
  1215. type = "ct pass-through";
  1216. break;
  1217. default:
  1218. ql_dbg(ql_dbg_user, vha, 0x503e,
  1219. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1220. return;
  1221. }
  1222. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1223. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1224. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1225. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1226. * fc payload to the caller
  1227. */
  1228. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1229. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1230. if (comp_status != CS_COMPLETE) {
  1231. if (comp_status == CS_DATA_UNDERRUN) {
  1232. res = DID_OK << 16;
  1233. bsg_job->reply->reply_payload_rcv_len =
  1234. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1235. ql_dbg(ql_dbg_user, vha, 0x503f,
  1236. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1237. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1238. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1239. le16_to_cpu(((struct els_sts_entry_24xx *)
  1240. pkt)->total_byte_count));
  1241. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1242. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1243. }
  1244. else {
  1245. ql_dbg(ql_dbg_user, vha, 0x5040,
  1246. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1247. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1248. type, sp->handle, comp_status,
  1249. le16_to_cpu(((struct els_sts_entry_24xx *)
  1250. pkt)->error_subcode_1),
  1251. le16_to_cpu(((struct els_sts_entry_24xx *)
  1252. pkt)->error_subcode_2));
  1253. res = DID_ERROR << 16;
  1254. bsg_job->reply->reply_payload_rcv_len = 0;
  1255. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1256. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1257. }
  1258. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1259. (uint8_t *)pkt, sizeof(*pkt));
  1260. }
  1261. else {
  1262. res = DID_OK << 16;
  1263. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1264. bsg_job->reply_len = 0;
  1265. }
  1266. sp->done(vha, sp, res);
  1267. }
  1268. static void
  1269. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1270. struct logio_entry_24xx *logio)
  1271. {
  1272. const char func[] = "LOGIO-IOCB";
  1273. const char *type;
  1274. fc_port_t *fcport;
  1275. srb_t *sp;
  1276. struct srb_iocb *lio;
  1277. uint16_t *data;
  1278. uint32_t iop[2];
  1279. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1280. if (!sp)
  1281. return;
  1282. lio = &sp->u.iocb_cmd;
  1283. type = sp->name;
  1284. fcport = sp->fcport;
  1285. data = lio->u.logio.data;
  1286. data[0] = MBS_COMMAND_ERROR;
  1287. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1288. QLA_LOGIO_LOGIN_RETRIED : 0;
  1289. if (logio->entry_status) {
  1290. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1291. "Async-%s error entry - hdl=%x"
  1292. "portid=%02x%02x%02x entry-status=%x.\n",
  1293. type, sp->handle, fcport->d_id.b.domain,
  1294. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1295. logio->entry_status);
  1296. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1297. (uint8_t *)logio, sizeof(*logio));
  1298. goto logio_done;
  1299. }
  1300. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1301. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1302. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1303. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1304. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1305. le32_to_cpu(logio->io_parameter[0]));
  1306. data[0] = MBS_COMMAND_COMPLETE;
  1307. if (sp->type != SRB_LOGIN_CMD)
  1308. goto logio_done;
  1309. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1310. if (iop[0] & BIT_4) {
  1311. fcport->port_type = FCT_TARGET;
  1312. if (iop[0] & BIT_8)
  1313. fcport->flags |= FCF_FCP2_DEVICE;
  1314. } else if (iop[0] & BIT_5)
  1315. fcport->port_type = FCT_INITIATOR;
  1316. if (iop[0] & BIT_7)
  1317. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1318. if (logio->io_parameter[7] || logio->io_parameter[8])
  1319. fcport->supported_classes |= FC_COS_CLASS2;
  1320. if (logio->io_parameter[9] || logio->io_parameter[10])
  1321. fcport->supported_classes |= FC_COS_CLASS3;
  1322. goto logio_done;
  1323. }
  1324. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1325. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1326. switch (iop[0]) {
  1327. case LSC_SCODE_PORTID_USED:
  1328. data[0] = MBS_PORT_ID_USED;
  1329. data[1] = LSW(iop[1]);
  1330. break;
  1331. case LSC_SCODE_NPORT_USED:
  1332. data[0] = MBS_LOOP_ID_USED;
  1333. break;
  1334. default:
  1335. data[0] = MBS_COMMAND_ERROR;
  1336. break;
  1337. }
  1338. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1339. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1340. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1341. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1342. le16_to_cpu(logio->comp_status),
  1343. le32_to_cpu(logio->io_parameter[0]),
  1344. le32_to_cpu(logio->io_parameter[1]));
  1345. logio_done:
  1346. sp->done(vha, sp, 0);
  1347. }
  1348. static void
  1349. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
  1350. {
  1351. const char func[] = "TMF-IOCB";
  1352. const char *type;
  1353. fc_port_t *fcport;
  1354. srb_t *sp;
  1355. struct srb_iocb *iocb;
  1356. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1357. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1358. if (!sp)
  1359. return;
  1360. iocb = &sp->u.iocb_cmd;
  1361. type = sp->name;
  1362. fcport = sp->fcport;
  1363. iocb->u.tmf.data = QLA_SUCCESS;
  1364. if (sts->entry_status) {
  1365. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1366. "Async-%s error - hdl=%x entry-status(%x).\n",
  1367. type, sp->handle, sts->entry_status);
  1368. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1369. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1370. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1371. "Async-%s error - hdl=%x completion status(%x).\n",
  1372. type, sp->handle, sts->comp_status);
  1373. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1374. } else if ((le16_to_cpu(sts->scsi_status) &
  1375. SS_RESPONSE_INFO_LEN_VALID)) {
  1376. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1377. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1378. "Async-%s error - hdl=%x not enough response(%d).\n",
  1379. type, sp->handle, sts->rsp_data_len);
  1380. } else if (sts->data[3]) {
  1381. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1382. "Async-%s error - hdl=%x response(%x).\n",
  1383. type, sp->handle, sts->data[3]);
  1384. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1385. }
  1386. }
  1387. if (iocb->u.tmf.data != QLA_SUCCESS)
  1388. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1389. (uint8_t *)sts, sizeof(*sts));
  1390. sp->done(vha, sp, 0);
  1391. }
  1392. /**
  1393. * qla2x00_process_response_queue() - Process response queue entries.
  1394. * @ha: SCSI driver HA context
  1395. */
  1396. void
  1397. qla2x00_process_response_queue(struct rsp_que *rsp)
  1398. {
  1399. struct scsi_qla_host *vha;
  1400. struct qla_hw_data *ha = rsp->hw;
  1401. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1402. sts_entry_t *pkt;
  1403. uint16_t handle_cnt;
  1404. uint16_t cnt;
  1405. vha = pci_get_drvdata(ha->pdev);
  1406. if (!vha->flags.online)
  1407. return;
  1408. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1409. pkt = (sts_entry_t *)rsp->ring_ptr;
  1410. rsp->ring_index++;
  1411. if (rsp->ring_index == rsp->length) {
  1412. rsp->ring_index = 0;
  1413. rsp->ring_ptr = rsp->ring;
  1414. } else {
  1415. rsp->ring_ptr++;
  1416. }
  1417. if (pkt->entry_status != 0) {
  1418. qla2x00_error_entry(vha, rsp, pkt);
  1419. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1420. wmb();
  1421. continue;
  1422. }
  1423. switch (pkt->entry_type) {
  1424. case STATUS_TYPE:
  1425. qla2x00_status_entry(vha, rsp, pkt);
  1426. break;
  1427. case STATUS_TYPE_21:
  1428. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1429. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1430. qla2x00_process_completed_request(vha, rsp->req,
  1431. ((sts21_entry_t *)pkt)->handle[cnt]);
  1432. }
  1433. break;
  1434. case STATUS_TYPE_22:
  1435. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1436. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1437. qla2x00_process_completed_request(vha, rsp->req,
  1438. ((sts22_entry_t *)pkt)->handle[cnt]);
  1439. }
  1440. break;
  1441. case STATUS_CONT_TYPE:
  1442. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1443. break;
  1444. case MBX_IOCB_TYPE:
  1445. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1446. (struct mbx_entry *)pkt);
  1447. break;
  1448. case CT_IOCB_TYPE:
  1449. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1450. break;
  1451. default:
  1452. /* Type Not Supported. */
  1453. ql_log(ql_log_warn, vha, 0x504a,
  1454. "Received unknown response pkt type %x "
  1455. "entry status=%x.\n",
  1456. pkt->entry_type, pkt->entry_status);
  1457. break;
  1458. }
  1459. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1460. wmb();
  1461. }
  1462. /* Adjust ring index */
  1463. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1464. }
  1465. static inline void
  1466. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1467. uint32_t sense_len, struct rsp_que *rsp, int res)
  1468. {
  1469. struct scsi_qla_host *vha = sp->fcport->vha;
  1470. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1471. uint32_t track_sense_len;
  1472. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1473. sense_len = SCSI_SENSE_BUFFERSIZE;
  1474. SET_CMD_SENSE_LEN(sp, sense_len);
  1475. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1476. track_sense_len = sense_len;
  1477. if (sense_len > par_sense_len)
  1478. sense_len = par_sense_len;
  1479. memcpy(cp->sense_buffer, sense_data, sense_len);
  1480. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1481. track_sense_len -= sense_len;
  1482. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1483. if (track_sense_len != 0) {
  1484. rsp->status_srb = sp;
  1485. cp->result = res;
  1486. }
  1487. if (sense_len) {
  1488. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1489. "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
  1490. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1491. cp);
  1492. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1493. cp->sense_buffer, sense_len);
  1494. }
  1495. }
  1496. struct scsi_dif_tuple {
  1497. __be16 guard; /* Checksum */
  1498. __be16 app_tag; /* APPL identifier */
  1499. __be32 ref_tag; /* Target LBA or indirect LBA */
  1500. };
  1501. /*
  1502. * Checks the guard or meta-data for the type of error
  1503. * detected by the HBA. In case of errors, we set the
  1504. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1505. * to indicate to the kernel that the HBA detected error.
  1506. */
  1507. static inline int
  1508. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1509. {
  1510. struct scsi_qla_host *vha = sp->fcport->vha;
  1511. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1512. uint8_t *ap = &sts24->data[12];
  1513. uint8_t *ep = &sts24->data[20];
  1514. uint32_t e_ref_tag, a_ref_tag;
  1515. uint16_t e_app_tag, a_app_tag;
  1516. uint16_t e_guard, a_guard;
  1517. /*
  1518. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1519. * would make guard field appear at offset 2
  1520. */
  1521. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1522. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1523. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1524. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1525. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1526. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1527. ql_dbg(ql_dbg_io, vha, 0x3023,
  1528. "iocb(s) %p Returned STATUS.\n", sts24);
  1529. ql_dbg(ql_dbg_io, vha, 0x3024,
  1530. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1531. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1532. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1533. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1534. a_app_tag, e_app_tag, a_guard, e_guard);
  1535. /*
  1536. * Ignore sector if:
  1537. * For type 3: ref & app tag is all 'f's
  1538. * For type 0,1,2: app tag is all 'f's
  1539. */
  1540. if ((a_app_tag == 0xffff) &&
  1541. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1542. (a_ref_tag == 0xffffffff))) {
  1543. uint32_t blocks_done, resid;
  1544. sector_t lba_s = scsi_get_lba(cmd);
  1545. /* 2TB boundary case covered automatically with this */
  1546. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1547. resid = scsi_bufflen(cmd) - (blocks_done *
  1548. cmd->device->sector_size);
  1549. scsi_set_resid(cmd, resid);
  1550. cmd->result = DID_OK << 16;
  1551. /* Update protection tag */
  1552. if (scsi_prot_sg_count(cmd)) {
  1553. uint32_t i, j = 0, k = 0, num_ent;
  1554. struct scatterlist *sg;
  1555. struct sd_dif_tuple *spt;
  1556. /* Patch the corresponding protection tags */
  1557. scsi_for_each_prot_sg(cmd, sg,
  1558. scsi_prot_sg_count(cmd), i) {
  1559. num_ent = sg_dma_len(sg) / 8;
  1560. if (k + num_ent < blocks_done) {
  1561. k += num_ent;
  1562. continue;
  1563. }
  1564. j = blocks_done - k - 1;
  1565. k = blocks_done;
  1566. break;
  1567. }
  1568. if (k != blocks_done) {
  1569. ql_log(ql_log_warn, vha, 0x302f,
  1570. "unexpected tag values tag:lba=%x:%llx)\n",
  1571. e_ref_tag, (unsigned long long)lba_s);
  1572. return 1;
  1573. }
  1574. spt = page_address(sg_page(sg)) + sg->offset;
  1575. spt += j;
  1576. spt->app_tag = 0xffff;
  1577. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1578. spt->ref_tag = 0xffffffff;
  1579. }
  1580. return 0;
  1581. }
  1582. /* check guard */
  1583. if (e_guard != a_guard) {
  1584. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1585. 0x10, 0x1);
  1586. set_driver_byte(cmd, DRIVER_SENSE);
  1587. set_host_byte(cmd, DID_ABORT);
  1588. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1589. return 1;
  1590. }
  1591. /* check ref tag */
  1592. if (e_ref_tag != a_ref_tag) {
  1593. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1594. 0x10, 0x3);
  1595. set_driver_byte(cmd, DRIVER_SENSE);
  1596. set_host_byte(cmd, DID_ABORT);
  1597. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1598. return 1;
  1599. }
  1600. /* check appl tag */
  1601. if (e_app_tag != a_app_tag) {
  1602. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1603. 0x10, 0x2);
  1604. set_driver_byte(cmd, DRIVER_SENSE);
  1605. set_host_byte(cmd, DID_ABORT);
  1606. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1607. return 1;
  1608. }
  1609. return 1;
  1610. }
  1611. static void
  1612. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1613. struct req_que *req, uint32_t index)
  1614. {
  1615. struct qla_hw_data *ha = vha->hw;
  1616. srb_t *sp;
  1617. uint16_t comp_status;
  1618. uint16_t scsi_status;
  1619. uint16_t thread_id;
  1620. uint32_t rval = EXT_STATUS_OK;
  1621. struct fc_bsg_job *bsg_job = NULL;
  1622. sts_entry_t *sts;
  1623. struct sts_entry_24xx *sts24;
  1624. sts = (sts_entry_t *) pkt;
  1625. sts24 = (struct sts_entry_24xx *) pkt;
  1626. /* Validate handle. */
  1627. if (index >= req->num_outstanding_cmds) {
  1628. ql_log(ql_log_warn, vha, 0x70af,
  1629. "Invalid SCSI completion handle 0x%x.\n", index);
  1630. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1631. return;
  1632. }
  1633. sp = req->outstanding_cmds[index];
  1634. if (sp) {
  1635. /* Free outstanding command slot. */
  1636. req->outstanding_cmds[index] = NULL;
  1637. bsg_job = sp->u.bsg_job;
  1638. } else {
  1639. ql_log(ql_log_warn, vha, 0x70b0,
  1640. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1641. req->id, index);
  1642. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1643. return;
  1644. }
  1645. if (IS_FWI2_CAPABLE(ha)) {
  1646. comp_status = le16_to_cpu(sts24->comp_status);
  1647. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1648. } else {
  1649. comp_status = le16_to_cpu(sts->comp_status);
  1650. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1651. }
  1652. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1653. switch (comp_status) {
  1654. case CS_COMPLETE:
  1655. if (scsi_status == 0) {
  1656. bsg_job->reply->reply_payload_rcv_len =
  1657. bsg_job->reply_payload.payload_len;
  1658. vha->qla_stats.input_bytes +=
  1659. bsg_job->reply->reply_payload_rcv_len;
  1660. vha->qla_stats.input_requests++;
  1661. rval = EXT_STATUS_OK;
  1662. }
  1663. goto done;
  1664. case CS_DATA_OVERRUN:
  1665. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1666. "Command completed with date overrun thread_id=%d\n",
  1667. thread_id);
  1668. rval = EXT_STATUS_DATA_OVERRUN;
  1669. break;
  1670. case CS_DATA_UNDERRUN:
  1671. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1672. "Command completed with date underrun thread_id=%d\n",
  1673. thread_id);
  1674. rval = EXT_STATUS_DATA_UNDERRUN;
  1675. break;
  1676. case CS_BIDIR_RD_OVERRUN:
  1677. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1678. "Command completed with read data overrun thread_id=%d\n",
  1679. thread_id);
  1680. rval = EXT_STATUS_DATA_OVERRUN;
  1681. break;
  1682. case CS_BIDIR_RD_WR_OVERRUN:
  1683. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1684. "Command completed with read and write data overrun "
  1685. "thread_id=%d\n", thread_id);
  1686. rval = EXT_STATUS_DATA_OVERRUN;
  1687. break;
  1688. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1689. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1690. "Command completed with read data over and write data "
  1691. "underrun thread_id=%d\n", thread_id);
  1692. rval = EXT_STATUS_DATA_OVERRUN;
  1693. break;
  1694. case CS_BIDIR_RD_UNDERRUN:
  1695. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1696. "Command completed with read data data underrun "
  1697. "thread_id=%d\n", thread_id);
  1698. rval = EXT_STATUS_DATA_UNDERRUN;
  1699. break;
  1700. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1701. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1702. "Command completed with read data under and write data "
  1703. "overrun thread_id=%d\n", thread_id);
  1704. rval = EXT_STATUS_DATA_UNDERRUN;
  1705. break;
  1706. case CS_BIDIR_RD_WR_UNDERRUN:
  1707. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1708. "Command completed with read and write data underrun "
  1709. "thread_id=%d\n", thread_id);
  1710. rval = EXT_STATUS_DATA_UNDERRUN;
  1711. break;
  1712. case CS_BIDIR_DMA:
  1713. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1714. "Command completed with data DMA error thread_id=%d\n",
  1715. thread_id);
  1716. rval = EXT_STATUS_DMA_ERR;
  1717. break;
  1718. case CS_TIMEOUT:
  1719. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1720. "Command completed with timeout thread_id=%d\n",
  1721. thread_id);
  1722. rval = EXT_STATUS_TIMEOUT;
  1723. break;
  1724. default:
  1725. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1726. "Command completed with completion status=0x%x "
  1727. "thread_id=%d\n", comp_status, thread_id);
  1728. rval = EXT_STATUS_ERR;
  1729. break;
  1730. }
  1731. bsg_job->reply->reply_payload_rcv_len = 0;
  1732. done:
  1733. /* Return the vendor specific reply to API */
  1734. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1735. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1736. /* Always return DID_OK, bsg will send the vendor specific response
  1737. * in this case only */
  1738. sp->done(vha, sp, (DID_OK << 6));
  1739. }
  1740. /**
  1741. * qla2x00_status_entry() - Process a Status IOCB entry.
  1742. * @ha: SCSI driver HA context
  1743. * @pkt: Entry pointer
  1744. */
  1745. static void
  1746. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1747. {
  1748. srb_t *sp;
  1749. fc_port_t *fcport;
  1750. struct scsi_cmnd *cp;
  1751. sts_entry_t *sts;
  1752. struct sts_entry_24xx *sts24;
  1753. uint16_t comp_status;
  1754. uint16_t scsi_status;
  1755. uint16_t ox_id;
  1756. uint8_t lscsi_status;
  1757. int32_t resid;
  1758. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1759. fw_resid_len;
  1760. uint8_t *rsp_info, *sense_data;
  1761. struct qla_hw_data *ha = vha->hw;
  1762. uint32_t handle;
  1763. uint16_t que;
  1764. struct req_que *req;
  1765. int logit = 1;
  1766. int res = 0;
  1767. uint16_t state_flags = 0;
  1768. uint16_t retry_delay = 0;
  1769. sts = (sts_entry_t *) pkt;
  1770. sts24 = (struct sts_entry_24xx *) pkt;
  1771. if (IS_FWI2_CAPABLE(ha)) {
  1772. comp_status = le16_to_cpu(sts24->comp_status);
  1773. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1774. state_flags = le16_to_cpu(sts24->state_flags);
  1775. } else {
  1776. comp_status = le16_to_cpu(sts->comp_status);
  1777. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1778. }
  1779. handle = (uint32_t) LSW(sts->handle);
  1780. que = MSW(sts->handle);
  1781. req = ha->req_q_map[que];
  1782. /* Check for invalid queue pointer */
  1783. if (req == NULL ||
  1784. que >= find_first_zero_bit(ha->req_qid_map, ha->max_req_queues)) {
  1785. ql_dbg(ql_dbg_io, vha, 0x3059,
  1786. "Invalid status handle (0x%x): Bad req pointer. req=%p, "
  1787. "que=%u.\n", sts->handle, req, que);
  1788. return;
  1789. }
  1790. /* Validate handle. */
  1791. if (handle < req->num_outstanding_cmds)
  1792. sp = req->outstanding_cmds[handle];
  1793. else
  1794. sp = NULL;
  1795. if (sp == NULL) {
  1796. ql_dbg(ql_dbg_io, vha, 0x3017,
  1797. "Invalid status handle (0x%x).\n", sts->handle);
  1798. if (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
  1799. if (IS_P3P_TYPE(ha))
  1800. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1801. else
  1802. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1803. qla2xxx_wake_dpc(vha);
  1804. }
  1805. return;
  1806. }
  1807. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1808. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1809. return;
  1810. }
  1811. /* Task Management completion. */
  1812. if (sp->type == SRB_TM_CMD) {
  1813. qla24xx_tm_iocb_entry(vha, req, pkt);
  1814. return;
  1815. }
  1816. /* Fast path completion. */
  1817. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1818. qla2x00_process_completed_request(vha, req, handle);
  1819. return;
  1820. }
  1821. req->outstanding_cmds[handle] = NULL;
  1822. cp = GET_CMD_SP(sp);
  1823. if (cp == NULL) {
  1824. ql_dbg(ql_dbg_io, vha, 0x3018,
  1825. "Command already returned (0x%x/%p).\n",
  1826. sts->handle, sp);
  1827. return;
  1828. }
  1829. lscsi_status = scsi_status & STATUS_MASK;
  1830. fcport = sp->fcport;
  1831. ox_id = 0;
  1832. sense_len = par_sense_len = rsp_info_len = resid_len =
  1833. fw_resid_len = 0;
  1834. if (IS_FWI2_CAPABLE(ha)) {
  1835. if (scsi_status & SS_SENSE_LEN_VALID)
  1836. sense_len = le32_to_cpu(sts24->sense_len);
  1837. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1838. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1839. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1840. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1841. if (comp_status == CS_DATA_UNDERRUN)
  1842. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1843. rsp_info = sts24->data;
  1844. sense_data = sts24->data;
  1845. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1846. ox_id = le16_to_cpu(sts24->ox_id);
  1847. par_sense_len = sizeof(sts24->data);
  1848. /* Valid values of the retry delay timer are 0x1-0xffef */
  1849. if (sts24->retry_delay > 0 && sts24->retry_delay < 0xfff1)
  1850. retry_delay = sts24->retry_delay;
  1851. } else {
  1852. if (scsi_status & SS_SENSE_LEN_VALID)
  1853. sense_len = le16_to_cpu(sts->req_sense_length);
  1854. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1855. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1856. resid_len = le32_to_cpu(sts->residual_length);
  1857. rsp_info = sts->rsp_info;
  1858. sense_data = sts->req_sense_data;
  1859. par_sense_len = sizeof(sts->req_sense_data);
  1860. }
  1861. /* Check for any FCP transport errors. */
  1862. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1863. /* Sense data lies beyond any FCP RESPONSE data. */
  1864. if (IS_FWI2_CAPABLE(ha)) {
  1865. sense_data += rsp_info_len;
  1866. par_sense_len -= rsp_info_len;
  1867. }
  1868. if (rsp_info_len > 3 && rsp_info[3]) {
  1869. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1870. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1871. rsp_info_len, rsp_info[3]);
  1872. res = DID_BUS_BUSY << 16;
  1873. goto out;
  1874. }
  1875. }
  1876. /* Check for overrun. */
  1877. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1878. scsi_status & SS_RESIDUAL_OVER)
  1879. comp_status = CS_DATA_OVERRUN;
  1880. /*
  1881. * Check retry_delay_timer value if we receive a busy or
  1882. * queue full.
  1883. */
  1884. if (lscsi_status == SAM_STAT_TASK_SET_FULL ||
  1885. lscsi_status == SAM_STAT_BUSY)
  1886. qla2x00_set_retry_delay_timestamp(fcport, retry_delay);
  1887. /*
  1888. * Based on Host and scsi status generate status code for Linux
  1889. */
  1890. switch (comp_status) {
  1891. case CS_COMPLETE:
  1892. case CS_QUEUE_FULL:
  1893. if (scsi_status == 0) {
  1894. res = DID_OK << 16;
  1895. break;
  1896. }
  1897. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1898. resid = resid_len;
  1899. scsi_set_resid(cp, resid);
  1900. if (!lscsi_status &&
  1901. ((unsigned)(scsi_bufflen(cp) - resid) <
  1902. cp->underflow)) {
  1903. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1904. "Mid-layer underflow "
  1905. "detected (0x%x of 0x%x bytes).\n",
  1906. resid, scsi_bufflen(cp));
  1907. res = DID_ERROR << 16;
  1908. break;
  1909. }
  1910. }
  1911. res = DID_OK << 16 | lscsi_status;
  1912. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1913. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1914. "QUEUE FULL detected.\n");
  1915. break;
  1916. }
  1917. logit = 0;
  1918. if (lscsi_status != SS_CHECK_CONDITION)
  1919. break;
  1920. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1921. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1922. break;
  1923. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1924. rsp, res);
  1925. break;
  1926. case CS_DATA_UNDERRUN:
  1927. /* Use F/W calculated residual length. */
  1928. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1929. scsi_set_resid(cp, resid);
  1930. if (scsi_status & SS_RESIDUAL_UNDER) {
  1931. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1932. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1933. "Dropped frame(s) detected "
  1934. "(0x%x of 0x%x bytes).\n",
  1935. resid, scsi_bufflen(cp));
  1936. res = DID_ERROR << 16 | lscsi_status;
  1937. goto check_scsi_status;
  1938. }
  1939. if (!lscsi_status &&
  1940. ((unsigned)(scsi_bufflen(cp) - resid) <
  1941. cp->underflow)) {
  1942. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1943. "Mid-layer underflow "
  1944. "detected (0x%x of 0x%x bytes).\n",
  1945. resid, scsi_bufflen(cp));
  1946. res = DID_ERROR << 16;
  1947. break;
  1948. }
  1949. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1950. lscsi_status != SAM_STAT_BUSY) {
  1951. /*
  1952. * scsi status of task set and busy are considered to be
  1953. * task not completed.
  1954. */
  1955. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1956. "Dropped frame(s) detected (0x%x "
  1957. "of 0x%x bytes).\n", resid,
  1958. scsi_bufflen(cp));
  1959. res = DID_ERROR << 16 | lscsi_status;
  1960. goto check_scsi_status;
  1961. } else {
  1962. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1963. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1964. scsi_status, lscsi_status);
  1965. }
  1966. res = DID_OK << 16 | lscsi_status;
  1967. logit = 0;
  1968. check_scsi_status:
  1969. /*
  1970. * Check to see if SCSI Status is non zero. If so report SCSI
  1971. * Status.
  1972. */
  1973. if (lscsi_status != 0) {
  1974. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1975. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1976. "QUEUE FULL detected.\n");
  1977. logit = 1;
  1978. break;
  1979. }
  1980. if (lscsi_status != SS_CHECK_CONDITION)
  1981. break;
  1982. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1983. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1984. break;
  1985. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1986. sense_len, rsp, res);
  1987. }
  1988. break;
  1989. case CS_PORT_LOGGED_OUT:
  1990. case CS_PORT_CONFIG_CHG:
  1991. case CS_PORT_BUSY:
  1992. case CS_INCOMPLETE:
  1993. case CS_PORT_UNAVAILABLE:
  1994. case CS_TIMEOUT:
  1995. case CS_RESET:
  1996. /*
  1997. * We are going to have the fc class block the rport
  1998. * while we try to recover so instruct the mid layer
  1999. * to requeue until the class decides how to handle this.
  2000. */
  2001. res = DID_TRANSPORT_DISRUPTED << 16;
  2002. if (comp_status == CS_TIMEOUT) {
  2003. if (IS_FWI2_CAPABLE(ha))
  2004. break;
  2005. else if ((le16_to_cpu(sts->status_flags) &
  2006. SF_LOGOUT_SENT) == 0)
  2007. break;
  2008. }
  2009. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  2010. "Port to be marked lost on fcport=%02x%02x%02x, current "
  2011. "port state= %s.\n", fcport->d_id.b.domain,
  2012. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  2013. port_state_str[atomic_read(&fcport->state)]);
  2014. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2015. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2016. break;
  2017. case CS_ABORTED:
  2018. res = DID_RESET << 16;
  2019. break;
  2020. case CS_DIF_ERROR:
  2021. logit = qla2x00_handle_dif_error(sp, sts24);
  2022. res = cp->result;
  2023. break;
  2024. case CS_TRANSPORT:
  2025. res = DID_ERROR << 16;
  2026. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  2027. break;
  2028. if (state_flags & BIT_4)
  2029. scmd_printk(KERN_WARNING, cp,
  2030. "Unsupported device '%s' found.\n",
  2031. cp->device->vendor);
  2032. break;
  2033. default:
  2034. res = DID_ERROR << 16;
  2035. break;
  2036. }
  2037. out:
  2038. if (logit)
  2039. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  2040. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
  2041. "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
  2042. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  2043. comp_status, scsi_status, res, vha->host_no,
  2044. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  2045. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  2046. cp->cmnd, scsi_bufflen(cp), rsp_info_len,
  2047. resid_len, fw_resid_len);
  2048. if (rsp->status_srb == NULL)
  2049. sp->done(ha, sp, res);
  2050. }
  2051. /**
  2052. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  2053. * @ha: SCSI driver HA context
  2054. * @pkt: Entry pointer
  2055. *
  2056. * Extended sense data.
  2057. */
  2058. static void
  2059. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2060. {
  2061. uint8_t sense_sz = 0;
  2062. struct qla_hw_data *ha = rsp->hw;
  2063. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2064. srb_t *sp = rsp->status_srb;
  2065. struct scsi_cmnd *cp;
  2066. uint32_t sense_len;
  2067. uint8_t *sense_ptr;
  2068. if (!sp || !GET_CMD_SENSE_LEN(sp))
  2069. return;
  2070. sense_len = GET_CMD_SENSE_LEN(sp);
  2071. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2072. cp = GET_CMD_SP(sp);
  2073. if (cp == NULL) {
  2074. ql_log(ql_log_warn, vha, 0x3025,
  2075. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2076. rsp->status_srb = NULL;
  2077. return;
  2078. }
  2079. if (sense_len > sizeof(pkt->data))
  2080. sense_sz = sizeof(pkt->data);
  2081. else
  2082. sense_sz = sense_len;
  2083. /* Move sense data. */
  2084. if (IS_FWI2_CAPABLE(ha))
  2085. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  2086. memcpy(sense_ptr, pkt->data, sense_sz);
  2087. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  2088. sense_ptr, sense_sz);
  2089. sense_len -= sense_sz;
  2090. sense_ptr += sense_sz;
  2091. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2092. SET_CMD_SENSE_LEN(sp, sense_len);
  2093. /* Place command on done queue. */
  2094. if (sense_len == 0) {
  2095. rsp->status_srb = NULL;
  2096. sp->done(ha, sp, cp->result);
  2097. }
  2098. }
  2099. /**
  2100. * qla2x00_error_entry() - Process an error entry.
  2101. * @ha: SCSI driver HA context
  2102. * @pkt: Entry pointer
  2103. */
  2104. static void
  2105. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2106. {
  2107. srb_t *sp;
  2108. struct qla_hw_data *ha = vha->hw;
  2109. const char func[] = "ERROR-IOCB";
  2110. uint16_t que = MSW(pkt->handle);
  2111. struct req_que *req = NULL;
  2112. int res = DID_ERROR << 16;
  2113. ql_dbg(ql_dbg_async, vha, 0x502a,
  2114. "type of error status in response: 0x%x\n", pkt->entry_status);
  2115. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2116. goto fatal;
  2117. req = ha->req_q_map[que];
  2118. if (pkt->entry_status & RF_BUSY)
  2119. res = DID_BUS_BUSY << 16;
  2120. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2121. if (sp) {
  2122. sp->done(ha, sp, res);
  2123. return;
  2124. }
  2125. fatal:
  2126. ql_log(ql_log_warn, vha, 0x5030,
  2127. "Error entry - invalid handle/queue.\n");
  2128. if (IS_P3P_TYPE(ha))
  2129. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2130. else
  2131. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2132. qla2xxx_wake_dpc(vha);
  2133. }
  2134. /**
  2135. * qla24xx_mbx_completion() - Process mailbox command completions.
  2136. * @ha: SCSI driver HA context
  2137. * @mb0: Mailbox0 register
  2138. */
  2139. static void
  2140. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2141. {
  2142. uint16_t cnt;
  2143. uint32_t mboxes;
  2144. uint16_t __iomem *wptr;
  2145. struct qla_hw_data *ha = vha->hw;
  2146. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2147. /* Read all mbox registers? */
  2148. mboxes = (1 << ha->mbx_count) - 1;
  2149. if (!ha->mcp)
  2150. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2151. else
  2152. mboxes = ha->mcp->in_mb;
  2153. /* Load return mailbox registers. */
  2154. ha->flags.mbox_int = 1;
  2155. ha->mailbox_out[0] = mb0;
  2156. mboxes >>= 1;
  2157. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2158. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2159. if (mboxes & BIT_0)
  2160. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2161. mboxes >>= 1;
  2162. wptr++;
  2163. }
  2164. }
  2165. static void
  2166. qla24xx_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  2167. struct abort_entry_24xx *pkt)
  2168. {
  2169. const char func[] = "ABT_IOCB";
  2170. srb_t *sp;
  2171. struct srb_iocb *abt;
  2172. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2173. if (!sp)
  2174. return;
  2175. abt = &sp->u.iocb_cmd;
  2176. abt->u.abt.comp_status = le32_to_cpu(pkt->nport_handle);
  2177. sp->done(vha, sp, 0);
  2178. }
  2179. /**
  2180. * qla24xx_process_response_queue() - Process response queue entries.
  2181. * @ha: SCSI driver HA context
  2182. */
  2183. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2184. struct rsp_que *rsp)
  2185. {
  2186. struct sts_entry_24xx *pkt;
  2187. struct qla_hw_data *ha = vha->hw;
  2188. if (!vha->flags.online)
  2189. return;
  2190. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2191. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2192. rsp->ring_index++;
  2193. if (rsp->ring_index == rsp->length) {
  2194. rsp->ring_index = 0;
  2195. rsp->ring_ptr = rsp->ring;
  2196. } else {
  2197. rsp->ring_ptr++;
  2198. }
  2199. if (pkt->entry_status != 0) {
  2200. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2201. if (qlt_24xx_process_response_error(vha, pkt))
  2202. goto process_err;
  2203. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2204. wmb();
  2205. continue;
  2206. }
  2207. process_err:
  2208. switch (pkt->entry_type) {
  2209. case STATUS_TYPE:
  2210. qla2x00_status_entry(vha, rsp, pkt);
  2211. break;
  2212. case STATUS_CONT_TYPE:
  2213. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2214. break;
  2215. case VP_RPT_ID_IOCB_TYPE:
  2216. qla24xx_report_id_acquisition(vha,
  2217. (struct vp_rpt_id_entry_24xx *)pkt);
  2218. break;
  2219. case LOGINOUT_PORT_IOCB_TYPE:
  2220. qla24xx_logio_entry(vha, rsp->req,
  2221. (struct logio_entry_24xx *)pkt);
  2222. break;
  2223. case CT_IOCB_TYPE:
  2224. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2225. break;
  2226. case ELS_IOCB_TYPE:
  2227. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2228. break;
  2229. case ABTS_RECV_24XX:
  2230. /* ensure that the ATIO queue is empty */
  2231. qlt_24xx_process_atio_queue(vha);
  2232. case ABTS_RESP_24XX:
  2233. case CTIO_TYPE7:
  2234. case NOTIFY_ACK_TYPE:
  2235. case CTIO_CRC2:
  2236. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2237. break;
  2238. case MARKER_TYPE:
  2239. /* Do nothing in this case, this check is to prevent it
  2240. * from falling into default case
  2241. */
  2242. break;
  2243. case ABORT_IOCB_TYPE:
  2244. qla24xx_abort_iocb_entry(vha, rsp->req,
  2245. (struct abort_entry_24xx *)pkt);
  2246. break;
  2247. default:
  2248. /* Type Not Supported. */
  2249. ql_dbg(ql_dbg_async, vha, 0x5042,
  2250. "Received unknown response pkt type %x "
  2251. "entry status=%x.\n",
  2252. pkt->entry_type, pkt->entry_status);
  2253. break;
  2254. }
  2255. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2256. wmb();
  2257. }
  2258. /* Adjust ring index */
  2259. if (IS_P3P_TYPE(ha)) {
  2260. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2261. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2262. } else
  2263. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2264. }
  2265. static void
  2266. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2267. {
  2268. int rval;
  2269. uint32_t cnt;
  2270. struct qla_hw_data *ha = vha->hw;
  2271. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2272. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
  2273. !IS_QLA27XX(ha))
  2274. return;
  2275. rval = QLA_SUCCESS;
  2276. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2277. RD_REG_DWORD(&reg->iobase_addr);
  2278. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2279. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2280. rval == QLA_SUCCESS; cnt--) {
  2281. if (cnt) {
  2282. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2283. udelay(10);
  2284. } else
  2285. rval = QLA_FUNCTION_TIMEOUT;
  2286. }
  2287. if (rval == QLA_SUCCESS)
  2288. goto next_test;
  2289. rval = QLA_SUCCESS;
  2290. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2291. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2292. rval == QLA_SUCCESS; cnt--) {
  2293. if (cnt) {
  2294. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2295. udelay(10);
  2296. } else
  2297. rval = QLA_FUNCTION_TIMEOUT;
  2298. }
  2299. if (rval != QLA_SUCCESS)
  2300. goto done;
  2301. next_test:
  2302. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2303. ql_log(ql_log_info, vha, 0x504c,
  2304. "Additional code -- 0x55AA.\n");
  2305. done:
  2306. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2307. RD_REG_DWORD(&reg->iobase_window);
  2308. }
  2309. /**
  2310. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2311. * @irq:
  2312. * @dev_id: SCSI driver HA context
  2313. *
  2314. * Called by system whenever the host adapter generates an interrupt.
  2315. *
  2316. * Returns handled flag.
  2317. */
  2318. irqreturn_t
  2319. qla24xx_intr_handler(int irq, void *dev_id)
  2320. {
  2321. scsi_qla_host_t *vha;
  2322. struct qla_hw_data *ha;
  2323. struct device_reg_24xx __iomem *reg;
  2324. int status;
  2325. unsigned long iter;
  2326. uint32_t stat;
  2327. uint32_t hccr;
  2328. uint16_t mb[8];
  2329. struct rsp_que *rsp;
  2330. unsigned long flags;
  2331. rsp = (struct rsp_que *) dev_id;
  2332. if (!rsp) {
  2333. ql_log(ql_log_info, NULL, 0x5059,
  2334. "%s: NULL response queue pointer.\n", __func__);
  2335. return IRQ_NONE;
  2336. }
  2337. ha = rsp->hw;
  2338. reg = &ha->iobase->isp24;
  2339. status = 0;
  2340. if (unlikely(pci_channel_offline(ha->pdev)))
  2341. return IRQ_HANDLED;
  2342. spin_lock_irqsave(&ha->hardware_lock, flags);
  2343. vha = pci_get_drvdata(ha->pdev);
  2344. for (iter = 50; iter--; ) {
  2345. stat = RD_REG_DWORD(&reg->host_status);
  2346. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2347. break;
  2348. if (stat & HSRX_RISC_PAUSED) {
  2349. if (unlikely(pci_channel_offline(ha->pdev)))
  2350. break;
  2351. hccr = RD_REG_DWORD(&reg->hccr);
  2352. ql_log(ql_log_warn, vha, 0x504b,
  2353. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2354. hccr);
  2355. qla2xxx_check_risc_status(vha);
  2356. ha->isp_ops->fw_dump(vha, 1);
  2357. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2358. break;
  2359. } else if ((stat & HSRX_RISC_INT) == 0)
  2360. break;
  2361. switch (stat & 0xff) {
  2362. case INTR_ROM_MB_SUCCESS:
  2363. case INTR_ROM_MB_FAILED:
  2364. case INTR_MB_SUCCESS:
  2365. case INTR_MB_FAILED:
  2366. qla24xx_mbx_completion(vha, MSW(stat));
  2367. status |= MBX_INTERRUPT;
  2368. break;
  2369. case INTR_ASYNC_EVENT:
  2370. mb[0] = MSW(stat);
  2371. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2372. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2373. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2374. qla2x00_async_event(vha, rsp, mb);
  2375. break;
  2376. case INTR_RSP_QUE_UPDATE:
  2377. case INTR_RSP_QUE_UPDATE_83XX:
  2378. qla24xx_process_response_queue(vha, rsp);
  2379. break;
  2380. case INTR_ATIO_QUE_UPDATE:
  2381. qlt_24xx_process_atio_queue(vha);
  2382. break;
  2383. case INTR_ATIO_RSP_QUE_UPDATE:
  2384. qlt_24xx_process_atio_queue(vha);
  2385. qla24xx_process_response_queue(vha, rsp);
  2386. break;
  2387. default:
  2388. ql_dbg(ql_dbg_async, vha, 0x504f,
  2389. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2390. break;
  2391. }
  2392. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2393. RD_REG_DWORD_RELAXED(&reg->hccr);
  2394. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2395. ndelay(3500);
  2396. }
  2397. qla2x00_handle_mbx_completion(ha, status);
  2398. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2399. return IRQ_HANDLED;
  2400. }
  2401. static irqreturn_t
  2402. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2403. {
  2404. struct qla_hw_data *ha;
  2405. struct rsp_que *rsp;
  2406. struct device_reg_24xx __iomem *reg;
  2407. struct scsi_qla_host *vha;
  2408. unsigned long flags;
  2409. uint32_t stat = 0;
  2410. rsp = (struct rsp_que *) dev_id;
  2411. if (!rsp) {
  2412. ql_log(ql_log_info, NULL, 0x505a,
  2413. "%s: NULL response queue pointer.\n", __func__);
  2414. return IRQ_NONE;
  2415. }
  2416. ha = rsp->hw;
  2417. reg = &ha->iobase->isp24;
  2418. spin_lock_irqsave(&ha->hardware_lock, flags);
  2419. vha = pci_get_drvdata(ha->pdev);
  2420. /*
  2421. * Use host_status register to check to PCI disconnection before we
  2422. * we process the response queue.
  2423. */
  2424. stat = RD_REG_DWORD(&reg->host_status);
  2425. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2426. goto out;
  2427. qla24xx_process_response_queue(vha, rsp);
  2428. if (!ha->flags.disable_msix_handshake) {
  2429. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2430. RD_REG_DWORD_RELAXED(&reg->hccr);
  2431. }
  2432. out:
  2433. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2434. return IRQ_HANDLED;
  2435. }
  2436. static irqreturn_t
  2437. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2438. {
  2439. struct qla_hw_data *ha;
  2440. scsi_qla_host_t *vha;
  2441. struct rsp_que *rsp;
  2442. struct device_reg_24xx __iomem *reg;
  2443. unsigned long flags;
  2444. uint32_t hccr = 0;
  2445. rsp = (struct rsp_que *) dev_id;
  2446. if (!rsp) {
  2447. ql_log(ql_log_info, NULL, 0x505b,
  2448. "%s: NULL response queue pointer.\n", __func__);
  2449. return IRQ_NONE;
  2450. }
  2451. ha = rsp->hw;
  2452. vha = pci_get_drvdata(ha->pdev);
  2453. /* Clear the interrupt, if enabled, for this response queue */
  2454. if (!ha->flags.disable_msix_handshake) {
  2455. reg = &ha->iobase->isp24;
  2456. spin_lock_irqsave(&ha->hardware_lock, flags);
  2457. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2458. hccr = RD_REG_DWORD_RELAXED(&reg->hccr);
  2459. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2460. }
  2461. if (qla2x00_check_reg32_for_disconnect(vha, hccr))
  2462. goto out;
  2463. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2464. out:
  2465. return IRQ_HANDLED;
  2466. }
  2467. static irqreturn_t
  2468. qla24xx_msix_default(int irq, void *dev_id)
  2469. {
  2470. scsi_qla_host_t *vha;
  2471. struct qla_hw_data *ha;
  2472. struct rsp_que *rsp;
  2473. struct device_reg_24xx __iomem *reg;
  2474. int status;
  2475. uint32_t stat;
  2476. uint32_t hccr;
  2477. uint16_t mb[8];
  2478. unsigned long flags;
  2479. rsp = (struct rsp_que *) dev_id;
  2480. if (!rsp) {
  2481. ql_log(ql_log_info, NULL, 0x505c,
  2482. "%s: NULL response queue pointer.\n", __func__);
  2483. return IRQ_NONE;
  2484. }
  2485. ha = rsp->hw;
  2486. reg = &ha->iobase->isp24;
  2487. status = 0;
  2488. spin_lock_irqsave(&ha->hardware_lock, flags);
  2489. vha = pci_get_drvdata(ha->pdev);
  2490. do {
  2491. stat = RD_REG_DWORD(&reg->host_status);
  2492. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2493. break;
  2494. if (stat & HSRX_RISC_PAUSED) {
  2495. if (unlikely(pci_channel_offline(ha->pdev)))
  2496. break;
  2497. hccr = RD_REG_DWORD(&reg->hccr);
  2498. ql_log(ql_log_info, vha, 0x5050,
  2499. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2500. hccr);
  2501. qla2xxx_check_risc_status(vha);
  2502. ha->isp_ops->fw_dump(vha, 1);
  2503. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2504. break;
  2505. } else if ((stat & HSRX_RISC_INT) == 0)
  2506. break;
  2507. switch (stat & 0xff) {
  2508. case INTR_ROM_MB_SUCCESS:
  2509. case INTR_ROM_MB_FAILED:
  2510. case INTR_MB_SUCCESS:
  2511. case INTR_MB_FAILED:
  2512. qla24xx_mbx_completion(vha, MSW(stat));
  2513. status |= MBX_INTERRUPT;
  2514. break;
  2515. case INTR_ASYNC_EVENT:
  2516. mb[0] = MSW(stat);
  2517. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2518. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2519. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2520. qla2x00_async_event(vha, rsp, mb);
  2521. break;
  2522. case INTR_RSP_QUE_UPDATE:
  2523. case INTR_RSP_QUE_UPDATE_83XX:
  2524. qla24xx_process_response_queue(vha, rsp);
  2525. break;
  2526. case INTR_ATIO_QUE_UPDATE:
  2527. qlt_24xx_process_atio_queue(vha);
  2528. break;
  2529. case INTR_ATIO_RSP_QUE_UPDATE:
  2530. qlt_24xx_process_atio_queue(vha);
  2531. qla24xx_process_response_queue(vha, rsp);
  2532. break;
  2533. default:
  2534. ql_dbg(ql_dbg_async, vha, 0x5051,
  2535. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2536. break;
  2537. }
  2538. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2539. } while (0);
  2540. qla2x00_handle_mbx_completion(ha, status);
  2541. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2542. return IRQ_HANDLED;
  2543. }
  2544. /* Interrupt handling helpers. */
  2545. struct qla_init_msix_entry {
  2546. const char *name;
  2547. irq_handler_t handler;
  2548. };
  2549. static struct qla_init_msix_entry msix_entries[3] = {
  2550. { "qla2xxx (default)", qla24xx_msix_default },
  2551. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2552. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2553. };
  2554. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2555. { "qla2xxx (default)", qla82xx_msix_default },
  2556. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2557. };
  2558. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2559. { "qla2xxx (default)", qla24xx_msix_default },
  2560. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2561. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2562. };
  2563. static void
  2564. qla24xx_disable_msix(struct qla_hw_data *ha)
  2565. {
  2566. int i;
  2567. struct qla_msix_entry *qentry;
  2568. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2569. for (i = 0; i < ha->msix_count; i++) {
  2570. qentry = &ha->msix_entries[i];
  2571. if (qentry->have_irq)
  2572. free_irq(qentry->vector, qentry->rsp);
  2573. }
  2574. pci_disable_msix(ha->pdev);
  2575. kfree(ha->msix_entries);
  2576. ha->msix_entries = NULL;
  2577. ha->flags.msix_enabled = 0;
  2578. ql_dbg(ql_dbg_init, vha, 0x0042,
  2579. "Disabled the MSI.\n");
  2580. }
  2581. static int
  2582. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2583. {
  2584. #define MIN_MSIX_COUNT 2
  2585. #define ATIO_VECTOR 2
  2586. int i, ret;
  2587. struct msix_entry *entries;
  2588. struct qla_msix_entry *qentry;
  2589. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2590. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2591. GFP_KERNEL);
  2592. if (!entries) {
  2593. ql_log(ql_log_warn, vha, 0x00bc,
  2594. "Failed to allocate memory for msix_entry.\n");
  2595. return -ENOMEM;
  2596. }
  2597. for (i = 0; i < ha->msix_count; i++)
  2598. entries[i].entry = i;
  2599. ret = pci_enable_msix_range(ha->pdev,
  2600. entries, MIN_MSIX_COUNT, ha->msix_count);
  2601. if (ret < 0) {
  2602. ql_log(ql_log_fatal, vha, 0x00c7,
  2603. "MSI-X: Failed to enable support, "
  2604. "giving up -- %d/%d.\n",
  2605. ha->msix_count, ret);
  2606. goto msix_out;
  2607. } else if (ret < ha->msix_count) {
  2608. ql_log(ql_log_warn, vha, 0x00c6,
  2609. "MSI-X: Failed to enable support "
  2610. "-- %d/%d\n Retry with %d vectors.\n",
  2611. ha->msix_count, ret, ret);
  2612. }
  2613. ha->msix_count = ret;
  2614. ha->max_rsp_queues = ha->msix_count - 1;
  2615. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2616. ha->msix_count, GFP_KERNEL);
  2617. if (!ha->msix_entries) {
  2618. ql_log(ql_log_fatal, vha, 0x00c8,
  2619. "Failed to allocate memory for ha->msix_entries.\n");
  2620. ret = -ENOMEM;
  2621. goto msix_out;
  2622. }
  2623. ha->flags.msix_enabled = 1;
  2624. for (i = 0; i < ha->msix_count; i++) {
  2625. qentry = &ha->msix_entries[i];
  2626. qentry->vector = entries[i].vector;
  2627. qentry->entry = entries[i].entry;
  2628. qentry->have_irq = 0;
  2629. qentry->rsp = NULL;
  2630. }
  2631. /* Enable MSI-X vectors for the base queue */
  2632. for (i = 0; i < 2; i++) {
  2633. qentry = &ha->msix_entries[i];
  2634. if (IS_P3P_TYPE(ha))
  2635. ret = request_irq(qentry->vector,
  2636. qla82xx_msix_entries[i].handler,
  2637. 0, qla82xx_msix_entries[i].name, rsp);
  2638. else
  2639. ret = request_irq(qentry->vector,
  2640. msix_entries[i].handler,
  2641. 0, msix_entries[i].name, rsp);
  2642. if (ret)
  2643. goto msix_register_fail;
  2644. qentry->have_irq = 1;
  2645. qentry->rsp = rsp;
  2646. rsp->msix = qentry;
  2647. }
  2648. /*
  2649. * If target mode is enable, also request the vector for the ATIO
  2650. * queue.
  2651. */
  2652. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2653. qentry = &ha->msix_entries[ATIO_VECTOR];
  2654. ret = request_irq(qentry->vector,
  2655. qla83xx_msix_entries[ATIO_VECTOR].handler,
  2656. 0, qla83xx_msix_entries[ATIO_VECTOR].name, rsp);
  2657. qentry->have_irq = 1;
  2658. qentry->rsp = rsp;
  2659. rsp->msix = qentry;
  2660. }
  2661. msix_register_fail:
  2662. if (ret) {
  2663. ql_log(ql_log_fatal, vha, 0x00cb,
  2664. "MSI-X: unable to register handler -- %x/%d.\n",
  2665. qentry->vector, ret);
  2666. qla24xx_disable_msix(ha);
  2667. ha->mqenable = 0;
  2668. goto msix_out;
  2669. }
  2670. /* Enable MSI-X vector for response queue update for queue 0 */
  2671. if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  2672. if (ha->msixbase && ha->mqiobase &&
  2673. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2674. ha->mqenable = 1;
  2675. } else
  2676. if (ha->mqiobase
  2677. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2678. ha->mqenable = 1;
  2679. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2680. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2681. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2682. ql_dbg(ql_dbg_init, vha, 0x0055,
  2683. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2684. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2685. msix_out:
  2686. kfree(entries);
  2687. return ret;
  2688. }
  2689. int
  2690. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2691. {
  2692. int ret = QLA_FUNCTION_FAILED;
  2693. device_reg_t *reg = ha->iobase;
  2694. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2695. /* If possible, enable MSI-X. */
  2696. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2697. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha) &&
  2698. !IS_QLA27XX(ha))
  2699. goto skip_msi;
  2700. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2701. (ha->pdev->subsystem_device == 0x7040 ||
  2702. ha->pdev->subsystem_device == 0x7041 ||
  2703. ha->pdev->subsystem_device == 0x1705)) {
  2704. ql_log(ql_log_warn, vha, 0x0034,
  2705. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2706. ha->pdev->subsystem_vendor,
  2707. ha->pdev->subsystem_device);
  2708. goto skip_msi;
  2709. }
  2710. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2711. ql_log(ql_log_warn, vha, 0x0035,
  2712. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2713. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2714. goto skip_msix;
  2715. }
  2716. ret = qla24xx_enable_msix(ha, rsp);
  2717. if (!ret) {
  2718. ql_dbg(ql_dbg_init, vha, 0x0036,
  2719. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2720. ha->chip_revision, ha->fw_attributes);
  2721. goto clear_risc_ints;
  2722. }
  2723. skip_msix:
  2724. ql_log(ql_log_info, vha, 0x0037,
  2725. "Falling back-to MSI mode -%d.\n", ret);
  2726. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2727. !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha) &&
  2728. !IS_QLA27XX(ha))
  2729. goto skip_msi;
  2730. ret = pci_enable_msi(ha->pdev);
  2731. if (!ret) {
  2732. ql_dbg(ql_dbg_init, vha, 0x0038,
  2733. "MSI: Enabled.\n");
  2734. ha->flags.msi_enabled = 1;
  2735. } else
  2736. ql_log(ql_log_warn, vha, 0x0039,
  2737. "Falling back-to INTa mode -- %d.\n", ret);
  2738. skip_msi:
  2739. /* Skip INTx on ISP82xx. */
  2740. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2741. return QLA_FUNCTION_FAILED;
  2742. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2743. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2744. QLA2XXX_DRIVER_NAME, rsp);
  2745. if (ret) {
  2746. ql_log(ql_log_warn, vha, 0x003a,
  2747. "Failed to reserve interrupt %d already in use.\n",
  2748. ha->pdev->irq);
  2749. goto fail;
  2750. } else if (!ha->flags.msi_enabled) {
  2751. ql_dbg(ql_dbg_init, vha, 0x0125,
  2752. "INTa mode: Enabled.\n");
  2753. ha->flags.mr_intr_valid = 1;
  2754. }
  2755. clear_risc_ints:
  2756. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2757. goto fail;
  2758. spin_lock_irq(&ha->hardware_lock);
  2759. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2760. spin_unlock_irq(&ha->hardware_lock);
  2761. fail:
  2762. return ret;
  2763. }
  2764. void
  2765. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2766. {
  2767. struct qla_hw_data *ha = vha->hw;
  2768. struct rsp_que *rsp;
  2769. /*
  2770. * We need to check that ha->rsp_q_map is valid in case we are called
  2771. * from a probe failure context.
  2772. */
  2773. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2774. return;
  2775. rsp = ha->rsp_q_map[0];
  2776. if (ha->flags.msix_enabled)
  2777. qla24xx_disable_msix(ha);
  2778. else if (ha->flags.msi_enabled) {
  2779. free_irq(ha->pdev->irq, rsp);
  2780. pci_disable_msi(ha->pdev);
  2781. } else
  2782. free_irq(ha->pdev->irq, rsp);
  2783. }
  2784. int qla25xx_request_irq(struct rsp_que *rsp)
  2785. {
  2786. struct qla_hw_data *ha = rsp->hw;
  2787. struct qla_init_msix_entry *intr = &msix_entries[2];
  2788. struct qla_msix_entry *msix = rsp->msix;
  2789. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2790. int ret;
  2791. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2792. if (ret) {
  2793. ql_log(ql_log_fatal, vha, 0x00e6,
  2794. "MSI-X: Unable to register handler -- %x/%d.\n",
  2795. msix->vector, ret);
  2796. return ret;
  2797. }
  2798. msix->have_irq = 1;
  2799. msix->rsp = rsp;
  2800. return ret;
  2801. }