ufshcd.c 144 KB

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  1. /*
  2. * Universal Flash Storage Host controller driver Core
  3. *
  4. * This code is based on drivers/scsi/ufs/ufshcd.c
  5. * Copyright (C) 2011-2013 Samsung India Software Operations
  6. * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  7. *
  8. * Authors:
  9. * Santosh Yaraganavi <santosh.sy@samsung.com>
  10. * Vinayak Holikatti <h.vinayak@samsung.com>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License
  14. * as published by the Free Software Foundation; either version 2
  15. * of the License, or (at your option) any later version.
  16. * See the COPYING file in the top-level directory or visit
  17. * <http://www.gnu.org/licenses/gpl-2.0.html>
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * This program is provided "AS IS" and "WITH ALL FAULTS" and
  25. * without warranty of any kind. You are solely responsible for
  26. * determining the appropriateness of using and distributing
  27. * the program and assume all risks associated with your exercise
  28. * of rights with respect to the program, including but not limited
  29. * to infringement of third party rights, the risks and costs of
  30. * program errors, damage to or loss of data, programs or equipment,
  31. * and unavailability or interruption of operations. Under no
  32. * circumstances will the contributor of this Program be liable for
  33. * any damages of any kind arising from your use or distribution of
  34. * this program.
  35. *
  36. * The Linux Foundation chooses to take subject only to the GPLv2
  37. * license terms, and distributes only under these terms.
  38. */
  39. #include <linux/async.h>
  40. #include <linux/devfreq.h>
  41. #include "ufshcd.h"
  42. #include "unipro.h"
  43. #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
  44. UTP_TASK_REQ_COMPL |\
  45. UFSHCD_ERROR_MASK)
  46. /* UIC command timeout, unit: ms */
  47. #define UIC_CMD_TIMEOUT 500
  48. /* NOP OUT retries waiting for NOP IN response */
  49. #define NOP_OUT_RETRIES 10
  50. /* Timeout after 30 msecs if NOP OUT hangs without response */
  51. #define NOP_OUT_TIMEOUT 30 /* msecs */
  52. /* Query request retries */
  53. #define QUERY_REQ_RETRIES 10
  54. /* Query request timeout */
  55. #define QUERY_REQ_TIMEOUT 30 /* msec */
  56. /* Task management command timeout */
  57. #define TM_CMD_TIMEOUT 100 /* msecs */
  58. /* maximum number of link-startup retries */
  59. #define DME_LINKSTARTUP_RETRIES 3
  60. /* maximum number of reset retries before giving up */
  61. #define MAX_HOST_RESET_RETRIES 5
  62. /* Expose the flag value from utp_upiu_query.value */
  63. #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  64. /* Interrupt aggregation default timeout, unit: 40us */
  65. #define INT_AGGR_DEF_TO 0x02
  66. #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
  67. ({ \
  68. int _ret; \
  69. if (_on) \
  70. _ret = ufshcd_enable_vreg(_dev, _vreg); \
  71. else \
  72. _ret = ufshcd_disable_vreg(_dev, _vreg); \
  73. _ret; \
  74. })
  75. static u32 ufs_query_desc_max_size[] = {
  76. QUERY_DESC_DEVICE_MAX_SIZE,
  77. QUERY_DESC_CONFIGURAION_MAX_SIZE,
  78. QUERY_DESC_UNIT_MAX_SIZE,
  79. QUERY_DESC_RFU_MAX_SIZE,
  80. QUERY_DESC_INTERCONNECT_MAX_SIZE,
  81. QUERY_DESC_STRING_MAX_SIZE,
  82. QUERY_DESC_RFU_MAX_SIZE,
  83. QUERY_DESC_GEOMETRY_MAZ_SIZE,
  84. QUERY_DESC_POWER_MAX_SIZE,
  85. QUERY_DESC_RFU_MAX_SIZE,
  86. };
  87. enum {
  88. UFSHCD_MAX_CHANNEL = 0,
  89. UFSHCD_MAX_ID = 1,
  90. UFSHCD_CMD_PER_LUN = 32,
  91. UFSHCD_CAN_QUEUE = 32,
  92. };
  93. /* UFSHCD states */
  94. enum {
  95. UFSHCD_STATE_RESET,
  96. UFSHCD_STATE_ERROR,
  97. UFSHCD_STATE_OPERATIONAL,
  98. };
  99. /* UFSHCD error handling flags */
  100. enum {
  101. UFSHCD_EH_IN_PROGRESS = (1 << 0),
  102. };
  103. /* UFSHCD UIC layer error flags */
  104. enum {
  105. UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
  106. UFSHCD_UIC_NL_ERROR = (1 << 1), /* Network layer error */
  107. UFSHCD_UIC_TL_ERROR = (1 << 2), /* Transport Layer error */
  108. UFSHCD_UIC_DME_ERROR = (1 << 3), /* DME error */
  109. };
  110. /* Interrupt configuration options */
  111. enum {
  112. UFSHCD_INT_DISABLE,
  113. UFSHCD_INT_ENABLE,
  114. UFSHCD_INT_CLEAR,
  115. };
  116. #define ufshcd_set_eh_in_progress(h) \
  117. (h->eh_flags |= UFSHCD_EH_IN_PROGRESS)
  118. #define ufshcd_eh_in_progress(h) \
  119. (h->eh_flags & UFSHCD_EH_IN_PROGRESS)
  120. #define ufshcd_clear_eh_in_progress(h) \
  121. (h->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
  122. #define ufshcd_set_ufs_dev_active(h) \
  123. ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
  124. #define ufshcd_set_ufs_dev_sleep(h) \
  125. ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
  126. #define ufshcd_set_ufs_dev_poweroff(h) \
  127. ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
  128. #define ufshcd_is_ufs_dev_active(h) \
  129. ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
  130. #define ufshcd_is_ufs_dev_sleep(h) \
  131. ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
  132. #define ufshcd_is_ufs_dev_poweroff(h) \
  133. ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
  134. static struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
  135. {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  136. {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  137. {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
  138. {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  139. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
  140. {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
  141. };
  142. static inline enum ufs_dev_pwr_mode
  143. ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
  144. {
  145. return ufs_pm_lvl_states[lvl].dev_state;
  146. }
  147. static inline enum uic_link_state
  148. ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
  149. {
  150. return ufs_pm_lvl_states[lvl].link_state;
  151. }
  152. static void ufshcd_tmc_handler(struct ufs_hba *hba);
  153. static void ufshcd_async_scan(void *data, async_cookie_t cookie);
  154. static int ufshcd_reset_and_restore(struct ufs_hba *hba);
  155. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
  156. static void ufshcd_hba_exit(struct ufs_hba *hba);
  157. static int ufshcd_probe_hba(struct ufs_hba *hba);
  158. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  159. bool skip_ref_clk);
  160. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
  161. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
  162. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
  163. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
  164. static irqreturn_t ufshcd_intr(int irq, void *__hba);
  165. static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
  166. struct ufs_pa_layer_attr *desired_pwr_mode);
  167. static inline int ufshcd_enable_irq(struct ufs_hba *hba)
  168. {
  169. int ret = 0;
  170. if (!hba->is_irq_enabled) {
  171. ret = request_irq(hba->irq, ufshcd_intr, IRQF_SHARED, UFSHCD,
  172. hba);
  173. if (ret)
  174. dev_err(hba->dev, "%s: request_irq failed, ret=%d\n",
  175. __func__, ret);
  176. hba->is_irq_enabled = true;
  177. }
  178. return ret;
  179. }
  180. static inline void ufshcd_disable_irq(struct ufs_hba *hba)
  181. {
  182. if (hba->is_irq_enabled) {
  183. free_irq(hba->irq, hba);
  184. hba->is_irq_enabled = false;
  185. }
  186. }
  187. /*
  188. * ufshcd_wait_for_register - wait for register value to change
  189. * @hba - per-adapter interface
  190. * @reg - mmio register offset
  191. * @mask - mask to apply to read register value
  192. * @val - wait condition
  193. * @interval_us - polling interval in microsecs
  194. * @timeout_ms - timeout in millisecs
  195. *
  196. * Returns -ETIMEDOUT on error, zero on success
  197. */
  198. static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
  199. u32 val, unsigned long interval_us, unsigned long timeout_ms)
  200. {
  201. int err = 0;
  202. unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
  203. /* ignore bits that we don't intend to wait on */
  204. val = val & mask;
  205. while ((ufshcd_readl(hba, reg) & mask) != val) {
  206. /* wakeup within 50us of expiry */
  207. usleep_range(interval_us, interval_us + 50);
  208. if (time_after(jiffies, timeout)) {
  209. if ((ufshcd_readl(hba, reg) & mask) != val)
  210. err = -ETIMEDOUT;
  211. break;
  212. }
  213. }
  214. return err;
  215. }
  216. /**
  217. * ufshcd_get_intr_mask - Get the interrupt bit mask
  218. * @hba - Pointer to adapter instance
  219. *
  220. * Returns interrupt bit mask per version
  221. */
  222. static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
  223. {
  224. if (hba->ufs_version == UFSHCI_VERSION_10)
  225. return INTERRUPT_MASK_ALL_VER_10;
  226. else
  227. return INTERRUPT_MASK_ALL_VER_11;
  228. }
  229. /**
  230. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  231. * @hba - Pointer to adapter instance
  232. *
  233. * Returns UFSHCI version supported by the controller
  234. */
  235. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  236. {
  237. return ufshcd_readl(hba, REG_UFS_VERSION);
  238. }
  239. /**
  240. * ufshcd_is_device_present - Check if any device connected to
  241. * the host controller
  242. * @hba: pointer to adapter instance
  243. *
  244. * Returns 1 if device present, 0 if no device detected
  245. */
  246. static inline int ufshcd_is_device_present(struct ufs_hba *hba)
  247. {
  248. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
  249. DEVICE_PRESENT) ? 1 : 0;
  250. }
  251. /**
  252. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  253. * @lrb: pointer to local command reference block
  254. *
  255. * This function is used to get the OCS field from UTRD
  256. * Returns the OCS field in the UTRD
  257. */
  258. static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
  259. {
  260. return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
  261. }
  262. /**
  263. * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
  264. * @task_req_descp: pointer to utp_task_req_desc structure
  265. *
  266. * This function is used to get the OCS field from UTMRD
  267. * Returns the OCS field in the UTMRD
  268. */
  269. static inline int
  270. ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
  271. {
  272. return le32_to_cpu(task_req_descp->header.dword_2) & MASK_OCS;
  273. }
  274. /**
  275. * ufshcd_get_tm_free_slot - get a free slot for task management request
  276. * @hba: per adapter instance
  277. * @free_slot: pointer to variable with available slot value
  278. *
  279. * Get a free tag and lock it until ufshcd_put_tm_slot() is called.
  280. * Returns 0 if free slot is not available, else return 1 with tag value
  281. * in @free_slot.
  282. */
  283. static bool ufshcd_get_tm_free_slot(struct ufs_hba *hba, int *free_slot)
  284. {
  285. int tag;
  286. bool ret = false;
  287. if (!free_slot)
  288. goto out;
  289. do {
  290. tag = find_first_zero_bit(&hba->tm_slots_in_use, hba->nutmrs);
  291. if (tag >= hba->nutmrs)
  292. goto out;
  293. } while (test_and_set_bit_lock(tag, &hba->tm_slots_in_use));
  294. *free_slot = tag;
  295. ret = true;
  296. out:
  297. return ret;
  298. }
  299. static inline void ufshcd_put_tm_slot(struct ufs_hba *hba, int slot)
  300. {
  301. clear_bit_unlock(slot, &hba->tm_slots_in_use);
  302. }
  303. /**
  304. * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
  305. * @hba: per adapter instance
  306. * @pos: position of the bit to be cleared
  307. */
  308. static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
  309. {
  310. ufshcd_writel(hba, ~(1 << pos), REG_UTP_TRANSFER_REQ_LIST_CLEAR);
  311. }
  312. /**
  313. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  314. * @reg: Register value of host controller status
  315. *
  316. * Returns integer, 0 on Success and positive value if failed
  317. */
  318. static inline int ufshcd_get_lists_status(u32 reg)
  319. {
  320. /*
  321. * The mask 0xFF is for the following HCS register bits
  322. * Bit Description
  323. * 0 Device Present
  324. * 1 UTRLRDY
  325. * 2 UTMRLRDY
  326. * 3 UCRDY
  327. * 4 HEI
  328. * 5 DEI
  329. * 6-7 reserved
  330. */
  331. return (((reg) & (0xFF)) >> 1) ^ (0x07);
  332. }
  333. /**
  334. * ufshcd_get_uic_cmd_result - Get the UIC command result
  335. * @hba: Pointer to adapter instance
  336. *
  337. * This function gets the result of UIC command completion
  338. * Returns 0 on success, non zero value on error
  339. */
  340. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  341. {
  342. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
  343. MASK_UIC_COMMAND_RESULT;
  344. }
  345. /**
  346. * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
  347. * @hba: Pointer to adapter instance
  348. *
  349. * This function gets UIC command argument3
  350. * Returns 0 on success, non zero value on error
  351. */
  352. static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
  353. {
  354. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
  355. }
  356. /**
  357. * ufshcd_get_req_rsp - returns the TR response transaction type
  358. * @ucd_rsp_ptr: pointer to response UPIU
  359. */
  360. static inline int
  361. ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  362. {
  363. return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
  364. }
  365. /**
  366. * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
  367. * @ucd_rsp_ptr: pointer to response UPIU
  368. *
  369. * This function gets the response status and scsi_status from response UPIU
  370. * Returns the response result code.
  371. */
  372. static inline int
  373. ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  374. {
  375. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  376. }
  377. /*
  378. * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
  379. * from response UPIU
  380. * @ucd_rsp_ptr: pointer to response UPIU
  381. *
  382. * Return the data segment length.
  383. */
  384. static inline unsigned int
  385. ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
  386. {
  387. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  388. MASK_RSP_UPIU_DATA_SEG_LEN;
  389. }
  390. /**
  391. * ufshcd_is_exception_event - Check if the device raised an exception event
  392. * @ucd_rsp_ptr: pointer to response UPIU
  393. *
  394. * The function checks if the device raised an exception event indicated in
  395. * the Device Information field of response UPIU.
  396. *
  397. * Returns true if exception is raised, false otherwise.
  398. */
  399. static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
  400. {
  401. return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
  402. MASK_RSP_EXCEPTION_EVENT ? true : false;
  403. }
  404. /**
  405. * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
  406. * @hba: per adapter instance
  407. */
  408. static inline void
  409. ufshcd_reset_intr_aggr(struct ufs_hba *hba)
  410. {
  411. ufshcd_writel(hba, INT_AGGR_ENABLE |
  412. INT_AGGR_COUNTER_AND_TIMER_RESET,
  413. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  414. }
  415. /**
  416. * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
  417. * @hba: per adapter instance
  418. * @cnt: Interrupt aggregation counter threshold
  419. * @tmout: Interrupt aggregation timeout value
  420. */
  421. static inline void
  422. ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
  423. {
  424. ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
  425. INT_AGGR_COUNTER_THLD_VAL(cnt) |
  426. INT_AGGR_TIMEOUT_VAL(tmout),
  427. REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  428. }
  429. /**
  430. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  431. * When run-stop registers are set to 1, it indicates the
  432. * host controller that it can process the requests
  433. * @hba: per adapter instance
  434. */
  435. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  436. {
  437. ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  438. REG_UTP_TASK_REQ_LIST_RUN_STOP);
  439. ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  440. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
  441. }
  442. /**
  443. * ufshcd_hba_start - Start controller initialization sequence
  444. * @hba: per adapter instance
  445. */
  446. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  447. {
  448. ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
  449. }
  450. /**
  451. * ufshcd_is_hba_active - Get controller state
  452. * @hba: per adapter instance
  453. *
  454. * Returns zero if controller is active, 1 otherwise
  455. */
  456. static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
  457. {
  458. return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
  459. }
  460. static void ufshcd_ungate_work(struct work_struct *work)
  461. {
  462. int ret;
  463. unsigned long flags;
  464. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  465. clk_gating.ungate_work);
  466. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  467. spin_lock_irqsave(hba->host->host_lock, flags);
  468. if (hba->clk_gating.state == CLKS_ON) {
  469. spin_unlock_irqrestore(hba->host->host_lock, flags);
  470. goto unblock_reqs;
  471. }
  472. spin_unlock_irqrestore(hba->host->host_lock, flags);
  473. ufshcd_setup_clocks(hba, true);
  474. /* Exit from hibern8 */
  475. if (ufshcd_can_hibern8_during_gating(hba)) {
  476. /* Prevent gating in this path */
  477. hba->clk_gating.is_suspended = true;
  478. if (ufshcd_is_link_hibern8(hba)) {
  479. ret = ufshcd_uic_hibern8_exit(hba);
  480. if (ret)
  481. dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
  482. __func__, ret);
  483. else
  484. ufshcd_set_link_active(hba);
  485. }
  486. hba->clk_gating.is_suspended = false;
  487. }
  488. unblock_reqs:
  489. if (ufshcd_is_clkscaling_enabled(hba))
  490. devfreq_resume_device(hba->devfreq);
  491. scsi_unblock_requests(hba->host);
  492. }
  493. /**
  494. * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
  495. * Also, exit from hibern8 mode and set the link as active.
  496. * @hba: per adapter instance
  497. * @async: This indicates whether caller should ungate clocks asynchronously.
  498. */
  499. int ufshcd_hold(struct ufs_hba *hba, bool async)
  500. {
  501. int rc = 0;
  502. unsigned long flags;
  503. if (!ufshcd_is_clkgating_allowed(hba))
  504. goto out;
  505. spin_lock_irqsave(hba->host->host_lock, flags);
  506. hba->clk_gating.active_reqs++;
  507. start:
  508. switch (hba->clk_gating.state) {
  509. case CLKS_ON:
  510. break;
  511. case REQ_CLKS_OFF:
  512. if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
  513. hba->clk_gating.state = CLKS_ON;
  514. break;
  515. }
  516. /*
  517. * If we here, it means gating work is either done or
  518. * currently running. Hence, fall through to cancel gating
  519. * work and to enable clocks.
  520. */
  521. case CLKS_OFF:
  522. scsi_block_requests(hba->host);
  523. hba->clk_gating.state = REQ_CLKS_ON;
  524. schedule_work(&hba->clk_gating.ungate_work);
  525. /*
  526. * fall through to check if we should wait for this
  527. * work to be done or not.
  528. */
  529. case REQ_CLKS_ON:
  530. if (async) {
  531. rc = -EAGAIN;
  532. hba->clk_gating.active_reqs--;
  533. break;
  534. }
  535. spin_unlock_irqrestore(hba->host->host_lock, flags);
  536. flush_work(&hba->clk_gating.ungate_work);
  537. /* Make sure state is CLKS_ON before returning */
  538. spin_lock_irqsave(hba->host->host_lock, flags);
  539. goto start;
  540. default:
  541. dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
  542. __func__, hba->clk_gating.state);
  543. break;
  544. }
  545. spin_unlock_irqrestore(hba->host->host_lock, flags);
  546. out:
  547. return rc;
  548. }
  549. static void ufshcd_gate_work(struct work_struct *work)
  550. {
  551. struct ufs_hba *hba = container_of(work, struct ufs_hba,
  552. clk_gating.gate_work.work);
  553. unsigned long flags;
  554. spin_lock_irqsave(hba->host->host_lock, flags);
  555. if (hba->clk_gating.is_suspended) {
  556. hba->clk_gating.state = CLKS_ON;
  557. goto rel_lock;
  558. }
  559. if (hba->clk_gating.active_reqs
  560. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  561. || hba->lrb_in_use || hba->outstanding_tasks
  562. || hba->active_uic_cmd || hba->uic_async_done)
  563. goto rel_lock;
  564. spin_unlock_irqrestore(hba->host->host_lock, flags);
  565. /* put the link into hibern8 mode before turning off clocks */
  566. if (ufshcd_can_hibern8_during_gating(hba)) {
  567. if (ufshcd_uic_hibern8_enter(hba)) {
  568. hba->clk_gating.state = CLKS_ON;
  569. goto out;
  570. }
  571. ufshcd_set_link_hibern8(hba);
  572. }
  573. if (ufshcd_is_clkscaling_enabled(hba)) {
  574. devfreq_suspend_device(hba->devfreq);
  575. hba->clk_scaling.window_start_t = 0;
  576. }
  577. if (!ufshcd_is_link_active(hba))
  578. ufshcd_setup_clocks(hba, false);
  579. else
  580. /* If link is active, device ref_clk can't be switched off */
  581. __ufshcd_setup_clocks(hba, false, true);
  582. /*
  583. * In case you are here to cancel this work the gating state
  584. * would be marked as REQ_CLKS_ON. In this case keep the state
  585. * as REQ_CLKS_ON which would anyway imply that clocks are off
  586. * and a request to turn them on is pending. By doing this way,
  587. * we keep the state machine in tact and this would ultimately
  588. * prevent from doing cancel work multiple times when there are
  589. * new requests arriving before the current cancel work is done.
  590. */
  591. spin_lock_irqsave(hba->host->host_lock, flags);
  592. if (hba->clk_gating.state == REQ_CLKS_OFF)
  593. hba->clk_gating.state = CLKS_OFF;
  594. rel_lock:
  595. spin_unlock_irqrestore(hba->host->host_lock, flags);
  596. out:
  597. return;
  598. }
  599. /* host lock must be held before calling this variant */
  600. static void __ufshcd_release(struct ufs_hba *hba)
  601. {
  602. if (!ufshcd_is_clkgating_allowed(hba))
  603. return;
  604. hba->clk_gating.active_reqs--;
  605. if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended
  606. || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
  607. || hba->lrb_in_use || hba->outstanding_tasks
  608. || hba->active_uic_cmd || hba->uic_async_done)
  609. return;
  610. hba->clk_gating.state = REQ_CLKS_OFF;
  611. schedule_delayed_work(&hba->clk_gating.gate_work,
  612. msecs_to_jiffies(hba->clk_gating.delay_ms));
  613. }
  614. void ufshcd_release(struct ufs_hba *hba)
  615. {
  616. unsigned long flags;
  617. spin_lock_irqsave(hba->host->host_lock, flags);
  618. __ufshcd_release(hba);
  619. spin_unlock_irqrestore(hba->host->host_lock, flags);
  620. }
  621. static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
  622. struct device_attribute *attr, char *buf)
  623. {
  624. struct ufs_hba *hba = dev_get_drvdata(dev);
  625. return snprintf(buf, PAGE_SIZE, "%lu\n", hba->clk_gating.delay_ms);
  626. }
  627. static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
  628. struct device_attribute *attr, const char *buf, size_t count)
  629. {
  630. struct ufs_hba *hba = dev_get_drvdata(dev);
  631. unsigned long flags, value;
  632. if (kstrtoul(buf, 0, &value))
  633. return -EINVAL;
  634. spin_lock_irqsave(hba->host->host_lock, flags);
  635. hba->clk_gating.delay_ms = value;
  636. spin_unlock_irqrestore(hba->host->host_lock, flags);
  637. return count;
  638. }
  639. static void ufshcd_init_clk_gating(struct ufs_hba *hba)
  640. {
  641. if (!ufshcd_is_clkgating_allowed(hba))
  642. return;
  643. hba->clk_gating.delay_ms = 150;
  644. INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
  645. INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
  646. hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
  647. hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
  648. sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
  649. hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
  650. hba->clk_gating.delay_attr.attr.mode = S_IRUGO | S_IWUSR;
  651. if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
  652. dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
  653. }
  654. static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
  655. {
  656. if (!ufshcd_is_clkgating_allowed(hba))
  657. return;
  658. device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
  659. cancel_work_sync(&hba->clk_gating.ungate_work);
  660. cancel_delayed_work_sync(&hba->clk_gating.gate_work);
  661. }
  662. /* Must be called with host lock acquired */
  663. static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
  664. {
  665. if (!ufshcd_is_clkscaling_enabled(hba))
  666. return;
  667. if (!hba->clk_scaling.is_busy_started) {
  668. hba->clk_scaling.busy_start_t = ktime_get();
  669. hba->clk_scaling.is_busy_started = true;
  670. }
  671. }
  672. static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
  673. {
  674. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  675. if (!ufshcd_is_clkscaling_enabled(hba))
  676. return;
  677. if (!hba->outstanding_reqs && scaling->is_busy_started) {
  678. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  679. scaling->busy_start_t));
  680. scaling->busy_start_t = ktime_set(0, 0);
  681. scaling->is_busy_started = false;
  682. }
  683. }
  684. /**
  685. * ufshcd_send_command - Send SCSI or device management commands
  686. * @hba: per adapter instance
  687. * @task_tag: Task tag of the command
  688. */
  689. static inline
  690. void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  691. {
  692. ufshcd_clk_scaling_start_busy(hba);
  693. __set_bit(task_tag, &hba->outstanding_reqs);
  694. ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  695. }
  696. /**
  697. * ufshcd_copy_sense_data - Copy sense data in case of check condition
  698. * @lrb - pointer to local reference block
  699. */
  700. static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
  701. {
  702. int len;
  703. if (lrbp->sense_buffer &&
  704. ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
  705. len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
  706. memcpy(lrbp->sense_buffer,
  707. lrbp->ucd_rsp_ptr->sr.sense_data,
  708. min_t(int, len, SCSI_SENSE_BUFFERSIZE));
  709. }
  710. }
  711. /**
  712. * ufshcd_copy_query_response() - Copy the Query Response and the data
  713. * descriptor
  714. * @hba: per adapter instance
  715. * @lrb - pointer to local reference block
  716. */
  717. static
  718. int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  719. {
  720. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  721. memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
  722. /* Get the descriptor */
  723. if (lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
  724. u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
  725. GENERAL_UPIU_REQUEST_SIZE;
  726. u16 resp_len;
  727. u16 buf_len;
  728. /* data segment length */
  729. resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
  730. MASK_QUERY_DATA_SEG_LEN;
  731. buf_len = be16_to_cpu(
  732. hba->dev_cmd.query.request.upiu_req.length);
  733. if (likely(buf_len >= resp_len)) {
  734. memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
  735. } else {
  736. dev_warn(hba->dev,
  737. "%s: Response size is bigger than buffer",
  738. __func__);
  739. return -EINVAL;
  740. }
  741. }
  742. return 0;
  743. }
  744. /**
  745. * ufshcd_hba_capabilities - Read controller capabilities
  746. * @hba: per adapter instance
  747. */
  748. static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
  749. {
  750. hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
  751. /* nutrs and nutmrs are 0 based values */
  752. hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
  753. hba->nutmrs =
  754. ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
  755. }
  756. /**
  757. * ufshcd_ready_for_uic_cmd - Check if controller is ready
  758. * to accept UIC commands
  759. * @hba: per adapter instance
  760. * Return true on success, else false
  761. */
  762. static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
  763. {
  764. if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
  765. return true;
  766. else
  767. return false;
  768. }
  769. /**
  770. * ufshcd_get_upmcrs - Get the power mode change request status
  771. * @hba: Pointer to adapter instance
  772. *
  773. * This function gets the UPMCRS field of HCS register
  774. * Returns value of UPMCRS field
  775. */
  776. static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
  777. {
  778. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
  779. }
  780. /**
  781. * ufshcd_dispatch_uic_cmd - Dispatch UIC commands to unipro layers
  782. * @hba: per adapter instance
  783. * @uic_cmd: UIC command
  784. *
  785. * Mutex must be held.
  786. */
  787. static inline void
  788. ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  789. {
  790. WARN_ON(hba->active_uic_cmd);
  791. hba->active_uic_cmd = uic_cmd;
  792. /* Write Args */
  793. ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
  794. ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
  795. ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
  796. /* Write UIC Cmd */
  797. ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
  798. REG_UIC_COMMAND);
  799. }
  800. /**
  801. * ufshcd_wait_for_uic_cmd - Wait complectioin of UIC command
  802. * @hba: per adapter instance
  803. * @uic_command: UIC command
  804. *
  805. * Must be called with mutex held.
  806. * Returns 0 only if success.
  807. */
  808. static int
  809. ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  810. {
  811. int ret;
  812. unsigned long flags;
  813. if (wait_for_completion_timeout(&uic_cmd->done,
  814. msecs_to_jiffies(UIC_CMD_TIMEOUT)))
  815. ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
  816. else
  817. ret = -ETIMEDOUT;
  818. spin_lock_irqsave(hba->host->host_lock, flags);
  819. hba->active_uic_cmd = NULL;
  820. spin_unlock_irqrestore(hba->host->host_lock, flags);
  821. return ret;
  822. }
  823. /**
  824. * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  825. * @hba: per adapter instance
  826. * @uic_cmd: UIC command
  827. *
  828. * Identical to ufshcd_send_uic_cmd() expect mutex. Must be called
  829. * with mutex held and host_lock locked.
  830. * Returns 0 only if success.
  831. */
  832. static int
  833. __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  834. {
  835. if (!ufshcd_ready_for_uic_cmd(hba)) {
  836. dev_err(hba->dev,
  837. "Controller not ready to accept UIC commands\n");
  838. return -EIO;
  839. }
  840. init_completion(&uic_cmd->done);
  841. ufshcd_dispatch_uic_cmd(hba, uic_cmd);
  842. return 0;
  843. }
  844. /**
  845. * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
  846. * @hba: per adapter instance
  847. * @uic_cmd: UIC command
  848. *
  849. * Returns 0 only if success.
  850. */
  851. static int
  852. ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  853. {
  854. int ret;
  855. unsigned long flags;
  856. ufshcd_hold(hba, false);
  857. mutex_lock(&hba->uic_cmd_mutex);
  858. spin_lock_irqsave(hba->host->host_lock, flags);
  859. ret = __ufshcd_send_uic_cmd(hba, uic_cmd);
  860. spin_unlock_irqrestore(hba->host->host_lock, flags);
  861. if (!ret)
  862. ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
  863. mutex_unlock(&hba->uic_cmd_mutex);
  864. ufshcd_release(hba);
  865. return ret;
  866. }
  867. /**
  868. * ufshcd_map_sg - Map scatter-gather list to prdt
  869. * @lrbp - pointer to local reference block
  870. *
  871. * Returns 0 in case of success, non-zero value in case of failure
  872. */
  873. static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
  874. {
  875. struct ufshcd_sg_entry *prd_table;
  876. struct scatterlist *sg;
  877. struct scsi_cmnd *cmd;
  878. int sg_segments;
  879. int i;
  880. cmd = lrbp->cmd;
  881. sg_segments = scsi_dma_map(cmd);
  882. if (sg_segments < 0)
  883. return sg_segments;
  884. if (sg_segments) {
  885. lrbp->utr_descriptor_ptr->prd_table_length =
  886. cpu_to_le16((u16) (sg_segments));
  887. prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
  888. scsi_for_each_sg(cmd, sg, sg_segments, i) {
  889. prd_table[i].size =
  890. cpu_to_le32(((u32) sg_dma_len(sg))-1);
  891. prd_table[i].base_addr =
  892. cpu_to_le32(lower_32_bits(sg->dma_address));
  893. prd_table[i].upper_addr =
  894. cpu_to_le32(upper_32_bits(sg->dma_address));
  895. }
  896. } else {
  897. lrbp->utr_descriptor_ptr->prd_table_length = 0;
  898. }
  899. return 0;
  900. }
  901. /**
  902. * ufshcd_enable_intr - enable interrupts
  903. * @hba: per adapter instance
  904. * @intrs: interrupt bits
  905. */
  906. static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
  907. {
  908. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  909. if (hba->ufs_version == UFSHCI_VERSION_10) {
  910. u32 rw;
  911. rw = set & INTERRUPT_MASK_RW_VER_10;
  912. set = rw | ((set ^ intrs) & intrs);
  913. } else {
  914. set |= intrs;
  915. }
  916. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  917. }
  918. /**
  919. * ufshcd_disable_intr - disable interrupts
  920. * @hba: per adapter instance
  921. * @intrs: interrupt bits
  922. */
  923. static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
  924. {
  925. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  926. if (hba->ufs_version == UFSHCI_VERSION_10) {
  927. u32 rw;
  928. rw = (set & INTERRUPT_MASK_RW_VER_10) &
  929. ~(intrs & INTERRUPT_MASK_RW_VER_10);
  930. set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
  931. } else {
  932. set &= ~intrs;
  933. }
  934. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  935. }
  936. /**
  937. * ufshcd_prepare_req_desc_hdr() - Fills the requests header
  938. * descriptor according to request
  939. * @lrbp: pointer to local reference block
  940. * @upiu_flags: flags required in the header
  941. * @cmd_dir: requests data direction
  942. */
  943. static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
  944. u32 *upiu_flags, enum dma_data_direction cmd_dir)
  945. {
  946. struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
  947. u32 data_direction;
  948. u32 dword_0;
  949. if (cmd_dir == DMA_FROM_DEVICE) {
  950. data_direction = UTP_DEVICE_TO_HOST;
  951. *upiu_flags = UPIU_CMD_FLAGS_READ;
  952. } else if (cmd_dir == DMA_TO_DEVICE) {
  953. data_direction = UTP_HOST_TO_DEVICE;
  954. *upiu_flags = UPIU_CMD_FLAGS_WRITE;
  955. } else {
  956. data_direction = UTP_NO_DATA_TRANSFER;
  957. *upiu_flags = UPIU_CMD_FLAGS_NONE;
  958. }
  959. dword_0 = data_direction | (lrbp->command_type
  960. << UPIU_COMMAND_TYPE_OFFSET);
  961. if (lrbp->intr_cmd)
  962. dword_0 |= UTP_REQ_DESC_INT_CMD;
  963. /* Transfer request descriptor header fields */
  964. req_desc->header.dword_0 = cpu_to_le32(dword_0);
  965. /*
  966. * assigning invalid value for command status. Controller
  967. * updates OCS on command completion, with the command
  968. * status
  969. */
  970. req_desc->header.dword_2 =
  971. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  972. }
  973. /**
  974. * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
  975. * for scsi commands
  976. * @lrbp - local reference block pointer
  977. * @upiu_flags - flags
  978. */
  979. static
  980. void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u32 upiu_flags)
  981. {
  982. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  983. /* command descriptor fields */
  984. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  985. UPIU_TRANSACTION_COMMAND, upiu_flags,
  986. lrbp->lun, lrbp->task_tag);
  987. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  988. UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
  989. /* Total EHS length and Data segment length will be zero */
  990. ucd_req_ptr->header.dword_2 = 0;
  991. ucd_req_ptr->sc.exp_data_transfer_len =
  992. cpu_to_be32(lrbp->cmd->sdb.length);
  993. memcpy(ucd_req_ptr->sc.cdb, lrbp->cmd->cmnd,
  994. (min_t(unsigned short, lrbp->cmd->cmd_len, MAX_CDB_SIZE)));
  995. }
  996. /**
  997. * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
  998. * for query requsts
  999. * @hba: UFS hba
  1000. * @lrbp: local reference block pointer
  1001. * @upiu_flags: flags
  1002. */
  1003. static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
  1004. struct ufshcd_lrb *lrbp, u32 upiu_flags)
  1005. {
  1006. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1007. struct ufs_query *query = &hba->dev_cmd.query;
  1008. u16 len = be16_to_cpu(query->request.upiu_req.length);
  1009. u8 *descp = (u8 *)lrbp->ucd_req_ptr + GENERAL_UPIU_REQUEST_SIZE;
  1010. /* Query request header */
  1011. ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
  1012. UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
  1013. lrbp->lun, lrbp->task_tag);
  1014. ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
  1015. 0, query->request.query_func, 0, 0);
  1016. /* Data segment length */
  1017. ucd_req_ptr->header.dword_2 = UPIU_HEADER_DWORD(
  1018. 0, 0, len >> 8, (u8)len);
  1019. /* Copy the Query Request buffer as is */
  1020. memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
  1021. QUERY_OSF_SIZE);
  1022. /* Copy the Descriptor */
  1023. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  1024. memcpy(descp, query->descriptor, len);
  1025. }
  1026. static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
  1027. {
  1028. struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
  1029. memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
  1030. /* command descriptor fields */
  1031. ucd_req_ptr->header.dword_0 =
  1032. UPIU_HEADER_DWORD(
  1033. UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
  1034. }
  1035. /**
  1036. * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
  1037. * @hba - per adapter instance
  1038. * @lrb - pointer to local reference block
  1039. */
  1040. static int ufshcd_compose_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1041. {
  1042. u32 upiu_flags;
  1043. int ret = 0;
  1044. switch (lrbp->command_type) {
  1045. case UTP_CMD_TYPE_SCSI:
  1046. if (likely(lrbp->cmd)) {
  1047. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
  1048. lrbp->cmd->sc_data_direction);
  1049. ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
  1050. } else {
  1051. ret = -EINVAL;
  1052. }
  1053. break;
  1054. case UTP_CMD_TYPE_DEV_MANAGE:
  1055. ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
  1056. if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
  1057. ufshcd_prepare_utp_query_req_upiu(
  1058. hba, lrbp, upiu_flags);
  1059. else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
  1060. ufshcd_prepare_utp_nop_upiu(lrbp);
  1061. else
  1062. ret = -EINVAL;
  1063. break;
  1064. case UTP_CMD_TYPE_UFS:
  1065. /* For UFS native command implementation */
  1066. ret = -ENOTSUPP;
  1067. dev_err(hba->dev, "%s: UFS native command are not supported\n",
  1068. __func__);
  1069. break;
  1070. default:
  1071. ret = -ENOTSUPP;
  1072. dev_err(hba->dev, "%s: unknown command type: 0x%x\n",
  1073. __func__, lrbp->command_type);
  1074. break;
  1075. } /* end of switch */
  1076. return ret;
  1077. }
  1078. /*
  1079. * ufshcd_scsi_to_upiu_lun - maps scsi LUN to UPIU LUN
  1080. * @scsi_lun: scsi LUN id
  1081. *
  1082. * Returns UPIU LUN id
  1083. */
  1084. static inline u8 ufshcd_scsi_to_upiu_lun(unsigned int scsi_lun)
  1085. {
  1086. if (scsi_is_wlun(scsi_lun))
  1087. return (scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID)
  1088. | UFS_UPIU_WLUN_ID;
  1089. else
  1090. return scsi_lun & UFS_UPIU_MAX_UNIT_NUM_ID;
  1091. }
  1092. /**
  1093. * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
  1094. * @scsi_lun: UPIU W-LUN id
  1095. *
  1096. * Returns SCSI W-LUN id
  1097. */
  1098. static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
  1099. {
  1100. return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
  1101. }
  1102. /**
  1103. * ufshcd_queuecommand - main entry point for SCSI requests
  1104. * @cmd: command from SCSI Midlayer
  1105. * @done: call back function
  1106. *
  1107. * Returns 0 for success, non-zero in case of failure
  1108. */
  1109. static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
  1110. {
  1111. struct ufshcd_lrb *lrbp;
  1112. struct ufs_hba *hba;
  1113. unsigned long flags;
  1114. int tag;
  1115. int err = 0;
  1116. hba = shost_priv(host);
  1117. tag = cmd->request->tag;
  1118. spin_lock_irqsave(hba->host->host_lock, flags);
  1119. switch (hba->ufshcd_state) {
  1120. case UFSHCD_STATE_OPERATIONAL:
  1121. break;
  1122. case UFSHCD_STATE_RESET:
  1123. err = SCSI_MLQUEUE_HOST_BUSY;
  1124. goto out_unlock;
  1125. case UFSHCD_STATE_ERROR:
  1126. set_host_byte(cmd, DID_ERROR);
  1127. cmd->scsi_done(cmd);
  1128. goto out_unlock;
  1129. default:
  1130. dev_WARN_ONCE(hba->dev, 1, "%s: invalid state %d\n",
  1131. __func__, hba->ufshcd_state);
  1132. set_host_byte(cmd, DID_BAD_TARGET);
  1133. cmd->scsi_done(cmd);
  1134. goto out_unlock;
  1135. }
  1136. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1137. /* acquire the tag to make sure device cmds don't use it */
  1138. if (test_and_set_bit_lock(tag, &hba->lrb_in_use)) {
  1139. /*
  1140. * Dev manage command in progress, requeue the command.
  1141. * Requeuing the command helps in cases where the request *may*
  1142. * find different tag instead of waiting for dev manage command
  1143. * completion.
  1144. */
  1145. err = SCSI_MLQUEUE_HOST_BUSY;
  1146. goto out;
  1147. }
  1148. err = ufshcd_hold(hba, true);
  1149. if (err) {
  1150. err = SCSI_MLQUEUE_HOST_BUSY;
  1151. clear_bit_unlock(tag, &hba->lrb_in_use);
  1152. goto out;
  1153. }
  1154. WARN_ON(hba->clk_gating.state != CLKS_ON);
  1155. lrbp = &hba->lrb[tag];
  1156. WARN_ON(lrbp->cmd);
  1157. lrbp->cmd = cmd;
  1158. lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
  1159. lrbp->sense_buffer = cmd->sense_buffer;
  1160. lrbp->task_tag = tag;
  1161. lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
  1162. lrbp->intr_cmd = false;
  1163. lrbp->command_type = UTP_CMD_TYPE_SCSI;
  1164. /* form UPIU before issuing the command */
  1165. ufshcd_compose_upiu(hba, lrbp);
  1166. err = ufshcd_map_sg(lrbp);
  1167. if (err) {
  1168. lrbp->cmd = NULL;
  1169. clear_bit_unlock(tag, &hba->lrb_in_use);
  1170. goto out;
  1171. }
  1172. /* issue command to the controller */
  1173. spin_lock_irqsave(hba->host->host_lock, flags);
  1174. ufshcd_send_command(hba, tag);
  1175. out_unlock:
  1176. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1177. out:
  1178. return err;
  1179. }
  1180. static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
  1181. struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
  1182. {
  1183. lrbp->cmd = NULL;
  1184. lrbp->sense_bufflen = 0;
  1185. lrbp->sense_buffer = NULL;
  1186. lrbp->task_tag = tag;
  1187. lrbp->lun = 0; /* device management cmd is not specific to any LUN */
  1188. lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
  1189. lrbp->intr_cmd = true; /* No interrupt aggregation */
  1190. hba->dev_cmd.type = cmd_type;
  1191. return ufshcd_compose_upiu(hba, lrbp);
  1192. }
  1193. static int
  1194. ufshcd_clear_cmd(struct ufs_hba *hba, int tag)
  1195. {
  1196. int err = 0;
  1197. unsigned long flags;
  1198. u32 mask = 1 << tag;
  1199. /* clear outstanding transaction before retry */
  1200. spin_lock_irqsave(hba->host->host_lock, flags);
  1201. ufshcd_utrl_clear(hba, tag);
  1202. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1203. /*
  1204. * wait for for h/w to clear corresponding bit in door-bell.
  1205. * max. wait is 1 sec.
  1206. */
  1207. err = ufshcd_wait_for_register(hba,
  1208. REG_UTP_TRANSFER_REQ_DOOR_BELL,
  1209. mask, ~mask, 1000, 1000);
  1210. return err;
  1211. }
  1212. static int
  1213. ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1214. {
  1215. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  1216. /* Get the UPIU response */
  1217. query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
  1218. UPIU_RSP_CODE_OFFSET;
  1219. return query_res->response;
  1220. }
  1221. /**
  1222. * ufshcd_dev_cmd_completion() - handles device management command responses
  1223. * @hba: per adapter instance
  1224. * @lrbp: pointer to local reference block
  1225. */
  1226. static int
  1227. ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  1228. {
  1229. int resp;
  1230. int err = 0;
  1231. resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  1232. switch (resp) {
  1233. case UPIU_TRANSACTION_NOP_IN:
  1234. if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
  1235. err = -EINVAL;
  1236. dev_err(hba->dev, "%s: unexpected response %x\n",
  1237. __func__, resp);
  1238. }
  1239. break;
  1240. case UPIU_TRANSACTION_QUERY_RSP:
  1241. err = ufshcd_check_query_response(hba, lrbp);
  1242. if (!err)
  1243. err = ufshcd_copy_query_response(hba, lrbp);
  1244. break;
  1245. case UPIU_TRANSACTION_REJECT_UPIU:
  1246. /* TODO: handle Reject UPIU Response */
  1247. err = -EPERM;
  1248. dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
  1249. __func__);
  1250. break;
  1251. default:
  1252. err = -EINVAL;
  1253. dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
  1254. __func__, resp);
  1255. break;
  1256. }
  1257. return err;
  1258. }
  1259. static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
  1260. struct ufshcd_lrb *lrbp, int max_timeout)
  1261. {
  1262. int err = 0;
  1263. unsigned long time_left;
  1264. unsigned long flags;
  1265. time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
  1266. msecs_to_jiffies(max_timeout));
  1267. spin_lock_irqsave(hba->host->host_lock, flags);
  1268. hba->dev_cmd.complete = NULL;
  1269. if (likely(time_left)) {
  1270. err = ufshcd_get_tr_ocs(lrbp);
  1271. if (!err)
  1272. err = ufshcd_dev_cmd_completion(hba, lrbp);
  1273. }
  1274. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1275. if (!time_left) {
  1276. err = -ETIMEDOUT;
  1277. if (!ufshcd_clear_cmd(hba, lrbp->task_tag))
  1278. /* sucessfully cleared the command, retry if needed */
  1279. err = -EAGAIN;
  1280. }
  1281. return err;
  1282. }
  1283. /**
  1284. * ufshcd_get_dev_cmd_tag - Get device management command tag
  1285. * @hba: per-adapter instance
  1286. * @tag: pointer to variable with available slot value
  1287. *
  1288. * Get a free slot and lock it until device management command
  1289. * completes.
  1290. *
  1291. * Returns false if free slot is unavailable for locking, else
  1292. * return true with tag value in @tag.
  1293. */
  1294. static bool ufshcd_get_dev_cmd_tag(struct ufs_hba *hba, int *tag_out)
  1295. {
  1296. int tag;
  1297. bool ret = false;
  1298. unsigned long tmp;
  1299. if (!tag_out)
  1300. goto out;
  1301. do {
  1302. tmp = ~hba->lrb_in_use;
  1303. tag = find_last_bit(&tmp, hba->nutrs);
  1304. if (tag >= hba->nutrs)
  1305. goto out;
  1306. } while (test_and_set_bit_lock(tag, &hba->lrb_in_use));
  1307. *tag_out = tag;
  1308. ret = true;
  1309. out:
  1310. return ret;
  1311. }
  1312. static inline void ufshcd_put_dev_cmd_tag(struct ufs_hba *hba, int tag)
  1313. {
  1314. clear_bit_unlock(tag, &hba->lrb_in_use);
  1315. }
  1316. /**
  1317. * ufshcd_exec_dev_cmd - API for sending device management requests
  1318. * @hba - UFS hba
  1319. * @cmd_type - specifies the type (NOP, Query...)
  1320. * @timeout - time in seconds
  1321. *
  1322. * NOTE: Since there is only one available tag for device management commands,
  1323. * it is expected you hold the hba->dev_cmd.lock mutex.
  1324. */
  1325. static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
  1326. enum dev_cmd_type cmd_type, int timeout)
  1327. {
  1328. struct ufshcd_lrb *lrbp;
  1329. int err;
  1330. int tag;
  1331. struct completion wait;
  1332. unsigned long flags;
  1333. /*
  1334. * Get free slot, sleep if slots are unavailable.
  1335. * Even though we use wait_event() which sleeps indefinitely,
  1336. * the maximum wait time is bounded by SCSI request timeout.
  1337. */
  1338. wait_event(hba->dev_cmd.tag_wq, ufshcd_get_dev_cmd_tag(hba, &tag));
  1339. init_completion(&wait);
  1340. lrbp = &hba->lrb[tag];
  1341. WARN_ON(lrbp->cmd);
  1342. err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
  1343. if (unlikely(err))
  1344. goto out_put_tag;
  1345. hba->dev_cmd.complete = &wait;
  1346. spin_lock_irqsave(hba->host->host_lock, flags);
  1347. ufshcd_send_command(hba, tag);
  1348. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1349. err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
  1350. out_put_tag:
  1351. ufshcd_put_dev_cmd_tag(hba, tag);
  1352. wake_up(&hba->dev_cmd.tag_wq);
  1353. return err;
  1354. }
  1355. /**
  1356. * ufshcd_init_query() - init the query response and request parameters
  1357. * @hba: per-adapter instance
  1358. * @request: address of the request pointer to be initialized
  1359. * @response: address of the response pointer to be initialized
  1360. * @opcode: operation to perform
  1361. * @idn: flag idn to access
  1362. * @index: LU number to access
  1363. * @selector: query/flag/descriptor further identification
  1364. */
  1365. static inline void ufshcd_init_query(struct ufs_hba *hba,
  1366. struct ufs_query_req **request, struct ufs_query_res **response,
  1367. enum query_opcode opcode, u8 idn, u8 index, u8 selector)
  1368. {
  1369. *request = &hba->dev_cmd.query.request;
  1370. *response = &hba->dev_cmd.query.response;
  1371. memset(*request, 0, sizeof(struct ufs_query_req));
  1372. memset(*response, 0, sizeof(struct ufs_query_res));
  1373. (*request)->upiu_req.opcode = opcode;
  1374. (*request)->upiu_req.idn = idn;
  1375. (*request)->upiu_req.index = index;
  1376. (*request)->upiu_req.selector = selector;
  1377. }
  1378. /**
  1379. * ufshcd_query_flag() - API function for sending flag query requests
  1380. * hba: per-adapter instance
  1381. * query_opcode: flag query to perform
  1382. * idn: flag idn to access
  1383. * flag_res: the flag value after the query request completes
  1384. *
  1385. * Returns 0 for success, non-zero in case of failure
  1386. */
  1387. static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
  1388. enum flag_idn idn, bool *flag_res)
  1389. {
  1390. struct ufs_query_req *request = NULL;
  1391. struct ufs_query_res *response = NULL;
  1392. int err, index = 0, selector = 0;
  1393. BUG_ON(!hba);
  1394. ufshcd_hold(hba, false);
  1395. mutex_lock(&hba->dev_cmd.lock);
  1396. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1397. selector);
  1398. switch (opcode) {
  1399. case UPIU_QUERY_OPCODE_SET_FLAG:
  1400. case UPIU_QUERY_OPCODE_CLEAR_FLAG:
  1401. case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
  1402. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1403. break;
  1404. case UPIU_QUERY_OPCODE_READ_FLAG:
  1405. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1406. if (!flag_res) {
  1407. /* No dummy reads */
  1408. dev_err(hba->dev, "%s: Invalid argument for read request\n",
  1409. __func__);
  1410. err = -EINVAL;
  1411. goto out_unlock;
  1412. }
  1413. break;
  1414. default:
  1415. dev_err(hba->dev,
  1416. "%s: Expected query flag opcode but got = %d\n",
  1417. __func__, opcode);
  1418. err = -EINVAL;
  1419. goto out_unlock;
  1420. }
  1421. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  1422. if (err) {
  1423. dev_err(hba->dev,
  1424. "%s: Sending flag query for idn %d failed, err = %d\n",
  1425. __func__, idn, err);
  1426. goto out_unlock;
  1427. }
  1428. if (flag_res)
  1429. *flag_res = (be32_to_cpu(response->upiu_res.value) &
  1430. MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
  1431. out_unlock:
  1432. mutex_unlock(&hba->dev_cmd.lock);
  1433. ufshcd_release(hba);
  1434. return err;
  1435. }
  1436. /**
  1437. * ufshcd_query_attr - API function for sending attribute requests
  1438. * hba: per-adapter instance
  1439. * opcode: attribute opcode
  1440. * idn: attribute idn to access
  1441. * index: index field
  1442. * selector: selector field
  1443. * attr_val: the attribute value after the query request completes
  1444. *
  1445. * Returns 0 for success, non-zero in case of failure
  1446. */
  1447. static int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
  1448. enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
  1449. {
  1450. struct ufs_query_req *request = NULL;
  1451. struct ufs_query_res *response = NULL;
  1452. int err;
  1453. BUG_ON(!hba);
  1454. ufshcd_hold(hba, false);
  1455. if (!attr_val) {
  1456. dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
  1457. __func__, opcode);
  1458. err = -EINVAL;
  1459. goto out;
  1460. }
  1461. mutex_lock(&hba->dev_cmd.lock);
  1462. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1463. selector);
  1464. switch (opcode) {
  1465. case UPIU_QUERY_OPCODE_WRITE_ATTR:
  1466. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1467. request->upiu_req.value = cpu_to_be32(*attr_val);
  1468. break;
  1469. case UPIU_QUERY_OPCODE_READ_ATTR:
  1470. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1471. break;
  1472. default:
  1473. dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
  1474. __func__, opcode);
  1475. err = -EINVAL;
  1476. goto out_unlock;
  1477. }
  1478. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  1479. if (err) {
  1480. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
  1481. __func__, opcode, idn, err);
  1482. goto out_unlock;
  1483. }
  1484. *attr_val = be32_to_cpu(response->upiu_res.value);
  1485. out_unlock:
  1486. mutex_unlock(&hba->dev_cmd.lock);
  1487. out:
  1488. ufshcd_release(hba);
  1489. return err;
  1490. }
  1491. /**
  1492. * ufshcd_query_descriptor - API function for sending descriptor requests
  1493. * hba: per-adapter instance
  1494. * opcode: attribute opcode
  1495. * idn: attribute idn to access
  1496. * index: index field
  1497. * selector: selector field
  1498. * desc_buf: the buffer that contains the descriptor
  1499. * buf_len: length parameter passed to the device
  1500. *
  1501. * Returns 0 for success, non-zero in case of failure.
  1502. * The buf_len parameter will contain, on return, the length parameter
  1503. * received on the response.
  1504. */
  1505. static int ufshcd_query_descriptor(struct ufs_hba *hba,
  1506. enum query_opcode opcode, enum desc_idn idn, u8 index,
  1507. u8 selector, u8 *desc_buf, int *buf_len)
  1508. {
  1509. struct ufs_query_req *request = NULL;
  1510. struct ufs_query_res *response = NULL;
  1511. int err;
  1512. BUG_ON(!hba);
  1513. ufshcd_hold(hba, false);
  1514. if (!desc_buf) {
  1515. dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
  1516. __func__, opcode);
  1517. err = -EINVAL;
  1518. goto out;
  1519. }
  1520. if (*buf_len <= QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
  1521. dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
  1522. __func__, *buf_len);
  1523. err = -EINVAL;
  1524. goto out;
  1525. }
  1526. mutex_lock(&hba->dev_cmd.lock);
  1527. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  1528. selector);
  1529. hba->dev_cmd.query.descriptor = desc_buf;
  1530. request->upiu_req.length = cpu_to_be16(*buf_len);
  1531. switch (opcode) {
  1532. case UPIU_QUERY_OPCODE_WRITE_DESC:
  1533. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  1534. break;
  1535. case UPIU_QUERY_OPCODE_READ_DESC:
  1536. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  1537. break;
  1538. default:
  1539. dev_err(hba->dev,
  1540. "%s: Expected query descriptor opcode but got = 0x%.2x\n",
  1541. __func__, opcode);
  1542. err = -EINVAL;
  1543. goto out_unlock;
  1544. }
  1545. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  1546. if (err) {
  1547. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, err = %d\n",
  1548. __func__, opcode, idn, err);
  1549. goto out_unlock;
  1550. }
  1551. hba->dev_cmd.query.descriptor = NULL;
  1552. *buf_len = be16_to_cpu(response->upiu_res.length);
  1553. out_unlock:
  1554. mutex_unlock(&hba->dev_cmd.lock);
  1555. out:
  1556. ufshcd_release(hba);
  1557. return err;
  1558. }
  1559. /**
  1560. * ufshcd_read_desc_param - read the specified descriptor parameter
  1561. * @hba: Pointer to adapter instance
  1562. * @desc_id: descriptor idn value
  1563. * @desc_index: descriptor index
  1564. * @param_offset: offset of the parameter to read
  1565. * @param_read_buf: pointer to buffer where parameter would be read
  1566. * @param_size: sizeof(param_read_buf)
  1567. *
  1568. * Return 0 in case of success, non-zero otherwise
  1569. */
  1570. static int ufshcd_read_desc_param(struct ufs_hba *hba,
  1571. enum desc_idn desc_id,
  1572. int desc_index,
  1573. u32 param_offset,
  1574. u8 *param_read_buf,
  1575. u32 param_size)
  1576. {
  1577. int ret;
  1578. u8 *desc_buf;
  1579. u32 buff_len;
  1580. bool is_kmalloc = true;
  1581. /* safety checks */
  1582. if (desc_id >= QUERY_DESC_IDN_MAX)
  1583. return -EINVAL;
  1584. buff_len = ufs_query_desc_max_size[desc_id];
  1585. if ((param_offset + param_size) > buff_len)
  1586. return -EINVAL;
  1587. if (!param_offset && (param_size == buff_len)) {
  1588. /* memory space already available to hold full descriptor */
  1589. desc_buf = param_read_buf;
  1590. is_kmalloc = false;
  1591. } else {
  1592. /* allocate memory to hold full descriptor */
  1593. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  1594. if (!desc_buf)
  1595. return -ENOMEM;
  1596. }
  1597. ret = ufshcd_query_descriptor(hba, UPIU_QUERY_OPCODE_READ_DESC,
  1598. desc_id, desc_index, 0, desc_buf,
  1599. &buff_len);
  1600. if (ret || (buff_len < ufs_query_desc_max_size[desc_id]) ||
  1601. (desc_buf[QUERY_DESC_LENGTH_OFFSET] !=
  1602. ufs_query_desc_max_size[desc_id])
  1603. || (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id)) {
  1604. dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d param_offset %d buff_len %d ret %d",
  1605. __func__, desc_id, param_offset, buff_len, ret);
  1606. if (!ret)
  1607. ret = -EINVAL;
  1608. goto out;
  1609. }
  1610. if (is_kmalloc)
  1611. memcpy(param_read_buf, &desc_buf[param_offset], param_size);
  1612. out:
  1613. if (is_kmalloc)
  1614. kfree(desc_buf);
  1615. return ret;
  1616. }
  1617. static inline int ufshcd_read_desc(struct ufs_hba *hba,
  1618. enum desc_idn desc_id,
  1619. int desc_index,
  1620. u8 *buf,
  1621. u32 size)
  1622. {
  1623. return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
  1624. }
  1625. static inline int ufshcd_read_power_desc(struct ufs_hba *hba,
  1626. u8 *buf,
  1627. u32 size)
  1628. {
  1629. return ufshcd_read_desc(hba, QUERY_DESC_IDN_POWER, 0, buf, size);
  1630. }
  1631. /**
  1632. * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
  1633. * @hba: Pointer to adapter instance
  1634. * @lun: lun id
  1635. * @param_offset: offset of the parameter to read
  1636. * @param_read_buf: pointer to buffer where parameter would be read
  1637. * @param_size: sizeof(param_read_buf)
  1638. *
  1639. * Return 0 in case of success, non-zero otherwise
  1640. */
  1641. static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
  1642. int lun,
  1643. enum unit_desc_param param_offset,
  1644. u8 *param_read_buf,
  1645. u32 param_size)
  1646. {
  1647. /*
  1648. * Unit descriptors are only available for general purpose LUs (LUN id
  1649. * from 0 to 7) and RPMB Well known LU.
  1650. */
  1651. if (lun != UFS_UPIU_RPMB_WLUN && (lun >= UFS_UPIU_MAX_GENERAL_LUN))
  1652. return -EOPNOTSUPP;
  1653. return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
  1654. param_offset, param_read_buf, param_size);
  1655. }
  1656. /**
  1657. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  1658. * @hba: per adapter instance
  1659. *
  1660. * 1. Allocate DMA memory for Command Descriptor array
  1661. * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
  1662. * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
  1663. * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
  1664. * (UTMRDL)
  1665. * 4. Allocate memory for local reference block(lrb).
  1666. *
  1667. * Returns 0 for success, non-zero in case of failure
  1668. */
  1669. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  1670. {
  1671. size_t utmrdl_size, utrdl_size, ucdl_size;
  1672. /* Allocate memory for UTP command descriptors */
  1673. ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
  1674. hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
  1675. ucdl_size,
  1676. &hba->ucdl_dma_addr,
  1677. GFP_KERNEL);
  1678. /*
  1679. * UFSHCI requires UTP command descriptor to be 128 byte aligned.
  1680. * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
  1681. * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
  1682. * be aligned to 128 bytes as well
  1683. */
  1684. if (!hba->ucdl_base_addr ||
  1685. WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
  1686. dev_err(hba->dev,
  1687. "Command Descriptor Memory allocation failed\n");
  1688. goto out;
  1689. }
  1690. /*
  1691. * Allocate memory for UTP Transfer descriptors
  1692. * UFSHCI requires 1024 byte alignment of UTRD
  1693. */
  1694. utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
  1695. hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
  1696. utrdl_size,
  1697. &hba->utrdl_dma_addr,
  1698. GFP_KERNEL);
  1699. if (!hba->utrdl_base_addr ||
  1700. WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
  1701. dev_err(hba->dev,
  1702. "Transfer Descriptor Memory allocation failed\n");
  1703. goto out;
  1704. }
  1705. /*
  1706. * Allocate memory for UTP Task Management descriptors
  1707. * UFSHCI requires 1024 byte alignment of UTMRD
  1708. */
  1709. utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
  1710. hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
  1711. utmrdl_size,
  1712. &hba->utmrdl_dma_addr,
  1713. GFP_KERNEL);
  1714. if (!hba->utmrdl_base_addr ||
  1715. WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
  1716. dev_err(hba->dev,
  1717. "Task Management Descriptor Memory allocation failed\n");
  1718. goto out;
  1719. }
  1720. /* Allocate memory for local reference block */
  1721. hba->lrb = devm_kzalloc(hba->dev,
  1722. hba->nutrs * sizeof(struct ufshcd_lrb),
  1723. GFP_KERNEL);
  1724. if (!hba->lrb) {
  1725. dev_err(hba->dev, "LRB Memory allocation failed\n");
  1726. goto out;
  1727. }
  1728. return 0;
  1729. out:
  1730. return -ENOMEM;
  1731. }
  1732. /**
  1733. * ufshcd_host_memory_configure - configure local reference block with
  1734. * memory offsets
  1735. * @hba: per adapter instance
  1736. *
  1737. * Configure Host memory space
  1738. * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
  1739. * address.
  1740. * 2. Update each UTRD with Response UPIU offset, Response UPIU length
  1741. * and PRDT offset.
  1742. * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
  1743. * into local reference block.
  1744. */
  1745. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  1746. {
  1747. struct utp_transfer_cmd_desc *cmd_descp;
  1748. struct utp_transfer_req_desc *utrdlp;
  1749. dma_addr_t cmd_desc_dma_addr;
  1750. dma_addr_t cmd_desc_element_addr;
  1751. u16 response_offset;
  1752. u16 prdt_offset;
  1753. int cmd_desc_size;
  1754. int i;
  1755. utrdlp = hba->utrdl_base_addr;
  1756. cmd_descp = hba->ucdl_base_addr;
  1757. response_offset =
  1758. offsetof(struct utp_transfer_cmd_desc, response_upiu);
  1759. prdt_offset =
  1760. offsetof(struct utp_transfer_cmd_desc, prd_table);
  1761. cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
  1762. cmd_desc_dma_addr = hba->ucdl_dma_addr;
  1763. for (i = 0; i < hba->nutrs; i++) {
  1764. /* Configure UTRD with command descriptor base address */
  1765. cmd_desc_element_addr =
  1766. (cmd_desc_dma_addr + (cmd_desc_size * i));
  1767. utrdlp[i].command_desc_base_addr_lo =
  1768. cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
  1769. utrdlp[i].command_desc_base_addr_hi =
  1770. cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
  1771. /* Response upiu and prdt offset should be in double words */
  1772. utrdlp[i].response_upiu_offset =
  1773. cpu_to_le16((response_offset >> 2));
  1774. utrdlp[i].prd_table_offset =
  1775. cpu_to_le16((prdt_offset >> 2));
  1776. utrdlp[i].response_upiu_length =
  1777. cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
  1778. hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
  1779. hba->lrb[i].ucd_req_ptr =
  1780. (struct utp_upiu_req *)(cmd_descp + i);
  1781. hba->lrb[i].ucd_rsp_ptr =
  1782. (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
  1783. hba->lrb[i].ucd_prdt_ptr =
  1784. (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
  1785. }
  1786. }
  1787. /**
  1788. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  1789. * @hba: per adapter instance
  1790. *
  1791. * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
  1792. * in order to initialize the Unipro link startup procedure.
  1793. * Once the Unipro links are up, the device connected to the controller
  1794. * is detected.
  1795. *
  1796. * Returns 0 on success, non-zero value on failure
  1797. */
  1798. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  1799. {
  1800. struct uic_command uic_cmd = {0};
  1801. int ret;
  1802. uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
  1803. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  1804. if (ret)
  1805. dev_err(hba->dev,
  1806. "dme-link-startup: error code %d\n", ret);
  1807. return ret;
  1808. }
  1809. /**
  1810. * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
  1811. * @hba: per adapter instance
  1812. * @attr_sel: uic command argument1
  1813. * @attr_set: attribute set type as uic command argument2
  1814. * @mib_val: setting value as uic command argument3
  1815. * @peer: indicate whether peer or local
  1816. *
  1817. * Returns 0 on success, non-zero value on failure
  1818. */
  1819. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
  1820. u8 attr_set, u32 mib_val, u8 peer)
  1821. {
  1822. struct uic_command uic_cmd = {0};
  1823. static const char *const action[] = {
  1824. "dme-set",
  1825. "dme-peer-set"
  1826. };
  1827. const char *set = action[!!peer];
  1828. int ret;
  1829. uic_cmd.command = peer ?
  1830. UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
  1831. uic_cmd.argument1 = attr_sel;
  1832. uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
  1833. uic_cmd.argument3 = mib_val;
  1834. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  1835. if (ret)
  1836. dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
  1837. set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
  1838. return ret;
  1839. }
  1840. EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
  1841. /**
  1842. * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
  1843. * @hba: per adapter instance
  1844. * @attr_sel: uic command argument1
  1845. * @mib_val: the value of the attribute as returned by the UIC command
  1846. * @peer: indicate whether peer or local
  1847. *
  1848. * Returns 0 on success, non-zero value on failure
  1849. */
  1850. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  1851. u32 *mib_val, u8 peer)
  1852. {
  1853. struct uic_command uic_cmd = {0};
  1854. static const char *const action[] = {
  1855. "dme-get",
  1856. "dme-peer-get"
  1857. };
  1858. const char *get = action[!!peer];
  1859. int ret;
  1860. uic_cmd.command = peer ?
  1861. UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
  1862. uic_cmd.argument1 = attr_sel;
  1863. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  1864. if (ret) {
  1865. dev_err(hba->dev, "%s: attr-id 0x%x error code %d\n",
  1866. get, UIC_GET_ATTR_ID(attr_sel), ret);
  1867. goto out;
  1868. }
  1869. if (mib_val)
  1870. *mib_val = uic_cmd.argument3;
  1871. out:
  1872. return ret;
  1873. }
  1874. EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
  1875. /**
  1876. * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
  1877. * state) and waits for it to take effect.
  1878. *
  1879. * @hba: per adapter instance
  1880. * @cmd: UIC command to execute
  1881. *
  1882. * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
  1883. * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
  1884. * and device UniPro link and hence it's final completion would be indicated by
  1885. * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
  1886. * addition to normal UIC command completion Status (UCCS). This function only
  1887. * returns after the relevant status bits indicate the completion.
  1888. *
  1889. * Returns 0 on success, non-zero value on failure
  1890. */
  1891. static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
  1892. {
  1893. struct completion uic_async_done;
  1894. unsigned long flags;
  1895. u8 status;
  1896. int ret;
  1897. mutex_lock(&hba->uic_cmd_mutex);
  1898. init_completion(&uic_async_done);
  1899. spin_lock_irqsave(hba->host->host_lock, flags);
  1900. hba->uic_async_done = &uic_async_done;
  1901. ret = __ufshcd_send_uic_cmd(hba, cmd);
  1902. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1903. if (ret) {
  1904. dev_err(hba->dev,
  1905. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  1906. cmd->command, cmd->argument3, ret);
  1907. goto out;
  1908. }
  1909. ret = ufshcd_wait_for_uic_cmd(hba, cmd);
  1910. if (ret) {
  1911. dev_err(hba->dev,
  1912. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  1913. cmd->command, cmd->argument3, ret);
  1914. goto out;
  1915. }
  1916. if (!wait_for_completion_timeout(hba->uic_async_done,
  1917. msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
  1918. dev_err(hba->dev,
  1919. "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
  1920. cmd->command, cmd->argument3);
  1921. ret = -ETIMEDOUT;
  1922. goto out;
  1923. }
  1924. status = ufshcd_get_upmcrs(hba);
  1925. if (status != PWR_LOCAL) {
  1926. dev_err(hba->dev,
  1927. "pwr ctrl cmd 0x%0x failed, host umpcrs:0x%x\n",
  1928. cmd->command, status);
  1929. ret = (status != PWR_OK) ? status : -1;
  1930. }
  1931. out:
  1932. spin_lock_irqsave(hba->host->host_lock, flags);
  1933. hba->uic_async_done = NULL;
  1934. spin_unlock_irqrestore(hba->host->host_lock, flags);
  1935. mutex_unlock(&hba->uic_cmd_mutex);
  1936. return ret;
  1937. }
  1938. /**
  1939. * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
  1940. * using DME_SET primitives.
  1941. * @hba: per adapter instance
  1942. * @mode: powr mode value
  1943. *
  1944. * Returns 0 on success, non-zero value on failure
  1945. */
  1946. static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
  1947. {
  1948. struct uic_command uic_cmd = {0};
  1949. int ret;
  1950. uic_cmd.command = UIC_CMD_DME_SET;
  1951. uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
  1952. uic_cmd.argument3 = mode;
  1953. ufshcd_hold(hba, false);
  1954. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  1955. ufshcd_release(hba);
  1956. return ret;
  1957. }
  1958. static int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
  1959. {
  1960. struct uic_command uic_cmd = {0};
  1961. uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
  1962. return ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  1963. }
  1964. static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
  1965. {
  1966. struct uic_command uic_cmd = {0};
  1967. int ret;
  1968. uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
  1969. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  1970. if (ret) {
  1971. ufshcd_set_link_off(hba);
  1972. ret = ufshcd_host_reset_and_restore(hba);
  1973. }
  1974. return ret;
  1975. }
  1976. /**
  1977. * ufshcd_init_pwr_info - setting the POR (power on reset)
  1978. * values in hba power info
  1979. * @hba: per-adapter instance
  1980. */
  1981. static void ufshcd_init_pwr_info(struct ufs_hba *hba)
  1982. {
  1983. hba->pwr_info.gear_rx = UFS_PWM_G1;
  1984. hba->pwr_info.gear_tx = UFS_PWM_G1;
  1985. hba->pwr_info.lane_rx = 1;
  1986. hba->pwr_info.lane_tx = 1;
  1987. hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
  1988. hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
  1989. hba->pwr_info.hs_rate = 0;
  1990. }
  1991. /**
  1992. * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
  1993. * @hba: per-adapter instance
  1994. */
  1995. static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
  1996. {
  1997. struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
  1998. if (hba->max_pwr_info.is_valid)
  1999. return 0;
  2000. pwr_info->pwr_tx = FASTAUTO_MODE;
  2001. pwr_info->pwr_rx = FASTAUTO_MODE;
  2002. pwr_info->hs_rate = PA_HS_MODE_B;
  2003. /* Get the connected lane count */
  2004. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
  2005. &pwr_info->lane_rx);
  2006. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  2007. &pwr_info->lane_tx);
  2008. if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
  2009. dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
  2010. __func__,
  2011. pwr_info->lane_rx,
  2012. pwr_info->lane_tx);
  2013. return -EINVAL;
  2014. }
  2015. /*
  2016. * First, get the maximum gears of HS speed.
  2017. * If a zero value, it means there is no HSGEAR capability.
  2018. * Then, get the maximum gears of PWM speed.
  2019. */
  2020. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
  2021. if (!pwr_info->gear_rx) {
  2022. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  2023. &pwr_info->gear_rx);
  2024. if (!pwr_info->gear_rx) {
  2025. dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
  2026. __func__, pwr_info->gear_rx);
  2027. return -EINVAL;
  2028. }
  2029. pwr_info->pwr_rx = SLOWAUTO_MODE;
  2030. }
  2031. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
  2032. &pwr_info->gear_tx);
  2033. if (!pwr_info->gear_tx) {
  2034. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  2035. &pwr_info->gear_tx);
  2036. if (!pwr_info->gear_tx) {
  2037. dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
  2038. __func__, pwr_info->gear_tx);
  2039. return -EINVAL;
  2040. }
  2041. pwr_info->pwr_tx = SLOWAUTO_MODE;
  2042. }
  2043. hba->max_pwr_info.is_valid = true;
  2044. return 0;
  2045. }
  2046. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  2047. struct ufs_pa_layer_attr *pwr_mode)
  2048. {
  2049. int ret;
  2050. /* if already configured to the requested pwr_mode */
  2051. if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
  2052. pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
  2053. pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
  2054. pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
  2055. pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
  2056. pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
  2057. pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
  2058. dev_dbg(hba->dev, "%s: power already configured\n", __func__);
  2059. return 0;
  2060. }
  2061. /*
  2062. * Configure attributes for power mode change with below.
  2063. * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
  2064. * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
  2065. * - PA_HSSERIES
  2066. */
  2067. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
  2068. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
  2069. pwr_mode->lane_rx);
  2070. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  2071. pwr_mode->pwr_rx == FAST_MODE)
  2072. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
  2073. else
  2074. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
  2075. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
  2076. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
  2077. pwr_mode->lane_tx);
  2078. if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
  2079. pwr_mode->pwr_tx == FAST_MODE)
  2080. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
  2081. else
  2082. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
  2083. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  2084. pwr_mode->pwr_tx == FASTAUTO_MODE ||
  2085. pwr_mode->pwr_rx == FAST_MODE ||
  2086. pwr_mode->pwr_tx == FAST_MODE)
  2087. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
  2088. pwr_mode->hs_rate);
  2089. ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
  2090. | pwr_mode->pwr_tx);
  2091. if (ret) {
  2092. dev_err(hba->dev,
  2093. "%s: power mode change failed %d\n", __func__, ret);
  2094. } else {
  2095. if (hba->vops && hba->vops->pwr_change_notify)
  2096. hba->vops->pwr_change_notify(hba,
  2097. POST_CHANGE, NULL, pwr_mode);
  2098. memcpy(&hba->pwr_info, pwr_mode,
  2099. sizeof(struct ufs_pa_layer_attr));
  2100. }
  2101. return ret;
  2102. }
  2103. /**
  2104. * ufshcd_config_pwr_mode - configure a new power mode
  2105. * @hba: per-adapter instance
  2106. * @desired_pwr_mode: desired power configuration
  2107. */
  2108. static int ufshcd_config_pwr_mode(struct ufs_hba *hba,
  2109. struct ufs_pa_layer_attr *desired_pwr_mode)
  2110. {
  2111. struct ufs_pa_layer_attr final_params = { 0 };
  2112. int ret;
  2113. if (hba->vops && hba->vops->pwr_change_notify)
  2114. hba->vops->pwr_change_notify(hba,
  2115. PRE_CHANGE, desired_pwr_mode, &final_params);
  2116. else
  2117. memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
  2118. ret = ufshcd_change_power_mode(hba, &final_params);
  2119. return ret;
  2120. }
  2121. /**
  2122. * ufshcd_complete_dev_init() - checks device readiness
  2123. * hba: per-adapter instance
  2124. *
  2125. * Set fDeviceInit flag and poll until device toggles it.
  2126. */
  2127. static int ufshcd_complete_dev_init(struct ufs_hba *hba)
  2128. {
  2129. int i, retries, err = 0;
  2130. bool flag_res = 1;
  2131. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  2132. /* Set the fDeviceInit flag */
  2133. err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  2134. QUERY_FLAG_IDN_FDEVICEINIT, NULL);
  2135. if (!err || err == -ETIMEDOUT)
  2136. break;
  2137. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  2138. }
  2139. if (err) {
  2140. dev_err(hba->dev,
  2141. "%s setting fDeviceInit flag failed with error %d\n",
  2142. __func__, err);
  2143. goto out;
  2144. }
  2145. /* poll for max. 100 iterations for fDeviceInit flag to clear */
  2146. for (i = 0; i < 100 && !err && flag_res; i++) {
  2147. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  2148. err = ufshcd_query_flag(hba,
  2149. UPIU_QUERY_OPCODE_READ_FLAG,
  2150. QUERY_FLAG_IDN_FDEVICEINIT, &flag_res);
  2151. if (!err || err == -ETIMEDOUT)
  2152. break;
  2153. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__,
  2154. err);
  2155. }
  2156. }
  2157. if (err)
  2158. dev_err(hba->dev,
  2159. "%s reading fDeviceInit flag failed with error %d\n",
  2160. __func__, err);
  2161. else if (flag_res)
  2162. dev_err(hba->dev,
  2163. "%s fDeviceInit was not cleared by the device\n",
  2164. __func__);
  2165. out:
  2166. return err;
  2167. }
  2168. /**
  2169. * ufshcd_make_hba_operational - Make UFS controller operational
  2170. * @hba: per adapter instance
  2171. *
  2172. * To bring UFS host controller to operational state,
  2173. * 1. Enable required interrupts
  2174. * 2. Configure interrupt aggregation
  2175. * 3. Program UTRL and UTMRL base addres
  2176. * 4. Configure run-stop-registers
  2177. *
  2178. * Returns 0 on success, non-zero value on failure
  2179. */
  2180. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  2181. {
  2182. int err = 0;
  2183. u32 reg;
  2184. /* Enable required interrupts */
  2185. ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
  2186. /* Configure interrupt aggregation */
  2187. ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
  2188. /* Configure UTRL and UTMRL base address registers */
  2189. ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
  2190. REG_UTP_TRANSFER_REQ_LIST_BASE_L);
  2191. ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
  2192. REG_UTP_TRANSFER_REQ_LIST_BASE_H);
  2193. ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
  2194. REG_UTP_TASK_REQ_LIST_BASE_L);
  2195. ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
  2196. REG_UTP_TASK_REQ_LIST_BASE_H);
  2197. /*
  2198. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  2199. * DEI, HEI bits must be 0
  2200. */
  2201. reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
  2202. if (!(ufshcd_get_lists_status(reg))) {
  2203. ufshcd_enable_run_stop_reg(hba);
  2204. } else {
  2205. dev_err(hba->dev,
  2206. "Host controller not ready to process requests");
  2207. err = -EIO;
  2208. goto out;
  2209. }
  2210. out:
  2211. return err;
  2212. }
  2213. /**
  2214. * ufshcd_hba_enable - initialize the controller
  2215. * @hba: per adapter instance
  2216. *
  2217. * The controller resets itself and controller firmware initialization
  2218. * sequence kicks off. When controller is ready it will set
  2219. * the Host Controller Enable bit to 1.
  2220. *
  2221. * Returns 0 on success, non-zero value on failure
  2222. */
  2223. static int ufshcd_hba_enable(struct ufs_hba *hba)
  2224. {
  2225. int retry;
  2226. /*
  2227. * msleep of 1 and 5 used in this function might result in msleep(20),
  2228. * but it was necessary to send the UFS FPGA to reset mode during
  2229. * development and testing of this driver. msleep can be changed to
  2230. * mdelay and retry count can be reduced based on the controller.
  2231. */
  2232. if (!ufshcd_is_hba_active(hba)) {
  2233. /* change controller state to "reset state" */
  2234. ufshcd_hba_stop(hba);
  2235. /*
  2236. * This delay is based on the testing done with UFS host
  2237. * controller FPGA. The delay can be changed based on the
  2238. * host controller used.
  2239. */
  2240. msleep(5);
  2241. }
  2242. /* UniPro link is disabled at this point */
  2243. ufshcd_set_link_off(hba);
  2244. if (hba->vops && hba->vops->hce_enable_notify)
  2245. hba->vops->hce_enable_notify(hba, PRE_CHANGE);
  2246. /* start controller initialization sequence */
  2247. ufshcd_hba_start(hba);
  2248. /*
  2249. * To initialize a UFS host controller HCE bit must be set to 1.
  2250. * During initialization the HCE bit value changes from 1->0->1.
  2251. * When the host controller completes initialization sequence
  2252. * it sets the value of HCE bit to 1. The same HCE bit is read back
  2253. * to check if the controller has completed initialization sequence.
  2254. * So without this delay the value HCE = 1, set in the previous
  2255. * instruction might be read back.
  2256. * This delay can be changed based on the controller.
  2257. */
  2258. msleep(1);
  2259. /* wait for the host controller to complete initialization */
  2260. retry = 10;
  2261. while (ufshcd_is_hba_active(hba)) {
  2262. if (retry) {
  2263. retry--;
  2264. } else {
  2265. dev_err(hba->dev,
  2266. "Controller enable failed\n");
  2267. return -EIO;
  2268. }
  2269. msleep(5);
  2270. }
  2271. /* enable UIC related interrupts */
  2272. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  2273. if (hba->vops && hba->vops->hce_enable_notify)
  2274. hba->vops->hce_enable_notify(hba, POST_CHANGE);
  2275. return 0;
  2276. }
  2277. /**
  2278. * ufshcd_link_startup - Initialize unipro link startup
  2279. * @hba: per adapter instance
  2280. *
  2281. * Returns 0 for success, non-zero in case of failure
  2282. */
  2283. static int ufshcd_link_startup(struct ufs_hba *hba)
  2284. {
  2285. int ret;
  2286. int retries = DME_LINKSTARTUP_RETRIES;
  2287. do {
  2288. if (hba->vops && hba->vops->link_startup_notify)
  2289. hba->vops->link_startup_notify(hba, PRE_CHANGE);
  2290. ret = ufshcd_dme_link_startup(hba);
  2291. /* check if device is detected by inter-connect layer */
  2292. if (!ret && !ufshcd_is_device_present(hba)) {
  2293. dev_err(hba->dev, "%s: Device not present\n", __func__);
  2294. ret = -ENXIO;
  2295. goto out;
  2296. }
  2297. /*
  2298. * DME link lost indication is only received when link is up,
  2299. * but we can't be sure if the link is up until link startup
  2300. * succeeds. So reset the local Uni-Pro and try again.
  2301. */
  2302. if (ret && ufshcd_hba_enable(hba))
  2303. goto out;
  2304. } while (ret && retries--);
  2305. if (ret)
  2306. /* failed to get the link up... retire */
  2307. goto out;
  2308. /* Include any host controller configuration via UIC commands */
  2309. if (hba->vops && hba->vops->link_startup_notify) {
  2310. ret = hba->vops->link_startup_notify(hba, POST_CHANGE);
  2311. if (ret)
  2312. goto out;
  2313. }
  2314. ret = ufshcd_make_hba_operational(hba);
  2315. out:
  2316. if (ret)
  2317. dev_err(hba->dev, "link startup failed %d\n", ret);
  2318. return ret;
  2319. }
  2320. /**
  2321. * ufshcd_verify_dev_init() - Verify device initialization
  2322. * @hba: per-adapter instance
  2323. *
  2324. * Send NOP OUT UPIU and wait for NOP IN response to check whether the
  2325. * device Transport Protocol (UTP) layer is ready after a reset.
  2326. * If the UTP layer at the device side is not initialized, it may
  2327. * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
  2328. * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
  2329. */
  2330. static int ufshcd_verify_dev_init(struct ufs_hba *hba)
  2331. {
  2332. int err = 0;
  2333. int retries;
  2334. ufshcd_hold(hba, false);
  2335. mutex_lock(&hba->dev_cmd.lock);
  2336. for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
  2337. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
  2338. NOP_OUT_TIMEOUT);
  2339. if (!err || err == -ETIMEDOUT)
  2340. break;
  2341. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  2342. }
  2343. mutex_unlock(&hba->dev_cmd.lock);
  2344. ufshcd_release(hba);
  2345. if (err)
  2346. dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
  2347. return err;
  2348. }
  2349. /**
  2350. * ufshcd_set_queue_depth - set lun queue depth
  2351. * @sdev: pointer to SCSI device
  2352. *
  2353. * Read bLUQueueDepth value and activate scsi tagged command
  2354. * queueing. For WLUN, queue depth is set to 1. For best-effort
  2355. * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
  2356. * value that host can queue.
  2357. */
  2358. static void ufshcd_set_queue_depth(struct scsi_device *sdev)
  2359. {
  2360. int ret = 0;
  2361. u8 lun_qdepth;
  2362. struct ufs_hba *hba;
  2363. hba = shost_priv(sdev->host);
  2364. lun_qdepth = hba->nutrs;
  2365. ret = ufshcd_read_unit_desc_param(hba,
  2366. ufshcd_scsi_to_upiu_lun(sdev->lun),
  2367. UNIT_DESC_PARAM_LU_Q_DEPTH,
  2368. &lun_qdepth,
  2369. sizeof(lun_qdepth));
  2370. /* Some WLUN doesn't support unit descriptor */
  2371. if (ret == -EOPNOTSUPP)
  2372. lun_qdepth = 1;
  2373. else if (!lun_qdepth)
  2374. /* eventually, we can figure out the real queue depth */
  2375. lun_qdepth = hba->nutrs;
  2376. else
  2377. lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
  2378. dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
  2379. __func__, lun_qdepth);
  2380. scsi_activate_tcq(sdev, lun_qdepth);
  2381. }
  2382. /*
  2383. * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
  2384. * @hba: per-adapter instance
  2385. * @lun: UFS device lun id
  2386. * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
  2387. *
  2388. * Returns 0 in case of success and b_lu_write_protect status would be returned
  2389. * @b_lu_write_protect parameter.
  2390. * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
  2391. * Returns -EINVAL in case of invalid parameters passed to this function.
  2392. */
  2393. static int ufshcd_get_lu_wp(struct ufs_hba *hba,
  2394. u8 lun,
  2395. u8 *b_lu_write_protect)
  2396. {
  2397. int ret;
  2398. if (!b_lu_write_protect)
  2399. ret = -EINVAL;
  2400. /*
  2401. * According to UFS device spec, RPMB LU can't be write
  2402. * protected so skip reading bLUWriteProtect parameter for
  2403. * it. For other W-LUs, UNIT DESCRIPTOR is not available.
  2404. */
  2405. else if (lun >= UFS_UPIU_MAX_GENERAL_LUN)
  2406. ret = -ENOTSUPP;
  2407. else
  2408. ret = ufshcd_read_unit_desc_param(hba,
  2409. lun,
  2410. UNIT_DESC_PARAM_LU_WR_PROTECT,
  2411. b_lu_write_protect,
  2412. sizeof(*b_lu_write_protect));
  2413. return ret;
  2414. }
  2415. /**
  2416. * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
  2417. * status
  2418. * @hba: per-adapter instance
  2419. * @sdev: pointer to SCSI device
  2420. *
  2421. */
  2422. static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
  2423. struct scsi_device *sdev)
  2424. {
  2425. if (hba->dev_info.f_power_on_wp_en &&
  2426. !hba->dev_info.is_lu_power_on_wp) {
  2427. u8 b_lu_write_protect;
  2428. if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
  2429. &b_lu_write_protect) &&
  2430. (b_lu_write_protect == UFS_LU_POWER_ON_WP))
  2431. hba->dev_info.is_lu_power_on_wp = true;
  2432. }
  2433. }
  2434. /**
  2435. * ufshcd_slave_alloc - handle initial SCSI device configurations
  2436. * @sdev: pointer to SCSI device
  2437. *
  2438. * Returns success
  2439. */
  2440. static int ufshcd_slave_alloc(struct scsi_device *sdev)
  2441. {
  2442. struct ufs_hba *hba;
  2443. hba = shost_priv(sdev->host);
  2444. sdev->tagged_supported = 1;
  2445. /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
  2446. sdev->use_10_for_ms = 1;
  2447. scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
  2448. /* allow SCSI layer to restart the device in case of errors */
  2449. sdev->allow_restart = 1;
  2450. /* REPORT SUPPORTED OPERATION CODES is not supported */
  2451. sdev->no_report_opcodes = 1;
  2452. ufshcd_set_queue_depth(sdev);
  2453. ufshcd_get_lu_power_on_wp_status(hba, sdev);
  2454. return 0;
  2455. }
  2456. /**
  2457. * ufshcd_change_queue_depth - change queue depth
  2458. * @sdev: pointer to SCSI device
  2459. * @depth: required depth to set
  2460. * @reason: reason for changing the depth
  2461. *
  2462. * Change queue depth according to the reason and make sure
  2463. * the max. limits are not crossed.
  2464. */
  2465. static int ufshcd_change_queue_depth(struct scsi_device *sdev,
  2466. int depth, int reason)
  2467. {
  2468. struct ufs_hba *hba = shost_priv(sdev->host);
  2469. if (depth > hba->nutrs)
  2470. depth = hba->nutrs;
  2471. switch (reason) {
  2472. case SCSI_QDEPTH_DEFAULT:
  2473. case SCSI_QDEPTH_RAMP_UP:
  2474. if (!sdev->tagged_supported)
  2475. depth = 1;
  2476. scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), depth);
  2477. break;
  2478. case SCSI_QDEPTH_QFULL:
  2479. scsi_track_queue_full(sdev, depth);
  2480. break;
  2481. default:
  2482. return -EOPNOTSUPP;
  2483. }
  2484. return depth;
  2485. }
  2486. /**
  2487. * ufshcd_slave_configure - adjust SCSI device configurations
  2488. * @sdev: pointer to SCSI device
  2489. */
  2490. static int ufshcd_slave_configure(struct scsi_device *sdev)
  2491. {
  2492. struct request_queue *q = sdev->request_queue;
  2493. blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
  2494. blk_queue_max_segment_size(q, PRDT_DATA_BYTE_COUNT_MAX);
  2495. return 0;
  2496. }
  2497. /**
  2498. * ufshcd_slave_destroy - remove SCSI device configurations
  2499. * @sdev: pointer to SCSI device
  2500. */
  2501. static void ufshcd_slave_destroy(struct scsi_device *sdev)
  2502. {
  2503. struct ufs_hba *hba;
  2504. hba = shost_priv(sdev->host);
  2505. scsi_deactivate_tcq(sdev, hba->nutrs);
  2506. /* Drop the reference as it won't be needed anymore */
  2507. if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
  2508. unsigned long flags;
  2509. spin_lock_irqsave(hba->host->host_lock, flags);
  2510. hba->sdev_ufs_device = NULL;
  2511. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2512. }
  2513. }
  2514. /**
  2515. * ufshcd_task_req_compl - handle task management request completion
  2516. * @hba: per adapter instance
  2517. * @index: index of the completed request
  2518. * @resp: task management service response
  2519. *
  2520. * Returns non-zero value on error, zero on success
  2521. */
  2522. static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index, u8 *resp)
  2523. {
  2524. struct utp_task_req_desc *task_req_descp;
  2525. struct utp_upiu_task_rsp *task_rsp_upiup;
  2526. unsigned long flags;
  2527. int ocs_value;
  2528. int task_result;
  2529. spin_lock_irqsave(hba->host->host_lock, flags);
  2530. /* Clear completed tasks from outstanding_tasks */
  2531. __clear_bit(index, &hba->outstanding_tasks);
  2532. task_req_descp = hba->utmrdl_base_addr;
  2533. ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
  2534. if (ocs_value == OCS_SUCCESS) {
  2535. task_rsp_upiup = (struct utp_upiu_task_rsp *)
  2536. task_req_descp[index].task_rsp_upiu;
  2537. task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
  2538. task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
  2539. if (resp)
  2540. *resp = (u8)task_result;
  2541. } else {
  2542. dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
  2543. __func__, ocs_value);
  2544. }
  2545. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2546. return ocs_value;
  2547. }
  2548. /**
  2549. * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
  2550. * @lrb: pointer to local reference block of completed command
  2551. * @scsi_status: SCSI command status
  2552. *
  2553. * Returns value base on SCSI command status
  2554. */
  2555. static inline int
  2556. ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
  2557. {
  2558. int result = 0;
  2559. switch (scsi_status) {
  2560. case SAM_STAT_CHECK_CONDITION:
  2561. ufshcd_copy_sense_data(lrbp);
  2562. case SAM_STAT_GOOD:
  2563. result |= DID_OK << 16 |
  2564. COMMAND_COMPLETE << 8 |
  2565. scsi_status;
  2566. break;
  2567. case SAM_STAT_TASK_SET_FULL:
  2568. case SAM_STAT_BUSY:
  2569. case SAM_STAT_TASK_ABORTED:
  2570. ufshcd_copy_sense_data(lrbp);
  2571. result |= scsi_status;
  2572. break;
  2573. default:
  2574. result |= DID_ERROR << 16;
  2575. break;
  2576. } /* end of switch */
  2577. return result;
  2578. }
  2579. /**
  2580. * ufshcd_transfer_rsp_status - Get overall status of the response
  2581. * @hba: per adapter instance
  2582. * @lrb: pointer to local reference block of completed command
  2583. *
  2584. * Returns result of the command to notify SCSI midlayer
  2585. */
  2586. static inline int
  2587. ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
  2588. {
  2589. int result = 0;
  2590. int scsi_status;
  2591. int ocs;
  2592. /* overall command status of utrd */
  2593. ocs = ufshcd_get_tr_ocs(lrbp);
  2594. switch (ocs) {
  2595. case OCS_SUCCESS:
  2596. result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
  2597. switch (result) {
  2598. case UPIU_TRANSACTION_RESPONSE:
  2599. /*
  2600. * get the response UPIU result to extract
  2601. * the SCSI command status
  2602. */
  2603. result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
  2604. /*
  2605. * get the result based on SCSI status response
  2606. * to notify the SCSI midlayer of the command status
  2607. */
  2608. scsi_status = result & MASK_SCSI_STATUS;
  2609. result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
  2610. if (ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
  2611. schedule_work(&hba->eeh_work);
  2612. break;
  2613. case UPIU_TRANSACTION_REJECT_UPIU:
  2614. /* TODO: handle Reject UPIU Response */
  2615. result = DID_ERROR << 16;
  2616. dev_err(hba->dev,
  2617. "Reject UPIU not fully implemented\n");
  2618. break;
  2619. default:
  2620. result = DID_ERROR << 16;
  2621. dev_err(hba->dev,
  2622. "Unexpected request response code = %x\n",
  2623. result);
  2624. break;
  2625. }
  2626. break;
  2627. case OCS_ABORTED:
  2628. result |= DID_ABORT << 16;
  2629. break;
  2630. case OCS_INVALID_COMMAND_STATUS:
  2631. result |= DID_REQUEUE << 16;
  2632. break;
  2633. case OCS_INVALID_CMD_TABLE_ATTR:
  2634. case OCS_INVALID_PRDT_ATTR:
  2635. case OCS_MISMATCH_DATA_BUF_SIZE:
  2636. case OCS_MISMATCH_RESP_UPIU_SIZE:
  2637. case OCS_PEER_COMM_FAILURE:
  2638. case OCS_FATAL_ERROR:
  2639. default:
  2640. result |= DID_ERROR << 16;
  2641. dev_err(hba->dev,
  2642. "OCS error from controller = %x\n", ocs);
  2643. break;
  2644. } /* end of switch */
  2645. return result;
  2646. }
  2647. /**
  2648. * ufshcd_uic_cmd_compl - handle completion of uic command
  2649. * @hba: per adapter instance
  2650. * @intr_status: interrupt status generated by the controller
  2651. */
  2652. static void ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
  2653. {
  2654. if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
  2655. hba->active_uic_cmd->argument2 |=
  2656. ufshcd_get_uic_cmd_result(hba);
  2657. hba->active_uic_cmd->argument3 =
  2658. ufshcd_get_dme_attr_val(hba);
  2659. complete(&hba->active_uic_cmd->done);
  2660. }
  2661. if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done)
  2662. complete(hba->uic_async_done);
  2663. }
  2664. /**
  2665. * ufshcd_transfer_req_compl - handle SCSI and query command completion
  2666. * @hba: per adapter instance
  2667. */
  2668. static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
  2669. {
  2670. struct ufshcd_lrb *lrbp;
  2671. struct scsi_cmnd *cmd;
  2672. unsigned long completed_reqs;
  2673. u32 tr_doorbell;
  2674. int result;
  2675. int index;
  2676. /* Resetting interrupt aggregation counters first and reading the
  2677. * DOOR_BELL afterward allows us to handle all the completed requests.
  2678. * In order to prevent other interrupts starvation the DB is read once
  2679. * after reset. The down side of this solution is the possibility of
  2680. * false interrupt if device completes another request after resetting
  2681. * aggregation and before reading the DB.
  2682. */
  2683. ufshcd_reset_intr_aggr(hba);
  2684. tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  2685. completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
  2686. for_each_set_bit(index, &completed_reqs, hba->nutrs) {
  2687. lrbp = &hba->lrb[index];
  2688. cmd = lrbp->cmd;
  2689. if (cmd) {
  2690. result = ufshcd_transfer_rsp_status(hba, lrbp);
  2691. scsi_dma_unmap(cmd);
  2692. cmd->result = result;
  2693. /* Mark completed command as NULL in LRB */
  2694. lrbp->cmd = NULL;
  2695. clear_bit_unlock(index, &hba->lrb_in_use);
  2696. /* Do not touch lrbp after scsi done */
  2697. cmd->scsi_done(cmd);
  2698. __ufshcd_release(hba);
  2699. } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE) {
  2700. if (hba->dev_cmd.complete)
  2701. complete(hba->dev_cmd.complete);
  2702. }
  2703. }
  2704. /* clear corresponding bits of completed commands */
  2705. hba->outstanding_reqs ^= completed_reqs;
  2706. ufshcd_clk_scaling_update_busy(hba);
  2707. /* we might have free'd some tags above */
  2708. wake_up(&hba->dev_cmd.tag_wq);
  2709. }
  2710. /**
  2711. * ufshcd_disable_ee - disable exception event
  2712. * @hba: per-adapter instance
  2713. * @mask: exception event to disable
  2714. *
  2715. * Disables exception event in the device so that the EVENT_ALERT
  2716. * bit is not set.
  2717. *
  2718. * Returns zero on success, non-zero error value on failure.
  2719. */
  2720. static int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
  2721. {
  2722. int err = 0;
  2723. u32 val;
  2724. if (!(hba->ee_ctrl_mask & mask))
  2725. goto out;
  2726. val = hba->ee_ctrl_mask & ~mask;
  2727. val &= 0xFFFF; /* 2 bytes */
  2728. err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  2729. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  2730. if (!err)
  2731. hba->ee_ctrl_mask &= ~mask;
  2732. out:
  2733. return err;
  2734. }
  2735. /**
  2736. * ufshcd_enable_ee - enable exception event
  2737. * @hba: per-adapter instance
  2738. * @mask: exception event to enable
  2739. *
  2740. * Enable corresponding exception event in the device to allow
  2741. * device to alert host in critical scenarios.
  2742. *
  2743. * Returns zero on success, non-zero error value on failure.
  2744. */
  2745. static int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
  2746. {
  2747. int err = 0;
  2748. u32 val;
  2749. if (hba->ee_ctrl_mask & mask)
  2750. goto out;
  2751. val = hba->ee_ctrl_mask | mask;
  2752. val &= 0xFFFF; /* 2 bytes */
  2753. err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  2754. QUERY_ATTR_IDN_EE_CONTROL, 0, 0, &val);
  2755. if (!err)
  2756. hba->ee_ctrl_mask |= mask;
  2757. out:
  2758. return err;
  2759. }
  2760. /**
  2761. * ufshcd_enable_auto_bkops - Allow device managed BKOPS
  2762. * @hba: per-adapter instance
  2763. *
  2764. * Allow device to manage background operations on its own. Enabling
  2765. * this might lead to inconsistent latencies during normal data transfers
  2766. * as the device is allowed to manage its own way of handling background
  2767. * operations.
  2768. *
  2769. * Returns zero on success, non-zero on failure.
  2770. */
  2771. static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
  2772. {
  2773. int err = 0;
  2774. if (hba->auto_bkops_enabled)
  2775. goto out;
  2776. err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  2777. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  2778. if (err) {
  2779. dev_err(hba->dev, "%s: failed to enable bkops %d\n",
  2780. __func__, err);
  2781. goto out;
  2782. }
  2783. hba->auto_bkops_enabled = true;
  2784. /* No need of URGENT_BKOPS exception from the device */
  2785. err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  2786. if (err)
  2787. dev_err(hba->dev, "%s: failed to disable exception event %d\n",
  2788. __func__, err);
  2789. out:
  2790. return err;
  2791. }
  2792. /**
  2793. * ufshcd_disable_auto_bkops - block device in doing background operations
  2794. * @hba: per-adapter instance
  2795. *
  2796. * Disabling background operations improves command response latency but
  2797. * has drawback of device moving into critical state where the device is
  2798. * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
  2799. * host is idle so that BKOPS are managed effectively without any negative
  2800. * impacts.
  2801. *
  2802. * Returns zero on success, non-zero on failure.
  2803. */
  2804. static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
  2805. {
  2806. int err = 0;
  2807. if (!hba->auto_bkops_enabled)
  2808. goto out;
  2809. /*
  2810. * If host assisted BKOPs is to be enabled, make sure
  2811. * urgent bkops exception is allowed.
  2812. */
  2813. err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
  2814. if (err) {
  2815. dev_err(hba->dev, "%s: failed to enable exception event %d\n",
  2816. __func__, err);
  2817. goto out;
  2818. }
  2819. err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
  2820. QUERY_FLAG_IDN_BKOPS_EN, NULL);
  2821. if (err) {
  2822. dev_err(hba->dev, "%s: failed to disable bkops %d\n",
  2823. __func__, err);
  2824. ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
  2825. goto out;
  2826. }
  2827. hba->auto_bkops_enabled = false;
  2828. out:
  2829. return err;
  2830. }
  2831. /**
  2832. * ufshcd_force_reset_auto_bkops - force enable of auto bkops
  2833. * @hba: per adapter instance
  2834. *
  2835. * After a device reset the device may toggle the BKOPS_EN flag
  2836. * to default value. The s/w tracking variables should be updated
  2837. * as well. Do this by forcing enable of auto bkops.
  2838. */
  2839. static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
  2840. {
  2841. hba->auto_bkops_enabled = false;
  2842. hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
  2843. ufshcd_enable_auto_bkops(hba);
  2844. }
  2845. static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
  2846. {
  2847. return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  2848. QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
  2849. }
  2850. /**
  2851. * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
  2852. * @hba: per-adapter instance
  2853. * @status: bkops_status value
  2854. *
  2855. * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
  2856. * flag in the device to permit background operations if the device
  2857. * bkops_status is greater than or equal to "status" argument passed to
  2858. * this function, disable otherwise.
  2859. *
  2860. * Returns 0 for success, non-zero in case of failure.
  2861. *
  2862. * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
  2863. * to know whether auto bkops is enabled or disabled after this function
  2864. * returns control to it.
  2865. */
  2866. static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
  2867. enum bkops_status status)
  2868. {
  2869. int err;
  2870. u32 curr_status = 0;
  2871. err = ufshcd_get_bkops_status(hba, &curr_status);
  2872. if (err) {
  2873. dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
  2874. __func__, err);
  2875. goto out;
  2876. } else if (curr_status > BKOPS_STATUS_MAX) {
  2877. dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
  2878. __func__, curr_status);
  2879. err = -EINVAL;
  2880. goto out;
  2881. }
  2882. if (curr_status >= status)
  2883. err = ufshcd_enable_auto_bkops(hba);
  2884. else
  2885. err = ufshcd_disable_auto_bkops(hba);
  2886. out:
  2887. return err;
  2888. }
  2889. /**
  2890. * ufshcd_urgent_bkops - handle urgent bkops exception event
  2891. * @hba: per-adapter instance
  2892. *
  2893. * Enable fBackgroundOpsEn flag in the device to permit background
  2894. * operations.
  2895. *
  2896. * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
  2897. * and negative error value for any other failure.
  2898. */
  2899. static int ufshcd_urgent_bkops(struct ufs_hba *hba)
  2900. {
  2901. return ufshcd_bkops_ctrl(hba, BKOPS_STATUS_PERF_IMPACT);
  2902. }
  2903. static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
  2904. {
  2905. return ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_READ_ATTR,
  2906. QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
  2907. }
  2908. /**
  2909. * ufshcd_exception_event_handler - handle exceptions raised by device
  2910. * @work: pointer to work data
  2911. *
  2912. * Read bExceptionEventStatus attribute from the device and handle the
  2913. * exception event accordingly.
  2914. */
  2915. static void ufshcd_exception_event_handler(struct work_struct *work)
  2916. {
  2917. struct ufs_hba *hba;
  2918. int err;
  2919. u32 status = 0;
  2920. hba = container_of(work, struct ufs_hba, eeh_work);
  2921. pm_runtime_get_sync(hba->dev);
  2922. err = ufshcd_get_ee_status(hba, &status);
  2923. if (err) {
  2924. dev_err(hba->dev, "%s: failed to get exception status %d\n",
  2925. __func__, err);
  2926. goto out;
  2927. }
  2928. status &= hba->ee_ctrl_mask;
  2929. if (status & MASK_EE_URGENT_BKOPS) {
  2930. err = ufshcd_urgent_bkops(hba);
  2931. if (err < 0)
  2932. dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
  2933. __func__, err);
  2934. }
  2935. out:
  2936. pm_runtime_put_sync(hba->dev);
  2937. return;
  2938. }
  2939. /**
  2940. * ufshcd_err_handler - handle UFS errors that require s/w attention
  2941. * @work: pointer to work structure
  2942. */
  2943. static void ufshcd_err_handler(struct work_struct *work)
  2944. {
  2945. struct ufs_hba *hba;
  2946. unsigned long flags;
  2947. u32 err_xfer = 0;
  2948. u32 err_tm = 0;
  2949. int err = 0;
  2950. int tag;
  2951. hba = container_of(work, struct ufs_hba, eh_work);
  2952. pm_runtime_get_sync(hba->dev);
  2953. ufshcd_hold(hba, false);
  2954. spin_lock_irqsave(hba->host->host_lock, flags);
  2955. if (hba->ufshcd_state == UFSHCD_STATE_RESET) {
  2956. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2957. goto out;
  2958. }
  2959. hba->ufshcd_state = UFSHCD_STATE_RESET;
  2960. ufshcd_set_eh_in_progress(hba);
  2961. /* Complete requests that have door-bell cleared by h/w */
  2962. ufshcd_transfer_req_compl(hba);
  2963. ufshcd_tmc_handler(hba);
  2964. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2965. /* Clear pending transfer requests */
  2966. for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs)
  2967. if (ufshcd_clear_cmd(hba, tag))
  2968. err_xfer |= 1 << tag;
  2969. /* Clear pending task management requests */
  2970. for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs)
  2971. if (ufshcd_clear_tm_cmd(hba, tag))
  2972. err_tm |= 1 << tag;
  2973. /* Complete the requests that are cleared by s/w */
  2974. spin_lock_irqsave(hba->host->host_lock, flags);
  2975. ufshcd_transfer_req_compl(hba);
  2976. ufshcd_tmc_handler(hba);
  2977. spin_unlock_irqrestore(hba->host->host_lock, flags);
  2978. /* Fatal errors need reset */
  2979. if (err_xfer || err_tm || (hba->saved_err & INT_FATAL_ERRORS) ||
  2980. ((hba->saved_err & UIC_ERROR) &&
  2981. (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR))) {
  2982. err = ufshcd_reset_and_restore(hba);
  2983. if (err) {
  2984. dev_err(hba->dev, "%s: reset and restore failed\n",
  2985. __func__);
  2986. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  2987. }
  2988. /*
  2989. * Inform scsi mid-layer that we did reset and allow to handle
  2990. * Unit Attention properly.
  2991. */
  2992. scsi_report_bus_reset(hba->host, 0);
  2993. hba->saved_err = 0;
  2994. hba->saved_uic_err = 0;
  2995. }
  2996. ufshcd_clear_eh_in_progress(hba);
  2997. out:
  2998. scsi_unblock_requests(hba->host);
  2999. ufshcd_release(hba);
  3000. pm_runtime_put_sync(hba->dev);
  3001. }
  3002. /**
  3003. * ufshcd_update_uic_error - check and set fatal UIC error flags.
  3004. * @hba: per-adapter instance
  3005. */
  3006. static void ufshcd_update_uic_error(struct ufs_hba *hba)
  3007. {
  3008. u32 reg;
  3009. /* PA_INIT_ERROR is fatal and needs UIC reset */
  3010. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
  3011. if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
  3012. hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
  3013. /* UIC NL/TL/DME errors needs software retry */
  3014. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
  3015. if (reg)
  3016. hba->uic_error |= UFSHCD_UIC_NL_ERROR;
  3017. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
  3018. if (reg)
  3019. hba->uic_error |= UFSHCD_UIC_TL_ERROR;
  3020. reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
  3021. if (reg)
  3022. hba->uic_error |= UFSHCD_UIC_DME_ERROR;
  3023. dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
  3024. __func__, hba->uic_error);
  3025. }
  3026. /**
  3027. * ufshcd_check_errors - Check for errors that need s/w attention
  3028. * @hba: per-adapter instance
  3029. */
  3030. static void ufshcd_check_errors(struct ufs_hba *hba)
  3031. {
  3032. bool queue_eh_work = false;
  3033. if (hba->errors & INT_FATAL_ERRORS)
  3034. queue_eh_work = true;
  3035. if (hba->errors & UIC_ERROR) {
  3036. hba->uic_error = 0;
  3037. ufshcd_update_uic_error(hba);
  3038. if (hba->uic_error)
  3039. queue_eh_work = true;
  3040. }
  3041. if (queue_eh_work) {
  3042. /* handle fatal errors only when link is functional */
  3043. if (hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL) {
  3044. /* block commands from scsi mid-layer */
  3045. scsi_block_requests(hba->host);
  3046. /* transfer error masks to sticky bits */
  3047. hba->saved_err |= hba->errors;
  3048. hba->saved_uic_err |= hba->uic_error;
  3049. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  3050. schedule_work(&hba->eh_work);
  3051. }
  3052. }
  3053. /*
  3054. * if (!queue_eh_work) -
  3055. * Other errors are either non-fatal where host recovers
  3056. * itself without s/w intervention or errors that will be
  3057. * handled by the SCSI core layer.
  3058. */
  3059. }
  3060. /**
  3061. * ufshcd_tmc_handler - handle task management function completion
  3062. * @hba: per adapter instance
  3063. */
  3064. static void ufshcd_tmc_handler(struct ufs_hba *hba)
  3065. {
  3066. u32 tm_doorbell;
  3067. tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
  3068. hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
  3069. wake_up(&hba->tm_wq);
  3070. }
  3071. /**
  3072. * ufshcd_sl_intr - Interrupt service routine
  3073. * @hba: per adapter instance
  3074. * @intr_status: contains interrupts generated by the controller
  3075. */
  3076. static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
  3077. {
  3078. hba->errors = UFSHCD_ERROR_MASK & intr_status;
  3079. if (hba->errors)
  3080. ufshcd_check_errors(hba);
  3081. if (intr_status & UFSHCD_UIC_MASK)
  3082. ufshcd_uic_cmd_compl(hba, intr_status);
  3083. if (intr_status & UTP_TASK_REQ_COMPL)
  3084. ufshcd_tmc_handler(hba);
  3085. if (intr_status & UTP_TRANSFER_REQ_COMPL)
  3086. ufshcd_transfer_req_compl(hba);
  3087. }
  3088. /**
  3089. * ufshcd_intr - Main interrupt service routine
  3090. * @irq: irq number
  3091. * @__hba: pointer to adapter instance
  3092. *
  3093. * Returns IRQ_HANDLED - If interrupt is valid
  3094. * IRQ_NONE - If invalid interrupt
  3095. */
  3096. static irqreturn_t ufshcd_intr(int irq, void *__hba)
  3097. {
  3098. u32 intr_status;
  3099. irqreturn_t retval = IRQ_NONE;
  3100. struct ufs_hba *hba = __hba;
  3101. spin_lock(hba->host->host_lock);
  3102. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  3103. if (intr_status) {
  3104. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  3105. ufshcd_sl_intr(hba, intr_status);
  3106. retval = IRQ_HANDLED;
  3107. }
  3108. spin_unlock(hba->host->host_lock);
  3109. return retval;
  3110. }
  3111. static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
  3112. {
  3113. int err = 0;
  3114. u32 mask = 1 << tag;
  3115. unsigned long flags;
  3116. if (!test_bit(tag, &hba->outstanding_tasks))
  3117. goto out;
  3118. spin_lock_irqsave(hba->host->host_lock, flags);
  3119. ufshcd_writel(hba, ~(1 << tag), REG_UTP_TASK_REQ_LIST_CLEAR);
  3120. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3121. /* poll for max. 1 sec to clear door bell register by h/w */
  3122. err = ufshcd_wait_for_register(hba,
  3123. REG_UTP_TASK_REQ_DOOR_BELL,
  3124. mask, 0, 1000, 1000);
  3125. out:
  3126. return err;
  3127. }
  3128. /**
  3129. * ufshcd_issue_tm_cmd - issues task management commands to controller
  3130. * @hba: per adapter instance
  3131. * @lun_id: LUN ID to which TM command is sent
  3132. * @task_id: task ID to which the TM command is applicable
  3133. * @tm_function: task management function opcode
  3134. * @tm_response: task management service response return value
  3135. *
  3136. * Returns non-zero value on error, zero on success.
  3137. */
  3138. static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
  3139. u8 tm_function, u8 *tm_response)
  3140. {
  3141. struct utp_task_req_desc *task_req_descp;
  3142. struct utp_upiu_task_req *task_req_upiup;
  3143. struct Scsi_Host *host;
  3144. unsigned long flags;
  3145. int free_slot;
  3146. int err;
  3147. int task_tag;
  3148. host = hba->host;
  3149. /*
  3150. * Get free slot, sleep if slots are unavailable.
  3151. * Even though we use wait_event() which sleeps indefinitely,
  3152. * the maximum wait time is bounded by %TM_CMD_TIMEOUT.
  3153. */
  3154. wait_event(hba->tm_tag_wq, ufshcd_get_tm_free_slot(hba, &free_slot));
  3155. ufshcd_hold(hba, false);
  3156. spin_lock_irqsave(host->host_lock, flags);
  3157. task_req_descp = hba->utmrdl_base_addr;
  3158. task_req_descp += free_slot;
  3159. /* Configure task request descriptor */
  3160. task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
  3161. task_req_descp->header.dword_2 =
  3162. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  3163. /* Configure task request UPIU */
  3164. task_req_upiup =
  3165. (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
  3166. task_tag = hba->nutrs + free_slot;
  3167. task_req_upiup->header.dword_0 =
  3168. UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
  3169. lun_id, task_tag);
  3170. task_req_upiup->header.dword_1 =
  3171. UPIU_HEADER_DWORD(0, tm_function, 0, 0);
  3172. /*
  3173. * The host shall provide the same value for LUN field in the basic
  3174. * header and for Input Parameter.
  3175. */
  3176. task_req_upiup->input_param1 = cpu_to_be32(lun_id);
  3177. task_req_upiup->input_param2 = cpu_to_be32(task_id);
  3178. /* send command to the controller */
  3179. __set_bit(free_slot, &hba->outstanding_tasks);
  3180. ufshcd_writel(hba, 1 << free_slot, REG_UTP_TASK_REQ_DOOR_BELL);
  3181. spin_unlock_irqrestore(host->host_lock, flags);
  3182. /* wait until the task management command is completed */
  3183. err = wait_event_timeout(hba->tm_wq,
  3184. test_bit(free_slot, &hba->tm_condition),
  3185. msecs_to_jiffies(TM_CMD_TIMEOUT));
  3186. if (!err) {
  3187. dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
  3188. __func__, tm_function);
  3189. if (ufshcd_clear_tm_cmd(hba, free_slot))
  3190. dev_WARN(hba->dev, "%s: unable clear tm cmd (slot %d) after timeout\n",
  3191. __func__, free_slot);
  3192. err = -ETIMEDOUT;
  3193. } else {
  3194. err = ufshcd_task_req_compl(hba, free_slot, tm_response);
  3195. }
  3196. clear_bit(free_slot, &hba->tm_condition);
  3197. ufshcd_put_tm_slot(hba, free_slot);
  3198. wake_up(&hba->tm_tag_wq);
  3199. ufshcd_release(hba);
  3200. return err;
  3201. }
  3202. /**
  3203. * ufshcd_eh_device_reset_handler - device reset handler registered to
  3204. * scsi layer.
  3205. * @cmd: SCSI command pointer
  3206. *
  3207. * Returns SUCCESS/FAILED
  3208. */
  3209. static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
  3210. {
  3211. struct Scsi_Host *host;
  3212. struct ufs_hba *hba;
  3213. unsigned int tag;
  3214. u32 pos;
  3215. int err;
  3216. u8 resp = 0xF;
  3217. struct ufshcd_lrb *lrbp;
  3218. unsigned long flags;
  3219. host = cmd->device->host;
  3220. hba = shost_priv(host);
  3221. tag = cmd->request->tag;
  3222. lrbp = &hba->lrb[tag];
  3223. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, 0, UFS_LOGICAL_RESET, &resp);
  3224. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3225. if (!err)
  3226. err = resp;
  3227. goto out;
  3228. }
  3229. /* clear the commands that were pending for corresponding LUN */
  3230. for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) {
  3231. if (hba->lrb[pos].lun == lrbp->lun) {
  3232. err = ufshcd_clear_cmd(hba, pos);
  3233. if (err)
  3234. break;
  3235. }
  3236. }
  3237. spin_lock_irqsave(host->host_lock, flags);
  3238. ufshcd_transfer_req_compl(hba);
  3239. spin_unlock_irqrestore(host->host_lock, flags);
  3240. out:
  3241. if (!err) {
  3242. err = SUCCESS;
  3243. } else {
  3244. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  3245. err = FAILED;
  3246. }
  3247. return err;
  3248. }
  3249. /**
  3250. * ufshcd_abort - abort a specific command
  3251. * @cmd: SCSI command pointer
  3252. *
  3253. * Abort the pending command in device by sending UFS_ABORT_TASK task management
  3254. * command, and in host controller by clearing the door-bell register. There can
  3255. * be race between controller sending the command to the device while abort is
  3256. * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
  3257. * really issued and then try to abort it.
  3258. *
  3259. * Returns SUCCESS/FAILED
  3260. */
  3261. static int ufshcd_abort(struct scsi_cmnd *cmd)
  3262. {
  3263. struct Scsi_Host *host;
  3264. struct ufs_hba *hba;
  3265. unsigned long flags;
  3266. unsigned int tag;
  3267. int err = 0;
  3268. int poll_cnt;
  3269. u8 resp = 0xF;
  3270. struct ufshcd_lrb *lrbp;
  3271. u32 reg;
  3272. host = cmd->device->host;
  3273. hba = shost_priv(host);
  3274. tag = cmd->request->tag;
  3275. ufshcd_hold(hba, false);
  3276. /* If command is already aborted/completed, return SUCCESS */
  3277. if (!(test_bit(tag, &hba->outstanding_reqs)))
  3278. goto out;
  3279. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  3280. if (!(reg & (1 << tag))) {
  3281. dev_err(hba->dev,
  3282. "%s: cmd was completed, but without a notifying intr, tag = %d",
  3283. __func__, tag);
  3284. }
  3285. lrbp = &hba->lrb[tag];
  3286. for (poll_cnt = 100; poll_cnt; poll_cnt--) {
  3287. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  3288. UFS_QUERY_TASK, &resp);
  3289. if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
  3290. /* cmd pending in the device */
  3291. break;
  3292. } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3293. /*
  3294. * cmd not pending in the device, check if it is
  3295. * in transition.
  3296. */
  3297. reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  3298. if (reg & (1 << tag)) {
  3299. /* sleep for max. 200us to stabilize */
  3300. usleep_range(100, 200);
  3301. continue;
  3302. }
  3303. /* command completed already */
  3304. goto out;
  3305. } else {
  3306. if (!err)
  3307. err = resp; /* service response error */
  3308. goto out;
  3309. }
  3310. }
  3311. if (!poll_cnt) {
  3312. err = -EBUSY;
  3313. goto out;
  3314. }
  3315. err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
  3316. UFS_ABORT_TASK, &resp);
  3317. if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
  3318. if (!err)
  3319. err = resp; /* service response error */
  3320. goto out;
  3321. }
  3322. err = ufshcd_clear_cmd(hba, tag);
  3323. if (err)
  3324. goto out;
  3325. scsi_dma_unmap(cmd);
  3326. spin_lock_irqsave(host->host_lock, flags);
  3327. __clear_bit(tag, &hba->outstanding_reqs);
  3328. hba->lrb[tag].cmd = NULL;
  3329. spin_unlock_irqrestore(host->host_lock, flags);
  3330. clear_bit_unlock(tag, &hba->lrb_in_use);
  3331. wake_up(&hba->dev_cmd.tag_wq);
  3332. out:
  3333. if (!err) {
  3334. err = SUCCESS;
  3335. } else {
  3336. dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
  3337. err = FAILED;
  3338. }
  3339. /*
  3340. * This ufshcd_release() corresponds to the original scsi cmd that got
  3341. * aborted here (as we won't get any IRQ for it).
  3342. */
  3343. ufshcd_release(hba);
  3344. return err;
  3345. }
  3346. /**
  3347. * ufshcd_host_reset_and_restore - reset and restore host controller
  3348. * @hba: per-adapter instance
  3349. *
  3350. * Note that host controller reset may issue DME_RESET to
  3351. * local and remote (device) Uni-Pro stack and the attributes
  3352. * are reset to default state.
  3353. *
  3354. * Returns zero on success, non-zero on failure
  3355. */
  3356. static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
  3357. {
  3358. int err;
  3359. unsigned long flags;
  3360. /* Reset the host controller */
  3361. spin_lock_irqsave(hba->host->host_lock, flags);
  3362. ufshcd_hba_stop(hba);
  3363. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3364. err = ufshcd_hba_enable(hba);
  3365. if (err)
  3366. goto out;
  3367. /* Establish the link again and restore the device */
  3368. err = ufshcd_probe_hba(hba);
  3369. if (!err && (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL))
  3370. err = -EIO;
  3371. out:
  3372. if (err)
  3373. dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
  3374. return err;
  3375. }
  3376. /**
  3377. * ufshcd_reset_and_restore - reset and re-initialize host/device
  3378. * @hba: per-adapter instance
  3379. *
  3380. * Reset and recover device, host and re-establish link. This
  3381. * is helpful to recover the communication in fatal error conditions.
  3382. *
  3383. * Returns zero on success, non-zero on failure
  3384. */
  3385. static int ufshcd_reset_and_restore(struct ufs_hba *hba)
  3386. {
  3387. int err = 0;
  3388. unsigned long flags;
  3389. int retries = MAX_HOST_RESET_RETRIES;
  3390. do {
  3391. err = ufshcd_host_reset_and_restore(hba);
  3392. } while (err && --retries);
  3393. /*
  3394. * After reset the door-bell might be cleared, complete
  3395. * outstanding requests in s/w here.
  3396. */
  3397. spin_lock_irqsave(hba->host->host_lock, flags);
  3398. ufshcd_transfer_req_compl(hba);
  3399. ufshcd_tmc_handler(hba);
  3400. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3401. return err;
  3402. }
  3403. /**
  3404. * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
  3405. * @cmd - SCSI command pointer
  3406. *
  3407. * Returns SUCCESS/FAILED
  3408. */
  3409. static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
  3410. {
  3411. int err;
  3412. unsigned long flags;
  3413. struct ufs_hba *hba;
  3414. hba = shost_priv(cmd->device->host);
  3415. ufshcd_hold(hba, false);
  3416. /*
  3417. * Check if there is any race with fatal error handling.
  3418. * If so, wait for it to complete. Even though fatal error
  3419. * handling does reset and restore in some cases, don't assume
  3420. * anything out of it. We are just avoiding race here.
  3421. */
  3422. do {
  3423. spin_lock_irqsave(hba->host->host_lock, flags);
  3424. if (!(work_pending(&hba->eh_work) ||
  3425. hba->ufshcd_state == UFSHCD_STATE_RESET))
  3426. break;
  3427. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3428. dev_dbg(hba->dev, "%s: reset in progress\n", __func__);
  3429. flush_work(&hba->eh_work);
  3430. } while (1);
  3431. hba->ufshcd_state = UFSHCD_STATE_RESET;
  3432. ufshcd_set_eh_in_progress(hba);
  3433. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3434. err = ufshcd_reset_and_restore(hba);
  3435. spin_lock_irqsave(hba->host->host_lock, flags);
  3436. if (!err) {
  3437. err = SUCCESS;
  3438. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  3439. } else {
  3440. err = FAILED;
  3441. hba->ufshcd_state = UFSHCD_STATE_ERROR;
  3442. }
  3443. ufshcd_clear_eh_in_progress(hba);
  3444. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3445. ufshcd_release(hba);
  3446. return err;
  3447. }
  3448. /**
  3449. * ufshcd_get_max_icc_level - calculate the ICC level
  3450. * @sup_curr_uA: max. current supported by the regulator
  3451. * @start_scan: row at the desc table to start scan from
  3452. * @buff: power descriptor buffer
  3453. *
  3454. * Returns calculated max ICC level for specific regulator
  3455. */
  3456. static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
  3457. {
  3458. int i;
  3459. int curr_uA;
  3460. u16 data;
  3461. u16 unit;
  3462. for (i = start_scan; i >= 0; i--) {
  3463. data = be16_to_cpu(*((u16 *)(buff + 2*i)));
  3464. unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
  3465. ATTR_ICC_LVL_UNIT_OFFSET;
  3466. curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
  3467. switch (unit) {
  3468. case UFSHCD_NANO_AMP:
  3469. curr_uA = curr_uA / 1000;
  3470. break;
  3471. case UFSHCD_MILI_AMP:
  3472. curr_uA = curr_uA * 1000;
  3473. break;
  3474. case UFSHCD_AMP:
  3475. curr_uA = curr_uA * 1000 * 1000;
  3476. break;
  3477. case UFSHCD_MICRO_AMP:
  3478. default:
  3479. break;
  3480. }
  3481. if (sup_curr_uA >= curr_uA)
  3482. break;
  3483. }
  3484. if (i < 0) {
  3485. i = 0;
  3486. pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
  3487. }
  3488. return (u32)i;
  3489. }
  3490. /**
  3491. * ufshcd_calc_icc_level - calculate the max ICC level
  3492. * In case regulators are not initialized we'll return 0
  3493. * @hba: per-adapter instance
  3494. * @desc_buf: power descriptor buffer to extract ICC levels from.
  3495. * @len: length of desc_buff
  3496. *
  3497. * Returns calculated ICC level
  3498. */
  3499. static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
  3500. u8 *desc_buf, int len)
  3501. {
  3502. u32 icc_level = 0;
  3503. if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
  3504. !hba->vreg_info.vccq2) {
  3505. dev_err(hba->dev,
  3506. "%s: Regulator capability was not set, actvIccLevel=%d",
  3507. __func__, icc_level);
  3508. goto out;
  3509. }
  3510. if (hba->vreg_info.vcc)
  3511. icc_level = ufshcd_get_max_icc_level(
  3512. hba->vreg_info.vcc->max_uA,
  3513. POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
  3514. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
  3515. if (hba->vreg_info.vccq)
  3516. icc_level = ufshcd_get_max_icc_level(
  3517. hba->vreg_info.vccq->max_uA,
  3518. icc_level,
  3519. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
  3520. if (hba->vreg_info.vccq2)
  3521. icc_level = ufshcd_get_max_icc_level(
  3522. hba->vreg_info.vccq2->max_uA,
  3523. icc_level,
  3524. &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
  3525. out:
  3526. return icc_level;
  3527. }
  3528. static void ufshcd_init_icc_levels(struct ufs_hba *hba)
  3529. {
  3530. int ret;
  3531. int buff_len = QUERY_DESC_POWER_MAX_SIZE;
  3532. u8 desc_buf[QUERY_DESC_POWER_MAX_SIZE];
  3533. ret = ufshcd_read_power_desc(hba, desc_buf, buff_len);
  3534. if (ret) {
  3535. dev_err(hba->dev,
  3536. "%s: Failed reading power descriptor.len = %d ret = %d",
  3537. __func__, buff_len, ret);
  3538. return;
  3539. }
  3540. hba->init_prefetch_data.icc_level =
  3541. ufshcd_find_max_sup_active_icc_level(hba,
  3542. desc_buf, buff_len);
  3543. dev_dbg(hba->dev, "%s: setting icc_level 0x%x",
  3544. __func__, hba->init_prefetch_data.icc_level);
  3545. ret = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
  3546. QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0,
  3547. &hba->init_prefetch_data.icc_level);
  3548. if (ret)
  3549. dev_err(hba->dev,
  3550. "%s: Failed configuring bActiveICCLevel = %d ret = %d",
  3551. __func__, hba->init_prefetch_data.icc_level , ret);
  3552. }
  3553. /**
  3554. * ufshcd_scsi_add_wlus - Adds required W-LUs
  3555. * @hba: per-adapter instance
  3556. *
  3557. * UFS device specification requires the UFS devices to support 4 well known
  3558. * logical units:
  3559. * "REPORT_LUNS" (address: 01h)
  3560. * "UFS Device" (address: 50h)
  3561. * "RPMB" (address: 44h)
  3562. * "BOOT" (address: 30h)
  3563. * UFS device's power management needs to be controlled by "POWER CONDITION"
  3564. * field of SSU (START STOP UNIT) command. But this "power condition" field
  3565. * will take effect only when its sent to "UFS device" well known logical unit
  3566. * hence we require the scsi_device instance to represent this logical unit in
  3567. * order for the UFS host driver to send the SSU command for power management.
  3568. * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
  3569. * Block) LU so user space process can control this LU. User space may also
  3570. * want to have access to BOOT LU.
  3571. * This function adds scsi device instances for each of all well known LUs
  3572. * (except "REPORT LUNS" LU).
  3573. *
  3574. * Returns zero on success (all required W-LUs are added successfully),
  3575. * non-zero error value on failure (if failed to add any of the required W-LU).
  3576. */
  3577. static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
  3578. {
  3579. int ret = 0;
  3580. struct scsi_device *sdev_rpmb;
  3581. struct scsi_device *sdev_boot;
  3582. hba->sdev_ufs_device = __scsi_add_device(hba->host, 0, 0,
  3583. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
  3584. if (IS_ERR(hba->sdev_ufs_device)) {
  3585. ret = PTR_ERR(hba->sdev_ufs_device);
  3586. hba->sdev_ufs_device = NULL;
  3587. goto out;
  3588. }
  3589. scsi_device_put(hba->sdev_ufs_device);
  3590. sdev_boot = __scsi_add_device(hba->host, 0, 0,
  3591. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
  3592. if (IS_ERR(sdev_boot)) {
  3593. ret = PTR_ERR(sdev_boot);
  3594. goto remove_sdev_ufs_device;
  3595. }
  3596. scsi_device_put(sdev_boot);
  3597. sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
  3598. ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
  3599. if (IS_ERR(sdev_rpmb)) {
  3600. ret = PTR_ERR(sdev_rpmb);
  3601. goto remove_sdev_boot;
  3602. }
  3603. scsi_device_put(sdev_rpmb);
  3604. goto out;
  3605. remove_sdev_boot:
  3606. scsi_remove_device(sdev_boot);
  3607. remove_sdev_ufs_device:
  3608. scsi_remove_device(hba->sdev_ufs_device);
  3609. out:
  3610. return ret;
  3611. }
  3612. /**
  3613. * ufshcd_probe_hba - probe hba to detect device and initialize
  3614. * @hba: per-adapter instance
  3615. *
  3616. * Execute link-startup and verify device initialization
  3617. */
  3618. static int ufshcd_probe_hba(struct ufs_hba *hba)
  3619. {
  3620. int ret;
  3621. ret = ufshcd_link_startup(hba);
  3622. if (ret)
  3623. goto out;
  3624. ufshcd_init_pwr_info(hba);
  3625. /* UniPro link is active now */
  3626. ufshcd_set_link_active(hba);
  3627. ret = ufshcd_verify_dev_init(hba);
  3628. if (ret)
  3629. goto out;
  3630. ret = ufshcd_complete_dev_init(hba);
  3631. if (ret)
  3632. goto out;
  3633. /* UFS device is also active now */
  3634. ufshcd_set_ufs_dev_active(hba);
  3635. ufshcd_force_reset_auto_bkops(hba);
  3636. hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
  3637. hba->wlun_dev_clr_ua = true;
  3638. if (ufshcd_get_max_pwr_mode(hba)) {
  3639. dev_err(hba->dev,
  3640. "%s: Failed getting max supported power mode\n",
  3641. __func__);
  3642. } else {
  3643. ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
  3644. if (ret)
  3645. dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
  3646. __func__, ret);
  3647. }
  3648. /*
  3649. * If we are in error handling context or in power management callbacks
  3650. * context, no need to scan the host
  3651. */
  3652. if (!ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  3653. bool flag;
  3654. /* clear any previous UFS device information */
  3655. memset(&hba->dev_info, 0, sizeof(hba->dev_info));
  3656. if (!ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  3657. QUERY_FLAG_IDN_PWR_ON_WPE, &flag))
  3658. hba->dev_info.f_power_on_wp_en = flag;
  3659. if (!hba->is_init_prefetch)
  3660. ufshcd_init_icc_levels(hba);
  3661. /* Add required well known logical units to scsi mid layer */
  3662. if (ufshcd_scsi_add_wlus(hba))
  3663. goto out;
  3664. scsi_scan_host(hba->host);
  3665. pm_runtime_put_sync(hba->dev);
  3666. }
  3667. if (!hba->is_init_prefetch)
  3668. hba->is_init_prefetch = true;
  3669. /* Resume devfreq after UFS device is detected */
  3670. if (ufshcd_is_clkscaling_enabled(hba))
  3671. devfreq_resume_device(hba->devfreq);
  3672. out:
  3673. /*
  3674. * If we failed to initialize the device or the device is not
  3675. * present, turn off the power/clocks etc.
  3676. */
  3677. if (ret && !ufshcd_eh_in_progress(hba) && !hba->pm_op_in_progress) {
  3678. pm_runtime_put_sync(hba->dev);
  3679. ufshcd_hba_exit(hba);
  3680. }
  3681. return ret;
  3682. }
  3683. /**
  3684. * ufshcd_async_scan - asynchronous execution for probing hba
  3685. * @data: data pointer to pass to this function
  3686. * @cookie: cookie data
  3687. */
  3688. static void ufshcd_async_scan(void *data, async_cookie_t cookie)
  3689. {
  3690. struct ufs_hba *hba = (struct ufs_hba *)data;
  3691. ufshcd_probe_hba(hba);
  3692. }
  3693. static struct scsi_host_template ufshcd_driver_template = {
  3694. .module = THIS_MODULE,
  3695. .name = UFSHCD,
  3696. .proc_name = UFSHCD,
  3697. .queuecommand = ufshcd_queuecommand,
  3698. .slave_alloc = ufshcd_slave_alloc,
  3699. .slave_configure = ufshcd_slave_configure,
  3700. .slave_destroy = ufshcd_slave_destroy,
  3701. .change_queue_depth = ufshcd_change_queue_depth,
  3702. .eh_abort_handler = ufshcd_abort,
  3703. .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
  3704. .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
  3705. .this_id = -1,
  3706. .sg_tablesize = SG_ALL,
  3707. .cmd_per_lun = UFSHCD_CMD_PER_LUN,
  3708. .can_queue = UFSHCD_CAN_QUEUE,
  3709. .max_host_blocked = 1,
  3710. };
  3711. static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
  3712. int ua)
  3713. {
  3714. int ret = 0;
  3715. struct regulator *reg = vreg->reg;
  3716. const char *name = vreg->name;
  3717. BUG_ON(!vreg);
  3718. ret = regulator_set_optimum_mode(reg, ua);
  3719. if (ret >= 0) {
  3720. /*
  3721. * regulator_set_optimum_mode() returns new regulator
  3722. * mode upon success.
  3723. */
  3724. ret = 0;
  3725. } else {
  3726. dev_err(dev, "%s: %s set optimum mode(ua=%d) failed, err=%d\n",
  3727. __func__, name, ua, ret);
  3728. }
  3729. return ret;
  3730. }
  3731. static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
  3732. struct ufs_vreg *vreg)
  3733. {
  3734. if (!vreg)
  3735. return 0;
  3736. return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
  3737. }
  3738. static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
  3739. struct ufs_vreg *vreg)
  3740. {
  3741. if (!vreg)
  3742. return 0;
  3743. return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
  3744. }
  3745. static int ufshcd_config_vreg(struct device *dev,
  3746. struct ufs_vreg *vreg, bool on)
  3747. {
  3748. int ret = 0;
  3749. struct regulator *reg = vreg->reg;
  3750. const char *name = vreg->name;
  3751. int min_uV, uA_load;
  3752. BUG_ON(!vreg);
  3753. if (regulator_count_voltages(reg) > 0) {
  3754. min_uV = on ? vreg->min_uV : 0;
  3755. ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
  3756. if (ret) {
  3757. dev_err(dev, "%s: %s set voltage failed, err=%d\n",
  3758. __func__, name, ret);
  3759. goto out;
  3760. }
  3761. uA_load = on ? vreg->max_uA : 0;
  3762. ret = ufshcd_config_vreg_load(dev, vreg, uA_load);
  3763. if (ret)
  3764. goto out;
  3765. }
  3766. out:
  3767. return ret;
  3768. }
  3769. static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
  3770. {
  3771. int ret = 0;
  3772. if (!vreg || vreg->enabled)
  3773. goto out;
  3774. ret = ufshcd_config_vreg(dev, vreg, true);
  3775. if (!ret)
  3776. ret = regulator_enable(vreg->reg);
  3777. if (!ret)
  3778. vreg->enabled = true;
  3779. else
  3780. dev_err(dev, "%s: %s enable failed, err=%d\n",
  3781. __func__, vreg->name, ret);
  3782. out:
  3783. return ret;
  3784. }
  3785. static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
  3786. {
  3787. int ret = 0;
  3788. if (!vreg || !vreg->enabled)
  3789. goto out;
  3790. ret = regulator_disable(vreg->reg);
  3791. if (!ret) {
  3792. /* ignore errors on applying disable config */
  3793. ufshcd_config_vreg(dev, vreg, false);
  3794. vreg->enabled = false;
  3795. } else {
  3796. dev_err(dev, "%s: %s disable failed, err=%d\n",
  3797. __func__, vreg->name, ret);
  3798. }
  3799. out:
  3800. return ret;
  3801. }
  3802. static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
  3803. {
  3804. int ret = 0;
  3805. struct device *dev = hba->dev;
  3806. struct ufs_vreg_info *info = &hba->vreg_info;
  3807. if (!info)
  3808. goto out;
  3809. ret = ufshcd_toggle_vreg(dev, info->vcc, on);
  3810. if (ret)
  3811. goto out;
  3812. ret = ufshcd_toggle_vreg(dev, info->vccq, on);
  3813. if (ret)
  3814. goto out;
  3815. ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
  3816. if (ret)
  3817. goto out;
  3818. out:
  3819. if (ret) {
  3820. ufshcd_toggle_vreg(dev, info->vccq2, false);
  3821. ufshcd_toggle_vreg(dev, info->vccq, false);
  3822. ufshcd_toggle_vreg(dev, info->vcc, false);
  3823. }
  3824. return ret;
  3825. }
  3826. static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
  3827. {
  3828. struct ufs_vreg_info *info = &hba->vreg_info;
  3829. if (info)
  3830. return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
  3831. return 0;
  3832. }
  3833. static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
  3834. {
  3835. int ret = 0;
  3836. if (!vreg)
  3837. goto out;
  3838. vreg->reg = devm_regulator_get(dev, vreg->name);
  3839. if (IS_ERR(vreg->reg)) {
  3840. ret = PTR_ERR(vreg->reg);
  3841. dev_err(dev, "%s: %s get failed, err=%d\n",
  3842. __func__, vreg->name, ret);
  3843. }
  3844. out:
  3845. return ret;
  3846. }
  3847. static int ufshcd_init_vreg(struct ufs_hba *hba)
  3848. {
  3849. int ret = 0;
  3850. struct device *dev = hba->dev;
  3851. struct ufs_vreg_info *info = &hba->vreg_info;
  3852. if (!info)
  3853. goto out;
  3854. ret = ufshcd_get_vreg(dev, info->vcc);
  3855. if (ret)
  3856. goto out;
  3857. ret = ufshcd_get_vreg(dev, info->vccq);
  3858. if (ret)
  3859. goto out;
  3860. ret = ufshcd_get_vreg(dev, info->vccq2);
  3861. out:
  3862. return ret;
  3863. }
  3864. static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
  3865. {
  3866. struct ufs_vreg_info *info = &hba->vreg_info;
  3867. if (info)
  3868. return ufshcd_get_vreg(hba->dev, info->vdd_hba);
  3869. return 0;
  3870. }
  3871. static int __ufshcd_setup_clocks(struct ufs_hba *hba, bool on,
  3872. bool skip_ref_clk)
  3873. {
  3874. int ret = 0;
  3875. struct ufs_clk_info *clki;
  3876. struct list_head *head = &hba->clk_list_head;
  3877. unsigned long flags;
  3878. if (!head || list_empty(head))
  3879. goto out;
  3880. list_for_each_entry(clki, head, list) {
  3881. if (!IS_ERR_OR_NULL(clki->clk)) {
  3882. if (skip_ref_clk && !strcmp(clki->name, "ref_clk"))
  3883. continue;
  3884. if (on && !clki->enabled) {
  3885. ret = clk_prepare_enable(clki->clk);
  3886. if (ret) {
  3887. dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
  3888. __func__, clki->name, ret);
  3889. goto out;
  3890. }
  3891. } else if (!on && clki->enabled) {
  3892. clk_disable_unprepare(clki->clk);
  3893. }
  3894. clki->enabled = on;
  3895. dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
  3896. clki->name, on ? "en" : "dis");
  3897. }
  3898. }
  3899. if (hba->vops && hba->vops->setup_clocks)
  3900. ret = hba->vops->setup_clocks(hba, on);
  3901. out:
  3902. if (ret) {
  3903. list_for_each_entry(clki, head, list) {
  3904. if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
  3905. clk_disable_unprepare(clki->clk);
  3906. }
  3907. } else if (on) {
  3908. spin_lock_irqsave(hba->host->host_lock, flags);
  3909. hba->clk_gating.state = CLKS_ON;
  3910. spin_unlock_irqrestore(hba->host->host_lock, flags);
  3911. }
  3912. return ret;
  3913. }
  3914. static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
  3915. {
  3916. return __ufshcd_setup_clocks(hba, on, false);
  3917. }
  3918. static int ufshcd_init_clocks(struct ufs_hba *hba)
  3919. {
  3920. int ret = 0;
  3921. struct ufs_clk_info *clki;
  3922. struct device *dev = hba->dev;
  3923. struct list_head *head = &hba->clk_list_head;
  3924. if (!head || list_empty(head))
  3925. goto out;
  3926. list_for_each_entry(clki, head, list) {
  3927. if (!clki->name)
  3928. continue;
  3929. clki->clk = devm_clk_get(dev, clki->name);
  3930. if (IS_ERR(clki->clk)) {
  3931. ret = PTR_ERR(clki->clk);
  3932. dev_err(dev, "%s: %s clk get failed, %d\n",
  3933. __func__, clki->name, ret);
  3934. goto out;
  3935. }
  3936. if (clki->max_freq) {
  3937. ret = clk_set_rate(clki->clk, clki->max_freq);
  3938. if (ret) {
  3939. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  3940. __func__, clki->name,
  3941. clki->max_freq, ret);
  3942. goto out;
  3943. }
  3944. clki->curr_freq = clki->max_freq;
  3945. }
  3946. dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
  3947. clki->name, clk_get_rate(clki->clk));
  3948. }
  3949. out:
  3950. return ret;
  3951. }
  3952. static int ufshcd_variant_hba_init(struct ufs_hba *hba)
  3953. {
  3954. int err = 0;
  3955. if (!hba->vops)
  3956. goto out;
  3957. if (hba->vops->init) {
  3958. err = hba->vops->init(hba);
  3959. if (err)
  3960. goto out;
  3961. }
  3962. if (hba->vops->setup_regulators) {
  3963. err = hba->vops->setup_regulators(hba, true);
  3964. if (err)
  3965. goto out_exit;
  3966. }
  3967. goto out;
  3968. out_exit:
  3969. if (hba->vops->exit)
  3970. hba->vops->exit(hba);
  3971. out:
  3972. if (err)
  3973. dev_err(hba->dev, "%s: variant %s init failed err %d\n",
  3974. __func__, hba->vops ? hba->vops->name : "", err);
  3975. return err;
  3976. }
  3977. static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
  3978. {
  3979. if (!hba->vops)
  3980. return;
  3981. if (hba->vops->setup_clocks)
  3982. hba->vops->setup_clocks(hba, false);
  3983. if (hba->vops->setup_regulators)
  3984. hba->vops->setup_regulators(hba, false);
  3985. if (hba->vops->exit)
  3986. hba->vops->exit(hba);
  3987. }
  3988. static int ufshcd_hba_init(struct ufs_hba *hba)
  3989. {
  3990. int err;
  3991. /*
  3992. * Handle host controller power separately from the UFS device power
  3993. * rails as it will help controlling the UFS host controller power
  3994. * collapse easily which is different than UFS device power collapse.
  3995. * Also, enable the host controller power before we go ahead with rest
  3996. * of the initialization here.
  3997. */
  3998. err = ufshcd_init_hba_vreg(hba);
  3999. if (err)
  4000. goto out;
  4001. err = ufshcd_setup_hba_vreg(hba, true);
  4002. if (err)
  4003. goto out;
  4004. err = ufshcd_init_clocks(hba);
  4005. if (err)
  4006. goto out_disable_hba_vreg;
  4007. err = ufshcd_setup_clocks(hba, true);
  4008. if (err)
  4009. goto out_disable_hba_vreg;
  4010. err = ufshcd_init_vreg(hba);
  4011. if (err)
  4012. goto out_disable_clks;
  4013. err = ufshcd_setup_vreg(hba, true);
  4014. if (err)
  4015. goto out_disable_clks;
  4016. err = ufshcd_variant_hba_init(hba);
  4017. if (err)
  4018. goto out_disable_vreg;
  4019. hba->is_powered = true;
  4020. goto out;
  4021. out_disable_vreg:
  4022. ufshcd_setup_vreg(hba, false);
  4023. out_disable_clks:
  4024. ufshcd_setup_clocks(hba, false);
  4025. out_disable_hba_vreg:
  4026. ufshcd_setup_hba_vreg(hba, false);
  4027. out:
  4028. return err;
  4029. }
  4030. static void ufshcd_hba_exit(struct ufs_hba *hba)
  4031. {
  4032. if (hba->is_powered) {
  4033. ufshcd_variant_hba_exit(hba);
  4034. ufshcd_setup_vreg(hba, false);
  4035. ufshcd_setup_clocks(hba, false);
  4036. ufshcd_setup_hba_vreg(hba, false);
  4037. hba->is_powered = false;
  4038. }
  4039. }
  4040. static int
  4041. ufshcd_send_request_sense(struct ufs_hba *hba, struct scsi_device *sdp)
  4042. {
  4043. unsigned char cmd[6] = {REQUEST_SENSE,
  4044. 0,
  4045. 0,
  4046. 0,
  4047. SCSI_SENSE_BUFFERSIZE,
  4048. 0};
  4049. char *buffer;
  4050. int ret;
  4051. buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  4052. if (!buffer) {
  4053. ret = -ENOMEM;
  4054. goto out;
  4055. }
  4056. ret = scsi_execute_req_flags(sdp, cmd, DMA_FROM_DEVICE, buffer,
  4057. SCSI_SENSE_BUFFERSIZE, NULL,
  4058. msecs_to_jiffies(1000), 3, NULL, REQ_PM);
  4059. if (ret)
  4060. pr_err("%s: failed with err %d\n", __func__, ret);
  4061. kfree(buffer);
  4062. out:
  4063. return ret;
  4064. }
  4065. /**
  4066. * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
  4067. * power mode
  4068. * @hba: per adapter instance
  4069. * @pwr_mode: device power mode to set
  4070. *
  4071. * Returns 0 if requested power mode is set successfully
  4072. * Returns non-zero if failed to set the requested power mode
  4073. */
  4074. static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
  4075. enum ufs_dev_pwr_mode pwr_mode)
  4076. {
  4077. unsigned char cmd[6] = { START_STOP };
  4078. struct scsi_sense_hdr sshdr;
  4079. struct scsi_device *sdp;
  4080. unsigned long flags;
  4081. int ret;
  4082. spin_lock_irqsave(hba->host->host_lock, flags);
  4083. sdp = hba->sdev_ufs_device;
  4084. if (sdp) {
  4085. ret = scsi_device_get(sdp);
  4086. if (!ret && !scsi_device_online(sdp)) {
  4087. ret = -ENODEV;
  4088. scsi_device_put(sdp);
  4089. }
  4090. } else {
  4091. ret = -ENODEV;
  4092. }
  4093. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4094. if (ret)
  4095. return ret;
  4096. /*
  4097. * If scsi commands fail, the scsi mid-layer schedules scsi error-
  4098. * handling, which would wait for host to be resumed. Since we know
  4099. * we are functional while we are here, skip host resume in error
  4100. * handling context.
  4101. */
  4102. hba->host->eh_noresume = 1;
  4103. if (hba->wlun_dev_clr_ua) {
  4104. ret = ufshcd_send_request_sense(hba, sdp);
  4105. if (ret)
  4106. goto out;
  4107. /* Unit attention condition is cleared now */
  4108. hba->wlun_dev_clr_ua = false;
  4109. }
  4110. cmd[4] = pwr_mode << 4;
  4111. /*
  4112. * Current function would be generally called from the power management
  4113. * callbacks hence set the REQ_PM flag so that it doesn't resume the
  4114. * already suspended childs.
  4115. */
  4116. ret = scsi_execute_req_flags(sdp, cmd, DMA_NONE, NULL, 0, &sshdr,
  4117. START_STOP_TIMEOUT, 0, NULL, REQ_PM);
  4118. if (ret) {
  4119. sdev_printk(KERN_WARNING, sdp,
  4120. "START_STOP failed for power mode: %d\n", pwr_mode);
  4121. scsi_show_result(ret);
  4122. if (driver_byte(ret) & DRIVER_SENSE) {
  4123. scsi_show_sense_hdr(&sshdr);
  4124. scsi_show_extd_sense(sshdr.asc, sshdr.ascq);
  4125. }
  4126. }
  4127. if (!ret)
  4128. hba->curr_dev_pwr_mode = pwr_mode;
  4129. out:
  4130. scsi_device_put(sdp);
  4131. hba->host->eh_noresume = 0;
  4132. return ret;
  4133. }
  4134. static int ufshcd_link_state_transition(struct ufs_hba *hba,
  4135. enum uic_link_state req_link_state,
  4136. int check_for_bkops)
  4137. {
  4138. int ret = 0;
  4139. if (req_link_state == hba->uic_link_state)
  4140. return 0;
  4141. if (req_link_state == UIC_LINK_HIBERN8_STATE) {
  4142. ret = ufshcd_uic_hibern8_enter(hba);
  4143. if (!ret)
  4144. ufshcd_set_link_hibern8(hba);
  4145. else
  4146. goto out;
  4147. }
  4148. /*
  4149. * If autobkops is enabled, link can't be turned off because
  4150. * turning off the link would also turn off the device.
  4151. */
  4152. else if ((req_link_state == UIC_LINK_OFF_STATE) &&
  4153. (!check_for_bkops || (check_for_bkops &&
  4154. !hba->auto_bkops_enabled))) {
  4155. /*
  4156. * Change controller state to "reset state" which
  4157. * should also put the link in off/reset state
  4158. */
  4159. ufshcd_hba_stop(hba);
  4160. /*
  4161. * TODO: Check if we need any delay to make sure that
  4162. * controller is reset
  4163. */
  4164. ufshcd_set_link_off(hba);
  4165. }
  4166. out:
  4167. return ret;
  4168. }
  4169. static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
  4170. {
  4171. /*
  4172. * If UFS device is either in UFS_Sleep turn off VCC rail to save some
  4173. * power.
  4174. *
  4175. * If UFS device and link is in OFF state, all power supplies (VCC,
  4176. * VCCQ, VCCQ2) can be turned off if power on write protect is not
  4177. * required. If UFS link is inactive (Hibern8 or OFF state) and device
  4178. * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
  4179. *
  4180. * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
  4181. * in low power state which would save some power.
  4182. */
  4183. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  4184. !hba->dev_info.is_lu_power_on_wp) {
  4185. ufshcd_setup_vreg(hba, false);
  4186. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  4187. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  4188. if (!ufshcd_is_link_active(hba)) {
  4189. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  4190. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
  4191. }
  4192. }
  4193. }
  4194. static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
  4195. {
  4196. int ret = 0;
  4197. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
  4198. !hba->dev_info.is_lu_power_on_wp) {
  4199. ret = ufshcd_setup_vreg(hba, true);
  4200. } else if (!ufshcd_is_ufs_dev_active(hba)) {
  4201. ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
  4202. if (!ret && !ufshcd_is_link_active(hba)) {
  4203. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
  4204. if (ret)
  4205. goto vcc_disable;
  4206. ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
  4207. if (ret)
  4208. goto vccq_lpm;
  4209. }
  4210. }
  4211. goto out;
  4212. vccq_lpm:
  4213. ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
  4214. vcc_disable:
  4215. ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
  4216. out:
  4217. return ret;
  4218. }
  4219. static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
  4220. {
  4221. if (ufshcd_is_link_off(hba))
  4222. ufshcd_setup_hba_vreg(hba, false);
  4223. }
  4224. static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
  4225. {
  4226. if (ufshcd_is_link_off(hba))
  4227. ufshcd_setup_hba_vreg(hba, true);
  4228. }
  4229. /**
  4230. * ufshcd_suspend - helper function for suspend operations
  4231. * @hba: per adapter instance
  4232. * @pm_op: desired low power operation type
  4233. *
  4234. * This function will try to put the UFS device and link into low power
  4235. * mode based on the "rpm_lvl" (Runtime PM level) or "spm_lvl"
  4236. * (System PM level).
  4237. *
  4238. * If this function is called during shutdown, it will make sure that
  4239. * both UFS device and UFS link is powered off.
  4240. *
  4241. * NOTE: UFS device & link must be active before we enter in this function.
  4242. *
  4243. * Returns 0 for success and non-zero for failure
  4244. */
  4245. static int ufshcd_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  4246. {
  4247. int ret = 0;
  4248. enum ufs_pm_level pm_lvl;
  4249. enum ufs_dev_pwr_mode req_dev_pwr_mode;
  4250. enum uic_link_state req_link_state;
  4251. hba->pm_op_in_progress = 1;
  4252. if (!ufshcd_is_shutdown_pm(pm_op)) {
  4253. pm_lvl = ufshcd_is_runtime_pm(pm_op) ?
  4254. hba->rpm_lvl : hba->spm_lvl;
  4255. req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
  4256. req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
  4257. } else {
  4258. req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
  4259. req_link_state = UIC_LINK_OFF_STATE;
  4260. }
  4261. /*
  4262. * If we can't transition into any of the low power modes
  4263. * just gate the clocks.
  4264. */
  4265. ufshcd_hold(hba, false);
  4266. hba->clk_gating.is_suspended = true;
  4267. if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
  4268. req_link_state == UIC_LINK_ACTIVE_STATE) {
  4269. goto disable_clks;
  4270. }
  4271. if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
  4272. (req_link_state == hba->uic_link_state))
  4273. goto out;
  4274. /* UFS device & link must be active before we enter in this function */
  4275. if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
  4276. ret = -EINVAL;
  4277. goto out;
  4278. }
  4279. if (ufshcd_is_runtime_pm(pm_op)) {
  4280. if (ufshcd_can_autobkops_during_suspend(hba)) {
  4281. /*
  4282. * The device is idle with no requests in the queue,
  4283. * allow background operations if bkops status shows
  4284. * that performance might be impacted.
  4285. */
  4286. ret = ufshcd_urgent_bkops(hba);
  4287. if (ret)
  4288. goto enable_gating;
  4289. } else {
  4290. /* make sure that auto bkops is disabled */
  4291. ufshcd_disable_auto_bkops(hba);
  4292. }
  4293. }
  4294. if ((req_dev_pwr_mode != hba->curr_dev_pwr_mode) &&
  4295. ((ufshcd_is_runtime_pm(pm_op) && !hba->auto_bkops_enabled) ||
  4296. !ufshcd_is_runtime_pm(pm_op))) {
  4297. /* ensure that bkops is disabled */
  4298. ufshcd_disable_auto_bkops(hba);
  4299. ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
  4300. if (ret)
  4301. goto enable_gating;
  4302. }
  4303. ret = ufshcd_link_state_transition(hba, req_link_state, 1);
  4304. if (ret)
  4305. goto set_dev_active;
  4306. ufshcd_vreg_set_lpm(hba);
  4307. disable_clks:
  4308. /*
  4309. * The clock scaling needs access to controller registers. Hence, Wait
  4310. * for pending clock scaling work to be done before clocks are
  4311. * turned off.
  4312. */
  4313. if (ufshcd_is_clkscaling_enabled(hba)) {
  4314. devfreq_suspend_device(hba->devfreq);
  4315. hba->clk_scaling.window_start_t = 0;
  4316. }
  4317. /*
  4318. * Call vendor specific suspend callback. As these callbacks may access
  4319. * vendor specific host controller register space call them before the
  4320. * host clocks are ON.
  4321. */
  4322. if (hba->vops && hba->vops->suspend) {
  4323. ret = hba->vops->suspend(hba, pm_op);
  4324. if (ret)
  4325. goto set_link_active;
  4326. }
  4327. if (hba->vops && hba->vops->setup_clocks) {
  4328. ret = hba->vops->setup_clocks(hba, false);
  4329. if (ret)
  4330. goto vops_resume;
  4331. }
  4332. if (!ufshcd_is_link_active(hba))
  4333. ufshcd_setup_clocks(hba, false);
  4334. else
  4335. /* If link is active, device ref_clk can't be switched off */
  4336. __ufshcd_setup_clocks(hba, false, true);
  4337. hba->clk_gating.state = CLKS_OFF;
  4338. /*
  4339. * Disable the host irq as host controller as there won't be any
  4340. * host controller trasanction expected till resume.
  4341. */
  4342. ufshcd_disable_irq(hba);
  4343. /* Put the host controller in low power mode if possible */
  4344. ufshcd_hba_vreg_set_lpm(hba);
  4345. goto out;
  4346. vops_resume:
  4347. if (hba->vops && hba->vops->resume)
  4348. hba->vops->resume(hba, pm_op);
  4349. set_link_active:
  4350. ufshcd_vreg_set_hpm(hba);
  4351. if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
  4352. ufshcd_set_link_active(hba);
  4353. else if (ufshcd_is_link_off(hba))
  4354. ufshcd_host_reset_and_restore(hba);
  4355. set_dev_active:
  4356. if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
  4357. ufshcd_disable_auto_bkops(hba);
  4358. enable_gating:
  4359. hba->clk_gating.is_suspended = false;
  4360. ufshcd_release(hba);
  4361. out:
  4362. hba->pm_op_in_progress = 0;
  4363. return ret;
  4364. }
  4365. /**
  4366. * ufshcd_resume - helper function for resume operations
  4367. * @hba: per adapter instance
  4368. * @pm_op: runtime PM or system PM
  4369. *
  4370. * This function basically brings the UFS device, UniPro link and controller
  4371. * to active state.
  4372. *
  4373. * Returns 0 for success and non-zero for failure
  4374. */
  4375. static int ufshcd_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
  4376. {
  4377. int ret;
  4378. enum uic_link_state old_link_state;
  4379. hba->pm_op_in_progress = 1;
  4380. old_link_state = hba->uic_link_state;
  4381. ufshcd_hba_vreg_set_hpm(hba);
  4382. /* Make sure clocks are enabled before accessing controller */
  4383. ret = ufshcd_setup_clocks(hba, true);
  4384. if (ret)
  4385. goto out;
  4386. /* enable the host irq as host controller would be active soon */
  4387. ret = ufshcd_enable_irq(hba);
  4388. if (ret)
  4389. goto disable_irq_and_vops_clks;
  4390. ret = ufshcd_vreg_set_hpm(hba);
  4391. if (ret)
  4392. goto disable_irq_and_vops_clks;
  4393. /*
  4394. * Call vendor specific resume callback. As these callbacks may access
  4395. * vendor specific host controller register space call them when the
  4396. * host clocks are ON.
  4397. */
  4398. if (hba->vops && hba->vops->resume) {
  4399. ret = hba->vops->resume(hba, pm_op);
  4400. if (ret)
  4401. goto disable_vreg;
  4402. }
  4403. if (ufshcd_is_link_hibern8(hba)) {
  4404. ret = ufshcd_uic_hibern8_exit(hba);
  4405. if (!ret)
  4406. ufshcd_set_link_active(hba);
  4407. else
  4408. goto vendor_suspend;
  4409. } else if (ufshcd_is_link_off(hba)) {
  4410. ret = ufshcd_host_reset_and_restore(hba);
  4411. /*
  4412. * ufshcd_host_reset_and_restore() should have already
  4413. * set the link state as active
  4414. */
  4415. if (ret || !ufshcd_is_link_active(hba))
  4416. goto vendor_suspend;
  4417. }
  4418. if (!ufshcd_is_ufs_dev_active(hba)) {
  4419. ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
  4420. if (ret)
  4421. goto set_old_link_state;
  4422. }
  4423. /*
  4424. * If BKOPs operations are urgently needed at this moment then
  4425. * keep auto-bkops enabled or else disable it.
  4426. */
  4427. ufshcd_urgent_bkops(hba);
  4428. hba->clk_gating.is_suspended = false;
  4429. if (ufshcd_is_clkscaling_enabled(hba))
  4430. devfreq_resume_device(hba->devfreq);
  4431. /* Schedule clock gating in case of no access to UFS device yet */
  4432. ufshcd_release(hba);
  4433. goto out;
  4434. set_old_link_state:
  4435. ufshcd_link_state_transition(hba, old_link_state, 0);
  4436. vendor_suspend:
  4437. if (hba->vops && hba->vops->suspend)
  4438. hba->vops->suspend(hba, pm_op);
  4439. disable_vreg:
  4440. ufshcd_vreg_set_lpm(hba);
  4441. disable_irq_and_vops_clks:
  4442. ufshcd_disable_irq(hba);
  4443. ufshcd_setup_clocks(hba, false);
  4444. out:
  4445. hba->pm_op_in_progress = 0;
  4446. return ret;
  4447. }
  4448. /**
  4449. * ufshcd_system_suspend - system suspend routine
  4450. * @hba: per adapter instance
  4451. * @pm_op: runtime PM or system PM
  4452. *
  4453. * Check the description of ufshcd_suspend() function for more details.
  4454. *
  4455. * Returns 0 for success and non-zero for failure
  4456. */
  4457. int ufshcd_system_suspend(struct ufs_hba *hba)
  4458. {
  4459. int ret = 0;
  4460. if (!hba || !hba->is_powered)
  4461. return 0;
  4462. if (pm_runtime_suspended(hba->dev)) {
  4463. if (hba->rpm_lvl == hba->spm_lvl)
  4464. /*
  4465. * There is possibility that device may still be in
  4466. * active state during the runtime suspend.
  4467. */
  4468. if ((ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl) ==
  4469. hba->curr_dev_pwr_mode) && !hba->auto_bkops_enabled)
  4470. goto out;
  4471. /*
  4472. * UFS device and/or UFS link low power states during runtime
  4473. * suspend seems to be different than what is expected during
  4474. * system suspend. Hence runtime resume the devic & link and
  4475. * let the system suspend low power states to take effect.
  4476. * TODO: If resume takes longer time, we might have optimize
  4477. * it in future by not resuming everything if possible.
  4478. */
  4479. ret = ufshcd_runtime_resume(hba);
  4480. if (ret)
  4481. goto out;
  4482. }
  4483. ret = ufshcd_suspend(hba, UFS_SYSTEM_PM);
  4484. out:
  4485. if (!ret)
  4486. hba->is_sys_suspended = true;
  4487. return ret;
  4488. }
  4489. EXPORT_SYMBOL(ufshcd_system_suspend);
  4490. /**
  4491. * ufshcd_system_resume - system resume routine
  4492. * @hba: per adapter instance
  4493. *
  4494. * Returns 0 for success and non-zero for failure
  4495. */
  4496. int ufshcd_system_resume(struct ufs_hba *hba)
  4497. {
  4498. if (!hba || !hba->is_powered || pm_runtime_suspended(hba->dev))
  4499. /*
  4500. * Let the runtime resume take care of resuming
  4501. * if runtime suspended.
  4502. */
  4503. return 0;
  4504. return ufshcd_resume(hba, UFS_SYSTEM_PM);
  4505. }
  4506. EXPORT_SYMBOL(ufshcd_system_resume);
  4507. /**
  4508. * ufshcd_runtime_suspend - runtime suspend routine
  4509. * @hba: per adapter instance
  4510. *
  4511. * Check the description of ufshcd_suspend() function for more details.
  4512. *
  4513. * Returns 0 for success and non-zero for failure
  4514. */
  4515. int ufshcd_runtime_suspend(struct ufs_hba *hba)
  4516. {
  4517. if (!hba || !hba->is_powered)
  4518. return 0;
  4519. return ufshcd_suspend(hba, UFS_RUNTIME_PM);
  4520. }
  4521. EXPORT_SYMBOL(ufshcd_runtime_suspend);
  4522. /**
  4523. * ufshcd_runtime_resume - runtime resume routine
  4524. * @hba: per adapter instance
  4525. *
  4526. * This function basically brings the UFS device, UniPro link and controller
  4527. * to active state. Following operations are done in this function:
  4528. *
  4529. * 1. Turn on all the controller related clocks
  4530. * 2. Bring the UniPro link out of Hibernate state
  4531. * 3. If UFS device is in sleep state, turn ON VCC rail and bring the UFS device
  4532. * to active state.
  4533. * 4. If auto-bkops is enabled on the device, disable it.
  4534. *
  4535. * So following would be the possible power state after this function return
  4536. * successfully:
  4537. * S1: UFS device in Active state with VCC rail ON
  4538. * UniPro link in Active state
  4539. * All the UFS/UniPro controller clocks are ON
  4540. *
  4541. * Returns 0 for success and non-zero for failure
  4542. */
  4543. int ufshcd_runtime_resume(struct ufs_hba *hba)
  4544. {
  4545. if (!hba || !hba->is_powered)
  4546. return 0;
  4547. else
  4548. return ufshcd_resume(hba, UFS_RUNTIME_PM);
  4549. }
  4550. EXPORT_SYMBOL(ufshcd_runtime_resume);
  4551. int ufshcd_runtime_idle(struct ufs_hba *hba)
  4552. {
  4553. return 0;
  4554. }
  4555. EXPORT_SYMBOL(ufshcd_runtime_idle);
  4556. /**
  4557. * ufshcd_shutdown - shutdown routine
  4558. * @hba: per adapter instance
  4559. *
  4560. * This function would power off both UFS device and UFS link.
  4561. *
  4562. * Returns 0 always to allow force shutdown even in case of errors.
  4563. */
  4564. int ufshcd_shutdown(struct ufs_hba *hba)
  4565. {
  4566. int ret = 0;
  4567. if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
  4568. goto out;
  4569. if (pm_runtime_suspended(hba->dev)) {
  4570. ret = ufshcd_runtime_resume(hba);
  4571. if (ret)
  4572. goto out;
  4573. }
  4574. ret = ufshcd_suspend(hba, UFS_SHUTDOWN_PM);
  4575. out:
  4576. if (ret)
  4577. dev_err(hba->dev, "%s failed, err %d\n", __func__, ret);
  4578. /* allow force shutdown even in case of errors */
  4579. return 0;
  4580. }
  4581. EXPORT_SYMBOL(ufshcd_shutdown);
  4582. /**
  4583. * ufshcd_remove - de-allocate SCSI host and host memory space
  4584. * data structure memory
  4585. * @hba - per adapter instance
  4586. */
  4587. void ufshcd_remove(struct ufs_hba *hba)
  4588. {
  4589. scsi_remove_host(hba->host);
  4590. /* disable interrupts */
  4591. ufshcd_disable_intr(hba, hba->intr_mask);
  4592. ufshcd_hba_stop(hba);
  4593. scsi_host_put(hba->host);
  4594. ufshcd_exit_clk_gating(hba);
  4595. if (ufshcd_is_clkscaling_enabled(hba))
  4596. devfreq_remove_device(hba->devfreq);
  4597. ufshcd_hba_exit(hba);
  4598. }
  4599. EXPORT_SYMBOL_GPL(ufshcd_remove);
  4600. /**
  4601. * ufshcd_set_dma_mask - Set dma mask based on the controller
  4602. * addressing capability
  4603. * @hba: per adapter instance
  4604. *
  4605. * Returns 0 for success, non-zero for failure
  4606. */
  4607. static int ufshcd_set_dma_mask(struct ufs_hba *hba)
  4608. {
  4609. if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
  4610. if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
  4611. return 0;
  4612. }
  4613. return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
  4614. }
  4615. /**
  4616. * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
  4617. * @dev: pointer to device handle
  4618. * @hba_handle: driver private handle
  4619. * Returns 0 on success, non-zero value on failure
  4620. */
  4621. int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
  4622. {
  4623. struct Scsi_Host *host;
  4624. struct ufs_hba *hba;
  4625. int err = 0;
  4626. if (!dev) {
  4627. dev_err(dev,
  4628. "Invalid memory reference for dev is NULL\n");
  4629. err = -ENODEV;
  4630. goto out_error;
  4631. }
  4632. host = scsi_host_alloc(&ufshcd_driver_template,
  4633. sizeof(struct ufs_hba));
  4634. if (!host) {
  4635. dev_err(dev, "scsi_host_alloc failed\n");
  4636. err = -ENOMEM;
  4637. goto out_error;
  4638. }
  4639. hba = shost_priv(host);
  4640. hba->host = host;
  4641. hba->dev = dev;
  4642. *hba_handle = hba;
  4643. out_error:
  4644. return err;
  4645. }
  4646. EXPORT_SYMBOL(ufshcd_alloc_host);
  4647. static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
  4648. {
  4649. int ret = 0;
  4650. struct ufs_clk_info *clki;
  4651. struct list_head *head = &hba->clk_list_head;
  4652. if (!head || list_empty(head))
  4653. goto out;
  4654. list_for_each_entry(clki, head, list) {
  4655. if (!IS_ERR_OR_NULL(clki->clk)) {
  4656. if (scale_up && clki->max_freq) {
  4657. if (clki->curr_freq == clki->max_freq)
  4658. continue;
  4659. ret = clk_set_rate(clki->clk, clki->max_freq);
  4660. if (ret) {
  4661. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  4662. __func__, clki->name,
  4663. clki->max_freq, ret);
  4664. break;
  4665. }
  4666. clki->curr_freq = clki->max_freq;
  4667. } else if (!scale_up && clki->min_freq) {
  4668. if (clki->curr_freq == clki->min_freq)
  4669. continue;
  4670. ret = clk_set_rate(clki->clk, clki->min_freq);
  4671. if (ret) {
  4672. dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
  4673. __func__, clki->name,
  4674. clki->min_freq, ret);
  4675. break;
  4676. }
  4677. clki->curr_freq = clki->min_freq;
  4678. }
  4679. }
  4680. dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
  4681. clki->name, clk_get_rate(clki->clk));
  4682. }
  4683. if (hba->vops->clk_scale_notify)
  4684. hba->vops->clk_scale_notify(hba);
  4685. out:
  4686. return ret;
  4687. }
  4688. static int ufshcd_devfreq_target(struct device *dev,
  4689. unsigned long *freq, u32 flags)
  4690. {
  4691. int err = 0;
  4692. struct ufs_hba *hba = dev_get_drvdata(dev);
  4693. if (!ufshcd_is_clkscaling_enabled(hba))
  4694. return -EINVAL;
  4695. if (*freq == UINT_MAX)
  4696. err = ufshcd_scale_clks(hba, true);
  4697. else if (*freq == 0)
  4698. err = ufshcd_scale_clks(hba, false);
  4699. return err;
  4700. }
  4701. static int ufshcd_devfreq_get_dev_status(struct device *dev,
  4702. struct devfreq_dev_status *stat)
  4703. {
  4704. struct ufs_hba *hba = dev_get_drvdata(dev);
  4705. struct ufs_clk_scaling *scaling = &hba->clk_scaling;
  4706. unsigned long flags;
  4707. if (!ufshcd_is_clkscaling_enabled(hba))
  4708. return -EINVAL;
  4709. memset(stat, 0, sizeof(*stat));
  4710. spin_lock_irqsave(hba->host->host_lock, flags);
  4711. if (!scaling->window_start_t)
  4712. goto start_window;
  4713. if (scaling->is_busy_started)
  4714. scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
  4715. scaling->busy_start_t));
  4716. stat->total_time = jiffies_to_usecs((long)jiffies -
  4717. (long)scaling->window_start_t);
  4718. stat->busy_time = scaling->tot_busy_t;
  4719. start_window:
  4720. scaling->window_start_t = jiffies;
  4721. scaling->tot_busy_t = 0;
  4722. if (hba->outstanding_reqs) {
  4723. scaling->busy_start_t = ktime_get();
  4724. scaling->is_busy_started = true;
  4725. } else {
  4726. scaling->busy_start_t = ktime_set(0, 0);
  4727. scaling->is_busy_started = false;
  4728. }
  4729. spin_unlock_irqrestore(hba->host->host_lock, flags);
  4730. return 0;
  4731. }
  4732. static struct devfreq_dev_profile ufs_devfreq_profile = {
  4733. .polling_ms = 100,
  4734. .target = ufshcd_devfreq_target,
  4735. .get_dev_status = ufshcd_devfreq_get_dev_status,
  4736. };
  4737. /**
  4738. * ufshcd_init - Driver initialization routine
  4739. * @hba: per-adapter instance
  4740. * @mmio_base: base register address
  4741. * @irq: Interrupt line of device
  4742. * Returns 0 on success, non-zero value on failure
  4743. */
  4744. int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
  4745. {
  4746. int err;
  4747. struct Scsi_Host *host = hba->host;
  4748. struct device *dev = hba->dev;
  4749. if (!mmio_base) {
  4750. dev_err(hba->dev,
  4751. "Invalid memory reference for mmio_base is NULL\n");
  4752. err = -ENODEV;
  4753. goto out_error;
  4754. }
  4755. hba->mmio_base = mmio_base;
  4756. hba->irq = irq;
  4757. err = ufshcd_hba_init(hba);
  4758. if (err)
  4759. goto out_error;
  4760. /* Read capabilities registers */
  4761. ufshcd_hba_capabilities(hba);
  4762. /* Get UFS version supported by the controller */
  4763. hba->ufs_version = ufshcd_get_ufs_version(hba);
  4764. /* Get Interrupt bit mask per version */
  4765. hba->intr_mask = ufshcd_get_intr_mask(hba);
  4766. err = ufshcd_set_dma_mask(hba);
  4767. if (err) {
  4768. dev_err(hba->dev, "set dma mask failed\n");
  4769. goto out_disable;
  4770. }
  4771. /* Allocate memory for host memory space */
  4772. err = ufshcd_memory_alloc(hba);
  4773. if (err) {
  4774. dev_err(hba->dev, "Memory allocation failed\n");
  4775. goto out_disable;
  4776. }
  4777. /* Configure LRB */
  4778. ufshcd_host_memory_configure(hba);
  4779. host->can_queue = hba->nutrs;
  4780. host->cmd_per_lun = hba->nutrs;
  4781. host->max_id = UFSHCD_MAX_ID;
  4782. host->max_lun = UFS_MAX_LUNS;
  4783. host->max_channel = UFSHCD_MAX_CHANNEL;
  4784. host->unique_id = host->host_no;
  4785. host->max_cmd_len = MAX_CDB_SIZE;
  4786. hba->max_pwr_info.is_valid = false;
  4787. /* Initailize wait queue for task management */
  4788. init_waitqueue_head(&hba->tm_wq);
  4789. init_waitqueue_head(&hba->tm_tag_wq);
  4790. /* Initialize work queues */
  4791. INIT_WORK(&hba->eh_work, ufshcd_err_handler);
  4792. INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
  4793. /* Initialize UIC command mutex */
  4794. mutex_init(&hba->uic_cmd_mutex);
  4795. /* Initialize mutex for device management commands */
  4796. mutex_init(&hba->dev_cmd.lock);
  4797. /* Initialize device management tag acquire wait queue */
  4798. init_waitqueue_head(&hba->dev_cmd.tag_wq);
  4799. ufshcd_init_clk_gating(hba);
  4800. /* IRQ registration */
  4801. err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
  4802. if (err) {
  4803. dev_err(hba->dev, "request irq failed\n");
  4804. goto exit_gating;
  4805. } else {
  4806. hba->is_irq_enabled = true;
  4807. }
  4808. /* Enable SCSI tag mapping */
  4809. err = scsi_init_shared_tag_map(host, host->can_queue);
  4810. if (err) {
  4811. dev_err(hba->dev, "init shared queue failed\n");
  4812. goto exit_gating;
  4813. }
  4814. err = scsi_add_host(host, hba->dev);
  4815. if (err) {
  4816. dev_err(hba->dev, "scsi_add_host failed\n");
  4817. goto exit_gating;
  4818. }
  4819. /* Host controller enable */
  4820. err = ufshcd_hba_enable(hba);
  4821. if (err) {
  4822. dev_err(hba->dev, "Host controller enable failed\n");
  4823. goto out_remove_scsi_host;
  4824. }
  4825. if (ufshcd_is_clkscaling_enabled(hba)) {
  4826. hba->devfreq = devfreq_add_device(dev, &ufs_devfreq_profile,
  4827. "simple_ondemand", NULL);
  4828. if (IS_ERR(hba->devfreq)) {
  4829. dev_err(hba->dev, "Unable to register with devfreq %ld\n",
  4830. PTR_ERR(hba->devfreq));
  4831. goto out_remove_scsi_host;
  4832. }
  4833. /* Suspend devfreq until the UFS device is detected */
  4834. devfreq_suspend_device(hba->devfreq);
  4835. hba->clk_scaling.window_start_t = 0;
  4836. }
  4837. /* Hold auto suspend until async scan completes */
  4838. pm_runtime_get_sync(dev);
  4839. /*
  4840. * The device-initialize-sequence hasn't been invoked yet.
  4841. * Set the device to power-off state
  4842. */
  4843. ufshcd_set_ufs_dev_poweroff(hba);
  4844. async_schedule(ufshcd_async_scan, hba);
  4845. return 0;
  4846. out_remove_scsi_host:
  4847. scsi_remove_host(hba->host);
  4848. exit_gating:
  4849. ufshcd_exit_clk_gating(hba);
  4850. out_disable:
  4851. hba->is_irq_enabled = false;
  4852. scsi_host_put(host);
  4853. ufshcd_hba_exit(hba);
  4854. out_error:
  4855. return err;
  4856. }
  4857. EXPORT_SYMBOL_GPL(ufshcd_init);
  4858. MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
  4859. MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
  4860. MODULE_DESCRIPTION("Generic UFS host controller driver Core");
  4861. MODULE_LICENSE("GPL");
  4862. MODULE_VERSION(UFSHCD_DRIVER_VERSION);