ethernet-rx.c 15 KB

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  1. /**********************************************************************
  2. * Author: Cavium Networks
  3. *
  4. * Contact: support@caviumnetworks.com
  5. * This file is part of the OCTEON SDK
  6. *
  7. * Copyright (c) 2003-2010 Cavium Networks
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this file; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22. * or visit http://www.gnu.org/licenses/.
  23. *
  24. * This file may also be available under a different license from Cavium.
  25. * Contact Cavium Networks for more information
  26. **********************************************************************/
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/cache.h>
  30. #include <linux/cpumask.h>
  31. #include <linux/netdevice.h>
  32. #include <linux/etherdevice.h>
  33. #include <linux/ip.h>
  34. #include <linux/string.h>
  35. #include <linux/prefetch.h>
  36. #include <linux/ratelimit.h>
  37. #include <linux/smp.h>
  38. #include <linux/interrupt.h>
  39. #include <net/dst.h>
  40. #ifdef CONFIG_XFRM
  41. #include <linux/xfrm.h>
  42. #include <net/xfrm.h>
  43. #endif /* CONFIG_XFRM */
  44. #include <linux/atomic.h>
  45. #include <asm/octeon/octeon.h>
  46. #include "ethernet-defines.h"
  47. #include "ethernet-mem.h"
  48. #include "ethernet-rx.h"
  49. #include "octeon-ethernet.h"
  50. #include "ethernet-util.h"
  51. #include <asm/octeon/cvmx-helper.h>
  52. #include <asm/octeon/cvmx-wqe.h>
  53. #include <asm/octeon/cvmx-fau.h>
  54. #include <asm/octeon/cvmx-pow.h>
  55. #include <asm/octeon/cvmx-pip.h>
  56. #include <asm/octeon/cvmx-scratch.h>
  57. #include <asm/octeon/cvmx-gmxx-defs.h>
  58. struct cvm_napi_wrapper {
  59. struct napi_struct napi;
  60. } ____cacheline_aligned_in_smp;
  61. static struct cvm_napi_wrapper cvm_oct_napi[NR_CPUS] __cacheline_aligned_in_smp;
  62. struct cvm_oct_core_state {
  63. int baseline_cores;
  64. /*
  65. * The number of additional cores that could be processing
  66. * input packets.
  67. */
  68. atomic_t available_cores;
  69. cpumask_t cpu_state;
  70. } ____cacheline_aligned_in_smp;
  71. static struct cvm_oct_core_state core_state __cacheline_aligned_in_smp;
  72. static int cvm_irq_cpu;
  73. static void cvm_oct_enable_napi(void *_)
  74. {
  75. int cpu = smp_processor_id();
  76. napi_schedule(&cvm_oct_napi[cpu].napi);
  77. }
  78. static void cvm_oct_enable_one_cpu(void)
  79. {
  80. int v;
  81. int cpu;
  82. /* Check to see if more CPUs are available for receive processing... */
  83. v = atomic_sub_if_positive(1, &core_state.available_cores);
  84. if (v < 0)
  85. return;
  86. /* ... if a CPU is available, Turn on NAPI polling for that CPU. */
  87. for_each_online_cpu(cpu) {
  88. if (!cpu_test_and_set(cpu, core_state.cpu_state)) {
  89. v = smp_call_function_single(cpu, cvm_oct_enable_napi,
  90. NULL, 0);
  91. if (v)
  92. panic("Can't enable NAPI.");
  93. break;
  94. }
  95. }
  96. }
  97. static void cvm_oct_no_more_work(void)
  98. {
  99. int cpu = smp_processor_id();
  100. if (cpu == cvm_irq_cpu) {
  101. enable_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group);
  102. return;
  103. }
  104. cpu_clear(cpu, core_state.cpu_state);
  105. atomic_add(1, &core_state.available_cores);
  106. }
  107. /**
  108. * cvm_oct_do_interrupt - interrupt handler.
  109. *
  110. * The interrupt occurs whenever the POW has packets in our group.
  111. *
  112. */
  113. static irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id)
  114. {
  115. /* Disable the IRQ and start napi_poll. */
  116. disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
  117. cvm_irq_cpu = smp_processor_id();
  118. cvm_oct_enable_napi(NULL);
  119. return IRQ_HANDLED;
  120. }
  121. /**
  122. * cvm_oct_check_rcv_error - process receive errors
  123. * @work: Work queue entry pointing to the packet.
  124. *
  125. * Returns Non-zero if the packet can be dropped, zero otherwise.
  126. */
  127. static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
  128. {
  129. if ((work->word2.snoip.err_code == 10) && (work->len <= 64)) {
  130. /*
  131. * Ignore length errors on min size packets. Some
  132. * equipment incorrectly pads packets to 64+4FCS
  133. * instead of 60+4FCS. Note these packets still get
  134. * counted as frame errors.
  135. */
  136. } else
  137. if (USE_10MBPS_PREAMBLE_WORKAROUND
  138. && ((work->word2.snoip.err_code == 5)
  139. || (work->word2.snoip.err_code == 7))) {
  140. /*
  141. * We received a packet with either an alignment error
  142. * or a FCS error. This may be signalling that we are
  143. * running 10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK]
  144. * off. If this is the case we need to parse the
  145. * packet to determine if we can remove a non spec
  146. * preamble and generate a correct packet.
  147. */
  148. int interface = cvmx_helper_get_interface_num(work->ipprt);
  149. int index = cvmx_helper_get_interface_index_num(work->ipprt);
  150. union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
  151. gmxx_rxx_frm_ctl.u64 =
  152. cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
  153. if (gmxx_rxx_frm_ctl.s.pre_chk == 0) {
  154. uint8_t *ptr =
  155. cvmx_phys_to_ptr(work->packet_ptr.s.addr);
  156. int i = 0;
  157. while (i < work->len - 1) {
  158. if (*ptr != 0x55)
  159. break;
  160. ptr++;
  161. i++;
  162. }
  163. if (*ptr == 0xd5) {
  164. /*
  165. printk_ratelimited("Port %d received 0xd5 preamble\n", work->ipprt);
  166. */
  167. work->packet_ptr.s.addr += i + 1;
  168. work->len -= i + 5;
  169. } else if ((*ptr & 0xf) == 0xd) {
  170. /*
  171. printk_ratelimited("Port %d received 0x?d preamble\n", work->ipprt);
  172. */
  173. work->packet_ptr.s.addr += i;
  174. work->len -= i + 4;
  175. for (i = 0; i < work->len; i++) {
  176. *ptr =
  177. ((*ptr & 0xf0) >> 4) |
  178. ((*(ptr + 1) & 0xf) << 4);
  179. ptr++;
  180. }
  181. } else {
  182. printk_ratelimited("Port %d unknown preamble, packet dropped\n",
  183. work->ipprt);
  184. /*
  185. cvmx_helper_dump_packet(work);
  186. */
  187. cvm_oct_free_work(work);
  188. return 1;
  189. }
  190. }
  191. } else {
  192. printk_ratelimited("Port %d receive error code %d, packet dropped\n",
  193. work->ipprt, work->word2.snoip.err_code);
  194. cvm_oct_free_work(work);
  195. return 1;
  196. }
  197. return 0;
  198. }
  199. /**
  200. * cvm_oct_napi_poll - the NAPI poll function.
  201. * @napi: The NAPI instance, or null if called from cvm_oct_poll_controller
  202. * @budget: Maximum number of packets to receive.
  203. *
  204. * Returns the number of packets processed.
  205. */
  206. static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
  207. {
  208. const int coreid = cvmx_get_core_num();
  209. uint64_t old_group_mask;
  210. uint64_t old_scratch;
  211. int rx_count = 0;
  212. int did_work_request = 0;
  213. int packet_not_copied;
  214. /* Prefetch cvm_oct_device since we know we need it soon */
  215. prefetch(cvm_oct_device);
  216. if (USE_ASYNC_IOBDMA) {
  217. /* Save scratch in case userspace is using it */
  218. CVMX_SYNCIOBDMA;
  219. old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
  220. }
  221. /* Only allow work for our group (and preserve priorities) */
  222. old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
  223. cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
  224. (old_group_mask & ~0xFFFFull) | 1 << pow_receive_group);
  225. if (USE_ASYNC_IOBDMA) {
  226. cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
  227. did_work_request = 1;
  228. }
  229. while (rx_count < budget) {
  230. struct sk_buff *skb = NULL;
  231. struct sk_buff **pskb = NULL;
  232. int skb_in_hw;
  233. cvmx_wqe_t *work;
  234. if (USE_ASYNC_IOBDMA && did_work_request)
  235. work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
  236. else
  237. work = cvmx_pow_work_request_sync(CVMX_POW_NO_WAIT);
  238. prefetch(work);
  239. did_work_request = 0;
  240. if (work == NULL) {
  241. union cvmx_pow_wq_int wq_int;
  242. wq_int.u64 = 0;
  243. wq_int.s.iq_dis = 1 << pow_receive_group;
  244. wq_int.s.wq_int = 1 << pow_receive_group;
  245. cvmx_write_csr(CVMX_POW_WQ_INT, wq_int.u64);
  246. break;
  247. }
  248. pskb = (struct sk_buff **)(cvm_oct_get_buffer_ptr(work->packet_ptr) - sizeof(void *));
  249. prefetch(pskb);
  250. if (USE_ASYNC_IOBDMA && rx_count < (budget - 1)) {
  251. cvmx_pow_work_request_async_nocheck(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
  252. did_work_request = 1;
  253. }
  254. if (rx_count == 0) {
  255. /*
  256. * First time through, see if there is enough
  257. * work waiting to merit waking another
  258. * CPU.
  259. */
  260. union cvmx_pow_wq_int_cntx counts;
  261. int backlog;
  262. int cores_in_use = core_state.baseline_cores - atomic_read(&core_state.available_cores);
  263. counts.u64 = cvmx_read_csr(CVMX_POW_WQ_INT_CNTX(pow_receive_group));
  264. backlog = counts.s.iq_cnt + counts.s.ds_cnt;
  265. if (backlog > budget * cores_in_use && napi != NULL)
  266. cvm_oct_enable_one_cpu();
  267. }
  268. rx_count++;
  269. skb_in_hw = USE_SKBUFFS_IN_HW && work->word2.s.bufs == 1;
  270. if (likely(skb_in_hw)) {
  271. skb = *pskb;
  272. prefetch(&skb->head);
  273. prefetch(&skb->len);
  274. }
  275. prefetch(cvm_oct_device[work->ipprt]);
  276. /* Immediately throw away all packets with receive errors */
  277. if (unlikely(work->word2.snoip.rcv_error)) {
  278. if (cvm_oct_check_rcv_error(work))
  279. continue;
  280. }
  281. /*
  282. * We can only use the zero copy path if skbuffs are
  283. * in the FPA pool and the packet fits in a single
  284. * buffer.
  285. */
  286. if (likely(skb_in_hw)) {
  287. skb->data = skb->head + work->packet_ptr.s.addr - cvmx_ptr_to_phys(skb->head);
  288. prefetch(skb->data);
  289. skb->len = work->len;
  290. skb_set_tail_pointer(skb, skb->len);
  291. packet_not_copied = 1;
  292. } else {
  293. /*
  294. * We have to copy the packet. First allocate
  295. * an skbuff for it.
  296. */
  297. skb = dev_alloc_skb(work->len);
  298. if (!skb) {
  299. cvm_oct_free_work(work);
  300. continue;
  301. }
  302. /*
  303. * Check if we've received a packet that was
  304. * entirely stored in the work entry.
  305. */
  306. if (unlikely(work->word2.s.bufs == 0)) {
  307. uint8_t *ptr = work->packet_data;
  308. if (likely(!work->word2.s.not_IP)) {
  309. /*
  310. * The beginning of the packet
  311. * moves for IP packets.
  312. */
  313. if (work->word2.s.is_v6)
  314. ptr += 2;
  315. else
  316. ptr += 6;
  317. }
  318. memcpy(skb_put(skb, work->len), ptr, work->len);
  319. /* No packet buffers to free */
  320. } else {
  321. int segments = work->word2.s.bufs;
  322. union cvmx_buf_ptr segment_ptr = work->packet_ptr;
  323. int len = work->len;
  324. while (segments--) {
  325. union cvmx_buf_ptr next_ptr =
  326. *(union cvmx_buf_ptr *)cvmx_phys_to_ptr(segment_ptr.s.addr - 8);
  327. /*
  328. * Octeon Errata PKI-100: The segment size is
  329. * wrong. Until it is fixed, calculate the
  330. * segment size based on the packet pool
  331. * buffer size. When it is fixed, the
  332. * following line should be replaced with this
  333. * one: int segment_size =
  334. * segment_ptr.s.size;
  335. */
  336. int segment_size = CVMX_FPA_PACKET_POOL_SIZE -
  337. (segment_ptr.s.addr - (((segment_ptr.s.addr >> 7) - segment_ptr.s.back) << 7));
  338. /*
  339. * Don't copy more than what
  340. * is left in the packet.
  341. */
  342. if (segment_size > len)
  343. segment_size = len;
  344. /* Copy the data into the packet */
  345. memcpy(skb_put(skb, segment_size),
  346. cvmx_phys_to_ptr(segment_ptr.s.addr),
  347. segment_size);
  348. len -= segment_size;
  349. segment_ptr = next_ptr;
  350. }
  351. }
  352. packet_not_copied = 0;
  353. }
  354. if (likely((work->ipprt < TOTAL_NUMBER_OF_PORTS) &&
  355. cvm_oct_device[work->ipprt])) {
  356. struct net_device *dev = cvm_oct_device[work->ipprt];
  357. struct octeon_ethernet *priv = netdev_priv(dev);
  358. /*
  359. * Only accept packets for devices that are
  360. * currently up.
  361. */
  362. if (likely(dev->flags & IFF_UP)) {
  363. skb->protocol = eth_type_trans(skb, dev);
  364. skb->dev = dev;
  365. if (unlikely(work->word2.s.not_IP || work->word2.s.IP_exc ||
  366. work->word2.s.L4_error || !work->word2.s.tcp_or_udp))
  367. skb->ip_summed = CHECKSUM_NONE;
  368. else
  369. skb->ip_summed = CHECKSUM_UNNECESSARY;
  370. /* Increment RX stats for virtual ports */
  371. if (work->ipprt >= CVMX_PIP_NUM_INPUT_PORTS) {
  372. #ifdef CONFIG_64BIT
  373. atomic64_add(1, (atomic64_t *)&priv->stats.rx_packets);
  374. atomic64_add(skb->len, (atomic64_t *)&priv->stats.rx_bytes);
  375. #else
  376. atomic_add(1, (atomic_t *)&priv->stats.rx_packets);
  377. atomic_add(skb->len, (atomic_t *)&priv->stats.rx_bytes);
  378. #endif
  379. }
  380. netif_receive_skb(skb);
  381. } else {
  382. /* Drop any packet received for a device that isn't up */
  383. /*
  384. printk_ratelimited("%s: Device not up, packet dropped\n",
  385. dev->name);
  386. */
  387. #ifdef CONFIG_64BIT
  388. atomic64_add(1, (atomic64_t *)&priv->stats.rx_dropped);
  389. #else
  390. atomic_add(1, (atomic_t *)&priv->stats.rx_dropped);
  391. #endif
  392. dev_kfree_skb_irq(skb);
  393. }
  394. } else {
  395. /*
  396. * Drop any packet received for a device that
  397. * doesn't exist.
  398. */
  399. printk_ratelimited("Port %d not controlled by Linux, packet dropped\n",
  400. work->ipprt);
  401. dev_kfree_skb_irq(skb);
  402. }
  403. /*
  404. * Check to see if the skbuff and work share the same
  405. * packet buffer.
  406. */
  407. if (USE_SKBUFFS_IN_HW && likely(packet_not_copied)) {
  408. /*
  409. * This buffer needs to be replaced, increment
  410. * the number of buffers we need to free by
  411. * one.
  412. */
  413. cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE,
  414. 1);
  415. cvmx_fpa_free(work, CVMX_FPA_WQE_POOL,
  416. DONT_WRITEBACK(1));
  417. } else {
  418. cvm_oct_free_work(work);
  419. }
  420. }
  421. /* Restore the original POW group mask */
  422. cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
  423. if (USE_ASYNC_IOBDMA) {
  424. /* Restore the scratch area */
  425. cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
  426. }
  427. cvm_oct_rx_refill_pool(0);
  428. if (rx_count < budget && napi != NULL) {
  429. /* No more work */
  430. napi_complete(napi);
  431. cvm_oct_no_more_work();
  432. }
  433. return rx_count;
  434. }
  435. #ifdef CONFIG_NET_POLL_CONTROLLER
  436. /**
  437. * cvm_oct_poll_controller - poll for receive packets
  438. * device.
  439. *
  440. * @dev: Device to poll. Unused
  441. */
  442. void cvm_oct_poll_controller(struct net_device *dev)
  443. {
  444. cvm_oct_napi_poll(NULL, 16);
  445. }
  446. #endif
  447. void cvm_oct_rx_initialize(void)
  448. {
  449. int i;
  450. struct net_device *dev_for_napi = NULL;
  451. union cvmx_pow_wq_int_thrx int_thr;
  452. union cvmx_pow_wq_int_pc int_pc;
  453. for (i = 0; i < TOTAL_NUMBER_OF_PORTS; i++) {
  454. if (cvm_oct_device[i]) {
  455. dev_for_napi = cvm_oct_device[i];
  456. break;
  457. }
  458. }
  459. if (NULL == dev_for_napi)
  460. panic("No net_devices were allocated.");
  461. if (max_rx_cpus >= 1 && max_rx_cpus < num_online_cpus())
  462. atomic_set(&core_state.available_cores, max_rx_cpus);
  463. else
  464. atomic_set(&core_state.available_cores, num_online_cpus());
  465. core_state.baseline_cores = atomic_read(&core_state.available_cores);
  466. core_state.cpu_state = CPU_MASK_NONE;
  467. for_each_possible_cpu(i) {
  468. netif_napi_add(dev_for_napi, &cvm_oct_napi[i].napi,
  469. cvm_oct_napi_poll, rx_napi_weight);
  470. napi_enable(&cvm_oct_napi[i].napi);
  471. }
  472. /* Register an IRQ handler to receive POW interrupts */
  473. i = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
  474. cvm_oct_do_interrupt, 0, "Ethernet", cvm_oct_device);
  475. if (i)
  476. panic("Could not acquire Ethernet IRQ %d\n",
  477. OCTEON_IRQ_WORKQ0 + pow_receive_group);
  478. disable_irq_nosync(OCTEON_IRQ_WORKQ0 + pow_receive_group);
  479. int_thr.u64 = 0;
  480. int_thr.s.tc_en = 1;
  481. int_thr.s.tc_thr = 1;
  482. /* Enable POW interrupt when our port has at least one packet */
  483. cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), int_thr.u64);
  484. int_pc.u64 = 0;
  485. int_pc.s.pc_thr = 5;
  486. cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);
  487. /* Scheduld NAPI now. This will indirectly enable interrupts. */
  488. cvm_oct_enable_one_cpu();
  489. }
  490. void cvm_oct_rx_shutdown(void)
  491. {
  492. int i;
  493. /* Shutdown all of the NAPIs */
  494. for_each_possible_cpu(i)
  495. netif_napi_del(&cvm_oct_napi[i].napi);
  496. }