ms.c 101 KB

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  1. /* Driver for Realtek PCI-Express card reader
  2. *
  3. * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2, or (at your option) any
  8. * later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * Author:
  19. * Wei WANG (wei_wang@realsil.com.cn)
  20. * Micky Ching (micky_ching@realsil.com.cn)
  21. */
  22. #include <linux/blkdev.h>
  23. #include <linux/kthread.h>
  24. #include <linux/sched.h>
  25. #include <linux/vmalloc.h>
  26. #include "rtsx.h"
  27. #include "rtsx_transport.h"
  28. #include "rtsx_scsi.h"
  29. #include "rtsx_card.h"
  30. #include "ms.h"
  31. static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
  32. {
  33. struct ms_info *ms_card = &(chip->ms_card);
  34. ms_card->err_code = err_code;
  35. }
  36. static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
  37. {
  38. struct ms_info *ms_card = &(chip->ms_card);
  39. return (ms_card->err_code == err_code);
  40. }
  41. static int ms_parse_err_code(struct rtsx_chip *chip)
  42. {
  43. TRACE_RET(chip, STATUS_FAIL);
  44. }
  45. static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode,
  46. u8 tpc, u8 cnt, u8 cfg)
  47. {
  48. struct ms_info *ms_card = &(chip->ms_card);
  49. int retval;
  50. u8 *ptr;
  51. dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc);
  52. rtsx_init_cmd(chip);
  53. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
  54. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
  55. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
  56. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
  57. 0x01, PINGPONG_BUFFER);
  58. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER,
  59. 0xFF, MS_TRANSFER_START | trans_mode);
  60. rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
  61. MS_TRANSFER_END, MS_TRANSFER_END);
  62. rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
  63. retval = rtsx_send_cmd(chip, MS_CARD, 5000);
  64. if (retval < 0) {
  65. rtsx_clear_ms_error(chip);
  66. ms_set_err_code(chip, MS_TO_ERROR);
  67. TRACE_RET(chip, ms_parse_err_code(chip));
  68. }
  69. ptr = rtsx_get_cmd_data(chip) + 1;
  70. if (!(tpc & 0x08)) { /* Read Packet */
  71. if (*ptr & MS_CRC16_ERR) {
  72. ms_set_err_code(chip, MS_CRC16_ERROR);
  73. TRACE_RET(chip, ms_parse_err_code(chip));
  74. }
  75. } else { /* Write Packet */
  76. if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
  77. if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
  78. ms_set_err_code(chip, MS_CMD_NK);
  79. TRACE_RET(chip, ms_parse_err_code(chip));
  80. }
  81. }
  82. }
  83. if (*ptr & MS_RDY_TIMEOUT) {
  84. rtsx_clear_ms_error(chip);
  85. ms_set_err_code(chip, MS_TO_ERROR);
  86. TRACE_RET(chip, ms_parse_err_code(chip));
  87. }
  88. return STATUS_SUCCESS;
  89. }
  90. static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode,
  91. u8 tpc, u16 sec_cnt, u8 cfg, int mode_2k,
  92. int use_sg, void *buf, int buf_len)
  93. {
  94. int retval;
  95. u8 val, err_code = 0;
  96. enum dma_data_direction dir;
  97. if (!buf || !buf_len)
  98. TRACE_RET(chip, STATUS_FAIL);
  99. if (trans_mode == MS_TM_AUTO_READ) {
  100. dir = DMA_FROM_DEVICE;
  101. err_code = MS_FLASH_READ_ERROR;
  102. } else if (trans_mode == MS_TM_AUTO_WRITE) {
  103. dir = DMA_TO_DEVICE;
  104. err_code = MS_FLASH_WRITE_ERROR;
  105. } else {
  106. TRACE_RET(chip, STATUS_FAIL);
  107. }
  108. rtsx_init_cmd(chip);
  109. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
  110. rtsx_add_cmd(chip, WRITE_REG_CMD,
  111. MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
  112. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
  113. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
  114. if (mode_2k) {
  115. rtsx_add_cmd(chip, WRITE_REG_CMD,
  116. MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
  117. } else {
  118. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
  119. }
  120. trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
  121. rtsx_add_cmd(chip, WRITE_REG_CMD,
  122. MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
  123. rtsx_add_cmd(chip, CHECK_REG_CMD,
  124. MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
  125. rtsx_send_cmd_no_wait(chip);
  126. retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len,
  127. use_sg, dir, chip->mspro_timeout);
  128. if (retval < 0) {
  129. ms_set_err_code(chip, err_code);
  130. if (retval == -ETIMEDOUT)
  131. retval = STATUS_TIMEDOUT;
  132. else
  133. retval = STATUS_FAIL;
  134. TRACE_RET(chip, retval);
  135. }
  136. RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
  137. if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT))
  138. TRACE_RET(chip, STATUS_FAIL);
  139. return STATUS_SUCCESS;
  140. }
  141. static int ms_write_bytes(struct rtsx_chip *chip,
  142. u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
  143. {
  144. struct ms_info *ms_card = &(chip->ms_card);
  145. int retval, i;
  146. if (!data || (data_len < cnt))
  147. TRACE_RET(chip, STATUS_ERROR);
  148. rtsx_init_cmd(chip);
  149. for (i = 0; i < cnt; i++) {
  150. rtsx_add_cmd(chip, WRITE_REG_CMD,
  151. PPBUF_BASE2 + i, 0xFF, data[i]);
  152. }
  153. if (cnt % 2)
  154. rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
  155. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
  156. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
  157. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
  158. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
  159. 0x01, PINGPONG_BUFFER);
  160. rtsx_add_cmd(chip, WRITE_REG_CMD,
  161. MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
  162. rtsx_add_cmd(chip, CHECK_REG_CMD,
  163. MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
  164. retval = rtsx_send_cmd(chip, MS_CARD, 5000);
  165. if (retval < 0) {
  166. u8 val = 0;
  167. rtsx_read_register(chip, MS_TRANS_CFG, &val);
  168. dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val);
  169. rtsx_clear_ms_error(chip);
  170. if (!(tpc & 0x08)) {
  171. if (val & MS_CRC16_ERR) {
  172. ms_set_err_code(chip, MS_CRC16_ERROR);
  173. TRACE_RET(chip, ms_parse_err_code(chip));
  174. }
  175. } else {
  176. if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
  177. if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
  178. ms_set_err_code(chip, MS_CMD_NK);
  179. TRACE_RET(chip,
  180. ms_parse_err_code(chip));
  181. }
  182. }
  183. }
  184. if (val & MS_RDY_TIMEOUT) {
  185. ms_set_err_code(chip, MS_TO_ERROR);
  186. TRACE_RET(chip, ms_parse_err_code(chip));
  187. }
  188. ms_set_err_code(chip, MS_TO_ERROR);
  189. TRACE_RET(chip, ms_parse_err_code(chip));
  190. }
  191. return STATUS_SUCCESS;
  192. }
  193. static int ms_read_bytes(struct rtsx_chip *chip,
  194. u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
  195. {
  196. struct ms_info *ms_card = &(chip->ms_card);
  197. int retval, i;
  198. u8 *ptr;
  199. if (!data)
  200. TRACE_RET(chip, STATUS_ERROR);
  201. rtsx_init_cmd(chip);
  202. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
  203. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
  204. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
  205. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
  206. 0x01, PINGPONG_BUFFER);
  207. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
  208. MS_TRANSFER_START | MS_TM_READ_BYTES);
  209. rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
  210. MS_TRANSFER_END, MS_TRANSFER_END);
  211. for (i = 0; i < data_len - 1; i++)
  212. rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
  213. if (data_len % 2)
  214. rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
  215. else
  216. rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
  217. 0, 0);
  218. retval = rtsx_send_cmd(chip, MS_CARD, 5000);
  219. if (retval < 0) {
  220. u8 val = 0;
  221. rtsx_read_register(chip, MS_TRANS_CFG, &val);
  222. rtsx_clear_ms_error(chip);
  223. if (!(tpc & 0x08)) {
  224. if (val & MS_CRC16_ERR) {
  225. ms_set_err_code(chip, MS_CRC16_ERROR);
  226. TRACE_RET(chip, ms_parse_err_code(chip));
  227. }
  228. } else {
  229. if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
  230. if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
  231. ms_set_err_code(chip, MS_CMD_NK);
  232. TRACE_RET(chip,
  233. ms_parse_err_code(chip));
  234. }
  235. }
  236. }
  237. if (val & MS_RDY_TIMEOUT) {
  238. ms_set_err_code(chip, MS_TO_ERROR);
  239. TRACE_RET(chip, ms_parse_err_code(chip));
  240. }
  241. ms_set_err_code(chip, MS_TO_ERROR);
  242. TRACE_RET(chip, ms_parse_err_code(chip));
  243. }
  244. ptr = rtsx_get_cmd_data(chip) + 1;
  245. for (i = 0; i < data_len; i++)
  246. data[i] = ptr[i];
  247. if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
  248. dev_dbg(rtsx_dev(chip), "Read format progress:\n");
  249. print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr,
  250. cnt);
  251. }
  252. return STATUS_SUCCESS;
  253. }
  254. static int ms_set_rw_reg_addr(struct rtsx_chip *chip,
  255. u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
  256. {
  257. int retval, i;
  258. u8 data[4];
  259. data[0] = read_start;
  260. data[1] = read_cnt;
  261. data[2] = write_start;
  262. data[3] = write_cnt;
  263. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  264. retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4,
  265. NO_WAIT_INT, data, 4);
  266. if (retval == STATUS_SUCCESS)
  267. return STATUS_SUCCESS;
  268. rtsx_clear_ms_error(chip);
  269. }
  270. TRACE_RET(chip, STATUS_FAIL);
  271. }
  272. static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
  273. {
  274. u8 data[2];
  275. data[0] = cmd;
  276. data[1] = 0;
  277. return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
  278. }
  279. static int ms_set_init_para(struct rtsx_chip *chip)
  280. {
  281. struct ms_info *ms_card = &(chip->ms_card);
  282. int retval;
  283. if (CHK_HG8BIT(ms_card)) {
  284. if (chip->asic_code)
  285. ms_card->ms_clock = chip->asic_ms_hg_clk;
  286. else
  287. ms_card->ms_clock = chip->fpga_ms_hg_clk;
  288. } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
  289. if (chip->asic_code)
  290. ms_card->ms_clock = chip->asic_ms_4bit_clk;
  291. else
  292. ms_card->ms_clock = chip->fpga_ms_4bit_clk;
  293. } else {
  294. if (chip->asic_code)
  295. ms_card->ms_clock = chip->asic_ms_1bit_clk;
  296. else
  297. ms_card->ms_clock = chip->fpga_ms_1bit_clk;
  298. }
  299. retval = switch_clock(chip, ms_card->ms_clock);
  300. if (retval != STATUS_SUCCESS)
  301. TRACE_RET(chip, STATUS_FAIL);
  302. retval = select_card(chip, MS_CARD);
  303. if (retval != STATUS_SUCCESS)
  304. TRACE_RET(chip, STATUS_FAIL);
  305. return STATUS_SUCCESS;
  306. }
  307. static int ms_switch_clock(struct rtsx_chip *chip)
  308. {
  309. struct ms_info *ms_card = &(chip->ms_card);
  310. int retval;
  311. retval = select_card(chip, MS_CARD);
  312. if (retval != STATUS_SUCCESS)
  313. TRACE_RET(chip, STATUS_FAIL);
  314. retval = switch_clock(chip, ms_card->ms_clock);
  315. if (retval != STATUS_SUCCESS)
  316. TRACE_RET(chip, STATUS_FAIL);
  317. return STATUS_SUCCESS;
  318. }
  319. static int ms_pull_ctl_disable(struct rtsx_chip *chip)
  320. {
  321. if (CHECK_PID(chip, 0x5208)) {
  322. RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
  323. MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD);
  324. RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
  325. MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD);
  326. RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
  327. MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
  328. RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
  329. XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
  330. RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
  331. MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
  332. RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF,
  333. MS_D5_PD | MS_D4_PD);
  334. } else if (CHECK_PID(chip, 0x5288)) {
  335. if (CHECK_BARO_PKG(chip, QFN)) {
  336. RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
  337. RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
  338. RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
  339. RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
  340. }
  341. }
  342. return STATUS_SUCCESS;
  343. }
  344. static int ms_pull_ctl_enable(struct rtsx_chip *chip)
  345. {
  346. int retval;
  347. rtsx_init_cmd(chip);
  348. if (CHECK_PID(chip, 0x5208)) {
  349. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
  350. MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD);
  351. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
  352. MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD);
  353. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
  354. MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
  355. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
  356. XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
  357. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
  358. MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
  359. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
  360. MS_D5_PD | MS_D4_PD);
  361. } else if (CHECK_PID(chip, 0x5288)) {
  362. if (CHECK_BARO_PKG(chip, QFN)) {
  363. rtsx_add_cmd(chip, WRITE_REG_CMD,
  364. CARD_PULL_CTL1, 0xFF, 0x55);
  365. rtsx_add_cmd(chip, WRITE_REG_CMD,
  366. CARD_PULL_CTL2, 0xFF, 0x45);
  367. rtsx_add_cmd(chip, WRITE_REG_CMD,
  368. CARD_PULL_CTL3, 0xFF, 0x4B);
  369. rtsx_add_cmd(chip, WRITE_REG_CMD,
  370. CARD_PULL_CTL4, 0xFF, 0x29);
  371. }
  372. }
  373. retval = rtsx_send_cmd(chip, MS_CARD, 100);
  374. if (retval < 0)
  375. TRACE_RET(chip, STATUS_FAIL);
  376. return STATUS_SUCCESS;
  377. }
  378. static int ms_prepare_reset(struct rtsx_chip *chip)
  379. {
  380. struct ms_info *ms_card = &(chip->ms_card);
  381. int retval;
  382. u8 oc_mask = 0;
  383. ms_card->ms_type = 0;
  384. ms_card->check_ms_flow = 0;
  385. ms_card->switch_8bit_fail = 0;
  386. ms_card->delay_write.delay_write_flag = 0;
  387. ms_card->pro_under_formatting = 0;
  388. retval = ms_power_off_card3v3(chip);
  389. if (retval != STATUS_SUCCESS)
  390. TRACE_RET(chip, STATUS_FAIL);
  391. if (!chip->ft2_fast_mode)
  392. wait_timeout(250);
  393. retval = enable_card_clock(chip, MS_CARD);
  394. if (retval != STATUS_SUCCESS)
  395. TRACE_RET(chip, STATUS_FAIL);
  396. if (chip->asic_code) {
  397. retval = ms_pull_ctl_enable(chip);
  398. if (retval != STATUS_SUCCESS)
  399. TRACE_RET(chip, STATUS_FAIL);
  400. } else {
  401. RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
  402. FPGA_MS_PULL_CTL_BIT | 0x20, 0);
  403. }
  404. if (!chip->ft2_fast_mode) {
  405. retval = card_power_on(chip, MS_CARD);
  406. if (retval != STATUS_SUCCESS)
  407. TRACE_RET(chip, STATUS_FAIL);
  408. wait_timeout(150);
  409. #ifdef SUPPORT_OCP
  410. if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
  411. oc_mask = MS_OC_NOW | MS_OC_EVER;
  412. else
  413. oc_mask = SD_OC_NOW | SD_OC_EVER;
  414. if (chip->ocp_stat & oc_mask) {
  415. dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
  416. chip->ocp_stat);
  417. TRACE_RET(chip, STATUS_FAIL);
  418. }
  419. #endif
  420. }
  421. RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, MS_OUTPUT_EN);
  422. if (chip->asic_code) {
  423. RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
  424. SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |
  425. NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
  426. } else {
  427. RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
  428. SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |
  429. NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
  430. }
  431. RTSX_WRITE_REG(chip, MS_TRANS_CFG,
  432. 0xFF, NO_WAIT_INT | NO_AUTO_READ_INT_REG);
  433. RTSX_WRITE_REG(chip, CARD_STOP,
  434. MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
  435. retval = ms_set_init_para(chip);
  436. if (retval != STATUS_SUCCESS)
  437. TRACE_RET(chip, STATUS_FAIL);
  438. return STATUS_SUCCESS;
  439. }
  440. static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
  441. {
  442. struct ms_info *ms_card = &(chip->ms_card);
  443. int retval, i;
  444. u8 val;
  445. retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
  446. if (retval != STATUS_SUCCESS)
  447. TRACE_RET(chip, STATUS_FAIL);
  448. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  449. retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG,
  450. 6, NO_WAIT_INT);
  451. if (retval == STATUS_SUCCESS)
  452. break;
  453. }
  454. if (i == MS_MAX_RETRY_COUNT)
  455. TRACE_RET(chip, STATUS_FAIL);
  456. RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val);
  457. dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val);
  458. if (val != 0x01) {
  459. if (val != 0x02)
  460. ms_card->check_ms_flow = 1;
  461. TRACE_RET(chip, STATUS_FAIL);
  462. }
  463. RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val);
  464. dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val);
  465. if (val != 0) {
  466. ms_card->check_ms_flow = 1;
  467. TRACE_RET(chip, STATUS_FAIL);
  468. }
  469. RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val);
  470. dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val);
  471. if (val == 0) {
  472. RTSX_READ_REG(chip, PPBUF_BASE2, &val);
  473. if (val & WRT_PRTCT)
  474. chip->card_wp |= MS_CARD;
  475. else
  476. chip->card_wp &= ~MS_CARD;
  477. } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
  478. chip->card_wp |= MS_CARD;
  479. } else {
  480. ms_card->check_ms_flow = 1;
  481. TRACE_RET(chip, STATUS_FAIL);
  482. }
  483. ms_card->ms_type |= TYPE_MSPRO;
  484. RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val);
  485. dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val);
  486. if (val == 0) {
  487. ms_card->ms_type &= 0x0F;
  488. } else if (val == 7) {
  489. if (switch_8bit_bus)
  490. ms_card->ms_type |= MS_HG;
  491. else
  492. ms_card->ms_type &= 0x0F;
  493. } else {
  494. TRACE_RET(chip, STATUS_FAIL);
  495. }
  496. return STATUS_SUCCESS;
  497. }
  498. static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
  499. {
  500. int retval, i, k;
  501. u8 val;
  502. /* Confirm CPU StartUp */
  503. k = 0;
  504. do {
  505. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  506. ms_set_err_code(chip, MS_NO_CARD);
  507. TRACE_RET(chip, STATUS_FAIL);
  508. }
  509. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  510. retval = ms_read_bytes(chip, GET_INT, 1,
  511. NO_WAIT_INT, &val, 1);
  512. if (retval == STATUS_SUCCESS)
  513. break;
  514. }
  515. if (i == MS_MAX_RETRY_COUNT)
  516. TRACE_RET(chip, STATUS_FAIL);
  517. if (k > 100)
  518. TRACE_RET(chip, STATUS_FAIL);
  519. k++;
  520. wait_timeout(100);
  521. } while (!(val & INT_REG_CED));
  522. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  523. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  524. if (retval == STATUS_SUCCESS)
  525. break;
  526. }
  527. if (i == MS_MAX_RETRY_COUNT)
  528. TRACE_RET(chip, STATUS_FAIL);
  529. if (val & INT_REG_ERR) {
  530. if (val & INT_REG_CMDNK)
  531. chip->card_wp |= (MS_CARD);
  532. else
  533. TRACE_RET(chip, STATUS_FAIL);
  534. }
  535. /* -- end confirm CPU startup */
  536. return STATUS_SUCCESS;
  537. }
  538. static int ms_switch_parallel_bus(struct rtsx_chip *chip)
  539. {
  540. int retval, i;
  541. u8 data[2];
  542. data[0] = PARALLEL_4BIT_IF;
  543. data[1] = 0;
  544. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  545. retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT,
  546. data, 2);
  547. if (retval == STATUS_SUCCESS)
  548. break;
  549. }
  550. if (retval != STATUS_SUCCESS)
  551. TRACE_RET(chip, STATUS_FAIL);
  552. return STATUS_SUCCESS;
  553. }
  554. static int ms_switch_8bit_bus(struct rtsx_chip *chip)
  555. {
  556. struct ms_info *ms_card = &(chip->ms_card);
  557. int retval, i;
  558. u8 data[2];
  559. data[0] = PARALLEL_8BIT_IF;
  560. data[1] = 0;
  561. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  562. retval = ms_write_bytes(chip, WRITE_REG, 1,
  563. NO_WAIT_INT, data, 2);
  564. if (retval == STATUS_SUCCESS)
  565. break;
  566. }
  567. if (retval != STATUS_SUCCESS)
  568. TRACE_RET(chip, STATUS_FAIL);
  569. RTSX_WRITE_REG(chip, MS_CFG, 0x98,
  570. MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
  571. ms_card->ms_type |= MS_8BIT;
  572. retval = ms_set_init_para(chip);
  573. if (retval != STATUS_SUCCESS)
  574. TRACE_RET(chip, STATUS_FAIL);
  575. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  576. retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT,
  577. 1, NO_WAIT_INT);
  578. if (retval != STATUS_SUCCESS)
  579. TRACE_RET(chip, STATUS_FAIL);
  580. }
  581. return STATUS_SUCCESS;
  582. }
  583. static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
  584. {
  585. struct ms_info *ms_card = &(chip->ms_card);
  586. int retval, i;
  587. for (i = 0; i < 3; i++) {
  588. retval = ms_prepare_reset(chip);
  589. if (retval != STATUS_SUCCESS)
  590. TRACE_RET(chip, STATUS_FAIL);
  591. retval = ms_identify_media_type(chip, switch_8bit_bus);
  592. if (retval != STATUS_SUCCESS)
  593. TRACE_RET(chip, STATUS_FAIL);
  594. retval = ms_confirm_cpu_startup(chip);
  595. if (retval != STATUS_SUCCESS)
  596. TRACE_RET(chip, STATUS_FAIL);
  597. retval = ms_switch_parallel_bus(chip);
  598. if (retval != STATUS_SUCCESS) {
  599. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  600. ms_set_err_code(chip, MS_NO_CARD);
  601. TRACE_RET(chip, STATUS_FAIL);
  602. }
  603. continue;
  604. } else {
  605. break;
  606. }
  607. }
  608. if (retval != STATUS_SUCCESS)
  609. TRACE_RET(chip, STATUS_FAIL);
  610. /* Switch MS-PRO into Parallel mode */
  611. RTSX_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
  612. RTSX_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
  613. retval = ms_set_init_para(chip);
  614. if (retval != STATUS_SUCCESS)
  615. TRACE_RET(chip, STATUS_FAIL);
  616. /* If MSPro HG Card, We shall try to switch to 8-bit bus */
  617. if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) {
  618. retval = ms_switch_8bit_bus(chip);
  619. if (retval != STATUS_SUCCESS) {
  620. ms_card->switch_8bit_fail = 1;
  621. TRACE_RET(chip, STATUS_FAIL);
  622. }
  623. }
  624. return STATUS_SUCCESS;
  625. }
  626. #ifdef XC_POWERCLASS
  627. static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
  628. {
  629. int retval;
  630. u8 buf[6];
  631. ms_cleanup_work(chip);
  632. retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
  633. if (retval != STATUS_SUCCESS)
  634. TRACE_RET(chip, STATUS_FAIL);
  635. buf[0] = 0;
  636. buf[1] = mode;
  637. buf[2] = 0;
  638. buf[3] = 0;
  639. buf[4] = 0;
  640. buf[5] = 0;
  641. retval = ms_write_bytes(chip, PRO_WRITE_REG , 6, NO_WAIT_INT, buf, 6);
  642. if (retval != STATUS_SUCCESS)
  643. TRACE_RET(chip, STATUS_FAIL);
  644. retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
  645. if (retval != STATUS_SUCCESS)
  646. TRACE_RET(chip, STATUS_FAIL);
  647. RTSX_READ_REG(chip, MS_TRANS_CFG, buf);
  648. if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR))
  649. TRACE_RET(chip, STATUS_FAIL);
  650. return STATUS_SUCCESS;
  651. }
  652. #endif
  653. static int ms_read_attribute_info(struct rtsx_chip *chip)
  654. {
  655. struct ms_info *ms_card = &(chip->ms_card);
  656. int retval, i;
  657. u8 val, *buf, class_code, device_type, sub_class, data[16];
  658. u16 total_blk = 0, blk_size = 0;
  659. #ifdef SUPPORT_MSXC
  660. u32 xc_total_blk = 0, xc_blk_size = 0;
  661. #endif
  662. u32 sys_info_addr = 0, sys_info_size;
  663. #ifdef SUPPORT_PCGL_1P18
  664. u32 model_name_addr = 0, model_name_size;
  665. int found_sys_info = 0, found_model_name = 0;
  666. #endif
  667. retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
  668. if (retval != STATUS_SUCCESS)
  669. TRACE_RET(chip, STATUS_FAIL);
  670. if (CHK_MS8BIT(ms_card))
  671. data[0] = PARALLEL_8BIT_IF;
  672. else
  673. data[0] = PARALLEL_4BIT_IF;
  674. data[1] = 0;
  675. data[2] = 0x40;
  676. data[3] = 0;
  677. data[4] = 0;
  678. data[5] = 0;
  679. data[6] = 0;
  680. data[7] = 0;
  681. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  682. retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT,
  683. data, 8);
  684. if (retval == STATUS_SUCCESS)
  685. break;
  686. }
  687. if (retval != STATUS_SUCCESS)
  688. TRACE_RET(chip, STATUS_FAIL);
  689. buf = kmalloc(64 * 512, GFP_KERNEL);
  690. if (buf == NULL)
  691. TRACE_RET(chip, STATUS_ERROR);
  692. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  693. retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
  694. if (retval != STATUS_SUCCESS)
  695. continue;
  696. retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
  697. if (retval != STATUS_SUCCESS) {
  698. kfree(buf);
  699. TRACE_RET(chip, STATUS_FAIL);
  700. }
  701. if (!(val & MS_INT_BREQ)) {
  702. kfree(buf);
  703. TRACE_RET(chip, STATUS_FAIL);
  704. }
  705. retval = ms_transfer_data(chip, MS_TM_AUTO_READ,
  706. PRO_READ_LONG_DATA, 0x40, WAIT_INT,
  707. 0, 0, buf, 64 * 512);
  708. if (retval == STATUS_SUCCESS)
  709. break;
  710. rtsx_clear_ms_error(chip);
  711. }
  712. if (retval != STATUS_SUCCESS) {
  713. kfree(buf);
  714. TRACE_RET(chip, STATUS_FAIL);
  715. }
  716. i = 0;
  717. do {
  718. retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
  719. if (retval != STATUS_SUCCESS) {
  720. kfree(buf);
  721. TRACE_RET(chip, STATUS_FAIL);
  722. }
  723. if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
  724. break;
  725. retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ,
  726. PRO_READ_LONG_DATA, 0, WAIT_INT);
  727. if (retval != STATUS_SUCCESS) {
  728. kfree(buf);
  729. TRACE_RET(chip, STATUS_FAIL);
  730. }
  731. i++;
  732. } while (i < 1024);
  733. if (retval != STATUS_SUCCESS) {
  734. kfree(buf);
  735. TRACE_RET(chip, STATUS_FAIL);
  736. }
  737. if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
  738. /* Signature code is wrong */
  739. kfree(buf);
  740. TRACE_RET(chip, STATUS_FAIL);
  741. }
  742. if ((buf[4] < 1) || (buf[4] > 12)) {
  743. kfree(buf);
  744. TRACE_RET(chip, STATUS_FAIL);
  745. }
  746. for (i = 0; i < buf[4]; i++) {
  747. int cur_addr_off = 16 + i * 12;
  748. #ifdef SUPPORT_MSXC
  749. if ((buf[cur_addr_off + 8] == 0x10) ||
  750. (buf[cur_addr_off + 8] == 0x13))
  751. #else
  752. if (buf[cur_addr_off + 8] == 0x10)
  753. #endif
  754. {
  755. sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
  756. ((u32)buf[cur_addr_off + 1] << 16) |
  757. ((u32)buf[cur_addr_off + 2] << 8) |
  758. buf[cur_addr_off + 3];
  759. sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
  760. ((u32)buf[cur_addr_off + 5] << 16) |
  761. ((u32)buf[cur_addr_off + 6] << 8) |
  762. buf[cur_addr_off + 7];
  763. dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
  764. sys_info_addr, sys_info_size);
  765. if (sys_info_size != 96) {
  766. kfree(buf);
  767. TRACE_RET(chip, STATUS_FAIL);
  768. }
  769. if (sys_info_addr < 0x1A0) {
  770. kfree(buf);
  771. TRACE_RET(chip, STATUS_FAIL);
  772. }
  773. if ((sys_info_size + sys_info_addr) > 0x8000) {
  774. kfree(buf);
  775. TRACE_RET(chip, STATUS_FAIL);
  776. }
  777. #ifdef SUPPORT_MSXC
  778. if (buf[cur_addr_off + 8] == 0x13)
  779. ms_card->ms_type |= MS_XC;
  780. #endif
  781. #ifdef SUPPORT_PCGL_1P18
  782. found_sys_info = 1;
  783. #else
  784. break;
  785. #endif
  786. }
  787. #ifdef SUPPORT_PCGL_1P18
  788. if (buf[cur_addr_off + 8] == 0x15) {
  789. model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
  790. ((u32)buf[cur_addr_off + 1] << 16) |
  791. ((u32)buf[cur_addr_off + 2] << 8) |
  792. buf[cur_addr_off + 3];
  793. model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
  794. ((u32)buf[cur_addr_off + 5] << 16) |
  795. ((u32)buf[cur_addr_off + 6] << 8) |
  796. buf[cur_addr_off + 7];
  797. dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n",
  798. model_name_addr, model_name_size);
  799. if (model_name_size != 48) {
  800. kfree(buf);
  801. TRACE_RET(chip, STATUS_FAIL);
  802. }
  803. if (model_name_addr < 0x1A0) {
  804. kfree(buf);
  805. TRACE_RET(chip, STATUS_FAIL);
  806. }
  807. if ((model_name_size + model_name_addr) > 0x8000) {
  808. kfree(buf);
  809. TRACE_RET(chip, STATUS_FAIL);
  810. }
  811. found_model_name = 1;
  812. }
  813. if (found_sys_info && found_model_name)
  814. break;
  815. #endif
  816. }
  817. if (i == buf[4]) {
  818. kfree(buf);
  819. TRACE_RET(chip, STATUS_FAIL);
  820. }
  821. class_code = buf[sys_info_addr + 0];
  822. device_type = buf[sys_info_addr + 56];
  823. sub_class = buf[sys_info_addr + 46];
  824. #ifdef SUPPORT_MSXC
  825. if (CHK_MSXC(ms_card)) {
  826. xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
  827. ((u32)buf[sys_info_addr + 7] << 16) |
  828. ((u32)buf[sys_info_addr + 8] << 8) |
  829. buf[sys_info_addr + 9];
  830. xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
  831. ((u32)buf[sys_info_addr + 33] << 16) |
  832. ((u32)buf[sys_info_addr + 34] << 8) |
  833. buf[sys_info_addr + 35];
  834. dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",
  835. xc_total_blk, xc_blk_size);
  836. } else {
  837. total_blk = ((u16)buf[sys_info_addr + 6] << 8) |
  838. buf[sys_info_addr + 7];
  839. blk_size = ((u16)buf[sys_info_addr + 2] << 8) |
  840. buf[sys_info_addr + 3];
  841. dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
  842. total_blk, blk_size);
  843. }
  844. #else
  845. total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
  846. blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
  847. dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
  848. total_blk, blk_size);
  849. #endif
  850. dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",
  851. class_code, device_type, sub_class);
  852. memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
  853. #ifdef SUPPORT_PCGL_1P18
  854. memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
  855. #endif
  856. kfree(buf);
  857. #ifdef SUPPORT_MSXC
  858. if (CHK_MSXC(ms_card)) {
  859. if (class_code != 0x03)
  860. TRACE_RET(chip, STATUS_FAIL);
  861. } else {
  862. if (class_code != 0x02)
  863. TRACE_RET(chip, STATUS_FAIL);
  864. }
  865. #else
  866. if (class_code != 0x02)
  867. TRACE_RET(chip, STATUS_FAIL);
  868. #endif
  869. if (device_type != 0x00) {
  870. if ((device_type == 0x01) || (device_type == 0x02) ||
  871. (device_type == 0x03)) {
  872. chip->card_wp |= MS_CARD;
  873. } else {
  874. TRACE_RET(chip, STATUS_FAIL);
  875. }
  876. }
  877. if (sub_class & 0xC0)
  878. TRACE_RET(chip, STATUS_FAIL);
  879. dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
  880. class_code, device_type, sub_class);
  881. #ifdef SUPPORT_MSXC
  882. if (CHK_MSXC(ms_card)) {
  883. chip->capacity[chip->card2lun[MS_CARD]] =
  884. ms_card->capacity = xc_total_blk * xc_blk_size;
  885. } else {
  886. chip->capacity[chip->card2lun[MS_CARD]] =
  887. ms_card->capacity = total_blk * blk_size;
  888. }
  889. #else
  890. ms_card->capacity = total_blk * blk_size;
  891. chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
  892. #endif
  893. return STATUS_SUCCESS;
  894. }
  895. #ifdef SUPPORT_MAGIC_GATE
  896. static int mg_set_tpc_para_sub(struct rtsx_chip *chip,
  897. int type, u8 mg_entry_num);
  898. #endif
  899. static int reset_ms_pro(struct rtsx_chip *chip)
  900. {
  901. struct ms_info *ms_card = &(chip->ms_card);
  902. int retval;
  903. #ifdef XC_POWERCLASS
  904. u8 change_power_class;
  905. if (chip->ms_power_class_en & 0x02)
  906. change_power_class = 2;
  907. else if (chip->ms_power_class_en & 0x01)
  908. change_power_class = 1;
  909. else
  910. change_power_class = 0;
  911. #endif
  912. #ifdef XC_POWERCLASS
  913. Retry:
  914. #endif
  915. retval = ms_pro_reset_flow(chip, 1);
  916. if (retval != STATUS_SUCCESS) {
  917. if (ms_card->switch_8bit_fail) {
  918. retval = ms_pro_reset_flow(chip, 0);
  919. if (retval != STATUS_SUCCESS)
  920. TRACE_RET(chip, STATUS_FAIL);
  921. } else {
  922. TRACE_RET(chip, STATUS_FAIL);
  923. }
  924. }
  925. retval = ms_read_attribute_info(chip);
  926. if (retval != STATUS_SUCCESS)
  927. TRACE_RET(chip, STATUS_FAIL);
  928. #ifdef XC_POWERCLASS
  929. if (CHK_HG8BIT(ms_card))
  930. change_power_class = 0;
  931. if (change_power_class && CHK_MSXC(ms_card)) {
  932. u8 power_class_en = chip->ms_power_class_en;
  933. dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n",
  934. power_class_en);
  935. dev_dbg(rtsx_dev(chip), "change_power_class = %d\n",
  936. change_power_class);
  937. if (change_power_class)
  938. power_class_en &= (1 << (change_power_class - 1));
  939. else
  940. power_class_en = 0;
  941. if (power_class_en) {
  942. u8 power_class_mode =
  943. (ms_card->raw_sys_info[46] & 0x18) >> 3;
  944. dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x",
  945. power_class_mode);
  946. if (change_power_class > power_class_mode)
  947. change_power_class = power_class_mode;
  948. if (change_power_class) {
  949. retval = msxc_change_power(chip,
  950. change_power_class);
  951. if (retval != STATUS_SUCCESS) {
  952. change_power_class--;
  953. goto Retry;
  954. }
  955. }
  956. }
  957. }
  958. #endif
  959. #ifdef SUPPORT_MAGIC_GATE
  960. retval = mg_set_tpc_para_sub(chip, 0, 0);
  961. if (retval != STATUS_SUCCESS)
  962. TRACE_RET(chip, STATUS_FAIL);
  963. #endif
  964. if (CHK_HG8BIT(ms_card))
  965. chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
  966. else
  967. chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
  968. return STATUS_SUCCESS;
  969. }
  970. static int ms_read_status_reg(struct rtsx_chip *chip)
  971. {
  972. int retval;
  973. u8 val[2];
  974. retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
  975. if (retval != STATUS_SUCCESS)
  976. TRACE_RET(chip, STATUS_FAIL);
  977. retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
  978. if (retval != STATUS_SUCCESS)
  979. TRACE_RET(chip, STATUS_FAIL);
  980. if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
  981. ms_set_err_code(chip, MS_FLASH_READ_ERROR);
  982. TRACE_RET(chip, STATUS_FAIL);
  983. }
  984. return STATUS_SUCCESS;
  985. }
  986. static int ms_read_extra_data(struct rtsx_chip *chip,
  987. u16 block_addr, u8 page_num, u8 *buf, int buf_len)
  988. {
  989. struct ms_info *ms_card = &(chip->ms_card);
  990. int retval, i;
  991. u8 val, data[10];
  992. retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
  993. SystemParm, 6);
  994. if (retval != STATUS_SUCCESS)
  995. TRACE_RET(chip, STATUS_FAIL);
  996. if (CHK_MS4BIT(ms_card)) {
  997. /* Parallel interface */
  998. data[0] = 0x88;
  999. } else {
  1000. /* Serial interface */
  1001. data[0] = 0x80;
  1002. }
  1003. data[1] = 0;
  1004. data[2] = (u8)(block_addr >> 8);
  1005. data[3] = (u8)block_addr;
  1006. data[4] = 0x40;
  1007. data[5] = page_num;
  1008. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  1009. retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
  1010. data, 6);
  1011. if (retval == STATUS_SUCCESS)
  1012. break;
  1013. }
  1014. if (i == MS_MAX_RETRY_COUNT)
  1015. TRACE_RET(chip, STATUS_FAIL);
  1016. ms_set_err_code(chip, MS_NO_ERROR);
  1017. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  1018. retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
  1019. if (retval == STATUS_SUCCESS)
  1020. break;
  1021. }
  1022. if (i == MS_MAX_RETRY_COUNT)
  1023. TRACE_RET(chip, STATUS_FAIL);
  1024. ms_set_err_code(chip, MS_NO_ERROR);
  1025. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  1026. if (retval != STATUS_SUCCESS)
  1027. TRACE_RET(chip, STATUS_FAIL);
  1028. if (val & INT_REG_CMDNK) {
  1029. ms_set_err_code(chip, MS_CMD_NK);
  1030. TRACE_RET(chip, STATUS_FAIL);
  1031. }
  1032. if (val & INT_REG_CED) {
  1033. if (val & INT_REG_ERR) {
  1034. retval = ms_read_status_reg(chip);
  1035. if (retval != STATUS_SUCCESS)
  1036. TRACE_RET(chip, STATUS_FAIL);
  1037. retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
  1038. MS_EXTRA_SIZE, SystemParm, 6);
  1039. if (retval != STATUS_SUCCESS)
  1040. TRACE_RET(chip, STATUS_FAIL);
  1041. }
  1042. }
  1043. retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT,
  1044. data, MS_EXTRA_SIZE);
  1045. if (retval != STATUS_SUCCESS)
  1046. TRACE_RET(chip, STATUS_FAIL);
  1047. if (buf && buf_len) {
  1048. if (buf_len > MS_EXTRA_SIZE)
  1049. buf_len = MS_EXTRA_SIZE;
  1050. memcpy(buf, data, buf_len);
  1051. }
  1052. return STATUS_SUCCESS;
  1053. }
  1054. static int ms_write_extra_data(struct rtsx_chip *chip,
  1055. u16 block_addr, u8 page_num, u8 *buf, int buf_len)
  1056. {
  1057. struct ms_info *ms_card = &(chip->ms_card);
  1058. int retval, i;
  1059. u8 val, data[16];
  1060. if (!buf || (buf_len < MS_EXTRA_SIZE))
  1061. TRACE_RET(chip, STATUS_FAIL);
  1062. retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
  1063. SystemParm, 6 + MS_EXTRA_SIZE);
  1064. if (retval != STATUS_SUCCESS)
  1065. TRACE_RET(chip, STATUS_FAIL);
  1066. if (CHK_MS4BIT(ms_card))
  1067. data[0] = 0x88;
  1068. else
  1069. data[0] = 0x80;
  1070. data[1] = 0;
  1071. data[2] = (u8)(block_addr >> 8);
  1072. data[3] = (u8)block_addr;
  1073. data[4] = 0x40;
  1074. data[5] = page_num;
  1075. for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
  1076. data[i] = buf[i - 6];
  1077. retval = ms_write_bytes(chip, WRITE_REG , (6+MS_EXTRA_SIZE),
  1078. NO_WAIT_INT, data, 16);
  1079. if (retval != STATUS_SUCCESS)
  1080. TRACE_RET(chip, STATUS_FAIL);
  1081. retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
  1082. if (retval != STATUS_SUCCESS)
  1083. TRACE_RET(chip, STATUS_FAIL);
  1084. ms_set_err_code(chip, MS_NO_ERROR);
  1085. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  1086. if (retval != STATUS_SUCCESS)
  1087. TRACE_RET(chip, STATUS_FAIL);
  1088. if (val & INT_REG_CMDNK) {
  1089. ms_set_err_code(chip, MS_CMD_NK);
  1090. TRACE_RET(chip, STATUS_FAIL);
  1091. }
  1092. if (val & INT_REG_CED) {
  1093. if (val & INT_REG_ERR) {
  1094. ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
  1095. TRACE_RET(chip, STATUS_FAIL);
  1096. }
  1097. }
  1098. return STATUS_SUCCESS;
  1099. }
  1100. static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num)
  1101. {
  1102. struct ms_info *ms_card = &(chip->ms_card);
  1103. int retval;
  1104. u8 val, data[6];
  1105. retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
  1106. SystemParm, 6);
  1107. if (retval != STATUS_SUCCESS)
  1108. TRACE_RET(chip, STATUS_FAIL);
  1109. if (CHK_MS4BIT(ms_card))
  1110. data[0] = 0x88;
  1111. else
  1112. data[0] = 0x80;
  1113. data[1] = 0;
  1114. data[2] = (u8)(block_addr >> 8);
  1115. data[3] = (u8)block_addr;
  1116. data[4] = 0x20;
  1117. data[5] = page_num;
  1118. retval = ms_write_bytes(chip, WRITE_REG , 6, NO_WAIT_INT, data, 6);
  1119. if (retval != STATUS_SUCCESS)
  1120. TRACE_RET(chip, STATUS_FAIL);
  1121. retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
  1122. if (retval != STATUS_SUCCESS)
  1123. TRACE_RET(chip, STATUS_FAIL);
  1124. ms_set_err_code(chip, MS_NO_ERROR);
  1125. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  1126. if (retval != STATUS_SUCCESS)
  1127. TRACE_RET(chip, STATUS_FAIL);
  1128. if (val & INT_REG_CMDNK) {
  1129. ms_set_err_code(chip, MS_CMD_NK);
  1130. TRACE_RET(chip, STATUS_FAIL);
  1131. }
  1132. if (val & INT_REG_CED) {
  1133. if (val & INT_REG_ERR) {
  1134. if (!(val & INT_REG_BREQ)) {
  1135. ms_set_err_code(chip, MS_FLASH_READ_ERROR);
  1136. TRACE_RET(chip, STATUS_FAIL);
  1137. }
  1138. retval = ms_read_status_reg(chip);
  1139. if (retval != STATUS_SUCCESS)
  1140. ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
  1141. } else {
  1142. if (!(val & INT_REG_BREQ)) {
  1143. ms_set_err_code(chip, MS_BREQ_ERROR);
  1144. TRACE_RET(chip, STATUS_FAIL);
  1145. }
  1146. }
  1147. }
  1148. retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA,
  1149. 0, NO_WAIT_INT);
  1150. if (retval != STATUS_SUCCESS)
  1151. TRACE_RET(chip, STATUS_FAIL);
  1152. if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR))
  1153. TRACE_RET(chip, STATUS_FAIL);
  1154. return STATUS_SUCCESS;
  1155. }
  1156. static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk)
  1157. {
  1158. struct ms_info *ms_card = &(chip->ms_card);
  1159. int retval;
  1160. u8 val, data[8], extra[MS_EXTRA_SIZE];
  1161. retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
  1162. if (retval != STATUS_SUCCESS)
  1163. TRACE_RET(chip, STATUS_FAIL);
  1164. retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
  1165. SystemParm, 7);
  1166. if (retval != STATUS_SUCCESS)
  1167. TRACE_RET(chip, STATUS_FAIL);
  1168. ms_set_err_code(chip, MS_NO_ERROR);
  1169. if (CHK_MS4BIT(ms_card))
  1170. data[0] = 0x88;
  1171. else
  1172. data[0] = 0x80;
  1173. data[1] = 0;
  1174. data[2] = (u8)(phy_blk >> 8);
  1175. data[3] = (u8)phy_blk;
  1176. data[4] = 0x80;
  1177. data[5] = 0;
  1178. data[6] = extra[0] & 0x7F;
  1179. data[7] = 0xFF;
  1180. retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7);
  1181. if (retval != STATUS_SUCCESS)
  1182. TRACE_RET(chip, STATUS_FAIL);
  1183. retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
  1184. if (retval != STATUS_SUCCESS)
  1185. TRACE_RET(chip, STATUS_FAIL);
  1186. ms_set_err_code(chip, MS_NO_ERROR);
  1187. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  1188. if (retval != STATUS_SUCCESS)
  1189. TRACE_RET(chip, STATUS_FAIL);
  1190. if (val & INT_REG_CMDNK) {
  1191. ms_set_err_code(chip, MS_CMD_NK);
  1192. TRACE_RET(chip, STATUS_FAIL);
  1193. }
  1194. if (val & INT_REG_CED) {
  1195. if (val & INT_REG_ERR) {
  1196. ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
  1197. TRACE_RET(chip, STATUS_FAIL);
  1198. }
  1199. }
  1200. return STATUS_SUCCESS;
  1201. }
  1202. static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk)
  1203. {
  1204. struct ms_info *ms_card = &(chip->ms_card);
  1205. int retval, i = 0;
  1206. u8 val, data[6];
  1207. retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
  1208. SystemParm, 6);
  1209. if (retval != STATUS_SUCCESS)
  1210. TRACE_RET(chip, STATUS_FAIL);
  1211. ms_set_err_code(chip, MS_NO_ERROR);
  1212. if (CHK_MS4BIT(ms_card))
  1213. data[0] = 0x88;
  1214. else
  1215. data[0] = 0x80;
  1216. data[1] = 0;
  1217. data[2] = (u8)(phy_blk >> 8);
  1218. data[3] = (u8)phy_blk;
  1219. data[4] = 0;
  1220. data[5] = 0;
  1221. retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
  1222. if (retval != STATUS_SUCCESS)
  1223. TRACE_RET(chip, STATUS_FAIL);
  1224. ERASE_RTY:
  1225. retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT);
  1226. if (retval != STATUS_SUCCESS)
  1227. TRACE_RET(chip, STATUS_FAIL);
  1228. ms_set_err_code(chip, MS_NO_ERROR);
  1229. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  1230. if (retval != STATUS_SUCCESS)
  1231. TRACE_RET(chip, STATUS_FAIL);
  1232. if (val & INT_REG_CMDNK) {
  1233. if (i < 3) {
  1234. i++;
  1235. goto ERASE_RTY;
  1236. }
  1237. ms_set_err_code(chip, MS_CMD_NK);
  1238. ms_set_bad_block(chip, phy_blk);
  1239. TRACE_RET(chip, STATUS_FAIL);
  1240. }
  1241. if (val & INT_REG_CED) {
  1242. if (val & INT_REG_ERR) {
  1243. ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
  1244. TRACE_RET(chip, STATUS_FAIL);
  1245. }
  1246. }
  1247. return STATUS_SUCCESS;
  1248. }
  1249. static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
  1250. {
  1251. if (!extra || (extra_len < MS_EXTRA_SIZE))
  1252. return;
  1253. memset(extra, 0xFF, MS_EXTRA_SIZE);
  1254. if (type == setPS_NG) {
  1255. /* set page status as 1:NG,and block status keep 1:OK */
  1256. extra[0] = 0xB8;
  1257. } else {
  1258. /* set page status as 0:Data Error,and block status keep 1:OK */
  1259. extra[0] = 0x98;
  1260. }
  1261. extra[2] = (u8)(log_blk >> 8);
  1262. extra[3] = (u8)log_blk;
  1263. }
  1264. static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk,
  1265. u8 start_page, u8 end_page)
  1266. {
  1267. int retval;
  1268. u8 extra[MS_EXTRA_SIZE], i;
  1269. memset(extra, 0xff, MS_EXTRA_SIZE);
  1270. extra[0] = 0xf8; /* Block, page OK, data erased */
  1271. extra[1] = 0xff;
  1272. extra[2] = (u8)(log_blk >> 8);
  1273. extra[3] = (u8)log_blk;
  1274. for (i = start_page; i < end_page; i++) {
  1275. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  1276. ms_set_err_code(chip, MS_NO_CARD);
  1277. TRACE_RET(chip, STATUS_FAIL);
  1278. }
  1279. retval = ms_write_extra_data(chip, phy_blk, i,
  1280. extra, MS_EXTRA_SIZE);
  1281. if (retval != STATUS_SUCCESS)
  1282. TRACE_RET(chip, STATUS_FAIL);
  1283. }
  1284. return STATUS_SUCCESS;
  1285. }
  1286. static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
  1287. u16 log_blk, u8 start_page, u8 end_page)
  1288. {
  1289. struct ms_info *ms_card = &(chip->ms_card);
  1290. int retval, rty_cnt, uncorrect_flag = 0;
  1291. u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
  1292. dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
  1293. old_blk, new_blk, log_blk);
  1294. dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n",
  1295. start_page, end_page);
  1296. retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
  1297. if (retval != STATUS_SUCCESS)
  1298. TRACE_RET(chip, STATUS_FAIL);
  1299. retval = ms_read_status_reg(chip);
  1300. if (retval != STATUS_SUCCESS)
  1301. TRACE_RET(chip, STATUS_FAIL);
  1302. RTSX_READ_REG(chip, PPBUF_BASE2, &val);
  1303. if (val & BUF_FULL) {
  1304. retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
  1305. if (retval != STATUS_SUCCESS)
  1306. TRACE_RET(chip, STATUS_FAIL);
  1307. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  1308. if (retval != STATUS_SUCCESS)
  1309. TRACE_RET(chip, STATUS_FAIL);
  1310. if (!(val & INT_REG_CED)) {
  1311. ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
  1312. TRACE_RET(chip, STATUS_FAIL);
  1313. }
  1314. }
  1315. for (i = start_page; i < end_page; i++) {
  1316. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  1317. ms_set_err_code(chip, MS_NO_CARD);
  1318. TRACE_RET(chip, STATUS_FAIL);
  1319. }
  1320. ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
  1321. retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
  1322. MS_EXTRA_SIZE, SystemParm, 6);
  1323. if (retval != STATUS_SUCCESS)
  1324. TRACE_RET(chip, STATUS_FAIL);
  1325. ms_set_err_code(chip, MS_NO_ERROR);
  1326. if (CHK_MS4BIT(ms_card))
  1327. data[0] = 0x88;
  1328. else
  1329. data[0] = 0x80;
  1330. data[1] = 0;
  1331. data[2] = (u8)(old_blk >> 8);
  1332. data[3] = (u8)old_blk;
  1333. data[4] = 0x20;
  1334. data[5] = i;
  1335. retval = ms_write_bytes(chip, WRITE_REG , 6, NO_WAIT_INT,
  1336. data, 6);
  1337. if (retval != STATUS_SUCCESS)
  1338. TRACE_RET(chip, STATUS_FAIL);
  1339. retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
  1340. if (retval != STATUS_SUCCESS)
  1341. TRACE_RET(chip, STATUS_FAIL);
  1342. ms_set_err_code(chip, MS_NO_ERROR);
  1343. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  1344. if (retval != STATUS_SUCCESS)
  1345. TRACE_RET(chip, STATUS_FAIL);
  1346. if (val & INT_REG_CMDNK) {
  1347. ms_set_err_code(chip, MS_CMD_NK);
  1348. TRACE_RET(chip, STATUS_FAIL);
  1349. }
  1350. if (val & INT_REG_CED) {
  1351. if (val & INT_REG_ERR) {
  1352. retval = ms_read_status_reg(chip);
  1353. if (retval != STATUS_SUCCESS) {
  1354. uncorrect_flag = 1;
  1355. dev_dbg(rtsx_dev(chip), "Uncorrectable error\n");
  1356. } else {
  1357. uncorrect_flag = 0;
  1358. }
  1359. retval = ms_transfer_tpc(chip,
  1360. MS_TM_NORMAL_READ,
  1361. READ_PAGE_DATA,
  1362. 0, NO_WAIT_INT);
  1363. if (retval != STATUS_SUCCESS)
  1364. TRACE_RET(chip, STATUS_FAIL);
  1365. if (uncorrect_flag) {
  1366. ms_set_page_status(log_blk, setPS_NG,
  1367. extra, MS_EXTRA_SIZE);
  1368. if (i == 0)
  1369. extra[0] &= 0xEF;
  1370. ms_write_extra_data(chip, old_blk, i,
  1371. extra, MS_EXTRA_SIZE);
  1372. dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n",
  1373. i, extra[0]);
  1374. MS_SET_BAD_BLOCK_FLG(ms_card);
  1375. ms_set_page_status(log_blk, setPS_Error,
  1376. extra, MS_EXTRA_SIZE);
  1377. ms_write_extra_data(chip, new_blk, i,
  1378. extra, MS_EXTRA_SIZE);
  1379. continue;
  1380. }
  1381. for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;
  1382. rty_cnt++) {
  1383. retval = ms_transfer_tpc(
  1384. chip,
  1385. MS_TM_NORMAL_WRITE,
  1386. WRITE_PAGE_DATA,
  1387. 0, NO_WAIT_INT);
  1388. if (retval == STATUS_SUCCESS)
  1389. break;
  1390. }
  1391. if (rty_cnt == MS_MAX_RETRY_COUNT)
  1392. TRACE_RET(chip, STATUS_FAIL);
  1393. }
  1394. if (!(val & INT_REG_BREQ)) {
  1395. ms_set_err_code(chip, MS_BREQ_ERROR);
  1396. TRACE_RET(chip, STATUS_FAIL);
  1397. }
  1398. }
  1399. retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
  1400. MS_EXTRA_SIZE, SystemParm, (6+MS_EXTRA_SIZE));
  1401. ms_set_err_code(chip, MS_NO_ERROR);
  1402. if (CHK_MS4BIT(ms_card))
  1403. data[0] = 0x88;
  1404. else
  1405. data[0] = 0x80;
  1406. data[1] = 0;
  1407. data[2] = (u8)(new_blk >> 8);
  1408. data[3] = (u8)new_blk;
  1409. data[4] = 0x20;
  1410. data[5] = i;
  1411. if ((extra[0] & 0x60) != 0x60)
  1412. data[6] = extra[0];
  1413. else
  1414. data[6] = 0xF8;
  1415. data[6 + 1] = 0xFF;
  1416. data[6 + 2] = (u8)(log_blk >> 8);
  1417. data[6 + 3] = (u8)log_blk;
  1418. for (j = 4; j <= MS_EXTRA_SIZE; j++)
  1419. data[6 + j] = 0xFF;
  1420. retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
  1421. NO_WAIT_INT, data, 16);
  1422. if (retval != STATUS_SUCCESS)
  1423. TRACE_RET(chip, STATUS_FAIL);
  1424. retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
  1425. if (retval != STATUS_SUCCESS)
  1426. TRACE_RET(chip, STATUS_FAIL);
  1427. ms_set_err_code(chip, MS_NO_ERROR);
  1428. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  1429. if (retval != STATUS_SUCCESS)
  1430. TRACE_RET(chip, STATUS_FAIL);
  1431. if (val & INT_REG_CMDNK) {
  1432. ms_set_err_code(chip, MS_CMD_NK);
  1433. TRACE_RET(chip, STATUS_FAIL);
  1434. }
  1435. if (val & INT_REG_CED) {
  1436. if (val & INT_REG_ERR) {
  1437. ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
  1438. TRACE_RET(chip, STATUS_FAIL);
  1439. }
  1440. }
  1441. if (i == 0) {
  1442. retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
  1443. MS_EXTRA_SIZE, SystemParm, 7);
  1444. if (retval != STATUS_SUCCESS)
  1445. TRACE_RET(chip, STATUS_FAIL);
  1446. ms_set_err_code(chip, MS_NO_ERROR);
  1447. if (CHK_MS4BIT(ms_card))
  1448. data[0] = 0x88;
  1449. else
  1450. data[0] = 0x80;
  1451. data[1] = 0;
  1452. data[2] = (u8)(old_blk >> 8);
  1453. data[3] = (u8)old_blk;
  1454. data[4] = 0x80;
  1455. data[5] = 0;
  1456. data[6] = 0xEF;
  1457. data[7] = 0xFF;
  1458. retval = ms_write_bytes(chip, WRITE_REG, 7,
  1459. NO_WAIT_INT, data, 8);
  1460. if (retval != STATUS_SUCCESS)
  1461. TRACE_RET(chip, STATUS_FAIL);
  1462. retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
  1463. if (retval != STATUS_SUCCESS)
  1464. TRACE_RET(chip, STATUS_FAIL);
  1465. ms_set_err_code(chip, MS_NO_ERROR);
  1466. retval = ms_read_bytes(chip, GET_INT, 1,
  1467. NO_WAIT_INT, &val, 1);
  1468. if (retval != STATUS_SUCCESS)
  1469. TRACE_RET(chip, STATUS_FAIL);
  1470. if (val & INT_REG_CMDNK) {
  1471. ms_set_err_code(chip, MS_CMD_NK);
  1472. TRACE_RET(chip, STATUS_FAIL);
  1473. }
  1474. if (val & INT_REG_CED) {
  1475. if (val & INT_REG_ERR) {
  1476. ms_set_err_code(chip,
  1477. MS_FLASH_WRITE_ERROR);
  1478. TRACE_RET(chip, STATUS_FAIL);
  1479. }
  1480. }
  1481. }
  1482. }
  1483. return STATUS_SUCCESS;
  1484. }
  1485. static int reset_ms(struct rtsx_chip *chip)
  1486. {
  1487. struct ms_info *ms_card = &(chip->ms_card);
  1488. int retval;
  1489. u16 i, reg_addr, block_size;
  1490. u8 val, extra[MS_EXTRA_SIZE], j, *ptr;
  1491. #ifndef SUPPORT_MAGIC_GATE
  1492. u16 eblock_cnt;
  1493. #endif
  1494. retval = ms_prepare_reset(chip);
  1495. if (retval != STATUS_SUCCESS)
  1496. TRACE_RET(chip, STATUS_FAIL);
  1497. ms_card->ms_type |= TYPE_MS;
  1498. retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
  1499. if (retval != STATUS_SUCCESS)
  1500. TRACE_RET(chip, STATUS_FAIL);
  1501. retval = ms_read_status_reg(chip);
  1502. if (retval != STATUS_SUCCESS)
  1503. TRACE_RET(chip, STATUS_FAIL);
  1504. RTSX_READ_REG(chip, PPBUF_BASE2, &val);
  1505. if (val & WRT_PRTCT)
  1506. chip->card_wp |= MS_CARD;
  1507. else
  1508. chip->card_wp &= ~MS_CARD;
  1509. i = 0;
  1510. RE_SEARCH:
  1511. /* Search Boot Block */
  1512. while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
  1513. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  1514. ms_set_err_code(chip, MS_NO_CARD);
  1515. TRACE_RET(chip, STATUS_FAIL);
  1516. }
  1517. retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);
  1518. if (retval != STATUS_SUCCESS) {
  1519. i++;
  1520. continue;
  1521. }
  1522. if (extra[0] & BLOCK_OK) {
  1523. if (!(extra[1] & NOT_BOOT_BLOCK)) {
  1524. ms_card->boot_block = i;
  1525. break;
  1526. }
  1527. }
  1528. i++;
  1529. }
  1530. if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
  1531. dev_dbg(rtsx_dev(chip), "No boot block found!");
  1532. TRACE_RET(chip, STATUS_FAIL);
  1533. }
  1534. for (j = 0; j < 3; j++) {
  1535. retval = ms_read_page(chip, ms_card->boot_block, j);
  1536. if (retval != STATUS_SUCCESS) {
  1537. if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
  1538. i = ms_card->boot_block + 1;
  1539. ms_set_err_code(chip, MS_NO_ERROR);
  1540. goto RE_SEARCH;
  1541. }
  1542. }
  1543. }
  1544. retval = ms_read_page(chip, ms_card->boot_block, 0);
  1545. if (retval != STATUS_SUCCESS)
  1546. TRACE_RET(chip, STATUS_FAIL);
  1547. /* Read MS system information as sys_info */
  1548. rtsx_init_cmd(chip);
  1549. for (i = 0; i < 96; i++)
  1550. rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);
  1551. retval = rtsx_send_cmd(chip, MS_CARD, 100);
  1552. if (retval < 0)
  1553. TRACE_RET(chip, STATUS_FAIL);
  1554. ptr = rtsx_get_cmd_data(chip);
  1555. memcpy(ms_card->raw_sys_info, ptr, 96);
  1556. /* Read useful block contents */
  1557. rtsx_init_cmd(chip);
  1558. rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
  1559. rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
  1560. for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;
  1561. reg_addr++)
  1562. rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
  1563. for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
  1564. rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
  1565. rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
  1566. rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
  1567. retval = rtsx_send_cmd(chip, MS_CARD, 100);
  1568. if (retval < 0)
  1569. TRACE_RET(chip, STATUS_FAIL);
  1570. ptr = rtsx_get_cmd_data(chip);
  1571. dev_dbg(rtsx_dev(chip), "Boot block data:\n");
  1572. dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr);
  1573. /* Block ID error
  1574. * HEADER_ID0, HEADER_ID1
  1575. */
  1576. if (ptr[0] != 0x00 || ptr[1] != 0x01) {
  1577. i = ms_card->boot_block + 1;
  1578. goto RE_SEARCH;
  1579. }
  1580. /* Page size error
  1581. * PAGE_SIZE_0, PAGE_SIZE_1
  1582. */
  1583. if (ptr[12] != 0x02 || ptr[13] != 0x00) {
  1584. i = ms_card->boot_block + 1;
  1585. goto RE_SEARCH;
  1586. }
  1587. if ((ptr[14] == 1) || (ptr[14] == 3))
  1588. chip->card_wp |= MS_CARD;
  1589. /* BLOCK_SIZE_0, BLOCK_SIZE_1 */
  1590. block_size = ((u16)ptr[6] << 8) | ptr[7];
  1591. if (block_size == 0x0010) {
  1592. /* Block size 16KB */
  1593. ms_card->block_shift = 5;
  1594. ms_card->page_off = 0x1F;
  1595. } else if (block_size == 0x0008) {
  1596. /* Block size 8KB */
  1597. ms_card->block_shift = 4;
  1598. ms_card->page_off = 0x0F;
  1599. }
  1600. /* BLOCK_COUNT_0, BLOCK_COUNT_1 */
  1601. ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];
  1602. #ifdef SUPPORT_MAGIC_GATE
  1603. j = ptr[10];
  1604. if (ms_card->block_shift == 4) { /* 4MB or 8MB */
  1605. if (j < 2) { /* Effective block for 4MB: 0x1F0 */
  1606. ms_card->capacity = 0x1EE0;
  1607. } else { /* Effective block for 8MB: 0x3E0 */
  1608. ms_card->capacity = 0x3DE0;
  1609. }
  1610. } else { /* 16MB, 32MB, 64MB or 128MB */
  1611. if (j < 5) { /* Effective block for 16MB: 0x3E0 */
  1612. ms_card->capacity = 0x7BC0;
  1613. } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */
  1614. ms_card->capacity = 0xF7C0;
  1615. } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */
  1616. ms_card->capacity = 0x1EF80;
  1617. } else { /* Effective block for 128MB: 0x1F00 */
  1618. ms_card->capacity = 0x3DF00;
  1619. }
  1620. }
  1621. #else
  1622. /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */
  1623. eblock_cnt = ((u16)ptr[10] << 8) | ptr[11];
  1624. ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;
  1625. #endif
  1626. chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
  1627. /* Switch I/F Mode */
  1628. if (ptr[15]) {
  1629. retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
  1630. if (retval != STATUS_SUCCESS)
  1631. TRACE_RET(chip, STATUS_FAIL);
  1632. RTSX_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);
  1633. RTSX_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);
  1634. retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG , 1,
  1635. NO_WAIT_INT);
  1636. if (retval != STATUS_SUCCESS)
  1637. TRACE_RET(chip, STATUS_FAIL);
  1638. RTSX_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,
  1639. MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT);
  1640. ms_card->ms_type |= MS_4BIT;
  1641. }
  1642. if (CHK_MS4BIT(ms_card))
  1643. chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
  1644. else
  1645. chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
  1646. return STATUS_SUCCESS;
  1647. }
  1648. static int ms_init_l2p_tbl(struct rtsx_chip *chip)
  1649. {
  1650. struct ms_info *ms_card = &(chip->ms_card);
  1651. int size, i, seg_no, retval;
  1652. u16 defect_block, reg_addr;
  1653. u8 val1, val2;
  1654. ms_card->segment_cnt = ms_card->total_block >> 9;
  1655. dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n",
  1656. ms_card->segment_cnt);
  1657. size = ms_card->segment_cnt * sizeof(struct zone_entry);
  1658. ms_card->segment = vzalloc(size);
  1659. if (ms_card->segment == NULL)
  1660. TRACE_RET(chip, STATUS_FAIL);
  1661. retval = ms_read_page(chip, ms_card->boot_block, 1);
  1662. if (retval != STATUS_SUCCESS)
  1663. TRACE_GOTO(chip, INIT_FAIL);
  1664. reg_addr = PPBUF_BASE2;
  1665. for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
  1666. retval = rtsx_read_register(chip, reg_addr++, &val1);
  1667. if (retval != STATUS_SUCCESS)
  1668. TRACE_GOTO(chip, INIT_FAIL);
  1669. retval = rtsx_read_register(chip, reg_addr++, &val2);
  1670. if (retval != STATUS_SUCCESS)
  1671. TRACE_GOTO(chip, INIT_FAIL);
  1672. defect_block = ((u16)val1 << 8) | val2;
  1673. if (defect_block == 0xFFFF)
  1674. break;
  1675. seg_no = defect_block / 512;
  1676. ms_card->segment[seg_no].defect_list[ms_card->segment[seg_no].disable_count++] = defect_block;
  1677. }
  1678. for (i = 0; i < ms_card->segment_cnt; i++) {
  1679. ms_card->segment[i].build_flag = 0;
  1680. ms_card->segment[i].l2p_table = NULL;
  1681. ms_card->segment[i].free_table = NULL;
  1682. ms_card->segment[i].get_index = 0;
  1683. ms_card->segment[i].set_index = 0;
  1684. ms_card->segment[i].unused_blk_cnt = 0;
  1685. dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n",
  1686. i, ms_card->segment[i].disable_count);
  1687. }
  1688. return STATUS_SUCCESS;
  1689. INIT_FAIL:
  1690. if (ms_card->segment) {
  1691. vfree(ms_card->segment);
  1692. ms_card->segment = NULL;
  1693. }
  1694. return STATUS_FAIL;
  1695. }
  1696. static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off)
  1697. {
  1698. struct ms_info *ms_card = &(chip->ms_card);
  1699. struct zone_entry *segment;
  1700. if (ms_card->segment == NULL)
  1701. return 0xFFFF;
  1702. segment = &(ms_card->segment[seg_no]);
  1703. if (segment->l2p_table)
  1704. return segment->l2p_table[log_off];
  1705. return 0xFFFF;
  1706. }
  1707. static void ms_set_l2p_tbl(struct rtsx_chip *chip,
  1708. int seg_no, u16 log_off, u16 phy_blk)
  1709. {
  1710. struct ms_info *ms_card = &(chip->ms_card);
  1711. struct zone_entry *segment;
  1712. if (ms_card->segment == NULL)
  1713. return;
  1714. segment = &(ms_card->segment[seg_no]);
  1715. if (segment->l2p_table)
  1716. segment->l2p_table[log_off] = phy_blk;
  1717. }
  1718. static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk)
  1719. {
  1720. struct ms_info *ms_card = &(chip->ms_card);
  1721. struct zone_entry *segment;
  1722. int seg_no;
  1723. seg_no = (int)phy_blk >> 9;
  1724. segment = &(ms_card->segment[seg_no]);
  1725. segment->free_table[segment->set_index++] = phy_blk;
  1726. if (segment->set_index >= MS_FREE_TABLE_CNT)
  1727. segment->set_index = 0;
  1728. segment->unused_blk_cnt++;
  1729. }
  1730. static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no)
  1731. {
  1732. struct ms_info *ms_card = &(chip->ms_card);
  1733. struct zone_entry *segment;
  1734. u16 phy_blk;
  1735. segment = &(ms_card->segment[seg_no]);
  1736. if (segment->unused_blk_cnt <= 0)
  1737. return 0xFFFF;
  1738. phy_blk = segment->free_table[segment->get_index];
  1739. segment->free_table[segment->get_index++] = 0xFFFF;
  1740. if (segment->get_index >= MS_FREE_TABLE_CNT)
  1741. segment->get_index = 0;
  1742. segment->unused_blk_cnt--;
  1743. return phy_blk;
  1744. }
  1745. static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478,
  1746. 2974, 3470, 3966, 4462, 4958,
  1747. 5454, 5950, 6446, 6942, 7438,
  1748. 7934};
  1749. static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk,
  1750. u16 log_off, u8 us1, u8 us2)
  1751. {
  1752. struct ms_info *ms_card = &(chip->ms_card);
  1753. struct zone_entry *segment;
  1754. int seg_no;
  1755. u16 tmp_blk;
  1756. seg_no = (int)phy_blk >> 9;
  1757. segment = &(ms_card->segment[seg_no]);
  1758. tmp_blk = segment->l2p_table[log_off];
  1759. if (us1 != us2) {
  1760. if (us1 == 0) {
  1761. if (!(chip->card_wp & MS_CARD))
  1762. ms_erase_block(chip, tmp_blk);
  1763. ms_set_unused_block(chip, tmp_blk);
  1764. segment->l2p_table[log_off] = phy_blk;
  1765. } else {
  1766. if (!(chip->card_wp & MS_CARD))
  1767. ms_erase_block(chip, phy_blk);
  1768. ms_set_unused_block(chip, phy_blk);
  1769. }
  1770. } else {
  1771. if (phy_blk < tmp_blk) {
  1772. if (!(chip->card_wp & MS_CARD))
  1773. ms_erase_block(chip, phy_blk);
  1774. ms_set_unused_block(chip, phy_blk);
  1775. } else {
  1776. if (!(chip->card_wp & MS_CARD))
  1777. ms_erase_block(chip, tmp_blk);
  1778. ms_set_unused_block(chip, tmp_blk);
  1779. segment->l2p_table[log_off] = phy_blk;
  1780. }
  1781. }
  1782. return STATUS_SUCCESS;
  1783. }
  1784. static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)
  1785. {
  1786. struct ms_info *ms_card = &(chip->ms_card);
  1787. struct zone_entry *segment;
  1788. int retval, table_size, disable_cnt, defect_flag, i;
  1789. u16 start, end, phy_blk, log_blk, tmp_blk;
  1790. u8 extra[MS_EXTRA_SIZE], us1, us2;
  1791. dev_dbg(rtsx_dev(chip), "ms_build_l2p_tbl: %d\n", seg_no);
  1792. if (ms_card->segment == NULL) {
  1793. retval = ms_init_l2p_tbl(chip);
  1794. if (retval != STATUS_SUCCESS)
  1795. TRACE_RET(chip, retval);
  1796. }
  1797. if (ms_card->segment[seg_no].build_flag) {
  1798. dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n",
  1799. seg_no);
  1800. return STATUS_SUCCESS;
  1801. }
  1802. if (seg_no == 0)
  1803. table_size = 494;
  1804. else
  1805. table_size = 496;
  1806. segment = &(ms_card->segment[seg_no]);
  1807. if (segment->l2p_table == NULL) {
  1808. segment->l2p_table = vmalloc(table_size * 2);
  1809. if (segment->l2p_table == NULL)
  1810. TRACE_GOTO(chip, BUILD_FAIL);
  1811. }
  1812. memset((u8 *)(segment->l2p_table), 0xff, table_size * 2);
  1813. if (segment->free_table == NULL) {
  1814. segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);
  1815. if (segment->free_table == NULL)
  1816. TRACE_GOTO(chip, BUILD_FAIL);
  1817. }
  1818. memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
  1819. start = (u16)seg_no << 9;
  1820. end = (u16)(seg_no + 1) << 9;
  1821. disable_cnt = segment->disable_count;
  1822. segment->get_index = segment->set_index = 0;
  1823. segment->unused_blk_cnt = 0;
  1824. for (phy_blk = start; phy_blk < end; phy_blk++) {
  1825. if (disable_cnt) {
  1826. defect_flag = 0;
  1827. for (i = 0; i < segment->disable_count; i++) {
  1828. if (phy_blk == segment->defect_list[i]) {
  1829. defect_flag = 1;
  1830. break;
  1831. }
  1832. }
  1833. if (defect_flag) {
  1834. disable_cnt--;
  1835. continue;
  1836. }
  1837. }
  1838. retval = ms_read_extra_data(chip, phy_blk, 0,
  1839. extra, MS_EXTRA_SIZE);
  1840. if (retval != STATUS_SUCCESS) {
  1841. dev_dbg(rtsx_dev(chip), "read extra data fail\n");
  1842. ms_set_bad_block(chip, phy_blk);
  1843. continue;
  1844. }
  1845. if (seg_no == ms_card->segment_cnt - 1) {
  1846. if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
  1847. if (!(chip->card_wp & MS_CARD)) {
  1848. retval = ms_erase_block(chip, phy_blk);
  1849. if (retval != STATUS_SUCCESS)
  1850. continue;
  1851. extra[2] = 0xff;
  1852. extra[3] = 0xff;
  1853. }
  1854. }
  1855. }
  1856. if (!(extra[0] & BLOCK_OK))
  1857. continue;
  1858. if (!(extra[1] & NOT_BOOT_BLOCK))
  1859. continue;
  1860. if ((extra[0] & PAGE_OK) != PAGE_OK)
  1861. continue;
  1862. log_blk = ((u16)extra[2] << 8) | extra[3];
  1863. if (log_blk == 0xFFFF) {
  1864. if (!(chip->card_wp & MS_CARD)) {
  1865. retval = ms_erase_block(chip, phy_blk);
  1866. if (retval != STATUS_SUCCESS)
  1867. continue;
  1868. }
  1869. ms_set_unused_block(chip, phy_blk);
  1870. continue;
  1871. }
  1872. if ((log_blk < ms_start_idx[seg_no]) ||
  1873. (log_blk >= ms_start_idx[seg_no+1])) {
  1874. if (!(chip->card_wp & MS_CARD)) {
  1875. retval = ms_erase_block(chip, phy_blk);
  1876. if (retval != STATUS_SUCCESS)
  1877. continue;
  1878. }
  1879. ms_set_unused_block(chip, phy_blk);
  1880. continue;
  1881. }
  1882. if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] == 0xFFFF) {
  1883. segment->l2p_table[log_blk - ms_start_idx[seg_no]] = phy_blk;
  1884. continue;
  1885. }
  1886. us1 = extra[0] & 0x10;
  1887. tmp_blk = segment->l2p_table[log_blk - ms_start_idx[seg_no]];
  1888. retval = ms_read_extra_data(chip, tmp_blk, 0,
  1889. extra, MS_EXTRA_SIZE);
  1890. if (retval != STATUS_SUCCESS)
  1891. continue;
  1892. us2 = extra[0] & 0x10;
  1893. (void)ms_arbitrate_l2p(chip, phy_blk,
  1894. log_blk-ms_start_idx[seg_no], us1, us2);
  1895. continue;
  1896. }
  1897. segment->build_flag = 1;
  1898. dev_dbg(rtsx_dev(chip), "unused block count: %d\n",
  1899. segment->unused_blk_cnt);
  1900. /* Logical Address Confirmation Process */
  1901. if (seg_no == ms_card->segment_cnt - 1) {
  1902. if (segment->unused_blk_cnt < 2)
  1903. chip->card_wp |= MS_CARD;
  1904. } else {
  1905. if (segment->unused_blk_cnt < 1)
  1906. chip->card_wp |= MS_CARD;
  1907. }
  1908. if (chip->card_wp & MS_CARD)
  1909. return STATUS_SUCCESS;
  1910. for (log_blk = ms_start_idx[seg_no];
  1911. log_blk < ms_start_idx[seg_no + 1]; log_blk++) {
  1912. if (segment->l2p_table[log_blk-ms_start_idx[seg_no]] == 0xFFFF) {
  1913. phy_blk = ms_get_unused_block(chip, seg_no);
  1914. if (phy_blk == 0xFFFF) {
  1915. chip->card_wp |= MS_CARD;
  1916. return STATUS_SUCCESS;
  1917. }
  1918. retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
  1919. if (retval != STATUS_SUCCESS)
  1920. TRACE_GOTO(chip, BUILD_FAIL);
  1921. segment->l2p_table[log_blk-ms_start_idx[seg_no]] = phy_blk;
  1922. if (seg_no == ms_card->segment_cnt - 1) {
  1923. if (segment->unused_blk_cnt < 2) {
  1924. chip->card_wp |= MS_CARD;
  1925. return STATUS_SUCCESS;
  1926. }
  1927. } else {
  1928. if (segment->unused_blk_cnt < 1) {
  1929. chip->card_wp |= MS_CARD;
  1930. return STATUS_SUCCESS;
  1931. }
  1932. }
  1933. }
  1934. }
  1935. /* Make boot block be the first normal block */
  1936. if (seg_no == 0) {
  1937. for (log_blk = 0; log_blk < 494; log_blk++) {
  1938. tmp_blk = segment->l2p_table[log_blk];
  1939. if (tmp_blk < ms_card->boot_block) {
  1940. dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n");
  1941. if (chip->card_wp & MS_CARD)
  1942. break;
  1943. phy_blk = ms_get_unused_block(chip, 0);
  1944. retval = ms_copy_page(chip, tmp_blk, phy_blk,
  1945. log_blk, 0, ms_card->page_off + 1);
  1946. if (retval != STATUS_SUCCESS)
  1947. TRACE_RET(chip, STATUS_FAIL);
  1948. segment->l2p_table[log_blk] = phy_blk;
  1949. retval = ms_set_bad_block(chip, tmp_blk);
  1950. if (retval != STATUS_SUCCESS)
  1951. TRACE_RET(chip, STATUS_FAIL);
  1952. }
  1953. }
  1954. }
  1955. return STATUS_SUCCESS;
  1956. BUILD_FAIL:
  1957. segment->build_flag = 0;
  1958. if (segment->l2p_table) {
  1959. vfree(segment->l2p_table);
  1960. segment->l2p_table = NULL;
  1961. }
  1962. if (segment->free_table) {
  1963. vfree(segment->free_table);
  1964. segment->free_table = NULL;
  1965. }
  1966. return STATUS_FAIL;
  1967. }
  1968. int reset_ms_card(struct rtsx_chip *chip)
  1969. {
  1970. struct ms_info *ms_card = &(chip->ms_card);
  1971. int retval;
  1972. memset(ms_card, 0, sizeof(struct ms_info));
  1973. retval = enable_card_clock(chip, MS_CARD);
  1974. if (retval != STATUS_SUCCESS)
  1975. TRACE_RET(chip, STATUS_FAIL);
  1976. retval = select_card(chip, MS_CARD);
  1977. if (retval != STATUS_SUCCESS)
  1978. TRACE_RET(chip, STATUS_FAIL);
  1979. ms_card->ms_type = 0;
  1980. retval = reset_ms_pro(chip);
  1981. if (retval != STATUS_SUCCESS) {
  1982. if (ms_card->check_ms_flow) {
  1983. retval = reset_ms(chip);
  1984. if (retval != STATUS_SUCCESS)
  1985. TRACE_RET(chip, STATUS_FAIL);
  1986. } else {
  1987. TRACE_RET(chip, STATUS_FAIL);
  1988. }
  1989. }
  1990. retval = ms_set_init_para(chip);
  1991. if (retval != STATUS_SUCCESS)
  1992. TRACE_RET(chip, STATUS_FAIL);
  1993. if (!CHK_MSPRO(ms_card)) {
  1994. /* Build table for the last segment,
  1995. * to check if L2P table block exists, erasing it
  1996. */
  1997. retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
  1998. if (retval != STATUS_SUCCESS)
  1999. TRACE_RET(chip, STATUS_FAIL);
  2000. }
  2001. dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type);
  2002. return STATUS_SUCCESS;
  2003. }
  2004. static int mspro_set_rw_cmd(struct rtsx_chip *chip,
  2005. u32 start_sec, u16 sec_cnt, u8 cmd)
  2006. {
  2007. int retval, i;
  2008. u8 data[8];
  2009. data[0] = cmd;
  2010. data[1] = (u8)(sec_cnt >> 8);
  2011. data[2] = (u8)sec_cnt;
  2012. data[3] = (u8)(start_sec >> 24);
  2013. data[4] = (u8)(start_sec >> 16);
  2014. data[5] = (u8)(start_sec >> 8);
  2015. data[6] = (u8)start_sec;
  2016. data[7] = 0;
  2017. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  2018. retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7,
  2019. WAIT_INT, data, 8);
  2020. if (retval == STATUS_SUCCESS)
  2021. break;
  2022. }
  2023. if (i == MS_MAX_RETRY_COUNT)
  2024. TRACE_RET(chip, STATUS_FAIL);
  2025. return STATUS_SUCCESS;
  2026. }
  2027. void mspro_stop_seq_mode(struct rtsx_chip *chip)
  2028. {
  2029. struct ms_info *ms_card = &(chip->ms_card);
  2030. int retval;
  2031. if (ms_card->seq_mode) {
  2032. retval = ms_switch_clock(chip);
  2033. if (retval != STATUS_SUCCESS)
  2034. return;
  2035. ms_card->seq_mode = 0;
  2036. ms_card->total_sec_cnt = 0;
  2037. ms_send_cmd(chip, PRO_STOP, WAIT_INT);
  2038. rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
  2039. }
  2040. }
  2041. static inline int ms_auto_tune_clock(struct rtsx_chip *chip)
  2042. {
  2043. struct ms_info *ms_card = &(chip->ms_card);
  2044. int retval;
  2045. if (chip->asic_code) {
  2046. if (ms_card->ms_clock > 30)
  2047. ms_card->ms_clock -= 20;
  2048. } else {
  2049. if (ms_card->ms_clock == CLK_80)
  2050. ms_card->ms_clock = CLK_60;
  2051. else if (ms_card->ms_clock == CLK_60)
  2052. ms_card->ms_clock = CLK_40;
  2053. }
  2054. retval = ms_switch_clock(chip);
  2055. if (retval != STATUS_SUCCESS)
  2056. TRACE_RET(chip, STATUS_FAIL);
  2057. return STATUS_SUCCESS;
  2058. }
  2059. static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
  2060. struct rtsx_chip *chip, u32 start_sector,
  2061. u16 sector_cnt)
  2062. {
  2063. struct ms_info *ms_card = &(chip->ms_card);
  2064. int retval, mode_2k = 0;
  2065. u16 count;
  2066. u8 val, trans_mode, rw_tpc, rw_cmd;
  2067. ms_set_err_code(chip, MS_NO_ERROR);
  2068. ms_card->cleanup_counter = 0;
  2069. if (CHK_MSHG(ms_card)) {
  2070. if ((start_sector % 4) || (sector_cnt % 4)) {
  2071. if (srb->sc_data_direction == DMA_FROM_DEVICE) {
  2072. rw_tpc = PRO_READ_LONG_DATA;
  2073. rw_cmd = PRO_READ_DATA;
  2074. } else {
  2075. rw_tpc = PRO_WRITE_LONG_DATA;
  2076. rw_cmd = PRO_WRITE_DATA;
  2077. }
  2078. } else {
  2079. if (srb->sc_data_direction == DMA_FROM_DEVICE) {
  2080. rw_tpc = PRO_READ_QUAD_DATA;
  2081. rw_cmd = PRO_READ_2K_DATA;
  2082. } else {
  2083. rw_tpc = PRO_WRITE_QUAD_DATA;
  2084. rw_cmd = PRO_WRITE_2K_DATA;
  2085. }
  2086. mode_2k = 1;
  2087. }
  2088. } else {
  2089. if (srb->sc_data_direction == DMA_FROM_DEVICE) {
  2090. rw_tpc = PRO_READ_LONG_DATA;
  2091. rw_cmd = PRO_READ_DATA;
  2092. } else {
  2093. rw_tpc = PRO_WRITE_LONG_DATA;
  2094. rw_cmd = PRO_WRITE_DATA;
  2095. }
  2096. }
  2097. retval = ms_switch_clock(chip);
  2098. if (retval != STATUS_SUCCESS)
  2099. TRACE_RET(chip, STATUS_FAIL);
  2100. if (srb->sc_data_direction == DMA_FROM_DEVICE)
  2101. trans_mode = MS_TM_AUTO_READ;
  2102. else
  2103. trans_mode = MS_TM_AUTO_WRITE;
  2104. RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
  2105. if (ms_card->seq_mode) {
  2106. if ((ms_card->pre_dir != srb->sc_data_direction)
  2107. || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector)
  2108. || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
  2109. || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
  2110. || !(val & MS_INT_BREQ)
  2111. || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
  2112. ms_card->seq_mode = 0;
  2113. ms_card->total_sec_cnt = 0;
  2114. if (val & MS_INT_BREQ) {
  2115. retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
  2116. if (retval != STATUS_SUCCESS)
  2117. TRACE_RET(chip, STATUS_FAIL);
  2118. rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
  2119. }
  2120. }
  2121. }
  2122. if (!ms_card->seq_mode) {
  2123. ms_card->total_sec_cnt = 0;
  2124. if (sector_cnt >= SEQ_START_CRITERIA) {
  2125. if ((ms_card->capacity - start_sector) > 0xFE00)
  2126. count = 0xFE00;
  2127. else
  2128. count = (u16)(ms_card->capacity - start_sector);
  2129. if (count > sector_cnt) {
  2130. if (mode_2k)
  2131. ms_card->seq_mode |= MODE_2K_SEQ;
  2132. else
  2133. ms_card->seq_mode |= MODE_512_SEQ;
  2134. }
  2135. } else {
  2136. count = sector_cnt;
  2137. }
  2138. retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
  2139. if (retval != STATUS_SUCCESS) {
  2140. ms_card->seq_mode = 0;
  2141. TRACE_RET(chip, STATUS_FAIL);
  2142. }
  2143. }
  2144. retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt,
  2145. WAIT_INT, mode_2k, scsi_sg_count(srb),
  2146. scsi_sglist(srb), scsi_bufflen(srb));
  2147. if (retval != STATUS_SUCCESS) {
  2148. ms_card->seq_mode = 0;
  2149. rtsx_read_register(chip, MS_TRANS_CFG, &val);
  2150. rtsx_clear_ms_error(chip);
  2151. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  2152. chip->rw_need_retry = 0;
  2153. dev_dbg(rtsx_dev(chip), "No card exist, exit mspro_rw_multi_sector\n");
  2154. TRACE_RET(chip, STATUS_FAIL);
  2155. }
  2156. if (val & MS_INT_BREQ)
  2157. ms_send_cmd(chip, PRO_STOP, WAIT_INT);
  2158. if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
  2159. dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n");
  2160. chip->rw_need_retry = 1;
  2161. ms_auto_tune_clock(chip);
  2162. }
  2163. TRACE_RET(chip, retval);
  2164. }
  2165. if (ms_card->seq_mode) {
  2166. ms_card->pre_sec_addr = start_sector;
  2167. ms_card->pre_sec_cnt = sector_cnt;
  2168. ms_card->pre_dir = srb->sc_data_direction;
  2169. ms_card->total_sec_cnt += sector_cnt;
  2170. }
  2171. return STATUS_SUCCESS;
  2172. }
  2173. static int mspro_read_format_progress(struct rtsx_chip *chip,
  2174. const int short_data_len)
  2175. {
  2176. struct ms_info *ms_card = &(chip->ms_card);
  2177. int retval, i;
  2178. u32 total_progress, cur_progress;
  2179. u8 cnt, tmp;
  2180. u8 data[8];
  2181. dev_dbg(rtsx_dev(chip), "mspro_read_format_progress, short_data_len = %d\n",
  2182. short_data_len);
  2183. retval = ms_switch_clock(chip);
  2184. if (retval != STATUS_SUCCESS) {
  2185. ms_card->format_status = FORMAT_FAIL;
  2186. TRACE_RET(chip, STATUS_FAIL);
  2187. }
  2188. retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
  2189. if (retval != STATUS_SUCCESS) {
  2190. ms_card->format_status = FORMAT_FAIL;
  2191. TRACE_RET(chip, STATUS_FAIL);
  2192. }
  2193. if (!(tmp & MS_INT_BREQ)) {
  2194. if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {
  2195. ms_card->format_status = FORMAT_SUCCESS;
  2196. return STATUS_SUCCESS;
  2197. }
  2198. ms_card->format_status = FORMAT_FAIL;
  2199. TRACE_RET(chip, STATUS_FAIL);
  2200. }
  2201. if (short_data_len >= 256)
  2202. cnt = 0;
  2203. else
  2204. cnt = (u8)short_data_len;
  2205. retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT,
  2206. MS_NO_CHECK_INT);
  2207. if (retval != STATUS_SUCCESS) {
  2208. ms_card->format_status = FORMAT_FAIL;
  2209. TRACE_RET(chip, STATUS_FAIL);
  2210. }
  2211. retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT,
  2212. data, 8);
  2213. if (retval != STATUS_SUCCESS) {
  2214. ms_card->format_status = FORMAT_FAIL;
  2215. TRACE_RET(chip, STATUS_FAIL);
  2216. }
  2217. total_progress = (data[0] << 24) | (data[1] << 16) |
  2218. (data[2] << 8) | data[3];
  2219. cur_progress = (data[4] << 24) | (data[5] << 16) |
  2220. (data[6] << 8) | data[7];
  2221. dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n",
  2222. total_progress, cur_progress);
  2223. if (total_progress == 0) {
  2224. ms_card->progress = 0;
  2225. } else {
  2226. u64 ulltmp = (u64)cur_progress * (u64)65535;
  2227. do_div(ulltmp, total_progress);
  2228. ms_card->progress = (u16)ulltmp;
  2229. }
  2230. dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress);
  2231. for (i = 0; i < 5000; i++) {
  2232. retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
  2233. if (retval != STATUS_SUCCESS) {
  2234. ms_card->format_status = FORMAT_FAIL;
  2235. TRACE_RET(chip, STATUS_FAIL);
  2236. }
  2237. if (tmp & (MS_INT_CED | MS_INT_CMDNK |
  2238. MS_INT_BREQ | MS_INT_ERR))
  2239. break;
  2240. wait_timeout(1);
  2241. }
  2242. retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0);
  2243. if (retval != STATUS_SUCCESS) {
  2244. ms_card->format_status = FORMAT_FAIL;
  2245. TRACE_RET(chip, STATUS_FAIL);
  2246. }
  2247. if (i == 5000) {
  2248. ms_card->format_status = FORMAT_FAIL;
  2249. TRACE_RET(chip, STATUS_FAIL);
  2250. }
  2251. if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
  2252. ms_card->format_status = FORMAT_FAIL;
  2253. TRACE_RET(chip, STATUS_FAIL);
  2254. }
  2255. if (tmp & MS_INT_CED) {
  2256. ms_card->format_status = FORMAT_SUCCESS;
  2257. ms_card->pro_under_formatting = 0;
  2258. } else if (tmp & MS_INT_BREQ) {
  2259. ms_card->format_status = FORMAT_IN_PROGRESS;
  2260. } else {
  2261. ms_card->format_status = FORMAT_FAIL;
  2262. ms_card->pro_under_formatting = 0;
  2263. TRACE_RET(chip, STATUS_FAIL);
  2264. }
  2265. return STATUS_SUCCESS;
  2266. }
  2267. void mspro_polling_format_status(struct rtsx_chip *chip)
  2268. {
  2269. struct ms_info *ms_card = &(chip->ms_card);
  2270. int i;
  2271. if (ms_card->pro_under_formatting &&
  2272. (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
  2273. rtsx_set_stat(chip, RTSX_STAT_RUN);
  2274. for (i = 0; i < 65535; i++) {
  2275. mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
  2276. if (ms_card->format_status != FORMAT_IN_PROGRESS)
  2277. break;
  2278. }
  2279. }
  2280. }
  2281. int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip,
  2282. int short_data_len, int quick_format)
  2283. {
  2284. struct ms_info *ms_card = &(chip->ms_card);
  2285. int retval, i;
  2286. u8 buf[8], tmp;
  2287. u16 para;
  2288. retval = ms_switch_clock(chip);
  2289. if (retval != STATUS_SUCCESS)
  2290. TRACE_RET(chip, STATUS_FAIL);
  2291. retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
  2292. if (retval != STATUS_SUCCESS)
  2293. TRACE_RET(chip, STATUS_FAIL);
  2294. memset(buf, 0, 2);
  2295. switch (short_data_len) {
  2296. case 32:
  2297. buf[0] = 0;
  2298. break;
  2299. case 64:
  2300. buf[0] = 1;
  2301. break;
  2302. case 128:
  2303. buf[0] = 2;
  2304. break;
  2305. case 256:
  2306. default:
  2307. buf[0] = 3;
  2308. break;
  2309. }
  2310. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  2311. retval = ms_write_bytes(chip, PRO_WRITE_REG, 1,
  2312. NO_WAIT_INT, buf, 2);
  2313. if (retval == STATUS_SUCCESS)
  2314. break;
  2315. }
  2316. if (i == MS_MAX_RETRY_COUNT)
  2317. TRACE_RET(chip, STATUS_FAIL);
  2318. if (quick_format)
  2319. para = 0x0000;
  2320. else
  2321. para = 0x0001;
  2322. retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
  2323. if (retval != STATUS_SUCCESS)
  2324. TRACE_RET(chip, STATUS_FAIL);
  2325. RTSX_READ_REG(chip, MS_TRANS_CFG, &tmp);
  2326. if (tmp & (MS_INT_CMDNK | MS_INT_ERR))
  2327. TRACE_RET(chip, STATUS_FAIL);
  2328. if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
  2329. ms_card->pro_under_formatting = 1;
  2330. ms_card->progress = 0;
  2331. ms_card->format_status = FORMAT_IN_PROGRESS;
  2332. return STATUS_SUCCESS;
  2333. }
  2334. if (tmp & MS_INT_CED) {
  2335. ms_card->pro_under_formatting = 0;
  2336. ms_card->progress = 0;
  2337. ms_card->format_status = FORMAT_SUCCESS;
  2338. set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
  2339. return STATUS_SUCCESS;
  2340. }
  2341. TRACE_RET(chip, STATUS_FAIL);
  2342. }
  2343. static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk,
  2344. u16 log_blk, u8 start_page, u8 end_page,
  2345. u8 *buf, unsigned int *index,
  2346. unsigned int *offset)
  2347. {
  2348. struct ms_info *ms_card = &(chip->ms_card);
  2349. int retval, i;
  2350. u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
  2351. u8 *ptr;
  2352. retval = ms_read_extra_data(chip, phy_blk, start_page,
  2353. extra, MS_EXTRA_SIZE);
  2354. if (retval == STATUS_SUCCESS) {
  2355. if ((extra[1] & 0x30) != 0x30) {
  2356. ms_set_err_code(chip, MS_FLASH_READ_ERROR);
  2357. TRACE_RET(chip, STATUS_FAIL);
  2358. }
  2359. }
  2360. retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
  2361. SystemParm, 6);
  2362. if (retval != STATUS_SUCCESS)
  2363. TRACE_RET(chip, STATUS_FAIL);
  2364. if (CHK_MS4BIT(ms_card))
  2365. data[0] = 0x88;
  2366. else
  2367. data[0] = 0x80;
  2368. data[1] = 0;
  2369. data[2] = (u8)(phy_blk >> 8);
  2370. data[3] = (u8)phy_blk;
  2371. data[4] = 0;
  2372. data[5] = start_page;
  2373. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  2374. retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
  2375. data, 6);
  2376. if (retval == STATUS_SUCCESS)
  2377. break;
  2378. }
  2379. if (i == MS_MAX_RETRY_COUNT)
  2380. TRACE_RET(chip, STATUS_FAIL);
  2381. ms_set_err_code(chip, MS_NO_ERROR);
  2382. retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
  2383. if (retval != STATUS_SUCCESS)
  2384. TRACE_RET(chip, STATUS_FAIL);
  2385. ptr = buf;
  2386. for (page_addr = start_page; page_addr < end_page; page_addr++) {
  2387. ms_set_err_code(chip, MS_NO_ERROR);
  2388. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  2389. ms_set_err_code(chip, MS_NO_CARD);
  2390. TRACE_RET(chip, STATUS_FAIL);
  2391. }
  2392. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  2393. if (retval != STATUS_SUCCESS)
  2394. TRACE_RET(chip, STATUS_FAIL);
  2395. if (val & INT_REG_CMDNK) {
  2396. ms_set_err_code(chip, MS_CMD_NK);
  2397. TRACE_RET(chip, STATUS_FAIL);
  2398. }
  2399. if (val & INT_REG_ERR) {
  2400. if (val & INT_REG_BREQ) {
  2401. retval = ms_read_status_reg(chip);
  2402. if (retval != STATUS_SUCCESS) {
  2403. if (!(chip->card_wp & MS_CARD)) {
  2404. reset_ms(chip);
  2405. ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE);
  2406. ms_write_extra_data(chip, phy_blk,
  2407. page_addr, extra, MS_EXTRA_SIZE);
  2408. }
  2409. ms_set_err_code(chip, MS_FLASH_READ_ERROR);
  2410. TRACE_RET(chip, STATUS_FAIL);
  2411. }
  2412. } else {
  2413. ms_set_err_code(chip, MS_FLASH_READ_ERROR);
  2414. TRACE_RET(chip, STATUS_FAIL);
  2415. }
  2416. } else {
  2417. if (!(val & INT_REG_BREQ)) {
  2418. ms_set_err_code(chip, MS_BREQ_ERROR);
  2419. TRACE_RET(chip, STATUS_FAIL);
  2420. }
  2421. }
  2422. if (page_addr == (end_page - 1)) {
  2423. if (!(val & INT_REG_CED)) {
  2424. retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
  2425. if (retval != STATUS_SUCCESS)
  2426. TRACE_RET(chip, STATUS_FAIL);
  2427. }
  2428. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,
  2429. &val, 1);
  2430. if (retval != STATUS_SUCCESS)
  2431. TRACE_RET(chip, STATUS_FAIL);
  2432. if (!(val & INT_REG_CED)) {
  2433. ms_set_err_code(chip, MS_FLASH_READ_ERROR);
  2434. TRACE_RET(chip, STATUS_FAIL);
  2435. }
  2436. trans_cfg = NO_WAIT_INT;
  2437. } else {
  2438. trans_cfg = WAIT_INT;
  2439. }
  2440. rtsx_init_cmd(chip);
  2441. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
  2442. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
  2443. 0xFF, trans_cfg);
  2444. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
  2445. 0x01, RING_BUFFER);
  2446. trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
  2447. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
  2448. MS_TRANSFER_START | MS_TM_NORMAL_READ);
  2449. rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
  2450. MS_TRANSFER_END, MS_TRANSFER_END);
  2451. rtsx_send_cmd_no_wait(chip);
  2452. retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr,
  2453. 512, scsi_sg_count(chip->srb),
  2454. index, offset, DMA_FROM_DEVICE,
  2455. chip->ms_timeout);
  2456. if (retval < 0) {
  2457. if (retval == -ETIMEDOUT) {
  2458. ms_set_err_code(chip, MS_TO_ERROR);
  2459. rtsx_clear_ms_error(chip);
  2460. TRACE_RET(chip, STATUS_TIMEDOUT);
  2461. }
  2462. retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
  2463. if (retval != STATUS_SUCCESS) {
  2464. ms_set_err_code(chip, MS_TO_ERROR);
  2465. rtsx_clear_ms_error(chip);
  2466. TRACE_RET(chip, STATUS_TIMEDOUT);
  2467. }
  2468. if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
  2469. ms_set_err_code(chip, MS_CRC16_ERROR);
  2470. rtsx_clear_ms_error(chip);
  2471. TRACE_RET(chip, STATUS_FAIL);
  2472. }
  2473. }
  2474. if (scsi_sg_count(chip->srb) == 0)
  2475. ptr += 512;
  2476. }
  2477. return STATUS_SUCCESS;
  2478. }
  2479. static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk,
  2480. u16 new_blk, u16 log_blk, u8 start_page,
  2481. u8 end_page, u8 *buf, unsigned int *index,
  2482. unsigned int *offset)
  2483. {
  2484. struct ms_info *ms_card = &(chip->ms_card);
  2485. int retval, i;
  2486. u8 page_addr, val, data[16];
  2487. u8 *ptr;
  2488. if (!start_page) {
  2489. retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
  2490. SystemParm, 7);
  2491. if (retval != STATUS_SUCCESS)
  2492. TRACE_RET(chip, STATUS_FAIL);
  2493. if (CHK_MS4BIT(ms_card))
  2494. data[0] = 0x88;
  2495. else
  2496. data[0] = 0x80;
  2497. data[1] = 0;
  2498. data[2] = (u8)(old_blk >> 8);
  2499. data[3] = (u8)old_blk;
  2500. data[4] = 0x80;
  2501. data[5] = 0;
  2502. data[6] = 0xEF;
  2503. data[7] = 0xFF;
  2504. retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,
  2505. data, 8);
  2506. if (retval != STATUS_SUCCESS)
  2507. TRACE_RET(chip, STATUS_FAIL);
  2508. retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
  2509. if (retval != STATUS_SUCCESS)
  2510. TRACE_RET(chip, STATUS_FAIL);
  2511. ms_set_err_code(chip, MS_NO_ERROR);
  2512. retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
  2513. NO_WAIT_INT);
  2514. if (retval != STATUS_SUCCESS)
  2515. TRACE_RET(chip, STATUS_FAIL);
  2516. }
  2517. retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
  2518. SystemParm, (6 + MS_EXTRA_SIZE));
  2519. if (retval != STATUS_SUCCESS)
  2520. TRACE_RET(chip, STATUS_FAIL);
  2521. ms_set_err_code(chip, MS_NO_ERROR);
  2522. if (CHK_MS4BIT(ms_card))
  2523. data[0] = 0x88;
  2524. else
  2525. data[0] = 0x80;
  2526. data[1] = 0;
  2527. data[2] = (u8)(new_blk >> 8);
  2528. data[3] = (u8)new_blk;
  2529. if ((end_page - start_page) == 1)
  2530. data[4] = 0x20;
  2531. else
  2532. data[4] = 0;
  2533. data[5] = start_page;
  2534. data[6] = 0xF8;
  2535. data[7] = 0xFF;
  2536. data[8] = (u8)(log_blk >> 8);
  2537. data[9] = (u8)log_blk;
  2538. for (i = 0x0A; i < 0x10; i++)
  2539. data[i] = 0xFF;
  2540. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  2541. retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,
  2542. NO_WAIT_INT, data, 16);
  2543. if (retval == STATUS_SUCCESS)
  2544. break;
  2545. }
  2546. if (i == MS_MAX_RETRY_COUNT)
  2547. TRACE_RET(chip, STATUS_FAIL);
  2548. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  2549. retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
  2550. if (retval == STATUS_SUCCESS)
  2551. break;
  2552. }
  2553. if (i == MS_MAX_RETRY_COUNT)
  2554. TRACE_RET(chip, STATUS_FAIL);
  2555. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  2556. if (retval != STATUS_SUCCESS)
  2557. TRACE_RET(chip, STATUS_FAIL);
  2558. ptr = buf;
  2559. for (page_addr = start_page; page_addr < end_page; page_addr++) {
  2560. ms_set_err_code(chip, MS_NO_ERROR);
  2561. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  2562. ms_set_err_code(chip, MS_NO_CARD);
  2563. TRACE_RET(chip, STATUS_FAIL);
  2564. }
  2565. if (val & INT_REG_CMDNK) {
  2566. ms_set_err_code(chip, MS_CMD_NK);
  2567. TRACE_RET(chip, STATUS_FAIL);
  2568. }
  2569. if (val & INT_REG_ERR) {
  2570. ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
  2571. TRACE_RET(chip, STATUS_FAIL);
  2572. }
  2573. if (!(val & INT_REG_BREQ)) {
  2574. ms_set_err_code(chip, MS_BREQ_ERROR);
  2575. TRACE_RET(chip, STATUS_FAIL);
  2576. }
  2577. udelay(30);
  2578. rtsx_init_cmd(chip);
  2579. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
  2580. 0xFF, WRITE_PAGE_DATA);
  2581. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
  2582. 0xFF, WAIT_INT);
  2583. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
  2584. 0x01, RING_BUFFER);
  2585. trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
  2586. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
  2587. MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
  2588. rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
  2589. MS_TRANSFER_END, MS_TRANSFER_END);
  2590. rtsx_send_cmd_no_wait(chip);
  2591. retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr,
  2592. 512, scsi_sg_count(chip->srb),
  2593. index, offset, DMA_TO_DEVICE,
  2594. chip->ms_timeout);
  2595. if (retval < 0) {
  2596. ms_set_err_code(chip, MS_TO_ERROR);
  2597. rtsx_clear_ms_error(chip);
  2598. if (retval == -ETIMEDOUT)
  2599. TRACE_RET(chip, STATUS_TIMEDOUT);
  2600. else
  2601. TRACE_RET(chip, STATUS_FAIL);
  2602. }
  2603. retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
  2604. if (retval != STATUS_SUCCESS)
  2605. TRACE_RET(chip, STATUS_FAIL);
  2606. if ((end_page - start_page) == 1) {
  2607. if (!(val & INT_REG_CED)) {
  2608. ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
  2609. TRACE_RET(chip, STATUS_FAIL);
  2610. }
  2611. } else {
  2612. if (page_addr == (end_page - 1)) {
  2613. if (!(val & INT_REG_CED)) {
  2614. retval = ms_send_cmd(chip, BLOCK_END,
  2615. WAIT_INT);
  2616. if (retval != STATUS_SUCCESS)
  2617. TRACE_RET(chip, STATUS_FAIL);
  2618. }
  2619. retval = ms_read_bytes(chip, GET_INT, 1,
  2620. NO_WAIT_INT, &val, 1);
  2621. if (retval != STATUS_SUCCESS)
  2622. TRACE_RET(chip, STATUS_FAIL);
  2623. }
  2624. if ((page_addr == (end_page - 1)) ||
  2625. (page_addr == ms_card->page_off)) {
  2626. if (!(val & INT_REG_CED)) {
  2627. ms_set_err_code(chip,
  2628. MS_FLASH_WRITE_ERROR);
  2629. TRACE_RET(chip, STATUS_FAIL);
  2630. }
  2631. }
  2632. }
  2633. if (scsi_sg_count(chip->srb) == 0)
  2634. ptr += 512;
  2635. }
  2636. return STATUS_SUCCESS;
  2637. }
  2638. static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
  2639. u16 log_blk, u8 page_off)
  2640. {
  2641. struct ms_info *ms_card = &(chip->ms_card);
  2642. int retval, seg_no;
  2643. retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
  2644. page_off, ms_card->page_off + 1);
  2645. if (retval != STATUS_SUCCESS)
  2646. TRACE_RET(chip, STATUS_FAIL);
  2647. seg_no = old_blk >> 9;
  2648. if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
  2649. MS_CLR_BAD_BLOCK_FLG(ms_card);
  2650. ms_set_bad_block(chip, old_blk);
  2651. } else {
  2652. retval = ms_erase_block(chip, old_blk);
  2653. if (retval == STATUS_SUCCESS)
  2654. ms_set_unused_block(chip, old_blk);
  2655. }
  2656. ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
  2657. return STATUS_SUCCESS;
  2658. }
  2659. static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
  2660. u16 log_blk, u8 start_page)
  2661. {
  2662. int retval;
  2663. if (start_page) {
  2664. retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
  2665. 0, start_page);
  2666. if (retval != STATUS_SUCCESS)
  2667. TRACE_RET(chip, STATUS_FAIL);
  2668. }
  2669. return STATUS_SUCCESS;
  2670. }
  2671. #ifdef MS_DELAY_WRITE
  2672. int ms_delay_write(struct rtsx_chip *chip)
  2673. {
  2674. struct ms_info *ms_card = &(chip->ms_card);
  2675. struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
  2676. int retval;
  2677. if (delay_write->delay_write_flag) {
  2678. retval = ms_set_init_para(chip);
  2679. if (retval != STATUS_SUCCESS)
  2680. TRACE_RET(chip, STATUS_FAIL);
  2681. delay_write->delay_write_flag = 0;
  2682. retval = ms_finish_write(chip,
  2683. delay_write->old_phyblock,
  2684. delay_write->new_phyblock,
  2685. delay_write->logblock,
  2686. delay_write->pageoff);
  2687. if (retval != STATUS_SUCCESS)
  2688. TRACE_RET(chip, STATUS_FAIL);
  2689. }
  2690. return STATUS_SUCCESS;
  2691. }
  2692. #endif
  2693. static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip)
  2694. {
  2695. if (srb->sc_data_direction == DMA_FROM_DEVICE)
  2696. set_sense_type(chip, SCSI_LUN(srb),
  2697. SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
  2698. else
  2699. set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
  2700. }
  2701. static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip,
  2702. u32 start_sector, u16 sector_cnt)
  2703. {
  2704. struct ms_info *ms_card = &(chip->ms_card);
  2705. unsigned int lun = SCSI_LUN(srb);
  2706. int retval, seg_no;
  2707. unsigned int index = 0, offset = 0;
  2708. u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
  2709. u8 start_page, end_page = 0, page_cnt;
  2710. u8 *ptr;
  2711. #ifdef MS_DELAY_WRITE
  2712. struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
  2713. #endif
  2714. ms_set_err_code(chip, MS_NO_ERROR);
  2715. ms_card->cleanup_counter = 0;
  2716. ptr = (u8 *)scsi_sglist(srb);
  2717. retval = ms_switch_clock(chip);
  2718. if (retval != STATUS_SUCCESS) {
  2719. ms_rw_fail(srb, chip);
  2720. TRACE_RET(chip, STATUS_FAIL);
  2721. }
  2722. log_blk = (u16)(start_sector >> ms_card->block_shift);
  2723. start_page = (u8)(start_sector & ms_card->page_off);
  2724. for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
  2725. if (log_blk < ms_start_idx[seg_no+1])
  2726. break;
  2727. }
  2728. if (ms_card->segment[seg_no].build_flag == 0) {
  2729. retval = ms_build_l2p_tbl(chip, seg_no);
  2730. if (retval != STATUS_SUCCESS) {
  2731. chip->card_fail |= MS_CARD;
  2732. set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
  2733. TRACE_RET(chip, STATUS_FAIL);
  2734. }
  2735. }
  2736. if (srb->sc_data_direction == DMA_TO_DEVICE) {
  2737. #ifdef MS_DELAY_WRITE
  2738. if (delay_write->delay_write_flag &&
  2739. (delay_write->logblock == log_blk) &&
  2740. (start_page > delay_write->pageoff)) {
  2741. delay_write->delay_write_flag = 0;
  2742. retval = ms_copy_page(chip,
  2743. delay_write->old_phyblock,
  2744. delay_write->new_phyblock, log_blk,
  2745. delay_write->pageoff, start_page);
  2746. if (retval != STATUS_SUCCESS) {
  2747. set_sense_type(chip, lun,
  2748. SENSE_TYPE_MEDIA_WRITE_ERR);
  2749. TRACE_RET(chip, STATUS_FAIL);
  2750. }
  2751. old_blk = delay_write->old_phyblock;
  2752. new_blk = delay_write->new_phyblock;
  2753. } else if (delay_write->delay_write_flag &&
  2754. (delay_write->logblock == log_blk) &&
  2755. (start_page == delay_write->pageoff)) {
  2756. delay_write->delay_write_flag = 0;
  2757. old_blk = delay_write->old_phyblock;
  2758. new_blk = delay_write->new_phyblock;
  2759. } else {
  2760. retval = ms_delay_write(chip);
  2761. if (retval != STATUS_SUCCESS) {
  2762. set_sense_type(chip, lun,
  2763. SENSE_TYPE_MEDIA_WRITE_ERR);
  2764. TRACE_RET(chip, STATUS_FAIL);
  2765. }
  2766. #endif
  2767. old_blk = ms_get_l2p_tbl(chip, seg_no,
  2768. log_blk - ms_start_idx[seg_no]);
  2769. new_blk = ms_get_unused_block(chip, seg_no);
  2770. if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
  2771. set_sense_type(chip, lun,
  2772. SENSE_TYPE_MEDIA_WRITE_ERR);
  2773. TRACE_RET(chip, STATUS_FAIL);
  2774. }
  2775. retval = ms_prepare_write(chip, old_blk, new_blk,
  2776. log_blk, start_page);
  2777. if (retval != STATUS_SUCCESS) {
  2778. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  2779. set_sense_type(chip, lun,
  2780. SENSE_TYPE_MEDIA_NOT_PRESENT);
  2781. TRACE_RET(chip, STATUS_FAIL);
  2782. }
  2783. set_sense_type(chip, lun,
  2784. SENSE_TYPE_MEDIA_WRITE_ERR);
  2785. TRACE_RET(chip, STATUS_FAIL);
  2786. }
  2787. #ifdef MS_DELAY_WRITE
  2788. }
  2789. #endif
  2790. } else {
  2791. #ifdef MS_DELAY_WRITE
  2792. retval = ms_delay_write(chip);
  2793. if (retval != STATUS_SUCCESS) {
  2794. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  2795. set_sense_type(chip, lun,
  2796. SENSE_TYPE_MEDIA_NOT_PRESENT);
  2797. TRACE_RET(chip, STATUS_FAIL);
  2798. }
  2799. set_sense_type(chip, lun,
  2800. SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
  2801. TRACE_RET(chip, STATUS_FAIL);
  2802. }
  2803. #endif
  2804. old_blk = ms_get_l2p_tbl(chip, seg_no,
  2805. log_blk - ms_start_idx[seg_no]);
  2806. if (old_blk == 0xFFFF) {
  2807. set_sense_type(chip, lun,
  2808. SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
  2809. TRACE_RET(chip, STATUS_FAIL);
  2810. }
  2811. }
  2812. dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
  2813. seg_no, old_blk, new_blk);
  2814. while (total_sec_cnt) {
  2815. if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
  2816. end_page = ms_card->page_off + 1;
  2817. else
  2818. end_page = start_page + (u8)total_sec_cnt;
  2819. page_cnt = end_page - start_page;
  2820. dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n",
  2821. start_page, end_page, page_cnt);
  2822. if (srb->sc_data_direction == DMA_FROM_DEVICE) {
  2823. retval = ms_read_multiple_pages(chip,
  2824. old_blk, log_blk, start_page, end_page,
  2825. ptr, &index, &offset);
  2826. } else {
  2827. retval = ms_write_multiple_pages(chip, old_blk,
  2828. new_blk, log_blk, start_page, end_page,
  2829. ptr, &index, &offset);
  2830. }
  2831. if (retval != STATUS_SUCCESS) {
  2832. toggle_gpio(chip, 1);
  2833. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  2834. set_sense_type(chip, lun,
  2835. SENSE_TYPE_MEDIA_NOT_PRESENT);
  2836. TRACE_RET(chip, STATUS_FAIL);
  2837. }
  2838. ms_rw_fail(srb, chip);
  2839. TRACE_RET(chip, STATUS_FAIL);
  2840. }
  2841. if (srb->sc_data_direction == DMA_TO_DEVICE) {
  2842. if (end_page == (ms_card->page_off + 1)) {
  2843. retval = ms_erase_block(chip, old_blk);
  2844. if (retval == STATUS_SUCCESS)
  2845. ms_set_unused_block(chip, old_blk);
  2846. ms_set_l2p_tbl(chip, seg_no,
  2847. log_blk - ms_start_idx[seg_no],
  2848. new_blk);
  2849. }
  2850. }
  2851. total_sec_cnt -= page_cnt;
  2852. if (scsi_sg_count(srb) == 0)
  2853. ptr += page_cnt * 512;
  2854. if (total_sec_cnt == 0)
  2855. break;
  2856. log_blk++;
  2857. for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;
  2858. seg_no++) {
  2859. if (log_blk < ms_start_idx[seg_no+1])
  2860. break;
  2861. }
  2862. if (ms_card->segment[seg_no].build_flag == 0) {
  2863. retval = ms_build_l2p_tbl(chip, seg_no);
  2864. if (retval != STATUS_SUCCESS) {
  2865. chip->card_fail |= MS_CARD;
  2866. set_sense_type(chip, lun,
  2867. SENSE_TYPE_MEDIA_NOT_PRESENT);
  2868. TRACE_RET(chip, STATUS_FAIL);
  2869. }
  2870. }
  2871. old_blk = ms_get_l2p_tbl(chip, seg_no,
  2872. log_blk - ms_start_idx[seg_no]);
  2873. if (old_blk == 0xFFFF) {
  2874. ms_rw_fail(srb, chip);
  2875. TRACE_RET(chip, STATUS_FAIL);
  2876. }
  2877. if (srb->sc_data_direction == DMA_TO_DEVICE) {
  2878. new_blk = ms_get_unused_block(chip, seg_no);
  2879. if (new_blk == 0xFFFF) {
  2880. ms_rw_fail(srb, chip);
  2881. TRACE_RET(chip, STATUS_FAIL);
  2882. }
  2883. }
  2884. dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
  2885. seg_no, old_blk, new_blk);
  2886. start_page = 0;
  2887. }
  2888. if (srb->sc_data_direction == DMA_TO_DEVICE) {
  2889. if (end_page < (ms_card->page_off + 1)) {
  2890. #ifdef MS_DELAY_WRITE
  2891. delay_write->delay_write_flag = 1;
  2892. delay_write->old_phyblock = old_blk;
  2893. delay_write->new_phyblock = new_blk;
  2894. delay_write->logblock = log_blk;
  2895. delay_write->pageoff = end_page;
  2896. #else
  2897. retval = ms_finish_write(chip, old_blk, new_blk,
  2898. log_blk, end_page);
  2899. if (retval != STATUS_SUCCESS) {
  2900. if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
  2901. set_sense_type(chip, lun,
  2902. SENSE_TYPE_MEDIA_NOT_PRESENT);
  2903. TRACE_RET(chip, STATUS_FAIL);
  2904. }
  2905. ms_rw_fail(srb, chip);
  2906. TRACE_RET(chip, STATUS_FAIL);
  2907. }
  2908. #endif
  2909. }
  2910. }
  2911. scsi_set_resid(srb, 0);
  2912. return STATUS_SUCCESS;
  2913. }
  2914. int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
  2915. u32 start_sector, u16 sector_cnt)
  2916. {
  2917. struct ms_info *ms_card = &(chip->ms_card);
  2918. int retval;
  2919. if (CHK_MSPRO(ms_card))
  2920. retval = mspro_rw_multi_sector(srb, chip, start_sector,
  2921. sector_cnt);
  2922. else
  2923. retval = ms_rw_multi_sector(srb, chip, start_sector,
  2924. sector_cnt);
  2925. return retval;
  2926. }
  2927. void ms_free_l2p_tbl(struct rtsx_chip *chip)
  2928. {
  2929. struct ms_info *ms_card = &(chip->ms_card);
  2930. int i = 0;
  2931. if (ms_card->segment != NULL) {
  2932. for (i = 0; i < ms_card->segment_cnt; i++) {
  2933. if (ms_card->segment[i].l2p_table != NULL) {
  2934. vfree(ms_card->segment[i].l2p_table);
  2935. ms_card->segment[i].l2p_table = NULL;
  2936. }
  2937. if (ms_card->segment[i].free_table != NULL) {
  2938. vfree(ms_card->segment[i].free_table);
  2939. ms_card->segment[i].free_table = NULL;
  2940. }
  2941. }
  2942. vfree(ms_card->segment);
  2943. ms_card->segment = NULL;
  2944. }
  2945. }
  2946. #ifdef SUPPORT_MAGIC_GATE
  2947. #ifdef READ_BYTES_WAIT_INT
  2948. static int ms_poll_int(struct rtsx_chip *chip)
  2949. {
  2950. int retval;
  2951. u8 val;
  2952. rtsx_init_cmd(chip);
  2953. rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED);
  2954. retval = rtsx_send_cmd(chip, MS_CARD, 5000);
  2955. if (retval != STATUS_SUCCESS)
  2956. TRACE_RET(chip, STATUS_FAIL);
  2957. val = *rtsx_get_cmd_data(chip);
  2958. if (val & MS_INT_ERR)
  2959. TRACE_RET(chip, STATUS_FAIL);
  2960. return STATUS_SUCCESS;
  2961. }
  2962. #endif
  2963. #ifdef MS_SAMPLE_INT_ERR
  2964. static int check_ms_err(struct rtsx_chip *chip)
  2965. {
  2966. int retval;
  2967. u8 val;
  2968. retval = rtsx_read_register(chip, MS_TRANSFER, &val);
  2969. if (retval != STATUS_SUCCESS)
  2970. return 1;
  2971. if (val & MS_TRANSFER_ERR)
  2972. return 1;
  2973. retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
  2974. if (retval != STATUS_SUCCESS)
  2975. return 1;
  2976. if (val & (MS_INT_ERR | MS_INT_CMDNK))
  2977. return 1;
  2978. return 0;
  2979. }
  2980. #else
  2981. static int check_ms_err(struct rtsx_chip *chip)
  2982. {
  2983. int retval;
  2984. u8 val;
  2985. retval = rtsx_read_register(chip, MS_TRANSFER, &val);
  2986. if (retval != STATUS_SUCCESS)
  2987. return 1;
  2988. if (val & MS_TRANSFER_ERR)
  2989. return 1;
  2990. return 0;
  2991. }
  2992. #endif
  2993. static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num)
  2994. {
  2995. int retval, i;
  2996. u8 data[8];
  2997. data[0] = cmd;
  2998. data[1] = 0;
  2999. data[2] = 0;
  3000. data[3] = 0;
  3001. data[4] = 0;
  3002. data[5] = 0;
  3003. data[6] = entry_num;
  3004. data[7] = 0;
  3005. for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
  3006. retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT,
  3007. data, 8);
  3008. if (retval == STATUS_SUCCESS)
  3009. break;
  3010. }
  3011. if (i == MS_MAX_RETRY_COUNT)
  3012. TRACE_RET(chip, STATUS_FAIL);
  3013. if (check_ms_err(chip)) {
  3014. rtsx_clear_ms_error(chip);
  3015. TRACE_RET(chip, STATUS_FAIL);
  3016. }
  3017. return STATUS_SUCCESS;
  3018. }
  3019. static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type,
  3020. u8 mg_entry_num)
  3021. {
  3022. int retval;
  3023. u8 buf[6];
  3024. if (type == 0)
  3025. retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1);
  3026. else
  3027. retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
  3028. if (retval != STATUS_SUCCESS)
  3029. TRACE_RET(chip, STATUS_FAIL);
  3030. buf[0] = 0;
  3031. buf[1] = 0;
  3032. if (type == 1) {
  3033. buf[2] = 0;
  3034. buf[3] = 0;
  3035. buf[4] = 0;
  3036. buf[5] = mg_entry_num;
  3037. }
  3038. retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6,
  3039. NO_WAIT_INT, buf, 6);
  3040. if (retval != STATUS_SUCCESS)
  3041. TRACE_RET(chip, STATUS_FAIL);
  3042. return STATUS_SUCCESS;
  3043. }
  3044. int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
  3045. {
  3046. int retval;
  3047. int i;
  3048. unsigned int lun = SCSI_LUN(srb);
  3049. u8 buf1[32], buf2[12];
  3050. if (scsi_bufflen(srb) < 12) {
  3051. set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
  3052. TRACE_RET(chip, STATUS_FAIL);
  3053. }
  3054. ms_cleanup_work(chip);
  3055. retval = ms_switch_clock(chip);
  3056. if (retval != STATUS_SUCCESS)
  3057. TRACE_RET(chip, STATUS_FAIL);
  3058. retval = mg_send_ex_cmd(chip, MG_SET_LID, 0);
  3059. if (retval != STATUS_SUCCESS) {
  3060. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
  3061. TRACE_RET(chip, STATUS_FAIL);
  3062. }
  3063. memset(buf1, 0, 32);
  3064. rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb);
  3065. for (i = 0; i < 8; i++)
  3066. buf1[8+i] = buf2[4+i];
  3067. retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
  3068. buf1, 32);
  3069. if (retval != STATUS_SUCCESS) {
  3070. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
  3071. TRACE_RET(chip, STATUS_FAIL);
  3072. }
  3073. if (check_ms_err(chip)) {
  3074. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
  3075. rtsx_clear_ms_error(chip);
  3076. TRACE_RET(chip, STATUS_FAIL);
  3077. }
  3078. return STATUS_SUCCESS;
  3079. }
  3080. int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip)
  3081. {
  3082. int retval = STATUS_FAIL;
  3083. int bufflen;
  3084. unsigned int lun = SCSI_LUN(srb);
  3085. u8 *buf = NULL;
  3086. ms_cleanup_work(chip);
  3087. retval = ms_switch_clock(chip);
  3088. if (retval != STATUS_SUCCESS)
  3089. TRACE_RET(chip, STATUS_FAIL);
  3090. buf = kmalloc(1540, GFP_KERNEL);
  3091. if (!buf)
  3092. TRACE_RET(chip, STATUS_ERROR);
  3093. buf[0] = 0x04;
  3094. buf[1] = 0x1A;
  3095. buf[2] = 0x00;
  3096. buf[3] = 0x00;
  3097. retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0);
  3098. if (retval != STATUS_SUCCESS) {
  3099. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3100. TRACE_GOTO(chip, GetEKBFinish);
  3101. }
  3102. retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
  3103. 3, WAIT_INT, 0, 0, buf + 4, 1536);
  3104. if (retval != STATUS_SUCCESS) {
  3105. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3106. rtsx_clear_ms_error(chip);
  3107. TRACE_GOTO(chip, GetEKBFinish);
  3108. }
  3109. if (check_ms_err(chip)) {
  3110. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3111. rtsx_clear_ms_error(chip);
  3112. TRACE_RET(chip, STATUS_FAIL);
  3113. }
  3114. bufflen = min_t(int, 1052, scsi_bufflen(srb));
  3115. rtsx_stor_set_xfer_buf(buf, bufflen, srb);
  3116. GetEKBFinish:
  3117. kfree(buf);
  3118. return retval;
  3119. }
  3120. int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
  3121. {
  3122. struct ms_info *ms_card = &(chip->ms_card);
  3123. int retval;
  3124. int bufflen;
  3125. int i;
  3126. unsigned int lun = SCSI_LUN(srb);
  3127. u8 buf[32];
  3128. ms_cleanup_work(chip);
  3129. retval = ms_switch_clock(chip);
  3130. if (retval != STATUS_SUCCESS)
  3131. TRACE_RET(chip, STATUS_FAIL);
  3132. retval = mg_send_ex_cmd(chip, MG_GET_ID, 0);
  3133. if (retval != STATUS_SUCCESS) {
  3134. set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
  3135. TRACE_RET(chip, STATUS_FAIL);
  3136. }
  3137. retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
  3138. buf, 32);
  3139. if (retval != STATUS_SUCCESS) {
  3140. set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
  3141. TRACE_RET(chip, STATUS_FAIL);
  3142. }
  3143. if (check_ms_err(chip)) {
  3144. set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
  3145. rtsx_clear_ms_error(chip);
  3146. TRACE_RET(chip, STATUS_FAIL);
  3147. }
  3148. memcpy(ms_card->magic_gate_id, buf, 16);
  3149. #ifdef READ_BYTES_WAIT_INT
  3150. retval = ms_poll_int(chip);
  3151. if (retval != STATUS_SUCCESS) {
  3152. set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
  3153. TRACE_RET(chip, STATUS_FAIL);
  3154. }
  3155. #endif
  3156. retval = mg_send_ex_cmd(chip, MG_SET_RD, 0);
  3157. if (retval != STATUS_SUCCESS) {
  3158. set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
  3159. TRACE_RET(chip, STATUS_FAIL);
  3160. }
  3161. bufflen = min_t(int, 12, scsi_bufflen(srb));
  3162. rtsx_stor_get_xfer_buf(buf, bufflen, srb);
  3163. for (i = 0; i < 8; i++)
  3164. buf[i] = buf[4+i];
  3165. for (i = 0; i < 24; i++)
  3166. buf[8+i] = 0;
  3167. retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA,
  3168. 32, WAIT_INT, buf, 32);
  3169. if (retval != STATUS_SUCCESS) {
  3170. set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
  3171. TRACE_RET(chip, STATUS_FAIL);
  3172. }
  3173. if (check_ms_err(chip)) {
  3174. set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
  3175. rtsx_clear_ms_error(chip);
  3176. TRACE_RET(chip, STATUS_FAIL);
  3177. }
  3178. ms_card->mg_auth = 0;
  3179. return STATUS_SUCCESS;
  3180. }
  3181. int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
  3182. {
  3183. struct ms_info *ms_card = &(chip->ms_card);
  3184. int retval;
  3185. int bufflen;
  3186. unsigned int lun = SCSI_LUN(srb);
  3187. u8 buf1[32], buf2[36];
  3188. ms_cleanup_work(chip);
  3189. retval = ms_switch_clock(chip);
  3190. if (retval != STATUS_SUCCESS)
  3191. TRACE_RET(chip, STATUS_FAIL);
  3192. retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0);
  3193. if (retval != STATUS_SUCCESS) {
  3194. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3195. TRACE_RET(chip, STATUS_FAIL);
  3196. }
  3197. retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
  3198. buf1, 32);
  3199. if (retval != STATUS_SUCCESS) {
  3200. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3201. TRACE_RET(chip, STATUS_FAIL);
  3202. }
  3203. if (check_ms_err(chip)) {
  3204. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3205. rtsx_clear_ms_error(chip);
  3206. TRACE_RET(chip, STATUS_FAIL);
  3207. }
  3208. buf2[0] = 0x00;
  3209. buf2[1] = 0x22;
  3210. buf2[2] = 0x00;
  3211. buf2[3] = 0x00;
  3212. memcpy(buf2 + 4, ms_card->magic_gate_id, 16);
  3213. memcpy(buf2 + 20, buf1, 16);
  3214. bufflen = min_t(int, 36, scsi_bufflen(srb));
  3215. rtsx_stor_set_xfer_buf(buf2, bufflen, srb);
  3216. #ifdef READ_BYTES_WAIT_INT
  3217. retval = ms_poll_int(chip);
  3218. if (retval != STATUS_SUCCESS) {
  3219. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3220. TRACE_RET(chip, STATUS_FAIL);
  3221. }
  3222. #endif
  3223. return STATUS_SUCCESS;
  3224. }
  3225. int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
  3226. {
  3227. struct ms_info *ms_card = &(chip->ms_card);
  3228. int retval;
  3229. int i;
  3230. int bufflen;
  3231. unsigned int lun = SCSI_LUN(srb);
  3232. u8 buf[32];
  3233. ms_cleanup_work(chip);
  3234. retval = ms_switch_clock(chip);
  3235. if (retval != STATUS_SUCCESS)
  3236. TRACE_RET(chip, STATUS_FAIL);
  3237. retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0);
  3238. if (retval != STATUS_SUCCESS) {
  3239. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3240. TRACE_RET(chip, STATUS_FAIL);
  3241. }
  3242. bufflen = min_t(int, 12, scsi_bufflen(srb));
  3243. rtsx_stor_get_xfer_buf(buf, bufflen, srb);
  3244. for (i = 0; i < 8; i++)
  3245. buf[i] = buf[4+i];
  3246. for (i = 0; i < 24; i++)
  3247. buf[8+i] = 0;
  3248. retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
  3249. buf, 32);
  3250. if (retval != STATUS_SUCCESS) {
  3251. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3252. TRACE_RET(chip, STATUS_FAIL);
  3253. }
  3254. if (check_ms_err(chip)) {
  3255. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
  3256. rtsx_clear_ms_error(chip);
  3257. TRACE_RET(chip, STATUS_FAIL);
  3258. }
  3259. ms_card->mg_auth = 1;
  3260. return STATUS_SUCCESS;
  3261. }
  3262. int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
  3263. {
  3264. struct ms_info *ms_card = &(chip->ms_card);
  3265. int retval;
  3266. int bufflen;
  3267. unsigned int lun = SCSI_LUN(srb);
  3268. u8 *buf = NULL;
  3269. ms_cleanup_work(chip);
  3270. retval = ms_switch_clock(chip);
  3271. if (retval != STATUS_SUCCESS)
  3272. TRACE_RET(chip, STATUS_FAIL);
  3273. buf = kmalloc(1028, GFP_KERNEL);
  3274. if (!buf)
  3275. TRACE_RET(chip, STATUS_ERROR);
  3276. buf[0] = 0x04;
  3277. buf[1] = 0x02;
  3278. buf[2] = 0x00;
  3279. buf[3] = 0x00;
  3280. retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num);
  3281. if (retval != STATUS_SUCCESS) {
  3282. set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
  3283. TRACE_GOTO(chip, GetICVFinish);
  3284. }
  3285. retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
  3286. 2, WAIT_INT, 0, 0, buf + 4, 1024);
  3287. if (retval != STATUS_SUCCESS) {
  3288. set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
  3289. rtsx_clear_ms_error(chip);
  3290. TRACE_GOTO(chip, GetICVFinish);
  3291. }
  3292. if (check_ms_err(chip)) {
  3293. set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
  3294. rtsx_clear_ms_error(chip);
  3295. TRACE_RET(chip, STATUS_FAIL);
  3296. }
  3297. bufflen = min_t(int, 1028, scsi_bufflen(srb));
  3298. rtsx_stor_set_xfer_buf(buf, bufflen, srb);
  3299. GetICVFinish:
  3300. kfree(buf);
  3301. return retval;
  3302. }
  3303. int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
  3304. {
  3305. struct ms_info *ms_card = &(chip->ms_card);
  3306. int retval;
  3307. int bufflen;
  3308. #ifdef MG_SET_ICV_SLOW
  3309. int i;
  3310. #endif
  3311. unsigned int lun = SCSI_LUN(srb);
  3312. u8 *buf = NULL;
  3313. ms_cleanup_work(chip);
  3314. retval = ms_switch_clock(chip);
  3315. if (retval != STATUS_SUCCESS)
  3316. TRACE_RET(chip, STATUS_FAIL);
  3317. buf = kmalloc(1028, GFP_KERNEL);
  3318. if (!buf)
  3319. TRACE_RET(chip, STATUS_ERROR);
  3320. bufflen = min_t(int, 1028, scsi_bufflen(srb));
  3321. rtsx_stor_get_xfer_buf(buf, bufflen, srb);
  3322. retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num);
  3323. if (retval != STATUS_SUCCESS) {
  3324. if (ms_card->mg_auth == 0) {
  3325. if ((buf[5] & 0xC0) != 0)
  3326. set_sense_type(chip, lun,
  3327. SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
  3328. else
  3329. set_sense_type(chip, lun,
  3330. SENSE_TYPE_MG_WRITE_ERR);
  3331. } else {
  3332. set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
  3333. }
  3334. TRACE_GOTO(chip, SetICVFinish);
  3335. }
  3336. #ifdef MG_SET_ICV_SLOW
  3337. for (i = 0; i < 2; i++) {
  3338. udelay(50);
  3339. rtsx_init_cmd(chip);
  3340. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
  3341. 0xFF, PRO_WRITE_LONG_DATA);
  3342. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
  3343. rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
  3344. 0x01, RING_BUFFER);
  3345. trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
  3346. rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
  3347. MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
  3348. rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
  3349. MS_TRANSFER_END, MS_TRANSFER_END);
  3350. rtsx_send_cmd_no_wait(chip);
  3351. retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i*512,
  3352. 512, 0, DMA_TO_DEVICE, 3000);
  3353. if ((retval < 0) || check_ms_err(chip)) {
  3354. rtsx_clear_ms_error(chip);
  3355. if (ms_card->mg_auth == 0) {
  3356. if ((buf[5] & 0xC0) != 0)
  3357. set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
  3358. else
  3359. set_sense_type(chip, lun,
  3360. SENSE_TYPE_MG_WRITE_ERR);
  3361. } else {
  3362. set_sense_type(chip, lun,
  3363. SENSE_TYPE_MG_WRITE_ERR);
  3364. }
  3365. retval = STATUS_FAIL;
  3366. TRACE_GOTO(chip, SetICVFinish);
  3367. }
  3368. }
  3369. #else
  3370. retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA,
  3371. 2, WAIT_INT, 0, 0, buf + 4, 1024);
  3372. if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) {
  3373. rtsx_clear_ms_error(chip);
  3374. if (ms_card->mg_auth == 0) {
  3375. if ((buf[5] & 0xC0) != 0)
  3376. set_sense_type(chip, lun,
  3377. SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
  3378. else
  3379. set_sense_type(chip, lun,
  3380. SENSE_TYPE_MG_WRITE_ERR);
  3381. } else {
  3382. set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
  3383. }
  3384. TRACE_GOTO(chip, SetICVFinish);
  3385. }
  3386. #endif
  3387. SetICVFinish:
  3388. kfree(buf);
  3389. return retval;
  3390. }
  3391. #endif /* SUPPORT_MAGIC_GATE */
  3392. void ms_cleanup_work(struct rtsx_chip *chip)
  3393. {
  3394. struct ms_info *ms_card = &(chip->ms_card);
  3395. if (CHK_MSPRO(ms_card)) {
  3396. if (ms_card->seq_mode) {
  3397. dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n");
  3398. mspro_stop_seq_mode(chip);
  3399. ms_card->cleanup_counter = 0;
  3400. }
  3401. if (CHK_MSHG(ms_card)) {
  3402. rtsx_write_register(chip, MS_CFG,
  3403. MS_2K_SECTOR_MODE, 0x00);
  3404. }
  3405. }
  3406. #ifdef MS_DELAY_WRITE
  3407. else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) {
  3408. dev_dbg(rtsx_dev(chip), "MS: delay write\n");
  3409. ms_delay_write(chip);
  3410. ms_card->cleanup_counter = 0;
  3411. }
  3412. #endif
  3413. }
  3414. int ms_power_off_card3v3(struct rtsx_chip *chip)
  3415. {
  3416. int retval;
  3417. retval = disable_card_clock(chip, MS_CARD);
  3418. if (retval != STATUS_SUCCESS)
  3419. TRACE_RET(chip, STATUS_FAIL);
  3420. if (chip->asic_code) {
  3421. retval = ms_pull_ctl_disable(chip);
  3422. if (retval != STATUS_SUCCESS)
  3423. TRACE_RET(chip, STATUS_FAIL);
  3424. } else {
  3425. RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
  3426. FPGA_MS_PULL_CTL_BIT | 0x20, FPGA_MS_PULL_CTL_BIT);
  3427. }
  3428. RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, 0);
  3429. if (!chip->ft2_fast_mode) {
  3430. retval = card_power_off(chip, MS_CARD);
  3431. if (retval != STATUS_SUCCESS)
  3432. TRACE_RET(chip, STATUS_FAIL);
  3433. }
  3434. return STATUS_SUCCESS;
  3435. }
  3436. int release_ms_card(struct rtsx_chip *chip)
  3437. {
  3438. struct ms_info *ms_card = &(chip->ms_card);
  3439. int retval;
  3440. #ifdef MS_DELAY_WRITE
  3441. ms_card->delay_write.delay_write_flag = 0;
  3442. #endif
  3443. ms_card->pro_under_formatting = 0;
  3444. chip->card_ready &= ~MS_CARD;
  3445. chip->card_fail &= ~MS_CARD;
  3446. chip->card_wp &= ~MS_CARD;
  3447. ms_free_l2p_tbl(chip);
  3448. memset(ms_card->raw_sys_info, 0, 96);
  3449. #ifdef SUPPORT_PCGL_1P18
  3450. memset(ms_card->raw_model_name, 0, 48);
  3451. #endif
  3452. retval = ms_power_off_card3v3(chip);
  3453. if (retval != STATUS_SUCCESS)
  3454. TRACE_RET(chip, STATUS_FAIL);
  3455. return STATUS_SUCCESS;
  3456. }