oxu210hp-hcd.c 98 KB

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  1. /*
  2. * Copyright (c) 2008 Rodolfo Giometti <giometti@linux.it>
  3. * Copyright (c) 2008 Eurotech S.p.A. <info@eurtech.it>
  4. *
  5. * This code is *strongly* based on EHCI-HCD code by David Brownell since
  6. * the chip is a quasi-EHCI compatible.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/dmapool.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/errno.h>
  31. #include <linux/timer.h>
  32. #include <linux/list.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/usb.h>
  35. #include <linux/usb/hcd.h>
  36. #include <linux/moduleparam.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/io.h>
  39. #include <asm/irq.h>
  40. #include <asm/unaligned.h>
  41. #include <linux/irq.h>
  42. #include <linux/platform_device.h>
  43. #include "oxu210hp.h"
  44. #define DRIVER_VERSION "0.0.50"
  45. /*
  46. * Main defines
  47. */
  48. #define oxu_dbg(oxu, fmt, args...) \
  49. dev_dbg(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  50. #define oxu_err(oxu, fmt, args...) \
  51. dev_err(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  52. #define oxu_info(oxu, fmt, args...) \
  53. dev_info(oxu_to_hcd(oxu)->self.controller , fmt , ## args)
  54. #ifdef CONFIG_DYNAMIC_DEBUG
  55. #define DEBUG
  56. #endif
  57. static inline struct usb_hcd *oxu_to_hcd(struct oxu_hcd *oxu)
  58. {
  59. return container_of((void *) oxu, struct usb_hcd, hcd_priv);
  60. }
  61. static inline struct oxu_hcd *hcd_to_oxu(struct usb_hcd *hcd)
  62. {
  63. return (struct oxu_hcd *) (hcd->hcd_priv);
  64. }
  65. /*
  66. * Debug stuff
  67. */
  68. #undef OXU_URB_TRACE
  69. #undef OXU_VERBOSE_DEBUG
  70. #ifdef OXU_VERBOSE_DEBUG
  71. #define oxu_vdbg oxu_dbg
  72. #else
  73. #define oxu_vdbg(oxu, fmt, args...) /* Nop */
  74. #endif
  75. #ifdef DEBUG
  76. static int __attribute__((__unused__))
  77. dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
  78. {
  79. return scnprintf(buf, len, "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
  80. label, label[0] ? " " : "", status,
  81. (status & STS_ASS) ? " Async" : "",
  82. (status & STS_PSS) ? " Periodic" : "",
  83. (status & STS_RECL) ? " Recl" : "",
  84. (status & STS_HALT) ? " Halt" : "",
  85. (status & STS_IAA) ? " IAA" : "",
  86. (status & STS_FATAL) ? " FATAL" : "",
  87. (status & STS_FLR) ? " FLR" : "",
  88. (status & STS_PCD) ? " PCD" : "",
  89. (status & STS_ERR) ? " ERR" : "",
  90. (status & STS_INT) ? " INT" : ""
  91. );
  92. }
  93. static int __attribute__((__unused__))
  94. dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
  95. {
  96. return scnprintf(buf, len, "%s%sintrenable %02x%s%s%s%s%s%s",
  97. label, label[0] ? " " : "", enable,
  98. (enable & STS_IAA) ? " IAA" : "",
  99. (enable & STS_FATAL) ? " FATAL" : "",
  100. (enable & STS_FLR) ? " FLR" : "",
  101. (enable & STS_PCD) ? " PCD" : "",
  102. (enable & STS_ERR) ? " ERR" : "",
  103. (enable & STS_INT) ? " INT" : ""
  104. );
  105. }
  106. static const char *const fls_strings[] =
  107. { "1024", "512", "256", "??" };
  108. static int dbg_command_buf(char *buf, unsigned len,
  109. const char *label, u32 command)
  110. {
  111. return scnprintf(buf, len,
  112. "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
  113. label, label[0] ? " " : "", command,
  114. (command & CMD_PARK) ? "park" : "(park)",
  115. CMD_PARK_CNT(command),
  116. (command >> 16) & 0x3f,
  117. (command & CMD_LRESET) ? " LReset" : "",
  118. (command & CMD_IAAD) ? " IAAD" : "",
  119. (command & CMD_ASE) ? " Async" : "",
  120. (command & CMD_PSE) ? " Periodic" : "",
  121. fls_strings[(command >> 2) & 0x3],
  122. (command & CMD_RESET) ? " Reset" : "",
  123. (command & CMD_RUN) ? "RUN" : "HALT"
  124. );
  125. }
  126. static int dbg_port_buf(char *buf, unsigned len, const char *label,
  127. int port, u32 status)
  128. {
  129. char *sig;
  130. /* signaling state */
  131. switch (status & (3 << 10)) {
  132. case 0 << 10:
  133. sig = "se0";
  134. break;
  135. case 1 << 10:
  136. sig = "k"; /* low speed */
  137. break;
  138. case 2 << 10:
  139. sig = "j";
  140. break;
  141. default:
  142. sig = "?";
  143. break;
  144. }
  145. return scnprintf(buf, len,
  146. "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
  147. label, label[0] ? " " : "", port, status,
  148. (status & PORT_POWER) ? " POWER" : "",
  149. (status & PORT_OWNER) ? " OWNER" : "",
  150. sig,
  151. (status & PORT_RESET) ? " RESET" : "",
  152. (status & PORT_SUSPEND) ? " SUSPEND" : "",
  153. (status & PORT_RESUME) ? " RESUME" : "",
  154. (status & PORT_OCC) ? " OCC" : "",
  155. (status & PORT_OC) ? " OC" : "",
  156. (status & PORT_PEC) ? " PEC" : "",
  157. (status & PORT_PE) ? " PE" : "",
  158. (status & PORT_CSC) ? " CSC" : "",
  159. (status & PORT_CONNECT) ? " CONNECT" : ""
  160. );
  161. }
  162. #else
  163. static inline int __attribute__((__unused__))
  164. dbg_status_buf(char *buf, unsigned len, const char *label, u32 status)
  165. { return 0; }
  166. static inline int __attribute__((__unused__))
  167. dbg_command_buf(char *buf, unsigned len, const char *label, u32 command)
  168. { return 0; }
  169. static inline int __attribute__((__unused__))
  170. dbg_intr_buf(char *buf, unsigned len, const char *label, u32 enable)
  171. { return 0; }
  172. static inline int __attribute__((__unused__))
  173. dbg_port_buf(char *buf, unsigned len, const char *label, int port, u32 status)
  174. { return 0; }
  175. #endif /* DEBUG */
  176. /* functions have the "wrong" filename when they're output... */
  177. #define dbg_status(oxu, label, status) { \
  178. char _buf[80]; \
  179. dbg_status_buf(_buf, sizeof _buf, label, status); \
  180. oxu_dbg(oxu, "%s\n", _buf); \
  181. }
  182. #define dbg_cmd(oxu, label, command) { \
  183. char _buf[80]; \
  184. dbg_command_buf(_buf, sizeof _buf, label, command); \
  185. oxu_dbg(oxu, "%s\n", _buf); \
  186. }
  187. #define dbg_port(oxu, label, port, status) { \
  188. char _buf[80]; \
  189. dbg_port_buf(_buf, sizeof _buf, label, port, status); \
  190. oxu_dbg(oxu, "%s\n", _buf); \
  191. }
  192. /*
  193. * Module parameters
  194. */
  195. /* Initial IRQ latency: faster than hw default */
  196. static int log2_irq_thresh; /* 0 to 6 */
  197. module_param(log2_irq_thresh, int, S_IRUGO);
  198. MODULE_PARM_DESC(log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
  199. /* Initial park setting: slower than hw default */
  200. static unsigned park;
  201. module_param(park, uint, S_IRUGO);
  202. MODULE_PARM_DESC(park, "park setting; 1-3 back-to-back async packets");
  203. /* For flakey hardware, ignore overcurrent indicators */
  204. static bool ignore_oc;
  205. module_param(ignore_oc, bool, S_IRUGO);
  206. MODULE_PARM_DESC(ignore_oc, "ignore bogus hardware overcurrent indications");
  207. static void ehci_work(struct oxu_hcd *oxu);
  208. static int oxu_hub_control(struct usb_hcd *hcd,
  209. u16 typeReq, u16 wValue, u16 wIndex,
  210. char *buf, u16 wLength);
  211. /*
  212. * Local functions
  213. */
  214. /* Low level read/write registers functions */
  215. static inline u32 oxu_readl(void *base, u32 reg)
  216. {
  217. return readl(base + reg);
  218. }
  219. static inline void oxu_writel(void *base, u32 reg, u32 val)
  220. {
  221. writel(val, base + reg);
  222. }
  223. static inline void timer_action_done(struct oxu_hcd *oxu,
  224. enum ehci_timer_action action)
  225. {
  226. clear_bit(action, &oxu->actions);
  227. }
  228. static inline void timer_action(struct oxu_hcd *oxu,
  229. enum ehci_timer_action action)
  230. {
  231. if (!test_and_set_bit(action, &oxu->actions)) {
  232. unsigned long t;
  233. switch (action) {
  234. case TIMER_IAA_WATCHDOG:
  235. t = EHCI_IAA_JIFFIES;
  236. break;
  237. case TIMER_IO_WATCHDOG:
  238. t = EHCI_IO_JIFFIES;
  239. break;
  240. case TIMER_ASYNC_OFF:
  241. t = EHCI_ASYNC_JIFFIES;
  242. break;
  243. case TIMER_ASYNC_SHRINK:
  244. default:
  245. t = EHCI_SHRINK_JIFFIES;
  246. break;
  247. }
  248. t += jiffies;
  249. /* all timings except IAA watchdog can be overridden.
  250. * async queue SHRINK often precedes IAA. while it's ready
  251. * to go OFF neither can matter, and afterwards the IO
  252. * watchdog stops unless there's still periodic traffic.
  253. */
  254. if (action != TIMER_IAA_WATCHDOG
  255. && t > oxu->watchdog.expires
  256. && timer_pending(&oxu->watchdog))
  257. return;
  258. mod_timer(&oxu->watchdog, t);
  259. }
  260. }
  261. /*
  262. * handshake - spin reading hc until handshake completes or fails
  263. * @ptr: address of hc register to be read
  264. * @mask: bits to look at in result of read
  265. * @done: value of those bits when handshake succeeds
  266. * @usec: timeout in microseconds
  267. *
  268. * Returns negative errno, or zero on success
  269. *
  270. * Success happens when the "mask" bits have the specified value (hardware
  271. * handshake done). There are two failure modes: "usec" have passed (major
  272. * hardware flakeout), or the register reads as all-ones (hardware removed).
  273. *
  274. * That last failure should_only happen in cases like physical cardbus eject
  275. * before driver shutdown. But it also seems to be caused by bugs in cardbus
  276. * bridge shutdown: shutting down the bridge before the devices using it.
  277. */
  278. static int handshake(struct oxu_hcd *oxu, void __iomem *ptr,
  279. u32 mask, u32 done, int usec)
  280. {
  281. u32 result;
  282. do {
  283. result = readl(ptr);
  284. if (result == ~(u32)0) /* card removed */
  285. return -ENODEV;
  286. result &= mask;
  287. if (result == done)
  288. return 0;
  289. udelay(1);
  290. usec--;
  291. } while (usec > 0);
  292. return -ETIMEDOUT;
  293. }
  294. /* Force HC to halt state from unknown (EHCI spec section 2.3) */
  295. static int ehci_halt(struct oxu_hcd *oxu)
  296. {
  297. u32 temp = readl(&oxu->regs->status);
  298. /* disable any irqs left enabled by previous code */
  299. writel(0, &oxu->regs->intr_enable);
  300. if ((temp & STS_HALT) != 0)
  301. return 0;
  302. temp = readl(&oxu->regs->command);
  303. temp &= ~CMD_RUN;
  304. writel(temp, &oxu->regs->command);
  305. return handshake(oxu, &oxu->regs->status,
  306. STS_HALT, STS_HALT, 16 * 125);
  307. }
  308. /* Put TDI/ARC silicon into EHCI mode */
  309. static void tdi_reset(struct oxu_hcd *oxu)
  310. {
  311. u32 __iomem *reg_ptr;
  312. u32 tmp;
  313. reg_ptr = (u32 __iomem *)(((u8 __iomem *)oxu->regs) + 0x68);
  314. tmp = readl(reg_ptr);
  315. tmp |= 0x3;
  316. writel(tmp, reg_ptr);
  317. }
  318. /* Reset a non-running (STS_HALT == 1) controller */
  319. static int ehci_reset(struct oxu_hcd *oxu)
  320. {
  321. int retval;
  322. u32 command = readl(&oxu->regs->command);
  323. command |= CMD_RESET;
  324. dbg_cmd(oxu, "reset", command);
  325. writel(command, &oxu->regs->command);
  326. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  327. oxu->next_statechange = jiffies;
  328. retval = handshake(oxu, &oxu->regs->command,
  329. CMD_RESET, 0, 250 * 1000);
  330. if (retval)
  331. return retval;
  332. tdi_reset(oxu);
  333. return retval;
  334. }
  335. /* Idle the controller (from running) */
  336. static void ehci_quiesce(struct oxu_hcd *oxu)
  337. {
  338. u32 temp;
  339. #ifdef DEBUG
  340. if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  341. BUG();
  342. #endif
  343. /* wait for any schedule enables/disables to take effect */
  344. temp = readl(&oxu->regs->command) << 10;
  345. temp &= STS_ASS | STS_PSS;
  346. if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
  347. temp, 16 * 125) != 0) {
  348. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  349. return;
  350. }
  351. /* then disable anything that's still active */
  352. temp = readl(&oxu->regs->command);
  353. temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
  354. writel(temp, &oxu->regs->command);
  355. /* hardware can take 16 microframes to turn off ... */
  356. if (handshake(oxu, &oxu->regs->status, STS_ASS | STS_PSS,
  357. 0, 16 * 125) != 0) {
  358. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  359. return;
  360. }
  361. }
  362. static int check_reset_complete(struct oxu_hcd *oxu, int index,
  363. u32 __iomem *status_reg, int port_status)
  364. {
  365. if (!(port_status & PORT_CONNECT)) {
  366. oxu->reset_done[index] = 0;
  367. return port_status;
  368. }
  369. /* if reset finished and it's still not enabled -- handoff */
  370. if (!(port_status & PORT_PE)) {
  371. oxu_dbg(oxu, "Failed to enable port %d on root hub TT\n",
  372. index+1);
  373. return port_status;
  374. } else
  375. oxu_dbg(oxu, "port %d high speed\n", index + 1);
  376. return port_status;
  377. }
  378. static void ehci_hub_descriptor(struct oxu_hcd *oxu,
  379. struct usb_hub_descriptor *desc)
  380. {
  381. int ports = HCS_N_PORTS(oxu->hcs_params);
  382. u16 temp;
  383. desc->bDescriptorType = 0x29;
  384. desc->bPwrOn2PwrGood = 10; /* oxu 1.0, 2.3.9 says 20ms max */
  385. desc->bHubContrCurrent = 0;
  386. desc->bNbrPorts = ports;
  387. temp = 1 + (ports / 8);
  388. desc->bDescLength = 7 + 2 * temp;
  389. /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
  390. memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
  391. memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
  392. temp = 0x0008; /* per-port overcurrent reporting */
  393. if (HCS_PPC(oxu->hcs_params))
  394. temp |= 0x0001; /* per-port power control */
  395. else
  396. temp |= 0x0002; /* no power switching */
  397. desc->wHubCharacteristics = (__force __u16)cpu_to_le16(temp);
  398. }
  399. /* Allocate an OXU210HP on-chip memory data buffer
  400. *
  401. * An on-chip memory data buffer is required for each OXU210HP USB transfer.
  402. * Each transfer descriptor has one or more on-chip memory data buffers.
  403. *
  404. * Data buffers are allocated from a fix sized pool of data blocks.
  405. * To minimise fragmentation and give reasonable memory utlisation,
  406. * data buffers are allocated with sizes the power of 2 multiples of
  407. * the block size, starting on an address a multiple of the allocated size.
  408. *
  409. * FIXME: callers of this function require a buffer to be allocated for
  410. * len=0. This is a waste of on-chip memory and should be fix. Then this
  411. * function should be changed to not allocate a buffer for len=0.
  412. */
  413. static int oxu_buf_alloc(struct oxu_hcd *oxu, struct ehci_qtd *qtd, int len)
  414. {
  415. int n_blocks; /* minium blocks needed to hold len */
  416. int a_blocks; /* blocks allocated */
  417. int i, j;
  418. /* Don't allocte bigger than supported */
  419. if (len > BUFFER_SIZE * BUFFER_NUM) {
  420. oxu_err(oxu, "buffer too big (%d)\n", len);
  421. return -ENOMEM;
  422. }
  423. spin_lock(&oxu->mem_lock);
  424. /* Number of blocks needed to hold len */
  425. n_blocks = (len + BUFFER_SIZE - 1) / BUFFER_SIZE;
  426. /* Round the number of blocks up to the power of 2 */
  427. for (a_blocks = 1; a_blocks < n_blocks; a_blocks <<= 1)
  428. ;
  429. /* Find a suitable available data buffer */
  430. for (i = 0; i < BUFFER_NUM;
  431. i += max(a_blocks, (int)oxu->db_used[i])) {
  432. /* Check all the required blocks are available */
  433. for (j = 0; j < a_blocks; j++)
  434. if (oxu->db_used[i + j])
  435. break;
  436. if (j != a_blocks)
  437. continue;
  438. /* Allocate blocks found! */
  439. qtd->buffer = (void *) &oxu->mem->db_pool[i];
  440. qtd->buffer_dma = virt_to_phys(qtd->buffer);
  441. qtd->qtd_buffer_len = BUFFER_SIZE * a_blocks;
  442. oxu->db_used[i] = a_blocks;
  443. spin_unlock(&oxu->mem_lock);
  444. return 0;
  445. }
  446. /* Failed */
  447. spin_unlock(&oxu->mem_lock);
  448. return -ENOMEM;
  449. }
  450. static void oxu_buf_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
  451. {
  452. int index;
  453. spin_lock(&oxu->mem_lock);
  454. index = (qtd->buffer - (void *) &oxu->mem->db_pool[0])
  455. / BUFFER_SIZE;
  456. oxu->db_used[index] = 0;
  457. qtd->qtd_buffer_len = 0;
  458. qtd->buffer_dma = 0;
  459. qtd->buffer = NULL;
  460. spin_unlock(&oxu->mem_lock);
  461. }
  462. static inline void ehci_qtd_init(struct ehci_qtd *qtd, dma_addr_t dma)
  463. {
  464. memset(qtd, 0, sizeof *qtd);
  465. qtd->qtd_dma = dma;
  466. qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
  467. qtd->hw_next = EHCI_LIST_END;
  468. qtd->hw_alt_next = EHCI_LIST_END;
  469. INIT_LIST_HEAD(&qtd->qtd_list);
  470. }
  471. static inline void oxu_qtd_free(struct oxu_hcd *oxu, struct ehci_qtd *qtd)
  472. {
  473. int index;
  474. if (qtd->buffer)
  475. oxu_buf_free(oxu, qtd);
  476. spin_lock(&oxu->mem_lock);
  477. index = qtd - &oxu->mem->qtd_pool[0];
  478. oxu->qtd_used[index] = 0;
  479. spin_unlock(&oxu->mem_lock);
  480. }
  481. static struct ehci_qtd *ehci_qtd_alloc(struct oxu_hcd *oxu)
  482. {
  483. int i;
  484. struct ehci_qtd *qtd = NULL;
  485. spin_lock(&oxu->mem_lock);
  486. for (i = 0; i < QTD_NUM; i++)
  487. if (!oxu->qtd_used[i])
  488. break;
  489. if (i < QTD_NUM) {
  490. qtd = (struct ehci_qtd *) &oxu->mem->qtd_pool[i];
  491. memset(qtd, 0, sizeof *qtd);
  492. qtd->hw_token = cpu_to_le32(QTD_STS_HALT);
  493. qtd->hw_next = EHCI_LIST_END;
  494. qtd->hw_alt_next = EHCI_LIST_END;
  495. INIT_LIST_HEAD(&qtd->qtd_list);
  496. qtd->qtd_dma = virt_to_phys(qtd);
  497. oxu->qtd_used[i] = 1;
  498. }
  499. spin_unlock(&oxu->mem_lock);
  500. return qtd;
  501. }
  502. static void oxu_qh_free(struct oxu_hcd *oxu, struct ehci_qh *qh)
  503. {
  504. int index;
  505. spin_lock(&oxu->mem_lock);
  506. index = qh - &oxu->mem->qh_pool[0];
  507. oxu->qh_used[index] = 0;
  508. spin_unlock(&oxu->mem_lock);
  509. }
  510. static void qh_destroy(struct kref *kref)
  511. {
  512. struct ehci_qh *qh = container_of(kref, struct ehci_qh, kref);
  513. struct oxu_hcd *oxu = qh->oxu;
  514. /* clean qtds first, and know this is not linked */
  515. if (!list_empty(&qh->qtd_list) || qh->qh_next.ptr) {
  516. oxu_dbg(oxu, "unused qh not empty!\n");
  517. BUG();
  518. }
  519. if (qh->dummy)
  520. oxu_qtd_free(oxu, qh->dummy);
  521. oxu_qh_free(oxu, qh);
  522. }
  523. static struct ehci_qh *oxu_qh_alloc(struct oxu_hcd *oxu)
  524. {
  525. int i;
  526. struct ehci_qh *qh = NULL;
  527. spin_lock(&oxu->mem_lock);
  528. for (i = 0; i < QHEAD_NUM; i++)
  529. if (!oxu->qh_used[i])
  530. break;
  531. if (i < QHEAD_NUM) {
  532. qh = (struct ehci_qh *) &oxu->mem->qh_pool[i];
  533. memset(qh, 0, sizeof *qh);
  534. kref_init(&qh->kref);
  535. qh->oxu = oxu;
  536. qh->qh_dma = virt_to_phys(qh);
  537. INIT_LIST_HEAD(&qh->qtd_list);
  538. /* dummy td enables safe urb queuing */
  539. qh->dummy = ehci_qtd_alloc(oxu);
  540. if (qh->dummy == NULL) {
  541. oxu_dbg(oxu, "no dummy td\n");
  542. oxu->qh_used[i] = 0;
  543. qh = NULL;
  544. goto unlock;
  545. }
  546. oxu->qh_used[i] = 1;
  547. }
  548. unlock:
  549. spin_unlock(&oxu->mem_lock);
  550. return qh;
  551. }
  552. /* to share a qh (cpu threads, or hc) */
  553. static inline struct ehci_qh *qh_get(struct ehci_qh *qh)
  554. {
  555. kref_get(&qh->kref);
  556. return qh;
  557. }
  558. static inline void qh_put(struct ehci_qh *qh)
  559. {
  560. kref_put(&qh->kref, qh_destroy);
  561. }
  562. static void oxu_murb_free(struct oxu_hcd *oxu, struct oxu_murb *murb)
  563. {
  564. int index;
  565. spin_lock(&oxu->mem_lock);
  566. index = murb - &oxu->murb_pool[0];
  567. oxu->murb_used[index] = 0;
  568. spin_unlock(&oxu->mem_lock);
  569. }
  570. static struct oxu_murb *oxu_murb_alloc(struct oxu_hcd *oxu)
  571. {
  572. int i;
  573. struct oxu_murb *murb = NULL;
  574. spin_lock(&oxu->mem_lock);
  575. for (i = 0; i < MURB_NUM; i++)
  576. if (!oxu->murb_used[i])
  577. break;
  578. if (i < MURB_NUM) {
  579. murb = &(oxu->murb_pool)[i];
  580. oxu->murb_used[i] = 1;
  581. }
  582. spin_unlock(&oxu->mem_lock);
  583. return murb;
  584. }
  585. /* The queue heads and transfer descriptors are managed from pools tied
  586. * to each of the "per device" structures.
  587. * This is the initialisation and cleanup code.
  588. */
  589. static void ehci_mem_cleanup(struct oxu_hcd *oxu)
  590. {
  591. kfree(oxu->murb_pool);
  592. oxu->murb_pool = NULL;
  593. if (oxu->async)
  594. qh_put(oxu->async);
  595. oxu->async = NULL;
  596. del_timer(&oxu->urb_timer);
  597. oxu->periodic = NULL;
  598. /* shadow periodic table */
  599. kfree(oxu->pshadow);
  600. oxu->pshadow = NULL;
  601. }
  602. /* Remember to add cleanup code (above) if you add anything here.
  603. */
  604. static int ehci_mem_init(struct oxu_hcd *oxu, gfp_t flags)
  605. {
  606. int i;
  607. for (i = 0; i < oxu->periodic_size; i++)
  608. oxu->mem->frame_list[i] = EHCI_LIST_END;
  609. for (i = 0; i < QHEAD_NUM; i++)
  610. oxu->qh_used[i] = 0;
  611. for (i = 0; i < QTD_NUM; i++)
  612. oxu->qtd_used[i] = 0;
  613. oxu->murb_pool = kcalloc(MURB_NUM, sizeof(struct oxu_murb), flags);
  614. if (!oxu->murb_pool)
  615. goto fail;
  616. for (i = 0; i < MURB_NUM; i++)
  617. oxu->murb_used[i] = 0;
  618. oxu->async = oxu_qh_alloc(oxu);
  619. if (!oxu->async)
  620. goto fail;
  621. oxu->periodic = (__le32 *) &oxu->mem->frame_list;
  622. oxu->periodic_dma = virt_to_phys(oxu->periodic);
  623. for (i = 0; i < oxu->periodic_size; i++)
  624. oxu->periodic[i] = EHCI_LIST_END;
  625. /* software shadow of hardware table */
  626. oxu->pshadow = kcalloc(oxu->periodic_size, sizeof(void *), flags);
  627. if (oxu->pshadow != NULL)
  628. return 0;
  629. fail:
  630. oxu_dbg(oxu, "couldn't init memory\n");
  631. ehci_mem_cleanup(oxu);
  632. return -ENOMEM;
  633. }
  634. /* Fill a qtd, returning how much of the buffer we were able to queue up.
  635. */
  636. static int qtd_fill(struct ehci_qtd *qtd, dma_addr_t buf, size_t len,
  637. int token, int maxpacket)
  638. {
  639. int i, count;
  640. u64 addr = buf;
  641. /* one buffer entry per 4K ... first might be short or unaligned */
  642. qtd->hw_buf[0] = cpu_to_le32((u32)addr);
  643. qtd->hw_buf_hi[0] = cpu_to_le32((u32)(addr >> 32));
  644. count = 0x1000 - (buf & 0x0fff); /* rest of that page */
  645. if (likely(len < count)) /* ... iff needed */
  646. count = len;
  647. else {
  648. buf += 0x1000;
  649. buf &= ~0x0fff;
  650. /* per-qtd limit: from 16K to 20K (best alignment) */
  651. for (i = 1; count < len && i < 5; i++) {
  652. addr = buf;
  653. qtd->hw_buf[i] = cpu_to_le32((u32)addr);
  654. qtd->hw_buf_hi[i] = cpu_to_le32((u32)(addr >> 32));
  655. buf += 0x1000;
  656. if ((count + 0x1000) < len)
  657. count += 0x1000;
  658. else
  659. count = len;
  660. }
  661. /* short packets may only terminate transfers */
  662. if (count != len)
  663. count -= (count % maxpacket);
  664. }
  665. qtd->hw_token = cpu_to_le32((count << 16) | token);
  666. qtd->length = count;
  667. return count;
  668. }
  669. static inline void qh_update(struct oxu_hcd *oxu,
  670. struct ehci_qh *qh, struct ehci_qtd *qtd)
  671. {
  672. /* writes to an active overlay are unsafe */
  673. BUG_ON(qh->qh_state != QH_STATE_IDLE);
  674. qh->hw_qtd_next = QTD_NEXT(qtd->qtd_dma);
  675. qh->hw_alt_next = EHCI_LIST_END;
  676. /* Except for control endpoints, we make hardware maintain data
  677. * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
  678. * and set the pseudo-toggle in udev. Only usb_clear_halt() will
  679. * ever clear it.
  680. */
  681. if (!(qh->hw_info1 & cpu_to_le32(1 << 14))) {
  682. unsigned is_out, epnum;
  683. is_out = !(qtd->hw_token & cpu_to_le32(1 << 8));
  684. epnum = (le32_to_cpup(&qh->hw_info1) >> 8) & 0x0f;
  685. if (unlikely(!usb_gettoggle(qh->dev, epnum, is_out))) {
  686. qh->hw_token &= ~cpu_to_le32(QTD_TOGGLE);
  687. usb_settoggle(qh->dev, epnum, is_out, 1);
  688. }
  689. }
  690. /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
  691. wmb();
  692. qh->hw_token &= cpu_to_le32(QTD_TOGGLE | QTD_STS_PING);
  693. }
  694. /* If it weren't for a common silicon quirk (writing the dummy into the qh
  695. * overlay, so qh->hw_token wrongly becomes inactive/halted), only fault
  696. * recovery (including urb dequeue) would need software changes to a QH...
  697. */
  698. static void qh_refresh(struct oxu_hcd *oxu, struct ehci_qh *qh)
  699. {
  700. struct ehci_qtd *qtd;
  701. if (list_empty(&qh->qtd_list))
  702. qtd = qh->dummy;
  703. else {
  704. qtd = list_entry(qh->qtd_list.next,
  705. struct ehci_qtd, qtd_list);
  706. /* first qtd may already be partially processed */
  707. if (cpu_to_le32(qtd->qtd_dma) == qh->hw_current)
  708. qtd = NULL;
  709. }
  710. if (qtd)
  711. qh_update(oxu, qh, qtd);
  712. }
  713. static void qtd_copy_status(struct oxu_hcd *oxu, struct urb *urb,
  714. size_t length, u32 token)
  715. {
  716. /* count IN/OUT bytes, not SETUP (even short packets) */
  717. if (likely(QTD_PID(token) != 2))
  718. urb->actual_length += length - QTD_LENGTH(token);
  719. /* don't modify error codes */
  720. if (unlikely(urb->status != -EINPROGRESS))
  721. return;
  722. /* force cleanup after short read; not always an error */
  723. if (unlikely(IS_SHORT_READ(token)))
  724. urb->status = -EREMOTEIO;
  725. /* serious "can't proceed" faults reported by the hardware */
  726. if (token & QTD_STS_HALT) {
  727. if (token & QTD_STS_BABBLE) {
  728. /* FIXME "must" disable babbling device's port too */
  729. urb->status = -EOVERFLOW;
  730. } else if (token & QTD_STS_MMF) {
  731. /* fs/ls interrupt xfer missed the complete-split */
  732. urb->status = -EPROTO;
  733. } else if (token & QTD_STS_DBE) {
  734. urb->status = (QTD_PID(token) == 1) /* IN ? */
  735. ? -ENOSR /* hc couldn't read data */
  736. : -ECOMM; /* hc couldn't write data */
  737. } else if (token & QTD_STS_XACT) {
  738. /* timeout, bad crc, wrong PID, etc; retried */
  739. if (QTD_CERR(token))
  740. urb->status = -EPIPE;
  741. else {
  742. oxu_dbg(oxu, "devpath %s ep%d%s 3strikes\n",
  743. urb->dev->devpath,
  744. usb_pipeendpoint(urb->pipe),
  745. usb_pipein(urb->pipe) ? "in" : "out");
  746. urb->status = -EPROTO;
  747. }
  748. /* CERR nonzero + no errors + halt --> stall */
  749. } else if (QTD_CERR(token))
  750. urb->status = -EPIPE;
  751. else /* unknown */
  752. urb->status = -EPROTO;
  753. oxu_vdbg(oxu, "dev%d ep%d%s qtd token %08x --> status %d\n",
  754. usb_pipedevice(urb->pipe),
  755. usb_pipeendpoint(urb->pipe),
  756. usb_pipein(urb->pipe) ? "in" : "out",
  757. token, urb->status);
  758. }
  759. }
  760. static void ehci_urb_done(struct oxu_hcd *oxu, struct urb *urb)
  761. __releases(oxu->lock)
  762. __acquires(oxu->lock)
  763. {
  764. if (likely(urb->hcpriv != NULL)) {
  765. struct ehci_qh *qh = (struct ehci_qh *) urb->hcpriv;
  766. /* S-mask in a QH means it's an interrupt urb */
  767. if ((qh->hw_info2 & cpu_to_le32(QH_SMASK)) != 0) {
  768. /* ... update hc-wide periodic stats (for usbfs) */
  769. oxu_to_hcd(oxu)->self.bandwidth_int_reqs--;
  770. }
  771. qh_put(qh);
  772. }
  773. urb->hcpriv = NULL;
  774. switch (urb->status) {
  775. case -EINPROGRESS: /* success */
  776. urb->status = 0;
  777. default: /* fault */
  778. break;
  779. case -EREMOTEIO: /* fault or normal */
  780. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  781. urb->status = 0;
  782. break;
  783. case -ECONNRESET: /* canceled */
  784. case -ENOENT:
  785. break;
  786. }
  787. #ifdef OXU_URB_TRACE
  788. oxu_dbg(oxu, "%s %s urb %p ep%d%s status %d len %d/%d\n",
  789. __func__, urb->dev->devpath, urb,
  790. usb_pipeendpoint(urb->pipe),
  791. usb_pipein(urb->pipe) ? "in" : "out",
  792. urb->status,
  793. urb->actual_length, urb->transfer_buffer_length);
  794. #endif
  795. /* complete() can reenter this HCD */
  796. spin_unlock(&oxu->lock);
  797. usb_hcd_giveback_urb(oxu_to_hcd(oxu), urb, urb->status);
  798. spin_lock(&oxu->lock);
  799. }
  800. static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
  801. static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh);
  802. static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
  803. static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh);
  804. #define HALT_BIT cpu_to_le32(QTD_STS_HALT)
  805. /* Process and free completed qtds for a qh, returning URBs to drivers.
  806. * Chases up to qh->hw_current. Returns number of completions called,
  807. * indicating how much "real" work we did.
  808. */
  809. static unsigned qh_completions(struct oxu_hcd *oxu, struct ehci_qh *qh)
  810. {
  811. struct ehci_qtd *last = NULL, *end = qh->dummy;
  812. struct list_head *entry, *tmp;
  813. int stopped;
  814. unsigned count = 0;
  815. int do_status = 0;
  816. u8 state;
  817. struct oxu_murb *murb = NULL;
  818. if (unlikely(list_empty(&qh->qtd_list)))
  819. return count;
  820. /* completions (or tasks on other cpus) must never clobber HALT
  821. * till we've gone through and cleaned everything up, even when
  822. * they add urbs to this qh's queue or mark them for unlinking.
  823. *
  824. * NOTE: unlinking expects to be done in queue order.
  825. */
  826. state = qh->qh_state;
  827. qh->qh_state = QH_STATE_COMPLETING;
  828. stopped = (state == QH_STATE_IDLE);
  829. /* remove de-activated QTDs from front of queue.
  830. * after faults (including short reads), cleanup this urb
  831. * then let the queue advance.
  832. * if queue is stopped, handles unlinks.
  833. */
  834. list_for_each_safe(entry, tmp, &qh->qtd_list) {
  835. struct ehci_qtd *qtd;
  836. struct urb *urb;
  837. u32 token = 0;
  838. qtd = list_entry(entry, struct ehci_qtd, qtd_list);
  839. urb = qtd->urb;
  840. /* Clean up any state from previous QTD ...*/
  841. if (last) {
  842. if (likely(last->urb != urb)) {
  843. if (last->urb->complete == NULL) {
  844. murb = (struct oxu_murb *) last->urb;
  845. last->urb = murb->main;
  846. if (murb->last) {
  847. ehci_urb_done(oxu, last->urb);
  848. count++;
  849. }
  850. oxu_murb_free(oxu, murb);
  851. } else {
  852. ehci_urb_done(oxu, last->urb);
  853. count++;
  854. }
  855. }
  856. oxu_qtd_free(oxu, last);
  857. last = NULL;
  858. }
  859. /* ignore urbs submitted during completions we reported */
  860. if (qtd == end)
  861. break;
  862. /* hardware copies qtd out of qh overlay */
  863. rmb();
  864. token = le32_to_cpu(qtd->hw_token);
  865. /* always clean up qtds the hc de-activated */
  866. if ((token & QTD_STS_ACTIVE) == 0) {
  867. if ((token & QTD_STS_HALT) != 0) {
  868. stopped = 1;
  869. /* magic dummy for some short reads; qh won't advance.
  870. * that silicon quirk can kick in with this dummy too.
  871. */
  872. } else if (IS_SHORT_READ(token) &&
  873. !(qtd->hw_alt_next & EHCI_LIST_END)) {
  874. stopped = 1;
  875. goto halt;
  876. }
  877. /* stop scanning when we reach qtds the hc is using */
  878. } else if (likely(!stopped &&
  879. HC_IS_RUNNING(oxu_to_hcd(oxu)->state))) {
  880. break;
  881. } else {
  882. stopped = 1;
  883. if (unlikely(!HC_IS_RUNNING(oxu_to_hcd(oxu)->state)))
  884. urb->status = -ESHUTDOWN;
  885. /* ignore active urbs unless some previous qtd
  886. * for the urb faulted (including short read) or
  887. * its urb was canceled. we may patch qh or qtds.
  888. */
  889. if (likely(urb->status == -EINPROGRESS))
  890. continue;
  891. /* issue status after short control reads */
  892. if (unlikely(do_status != 0)
  893. && QTD_PID(token) == 0 /* OUT */) {
  894. do_status = 0;
  895. continue;
  896. }
  897. /* token in overlay may be most current */
  898. if (state == QH_STATE_IDLE
  899. && cpu_to_le32(qtd->qtd_dma)
  900. == qh->hw_current)
  901. token = le32_to_cpu(qh->hw_token);
  902. /* force halt for unlinked or blocked qh, so we'll
  903. * patch the qh later and so that completions can't
  904. * activate it while we "know" it's stopped.
  905. */
  906. if ((HALT_BIT & qh->hw_token) == 0) {
  907. halt:
  908. qh->hw_token |= HALT_BIT;
  909. wmb();
  910. }
  911. }
  912. /* Remove it from the queue */
  913. qtd_copy_status(oxu, urb->complete ?
  914. urb : ((struct oxu_murb *) urb)->main,
  915. qtd->length, token);
  916. if ((usb_pipein(qtd->urb->pipe)) &&
  917. (NULL != qtd->transfer_buffer))
  918. memcpy(qtd->transfer_buffer, qtd->buffer, qtd->length);
  919. do_status = (urb->status == -EREMOTEIO)
  920. && usb_pipecontrol(urb->pipe);
  921. if (stopped && qtd->qtd_list.prev != &qh->qtd_list) {
  922. last = list_entry(qtd->qtd_list.prev,
  923. struct ehci_qtd, qtd_list);
  924. last->hw_next = qtd->hw_next;
  925. }
  926. list_del(&qtd->qtd_list);
  927. last = qtd;
  928. }
  929. /* last urb's completion might still need calling */
  930. if (likely(last != NULL)) {
  931. if (last->urb->complete == NULL) {
  932. murb = (struct oxu_murb *) last->urb;
  933. last->urb = murb->main;
  934. if (murb->last) {
  935. ehci_urb_done(oxu, last->urb);
  936. count++;
  937. }
  938. oxu_murb_free(oxu, murb);
  939. } else {
  940. ehci_urb_done(oxu, last->urb);
  941. count++;
  942. }
  943. oxu_qtd_free(oxu, last);
  944. }
  945. /* restore original state; caller must unlink or relink */
  946. qh->qh_state = state;
  947. /* be sure the hardware's done with the qh before refreshing
  948. * it after fault cleanup, or recovering from silicon wrongly
  949. * overlaying the dummy qtd (which reduces DMA chatter).
  950. */
  951. if (stopped != 0 || qh->hw_qtd_next == EHCI_LIST_END) {
  952. switch (state) {
  953. case QH_STATE_IDLE:
  954. qh_refresh(oxu, qh);
  955. break;
  956. case QH_STATE_LINKED:
  957. /* should be rare for periodic transfers,
  958. * except maybe high bandwidth ...
  959. */
  960. if ((cpu_to_le32(QH_SMASK)
  961. & qh->hw_info2) != 0) {
  962. intr_deschedule(oxu, qh);
  963. (void) qh_schedule(oxu, qh);
  964. } else
  965. unlink_async(oxu, qh);
  966. break;
  967. /* otherwise, unlink already started */
  968. }
  969. }
  970. return count;
  971. }
  972. /* High bandwidth multiplier, as encoded in highspeed endpoint descriptors */
  973. #define hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
  974. /* ... and packet size, for any kind of endpoint descriptor */
  975. #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
  976. /* Reverse of qh_urb_transaction: free a list of TDs.
  977. * used for cleanup after errors, before HC sees an URB's TDs.
  978. */
  979. static void qtd_list_free(struct oxu_hcd *oxu,
  980. struct urb *urb, struct list_head *qtd_list)
  981. {
  982. struct list_head *entry, *temp;
  983. list_for_each_safe(entry, temp, qtd_list) {
  984. struct ehci_qtd *qtd;
  985. qtd = list_entry(entry, struct ehci_qtd, qtd_list);
  986. list_del(&qtd->qtd_list);
  987. oxu_qtd_free(oxu, qtd);
  988. }
  989. }
  990. /* Create a list of filled qtds for this URB; won't link into qh.
  991. */
  992. static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu,
  993. struct urb *urb,
  994. struct list_head *head,
  995. gfp_t flags)
  996. {
  997. struct ehci_qtd *qtd, *qtd_prev;
  998. dma_addr_t buf;
  999. int len, maxpacket;
  1000. int is_input;
  1001. u32 token;
  1002. void *transfer_buf = NULL;
  1003. int ret;
  1004. /*
  1005. * URBs map to sequences of QTDs: one logical transaction
  1006. */
  1007. qtd = ehci_qtd_alloc(oxu);
  1008. if (unlikely(!qtd))
  1009. return NULL;
  1010. list_add_tail(&qtd->qtd_list, head);
  1011. qtd->urb = urb;
  1012. token = QTD_STS_ACTIVE;
  1013. token |= (EHCI_TUNE_CERR << 10);
  1014. /* for split transactions, SplitXState initialized to zero */
  1015. len = urb->transfer_buffer_length;
  1016. is_input = usb_pipein(urb->pipe);
  1017. if (!urb->transfer_buffer && urb->transfer_buffer_length && is_input)
  1018. urb->transfer_buffer = phys_to_virt(urb->transfer_dma);
  1019. if (usb_pipecontrol(urb->pipe)) {
  1020. /* SETUP pid */
  1021. ret = oxu_buf_alloc(oxu, qtd, sizeof(struct usb_ctrlrequest));
  1022. if (ret)
  1023. goto cleanup;
  1024. qtd_fill(qtd, qtd->buffer_dma, sizeof(struct usb_ctrlrequest),
  1025. token | (2 /* "setup" */ << 8), 8);
  1026. memcpy(qtd->buffer, qtd->urb->setup_packet,
  1027. sizeof(struct usb_ctrlrequest));
  1028. /* ... and always at least one more pid */
  1029. token ^= QTD_TOGGLE;
  1030. qtd_prev = qtd;
  1031. qtd = ehci_qtd_alloc(oxu);
  1032. if (unlikely(!qtd))
  1033. goto cleanup;
  1034. qtd->urb = urb;
  1035. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1036. list_add_tail(&qtd->qtd_list, head);
  1037. /* for zero length DATA stages, STATUS is always IN */
  1038. if (len == 0)
  1039. token |= (1 /* "in" */ << 8);
  1040. }
  1041. /*
  1042. * Data transfer stage: buffer setup
  1043. */
  1044. ret = oxu_buf_alloc(oxu, qtd, len);
  1045. if (ret)
  1046. goto cleanup;
  1047. buf = qtd->buffer_dma;
  1048. transfer_buf = urb->transfer_buffer;
  1049. if (!is_input)
  1050. memcpy(qtd->buffer, qtd->urb->transfer_buffer, len);
  1051. if (is_input)
  1052. token |= (1 /* "in" */ << 8);
  1053. /* else it's already initted to "out" pid (0 << 8) */
  1054. maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
  1055. /*
  1056. * buffer gets wrapped in one or more qtds;
  1057. * last one may be "short" (including zero len)
  1058. * and may serve as a control status ack
  1059. */
  1060. for (;;) {
  1061. int this_qtd_len;
  1062. this_qtd_len = qtd_fill(qtd, buf, len, token, maxpacket);
  1063. qtd->transfer_buffer = transfer_buf;
  1064. len -= this_qtd_len;
  1065. buf += this_qtd_len;
  1066. transfer_buf += this_qtd_len;
  1067. if (is_input)
  1068. qtd->hw_alt_next = oxu->async->hw_alt_next;
  1069. /* qh makes control packets use qtd toggle; maybe switch it */
  1070. if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
  1071. token ^= QTD_TOGGLE;
  1072. if (likely(len <= 0))
  1073. break;
  1074. qtd_prev = qtd;
  1075. qtd = ehci_qtd_alloc(oxu);
  1076. if (unlikely(!qtd))
  1077. goto cleanup;
  1078. if (likely(len > 0)) {
  1079. ret = oxu_buf_alloc(oxu, qtd, len);
  1080. if (ret)
  1081. goto cleanup;
  1082. }
  1083. qtd->urb = urb;
  1084. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1085. list_add_tail(&qtd->qtd_list, head);
  1086. }
  1087. /* unless the bulk/interrupt caller wants a chance to clean
  1088. * up after short reads, hc should advance qh past this urb
  1089. */
  1090. if (likely((urb->transfer_flags & URB_SHORT_NOT_OK) == 0
  1091. || usb_pipecontrol(urb->pipe)))
  1092. qtd->hw_alt_next = EHCI_LIST_END;
  1093. /*
  1094. * control requests may need a terminating data "status" ack;
  1095. * bulk ones may need a terminating short packet (zero length).
  1096. */
  1097. if (likely(urb->transfer_buffer_length != 0)) {
  1098. int one_more = 0;
  1099. if (usb_pipecontrol(urb->pipe)) {
  1100. one_more = 1;
  1101. token ^= 0x0100; /* "in" <--> "out" */
  1102. token |= QTD_TOGGLE; /* force DATA1 */
  1103. } else if (usb_pipebulk(urb->pipe)
  1104. && (urb->transfer_flags & URB_ZERO_PACKET)
  1105. && !(urb->transfer_buffer_length % maxpacket)) {
  1106. one_more = 1;
  1107. }
  1108. if (one_more) {
  1109. qtd_prev = qtd;
  1110. qtd = ehci_qtd_alloc(oxu);
  1111. if (unlikely(!qtd))
  1112. goto cleanup;
  1113. qtd->urb = urb;
  1114. qtd_prev->hw_next = QTD_NEXT(qtd->qtd_dma);
  1115. list_add_tail(&qtd->qtd_list, head);
  1116. /* never any data in such packets */
  1117. qtd_fill(qtd, 0, 0, token, 0);
  1118. }
  1119. }
  1120. /* by default, enable interrupt on urb completion */
  1121. qtd->hw_token |= cpu_to_le32(QTD_IOC);
  1122. return head;
  1123. cleanup:
  1124. qtd_list_free(oxu, urb, head);
  1125. return NULL;
  1126. }
  1127. /* Each QH holds a qtd list; a QH is used for everything except iso.
  1128. *
  1129. * For interrupt urbs, the scheduler must set the microframe scheduling
  1130. * mask(s) each time the QH gets scheduled. For highspeed, that's
  1131. * just one microframe in the s-mask. For split interrupt transactions
  1132. * there are additional complications: c-mask, maybe FSTNs.
  1133. */
  1134. static struct ehci_qh *qh_make(struct oxu_hcd *oxu,
  1135. struct urb *urb, gfp_t flags)
  1136. {
  1137. struct ehci_qh *qh = oxu_qh_alloc(oxu);
  1138. u32 info1 = 0, info2 = 0;
  1139. int is_input, type;
  1140. int maxp = 0;
  1141. if (!qh)
  1142. return qh;
  1143. /*
  1144. * init endpoint/device data for this QH
  1145. */
  1146. info1 |= usb_pipeendpoint(urb->pipe) << 8;
  1147. info1 |= usb_pipedevice(urb->pipe) << 0;
  1148. is_input = usb_pipein(urb->pipe);
  1149. type = usb_pipetype(urb->pipe);
  1150. maxp = usb_maxpacket(urb->dev, urb->pipe, !is_input);
  1151. /* Compute interrupt scheduling parameters just once, and save.
  1152. * - allowing for high bandwidth, how many nsec/uframe are used?
  1153. * - split transactions need a second CSPLIT uframe; same question
  1154. * - splits also need a schedule gap (for full/low speed I/O)
  1155. * - qh has a polling interval
  1156. *
  1157. * For control/bulk requests, the HC or TT handles these.
  1158. */
  1159. if (type == PIPE_INTERRUPT) {
  1160. qh->usecs = NS_TO_US(usb_calc_bus_time(USB_SPEED_HIGH,
  1161. is_input, 0,
  1162. hb_mult(maxp) * max_packet(maxp)));
  1163. qh->start = NO_FRAME;
  1164. if (urb->dev->speed == USB_SPEED_HIGH) {
  1165. qh->c_usecs = 0;
  1166. qh->gap_uf = 0;
  1167. qh->period = urb->interval >> 3;
  1168. if (qh->period == 0 && urb->interval != 1) {
  1169. /* NOTE interval 2 or 4 uframes could work.
  1170. * But interval 1 scheduling is simpler, and
  1171. * includes high bandwidth.
  1172. */
  1173. oxu_dbg(oxu, "intr period %d uframes, NYET!\n",
  1174. urb->interval);
  1175. goto done;
  1176. }
  1177. } else {
  1178. struct usb_tt *tt = urb->dev->tt;
  1179. int think_time;
  1180. /* gap is f(FS/LS transfer times) */
  1181. qh->gap_uf = 1 + usb_calc_bus_time(urb->dev->speed,
  1182. is_input, 0, maxp) / (125 * 1000);
  1183. /* FIXME this just approximates SPLIT/CSPLIT times */
  1184. if (is_input) { /* SPLIT, gap, CSPLIT+DATA */
  1185. qh->c_usecs = qh->usecs + HS_USECS(0);
  1186. qh->usecs = HS_USECS(1);
  1187. } else { /* SPLIT+DATA, gap, CSPLIT */
  1188. qh->usecs += HS_USECS(1);
  1189. qh->c_usecs = HS_USECS(0);
  1190. }
  1191. think_time = tt ? tt->think_time : 0;
  1192. qh->tt_usecs = NS_TO_US(think_time +
  1193. usb_calc_bus_time(urb->dev->speed,
  1194. is_input, 0, max_packet(maxp)));
  1195. qh->period = urb->interval;
  1196. }
  1197. }
  1198. /* support for tt scheduling, and access to toggles */
  1199. qh->dev = urb->dev;
  1200. /* using TT? */
  1201. switch (urb->dev->speed) {
  1202. case USB_SPEED_LOW:
  1203. info1 |= (1 << 12); /* EPS "low" */
  1204. /* FALL THROUGH */
  1205. case USB_SPEED_FULL:
  1206. /* EPS 0 means "full" */
  1207. if (type != PIPE_INTERRUPT)
  1208. info1 |= (EHCI_TUNE_RL_TT << 28);
  1209. if (type == PIPE_CONTROL) {
  1210. info1 |= (1 << 27); /* for TT */
  1211. info1 |= 1 << 14; /* toggle from qtd */
  1212. }
  1213. info1 |= maxp << 16;
  1214. info2 |= (EHCI_TUNE_MULT_TT << 30);
  1215. info2 |= urb->dev->ttport << 23;
  1216. /* NOTE: if (PIPE_INTERRUPT) { scheduler sets c-mask } */
  1217. break;
  1218. case USB_SPEED_HIGH: /* no TT involved */
  1219. info1 |= (2 << 12); /* EPS "high" */
  1220. if (type == PIPE_CONTROL) {
  1221. info1 |= (EHCI_TUNE_RL_HS << 28);
  1222. info1 |= 64 << 16; /* usb2 fixed maxpacket */
  1223. info1 |= 1 << 14; /* toggle from qtd */
  1224. info2 |= (EHCI_TUNE_MULT_HS << 30);
  1225. } else if (type == PIPE_BULK) {
  1226. info1 |= (EHCI_TUNE_RL_HS << 28);
  1227. info1 |= 512 << 16; /* usb2 fixed maxpacket */
  1228. info2 |= (EHCI_TUNE_MULT_HS << 30);
  1229. } else { /* PIPE_INTERRUPT */
  1230. info1 |= max_packet(maxp) << 16;
  1231. info2 |= hb_mult(maxp) << 30;
  1232. }
  1233. break;
  1234. default:
  1235. oxu_dbg(oxu, "bogus dev %p speed %d\n", urb->dev, urb->dev->speed);
  1236. done:
  1237. qh_put(qh);
  1238. return NULL;
  1239. }
  1240. /* NOTE: if (PIPE_INTERRUPT) { scheduler sets s-mask } */
  1241. /* init as live, toggle clear, advance to dummy */
  1242. qh->qh_state = QH_STATE_IDLE;
  1243. qh->hw_info1 = cpu_to_le32(info1);
  1244. qh->hw_info2 = cpu_to_le32(info2);
  1245. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input, 1);
  1246. qh_refresh(oxu, qh);
  1247. return qh;
  1248. }
  1249. /* Move qh (and its qtds) onto async queue; maybe enable queue.
  1250. */
  1251. static void qh_link_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1252. {
  1253. __le32 dma = QH_NEXT(qh->qh_dma);
  1254. struct ehci_qh *head;
  1255. /* (re)start the async schedule? */
  1256. head = oxu->async;
  1257. timer_action_done(oxu, TIMER_ASYNC_OFF);
  1258. if (!head->qh_next.qh) {
  1259. u32 cmd = readl(&oxu->regs->command);
  1260. if (!(cmd & CMD_ASE)) {
  1261. /* in case a clear of CMD_ASE didn't take yet */
  1262. (void)handshake(oxu, &oxu->regs->status,
  1263. STS_ASS, 0, 150);
  1264. cmd |= CMD_ASE | CMD_RUN;
  1265. writel(cmd, &oxu->regs->command);
  1266. oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
  1267. /* posted write need not be known to HC yet ... */
  1268. }
  1269. }
  1270. /* clear halt and/or toggle; and maybe recover from silicon quirk */
  1271. if (qh->qh_state == QH_STATE_IDLE)
  1272. qh_refresh(oxu, qh);
  1273. /* splice right after start */
  1274. qh->qh_next = head->qh_next;
  1275. qh->hw_next = head->hw_next;
  1276. wmb();
  1277. head->qh_next.qh = qh;
  1278. head->hw_next = dma;
  1279. qh->qh_state = QH_STATE_LINKED;
  1280. /* qtd completions reported later by interrupt */
  1281. }
  1282. #define QH_ADDR_MASK cpu_to_le32(0x7f)
  1283. /*
  1284. * For control/bulk/interrupt, return QH with these TDs appended.
  1285. * Allocates and initializes the QH if necessary.
  1286. * Returns null if it can't allocate a QH it needs to.
  1287. * If the QH has TDs (urbs) already, that's great.
  1288. */
  1289. static struct ehci_qh *qh_append_tds(struct oxu_hcd *oxu,
  1290. struct urb *urb, struct list_head *qtd_list,
  1291. int epnum, void **ptr)
  1292. {
  1293. struct ehci_qh *qh = NULL;
  1294. qh = (struct ehci_qh *) *ptr;
  1295. if (unlikely(qh == NULL)) {
  1296. /* can't sleep here, we have oxu->lock... */
  1297. qh = qh_make(oxu, urb, GFP_ATOMIC);
  1298. *ptr = qh;
  1299. }
  1300. if (likely(qh != NULL)) {
  1301. struct ehci_qtd *qtd;
  1302. if (unlikely(list_empty(qtd_list)))
  1303. qtd = NULL;
  1304. else
  1305. qtd = list_entry(qtd_list->next, struct ehci_qtd,
  1306. qtd_list);
  1307. /* control qh may need patching ... */
  1308. if (unlikely(epnum == 0)) {
  1309. /* usb_reset_device() briefly reverts to address 0 */
  1310. if (usb_pipedevice(urb->pipe) == 0)
  1311. qh->hw_info1 &= ~QH_ADDR_MASK;
  1312. }
  1313. /* just one way to queue requests: swap with the dummy qtd.
  1314. * only hc or qh_refresh() ever modify the overlay.
  1315. */
  1316. if (likely(qtd != NULL)) {
  1317. struct ehci_qtd *dummy;
  1318. dma_addr_t dma;
  1319. __le32 token;
  1320. /* to avoid racing the HC, use the dummy td instead of
  1321. * the first td of our list (becomes new dummy). both
  1322. * tds stay deactivated until we're done, when the
  1323. * HC is allowed to fetch the old dummy (4.10.2).
  1324. */
  1325. token = qtd->hw_token;
  1326. qtd->hw_token = HALT_BIT;
  1327. wmb();
  1328. dummy = qh->dummy;
  1329. dma = dummy->qtd_dma;
  1330. *dummy = *qtd;
  1331. dummy->qtd_dma = dma;
  1332. list_del(&qtd->qtd_list);
  1333. list_add(&dummy->qtd_list, qtd_list);
  1334. list_splice(qtd_list, qh->qtd_list.prev);
  1335. ehci_qtd_init(qtd, qtd->qtd_dma);
  1336. qh->dummy = qtd;
  1337. /* hc must see the new dummy at list end */
  1338. dma = qtd->qtd_dma;
  1339. qtd = list_entry(qh->qtd_list.prev,
  1340. struct ehci_qtd, qtd_list);
  1341. qtd->hw_next = QTD_NEXT(dma);
  1342. /* let the hc process these next qtds */
  1343. dummy->hw_token = (token & ~(0x80));
  1344. wmb();
  1345. dummy->hw_token = token;
  1346. urb->hcpriv = qh_get(qh);
  1347. }
  1348. }
  1349. return qh;
  1350. }
  1351. static int submit_async(struct oxu_hcd *oxu, struct urb *urb,
  1352. struct list_head *qtd_list, gfp_t mem_flags)
  1353. {
  1354. struct ehci_qtd *qtd;
  1355. int epnum;
  1356. unsigned long flags;
  1357. struct ehci_qh *qh = NULL;
  1358. int rc = 0;
  1359. qtd = list_entry(qtd_list->next, struct ehci_qtd, qtd_list);
  1360. epnum = urb->ep->desc.bEndpointAddress;
  1361. #ifdef OXU_URB_TRACE
  1362. oxu_dbg(oxu, "%s %s urb %p ep%d%s len %d, qtd %p [qh %p]\n",
  1363. __func__, urb->dev->devpath, urb,
  1364. epnum & 0x0f, (epnum & USB_DIR_IN) ? "in" : "out",
  1365. urb->transfer_buffer_length,
  1366. qtd, urb->ep->hcpriv);
  1367. #endif
  1368. spin_lock_irqsave(&oxu->lock, flags);
  1369. if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) {
  1370. rc = -ESHUTDOWN;
  1371. goto done;
  1372. }
  1373. qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1374. if (unlikely(qh == NULL)) {
  1375. rc = -ENOMEM;
  1376. goto done;
  1377. }
  1378. /* Control/bulk operations through TTs don't need scheduling,
  1379. * the HC and TT handle it when the TT has a buffer ready.
  1380. */
  1381. if (likely(qh->qh_state == QH_STATE_IDLE))
  1382. qh_link_async(oxu, qh_get(qh));
  1383. done:
  1384. spin_unlock_irqrestore(&oxu->lock, flags);
  1385. if (unlikely(qh == NULL))
  1386. qtd_list_free(oxu, urb, qtd_list);
  1387. return rc;
  1388. }
  1389. /* The async qh for the qtds being reclaimed are now unlinked from the HC */
  1390. static void end_unlink_async(struct oxu_hcd *oxu)
  1391. {
  1392. struct ehci_qh *qh = oxu->reclaim;
  1393. struct ehci_qh *next;
  1394. timer_action_done(oxu, TIMER_IAA_WATCHDOG);
  1395. qh->qh_state = QH_STATE_IDLE;
  1396. qh->qh_next.qh = NULL;
  1397. qh_put(qh); /* refcount from reclaim */
  1398. /* other unlink(s) may be pending (in QH_STATE_UNLINK_WAIT) */
  1399. next = qh->reclaim;
  1400. oxu->reclaim = next;
  1401. oxu->reclaim_ready = 0;
  1402. qh->reclaim = NULL;
  1403. qh_completions(oxu, qh);
  1404. if (!list_empty(&qh->qtd_list)
  1405. && HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1406. qh_link_async(oxu, qh);
  1407. else {
  1408. qh_put(qh); /* refcount from async list */
  1409. /* it's not free to turn the async schedule on/off; leave it
  1410. * active but idle for a while once it empties.
  1411. */
  1412. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state)
  1413. && oxu->async->qh_next.qh == NULL)
  1414. timer_action(oxu, TIMER_ASYNC_OFF);
  1415. }
  1416. if (next) {
  1417. oxu->reclaim = NULL;
  1418. start_unlink_async(oxu, next);
  1419. }
  1420. }
  1421. /* makes sure the async qh will become idle */
  1422. /* caller must own oxu->lock */
  1423. static void start_unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1424. {
  1425. int cmd = readl(&oxu->regs->command);
  1426. struct ehci_qh *prev;
  1427. #ifdef DEBUG
  1428. assert_spin_locked(&oxu->lock);
  1429. if (oxu->reclaim || (qh->qh_state != QH_STATE_LINKED
  1430. && qh->qh_state != QH_STATE_UNLINK_WAIT))
  1431. BUG();
  1432. #endif
  1433. /* stop async schedule right now? */
  1434. if (unlikely(qh == oxu->async)) {
  1435. /* can't get here without STS_ASS set */
  1436. if (oxu_to_hcd(oxu)->state != HC_STATE_HALT
  1437. && !oxu->reclaim) {
  1438. /* ... and CMD_IAAD clear */
  1439. writel(cmd & ~CMD_ASE, &oxu->regs->command);
  1440. wmb();
  1441. /* handshake later, if we need to */
  1442. timer_action_done(oxu, TIMER_ASYNC_OFF);
  1443. }
  1444. return;
  1445. }
  1446. qh->qh_state = QH_STATE_UNLINK;
  1447. oxu->reclaim = qh = qh_get(qh);
  1448. prev = oxu->async;
  1449. while (prev->qh_next.qh != qh)
  1450. prev = prev->qh_next.qh;
  1451. prev->hw_next = qh->hw_next;
  1452. prev->qh_next = qh->qh_next;
  1453. wmb();
  1454. if (unlikely(oxu_to_hcd(oxu)->state == HC_STATE_HALT)) {
  1455. /* if (unlikely(qh->reclaim != 0))
  1456. * this will recurse, probably not much
  1457. */
  1458. end_unlink_async(oxu);
  1459. return;
  1460. }
  1461. oxu->reclaim_ready = 0;
  1462. cmd |= CMD_IAAD;
  1463. writel(cmd, &oxu->regs->command);
  1464. (void) readl(&oxu->regs->command);
  1465. timer_action(oxu, TIMER_IAA_WATCHDOG);
  1466. }
  1467. static void scan_async(struct oxu_hcd *oxu)
  1468. {
  1469. struct ehci_qh *qh;
  1470. enum ehci_timer_action action = TIMER_IO_WATCHDOG;
  1471. if (!++(oxu->stamp))
  1472. oxu->stamp++;
  1473. timer_action_done(oxu, TIMER_ASYNC_SHRINK);
  1474. rescan:
  1475. qh = oxu->async->qh_next.qh;
  1476. if (likely(qh != NULL)) {
  1477. do {
  1478. /* clean any finished work for this qh */
  1479. if (!list_empty(&qh->qtd_list)
  1480. && qh->stamp != oxu->stamp) {
  1481. int temp;
  1482. /* unlinks could happen here; completion
  1483. * reporting drops the lock. rescan using
  1484. * the latest schedule, but don't rescan
  1485. * qhs we already finished (no looping).
  1486. */
  1487. qh = qh_get(qh);
  1488. qh->stamp = oxu->stamp;
  1489. temp = qh_completions(oxu, qh);
  1490. qh_put(qh);
  1491. if (temp != 0)
  1492. goto rescan;
  1493. }
  1494. /* unlink idle entries, reducing HC PCI usage as well
  1495. * as HCD schedule-scanning costs. delay for any qh
  1496. * we just scanned, there's a not-unusual case that it
  1497. * doesn't stay idle for long.
  1498. * (plus, avoids some kind of re-activation race.)
  1499. */
  1500. if (list_empty(&qh->qtd_list)) {
  1501. if (qh->stamp == oxu->stamp)
  1502. action = TIMER_ASYNC_SHRINK;
  1503. else if (!oxu->reclaim
  1504. && qh->qh_state == QH_STATE_LINKED)
  1505. start_unlink_async(oxu, qh);
  1506. }
  1507. qh = qh->qh_next.qh;
  1508. } while (qh);
  1509. }
  1510. if (action == TIMER_ASYNC_SHRINK)
  1511. timer_action(oxu, TIMER_ASYNC_SHRINK);
  1512. }
  1513. /*
  1514. * periodic_next_shadow - return "next" pointer on shadow list
  1515. * @periodic: host pointer to qh/itd/sitd
  1516. * @tag: hardware tag for type of this record
  1517. */
  1518. static union ehci_shadow *periodic_next_shadow(union ehci_shadow *periodic,
  1519. __le32 tag)
  1520. {
  1521. switch (tag) {
  1522. default:
  1523. case Q_TYPE_QH:
  1524. return &periodic->qh->qh_next;
  1525. }
  1526. }
  1527. /* caller must hold oxu->lock */
  1528. static void periodic_unlink(struct oxu_hcd *oxu, unsigned frame, void *ptr)
  1529. {
  1530. union ehci_shadow *prev_p = &oxu->pshadow[frame];
  1531. __le32 *hw_p = &oxu->periodic[frame];
  1532. union ehci_shadow here = *prev_p;
  1533. /* find predecessor of "ptr"; hw and shadow lists are in sync */
  1534. while (here.ptr && here.ptr != ptr) {
  1535. prev_p = periodic_next_shadow(prev_p, Q_NEXT_TYPE(*hw_p));
  1536. hw_p = here.hw_next;
  1537. here = *prev_p;
  1538. }
  1539. /* an interrupt entry (at list end) could have been shared */
  1540. if (!here.ptr)
  1541. return;
  1542. /* update shadow and hardware lists ... the old "next" pointers
  1543. * from ptr may still be in use, the caller updates them.
  1544. */
  1545. *prev_p = *periodic_next_shadow(&here, Q_NEXT_TYPE(*hw_p));
  1546. *hw_p = *here.hw_next;
  1547. }
  1548. /* how many of the uframe's 125 usecs are allocated? */
  1549. static unsigned short periodic_usecs(struct oxu_hcd *oxu,
  1550. unsigned frame, unsigned uframe)
  1551. {
  1552. __le32 *hw_p = &oxu->periodic[frame];
  1553. union ehci_shadow *q = &oxu->pshadow[frame];
  1554. unsigned usecs = 0;
  1555. while (q->ptr) {
  1556. switch (Q_NEXT_TYPE(*hw_p)) {
  1557. case Q_TYPE_QH:
  1558. default:
  1559. /* is it in the S-mask? */
  1560. if (q->qh->hw_info2 & cpu_to_le32(1 << uframe))
  1561. usecs += q->qh->usecs;
  1562. /* ... or C-mask? */
  1563. if (q->qh->hw_info2 & cpu_to_le32(1 << (8 + uframe)))
  1564. usecs += q->qh->c_usecs;
  1565. hw_p = &q->qh->hw_next;
  1566. q = &q->qh->qh_next;
  1567. break;
  1568. }
  1569. }
  1570. #ifdef DEBUG
  1571. if (usecs > 100)
  1572. oxu_err(oxu, "uframe %d sched overrun: %d usecs\n",
  1573. frame * 8 + uframe, usecs);
  1574. #endif
  1575. return usecs;
  1576. }
  1577. static int enable_periodic(struct oxu_hcd *oxu)
  1578. {
  1579. u32 cmd;
  1580. int status;
  1581. /* did clearing PSE did take effect yet?
  1582. * takes effect only at frame boundaries...
  1583. */
  1584. status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125);
  1585. if (status != 0) {
  1586. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  1587. usb_hc_died(oxu_to_hcd(oxu));
  1588. return status;
  1589. }
  1590. cmd = readl(&oxu->regs->command) | CMD_PSE;
  1591. writel(cmd, &oxu->regs->command);
  1592. /* posted write ... PSS happens later */
  1593. oxu_to_hcd(oxu)->state = HC_STATE_RUNNING;
  1594. /* make sure ehci_work scans these */
  1595. oxu->next_uframe = readl(&oxu->regs->frame_index)
  1596. % (oxu->periodic_size << 3);
  1597. return 0;
  1598. }
  1599. static int disable_periodic(struct oxu_hcd *oxu)
  1600. {
  1601. u32 cmd;
  1602. int status;
  1603. /* did setting PSE not take effect yet?
  1604. * takes effect only at frame boundaries...
  1605. */
  1606. status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125);
  1607. if (status != 0) {
  1608. oxu_to_hcd(oxu)->state = HC_STATE_HALT;
  1609. usb_hc_died(oxu_to_hcd(oxu));
  1610. return status;
  1611. }
  1612. cmd = readl(&oxu->regs->command) & ~CMD_PSE;
  1613. writel(cmd, &oxu->regs->command);
  1614. /* posted write ... */
  1615. oxu->next_uframe = -1;
  1616. return 0;
  1617. }
  1618. /* periodic schedule slots have iso tds (normal or split) first, then a
  1619. * sparse tree for active interrupt transfers.
  1620. *
  1621. * this just links in a qh; caller guarantees uframe masks are set right.
  1622. * no FSTN support (yet; oxu 0.96+)
  1623. */
  1624. static int qh_link_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1625. {
  1626. unsigned i;
  1627. unsigned period = qh->period;
  1628. dev_dbg(&qh->dev->dev,
  1629. "link qh%d-%04x/%p start %d [%d/%d us]\n",
  1630. period, le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
  1631. qh, qh->start, qh->usecs, qh->c_usecs);
  1632. /* high bandwidth, or otherwise every microframe */
  1633. if (period == 0)
  1634. period = 1;
  1635. for (i = qh->start; i < oxu->periodic_size; i += period) {
  1636. union ehci_shadow *prev = &oxu->pshadow[i];
  1637. __le32 *hw_p = &oxu->periodic[i];
  1638. union ehci_shadow here = *prev;
  1639. __le32 type = 0;
  1640. /* skip the iso nodes at list head */
  1641. while (here.ptr) {
  1642. type = Q_NEXT_TYPE(*hw_p);
  1643. if (type == Q_TYPE_QH)
  1644. break;
  1645. prev = periodic_next_shadow(prev, type);
  1646. hw_p = &here.qh->hw_next;
  1647. here = *prev;
  1648. }
  1649. /* sorting each branch by period (slow-->fast)
  1650. * enables sharing interior tree nodes
  1651. */
  1652. while (here.ptr && qh != here.qh) {
  1653. if (qh->period > here.qh->period)
  1654. break;
  1655. prev = &here.qh->qh_next;
  1656. hw_p = &here.qh->hw_next;
  1657. here = *prev;
  1658. }
  1659. /* link in this qh, unless some earlier pass did that */
  1660. if (qh != here.qh) {
  1661. qh->qh_next = here;
  1662. if (here.qh)
  1663. qh->hw_next = *hw_p;
  1664. wmb();
  1665. prev->qh = qh;
  1666. *hw_p = QH_NEXT(qh->qh_dma);
  1667. }
  1668. }
  1669. qh->qh_state = QH_STATE_LINKED;
  1670. qh_get(qh);
  1671. /* update per-qh bandwidth for usbfs */
  1672. oxu_to_hcd(oxu)->self.bandwidth_allocated += qh->period
  1673. ? ((qh->usecs + qh->c_usecs) / qh->period)
  1674. : (qh->usecs * 8);
  1675. /* maybe enable periodic schedule processing */
  1676. if (!oxu->periodic_sched++)
  1677. return enable_periodic(oxu);
  1678. return 0;
  1679. }
  1680. static void qh_unlink_periodic(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1681. {
  1682. unsigned i;
  1683. unsigned period;
  1684. /* FIXME:
  1685. * IF this isn't high speed
  1686. * and this qh is active in the current uframe
  1687. * (and overlay token SplitXstate is false?)
  1688. * THEN
  1689. * qh->hw_info1 |= cpu_to_le32(1 << 7 "ignore");
  1690. */
  1691. /* high bandwidth, or otherwise part of every microframe */
  1692. period = qh->period;
  1693. if (period == 0)
  1694. period = 1;
  1695. for (i = qh->start; i < oxu->periodic_size; i += period)
  1696. periodic_unlink(oxu, i, qh);
  1697. /* update per-qh bandwidth for usbfs */
  1698. oxu_to_hcd(oxu)->self.bandwidth_allocated -= qh->period
  1699. ? ((qh->usecs + qh->c_usecs) / qh->period)
  1700. : (qh->usecs * 8);
  1701. dev_dbg(&qh->dev->dev,
  1702. "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
  1703. qh->period,
  1704. le32_to_cpup(&qh->hw_info2) & (QH_CMASK | QH_SMASK),
  1705. qh, qh->start, qh->usecs, qh->c_usecs);
  1706. /* qh->qh_next still "live" to HC */
  1707. qh->qh_state = QH_STATE_UNLINK;
  1708. qh->qh_next.ptr = NULL;
  1709. qh_put(qh);
  1710. /* maybe turn off periodic schedule */
  1711. oxu->periodic_sched--;
  1712. if (!oxu->periodic_sched)
  1713. (void) disable_periodic(oxu);
  1714. }
  1715. static void intr_deschedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1716. {
  1717. unsigned wait;
  1718. qh_unlink_periodic(oxu, qh);
  1719. /* simple/paranoid: always delay, expecting the HC needs to read
  1720. * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
  1721. * expect hub_wq to clean up after any CSPLITs we won't issue.
  1722. * active high speed queues may need bigger delays...
  1723. */
  1724. if (list_empty(&qh->qtd_list)
  1725. || (cpu_to_le32(QH_CMASK) & qh->hw_info2) != 0)
  1726. wait = 2;
  1727. else
  1728. wait = 55; /* worst case: 3 * 1024 */
  1729. udelay(wait);
  1730. qh->qh_state = QH_STATE_IDLE;
  1731. qh->hw_next = EHCI_LIST_END;
  1732. wmb();
  1733. }
  1734. static int check_period(struct oxu_hcd *oxu,
  1735. unsigned frame, unsigned uframe,
  1736. unsigned period, unsigned usecs)
  1737. {
  1738. int claimed;
  1739. /* complete split running into next frame?
  1740. * given FSTN support, we could sometimes check...
  1741. */
  1742. if (uframe >= 8)
  1743. return 0;
  1744. /*
  1745. * 80% periodic == 100 usec/uframe available
  1746. * convert "usecs we need" to "max already claimed"
  1747. */
  1748. usecs = 100 - usecs;
  1749. /* we "know" 2 and 4 uframe intervals were rejected; so
  1750. * for period 0, check _every_ microframe in the schedule.
  1751. */
  1752. if (unlikely(period == 0)) {
  1753. do {
  1754. for (uframe = 0; uframe < 7; uframe++) {
  1755. claimed = periodic_usecs(oxu, frame, uframe);
  1756. if (claimed > usecs)
  1757. return 0;
  1758. }
  1759. } while ((frame += 1) < oxu->periodic_size);
  1760. /* just check the specified uframe, at that period */
  1761. } else {
  1762. do {
  1763. claimed = periodic_usecs(oxu, frame, uframe);
  1764. if (claimed > usecs)
  1765. return 0;
  1766. } while ((frame += period) < oxu->periodic_size);
  1767. }
  1768. return 1;
  1769. }
  1770. static int check_intr_schedule(struct oxu_hcd *oxu,
  1771. unsigned frame, unsigned uframe,
  1772. const struct ehci_qh *qh, __le32 *c_maskp)
  1773. {
  1774. int retval = -ENOSPC;
  1775. if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
  1776. goto done;
  1777. if (!check_period(oxu, frame, uframe, qh->period, qh->usecs))
  1778. goto done;
  1779. if (!qh->c_usecs) {
  1780. retval = 0;
  1781. *c_maskp = 0;
  1782. goto done;
  1783. }
  1784. done:
  1785. return retval;
  1786. }
  1787. /* "first fit" scheduling policy used the first time through,
  1788. * or when the previous schedule slot can't be re-used.
  1789. */
  1790. static int qh_schedule(struct oxu_hcd *oxu, struct ehci_qh *qh)
  1791. {
  1792. int status;
  1793. unsigned uframe;
  1794. __le32 c_mask;
  1795. unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
  1796. qh_refresh(oxu, qh);
  1797. qh->hw_next = EHCI_LIST_END;
  1798. frame = qh->start;
  1799. /* reuse the previous schedule slots, if we can */
  1800. if (frame < qh->period) {
  1801. uframe = ffs(le32_to_cpup(&qh->hw_info2) & QH_SMASK);
  1802. status = check_intr_schedule(oxu, frame, --uframe,
  1803. qh, &c_mask);
  1804. } else {
  1805. uframe = 0;
  1806. c_mask = 0;
  1807. status = -ENOSPC;
  1808. }
  1809. /* else scan the schedule to find a group of slots such that all
  1810. * uframes have enough periodic bandwidth available.
  1811. */
  1812. if (status) {
  1813. /* "normal" case, uframing flexible except with splits */
  1814. if (qh->period) {
  1815. frame = qh->period - 1;
  1816. do {
  1817. for (uframe = 0; uframe < 8; uframe++) {
  1818. status = check_intr_schedule(oxu,
  1819. frame, uframe, qh,
  1820. &c_mask);
  1821. if (status == 0)
  1822. break;
  1823. }
  1824. } while (status && frame--);
  1825. /* qh->period == 0 means every uframe */
  1826. } else {
  1827. frame = 0;
  1828. status = check_intr_schedule(oxu, 0, 0, qh, &c_mask);
  1829. }
  1830. if (status)
  1831. goto done;
  1832. qh->start = frame;
  1833. /* reset S-frame and (maybe) C-frame masks */
  1834. qh->hw_info2 &= cpu_to_le32(~(QH_CMASK | QH_SMASK));
  1835. qh->hw_info2 |= qh->period
  1836. ? cpu_to_le32(1 << uframe)
  1837. : cpu_to_le32(QH_SMASK);
  1838. qh->hw_info2 |= c_mask;
  1839. } else
  1840. oxu_dbg(oxu, "reused qh %p schedule\n", qh);
  1841. /* stuff into the periodic schedule */
  1842. status = qh_link_periodic(oxu, qh);
  1843. done:
  1844. return status;
  1845. }
  1846. static int intr_submit(struct oxu_hcd *oxu, struct urb *urb,
  1847. struct list_head *qtd_list, gfp_t mem_flags)
  1848. {
  1849. unsigned epnum;
  1850. unsigned long flags;
  1851. struct ehci_qh *qh;
  1852. int status = 0;
  1853. struct list_head empty;
  1854. /* get endpoint and transfer/schedule data */
  1855. epnum = urb->ep->desc.bEndpointAddress;
  1856. spin_lock_irqsave(&oxu->lock, flags);
  1857. if (unlikely(!HCD_HW_ACCESSIBLE(oxu_to_hcd(oxu)))) {
  1858. status = -ESHUTDOWN;
  1859. goto done;
  1860. }
  1861. /* get qh and force any scheduling errors */
  1862. INIT_LIST_HEAD(&empty);
  1863. qh = qh_append_tds(oxu, urb, &empty, epnum, &urb->ep->hcpriv);
  1864. if (qh == NULL) {
  1865. status = -ENOMEM;
  1866. goto done;
  1867. }
  1868. if (qh->qh_state == QH_STATE_IDLE) {
  1869. status = qh_schedule(oxu, qh);
  1870. if (status != 0)
  1871. goto done;
  1872. }
  1873. /* then queue the urb's tds to the qh */
  1874. qh = qh_append_tds(oxu, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1875. BUG_ON(qh == NULL);
  1876. /* ... update usbfs periodic stats */
  1877. oxu_to_hcd(oxu)->self.bandwidth_int_reqs++;
  1878. done:
  1879. spin_unlock_irqrestore(&oxu->lock, flags);
  1880. if (status)
  1881. qtd_list_free(oxu, urb, qtd_list);
  1882. return status;
  1883. }
  1884. static inline int itd_submit(struct oxu_hcd *oxu, struct urb *urb,
  1885. gfp_t mem_flags)
  1886. {
  1887. oxu_dbg(oxu, "iso support is missing!\n");
  1888. return -ENOSYS;
  1889. }
  1890. static inline int sitd_submit(struct oxu_hcd *oxu, struct urb *urb,
  1891. gfp_t mem_flags)
  1892. {
  1893. oxu_dbg(oxu, "split iso support is missing!\n");
  1894. return -ENOSYS;
  1895. }
  1896. static void scan_periodic(struct oxu_hcd *oxu)
  1897. {
  1898. unsigned frame, clock, now_uframe, mod;
  1899. unsigned modified;
  1900. mod = oxu->periodic_size << 3;
  1901. /*
  1902. * When running, scan from last scan point up to "now"
  1903. * else clean up by scanning everything that's left.
  1904. * Touches as few pages as possible: cache-friendly.
  1905. */
  1906. now_uframe = oxu->next_uframe;
  1907. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1908. clock = readl(&oxu->regs->frame_index);
  1909. else
  1910. clock = now_uframe + mod - 1;
  1911. clock %= mod;
  1912. for (;;) {
  1913. union ehci_shadow q, *q_p;
  1914. __le32 type, *hw_p;
  1915. unsigned uframes;
  1916. /* don't scan past the live uframe */
  1917. frame = now_uframe >> 3;
  1918. if (frame == (clock >> 3))
  1919. uframes = now_uframe & 0x07;
  1920. else {
  1921. /* safe to scan the whole frame at once */
  1922. now_uframe |= 0x07;
  1923. uframes = 8;
  1924. }
  1925. restart:
  1926. /* scan each element in frame's queue for completions */
  1927. q_p = &oxu->pshadow[frame];
  1928. hw_p = &oxu->periodic[frame];
  1929. q.ptr = q_p->ptr;
  1930. type = Q_NEXT_TYPE(*hw_p);
  1931. modified = 0;
  1932. while (q.ptr != NULL) {
  1933. union ehci_shadow temp;
  1934. int live;
  1935. live = HC_IS_RUNNING(oxu_to_hcd(oxu)->state);
  1936. switch (type) {
  1937. case Q_TYPE_QH:
  1938. /* handle any completions */
  1939. temp.qh = qh_get(q.qh);
  1940. type = Q_NEXT_TYPE(q.qh->hw_next);
  1941. q = q.qh->qh_next;
  1942. modified = qh_completions(oxu, temp.qh);
  1943. if (unlikely(list_empty(&temp.qh->qtd_list)))
  1944. intr_deschedule(oxu, temp.qh);
  1945. qh_put(temp.qh);
  1946. break;
  1947. default:
  1948. oxu_dbg(oxu, "corrupt type %d frame %d shadow %p\n",
  1949. type, frame, q.ptr);
  1950. q.ptr = NULL;
  1951. }
  1952. /* assume completion callbacks modify the queue */
  1953. if (unlikely(modified))
  1954. goto restart;
  1955. }
  1956. /* Stop when we catch up to the HC */
  1957. /* FIXME: this assumes we won't get lapped when
  1958. * latencies climb; that should be rare, but...
  1959. * detect it, and just go all the way around.
  1960. * FLR might help detect this case, so long as latencies
  1961. * don't exceed periodic_size msec (default 1.024 sec).
  1962. */
  1963. /* FIXME: likewise assumes HC doesn't halt mid-scan */
  1964. if (now_uframe == clock) {
  1965. unsigned now;
  1966. if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state))
  1967. break;
  1968. oxu->next_uframe = now_uframe;
  1969. now = readl(&oxu->regs->frame_index) % mod;
  1970. if (now_uframe == now)
  1971. break;
  1972. /* rescan the rest of this frame, then ... */
  1973. clock = now;
  1974. } else {
  1975. now_uframe++;
  1976. now_uframe %= mod;
  1977. }
  1978. }
  1979. }
  1980. /* On some systems, leaving remote wakeup enabled prevents system shutdown.
  1981. * The firmware seems to think that powering off is a wakeup event!
  1982. * This routine turns off remote wakeup and everything else, on all ports.
  1983. */
  1984. static void ehci_turn_off_all_ports(struct oxu_hcd *oxu)
  1985. {
  1986. int port = HCS_N_PORTS(oxu->hcs_params);
  1987. while (port--)
  1988. writel(PORT_RWC_BITS, &oxu->regs->port_status[port]);
  1989. }
  1990. static void ehci_port_power(struct oxu_hcd *oxu, int is_on)
  1991. {
  1992. unsigned port;
  1993. if (!HCS_PPC(oxu->hcs_params))
  1994. return;
  1995. oxu_dbg(oxu, "...power%s ports...\n", is_on ? "up" : "down");
  1996. for (port = HCS_N_PORTS(oxu->hcs_params); port > 0; )
  1997. (void) oxu_hub_control(oxu_to_hcd(oxu),
  1998. is_on ? SetPortFeature : ClearPortFeature,
  1999. USB_PORT_FEAT_POWER,
  2000. port--, NULL, 0);
  2001. msleep(20);
  2002. }
  2003. /* Called from some interrupts, timers, and so on.
  2004. * It calls driver completion functions, after dropping oxu->lock.
  2005. */
  2006. static void ehci_work(struct oxu_hcd *oxu)
  2007. {
  2008. timer_action_done(oxu, TIMER_IO_WATCHDOG);
  2009. if (oxu->reclaim_ready)
  2010. end_unlink_async(oxu);
  2011. /* another CPU may drop oxu->lock during a schedule scan while
  2012. * it reports urb completions. this flag guards against bogus
  2013. * attempts at re-entrant schedule scanning.
  2014. */
  2015. if (oxu->scanning)
  2016. return;
  2017. oxu->scanning = 1;
  2018. scan_async(oxu);
  2019. if (oxu->next_uframe != -1)
  2020. scan_periodic(oxu);
  2021. oxu->scanning = 0;
  2022. /* the IO watchdog guards against hardware or driver bugs that
  2023. * misplace IRQs, and should let us run completely without IRQs.
  2024. * such lossage has been observed on both VT6202 and VT8235.
  2025. */
  2026. if (HC_IS_RUNNING(oxu_to_hcd(oxu)->state) &&
  2027. (oxu->async->qh_next.ptr != NULL ||
  2028. oxu->periodic_sched != 0))
  2029. timer_action(oxu, TIMER_IO_WATCHDOG);
  2030. }
  2031. static void unlink_async(struct oxu_hcd *oxu, struct ehci_qh *qh)
  2032. {
  2033. /* if we need to use IAA and it's busy, defer */
  2034. if (qh->qh_state == QH_STATE_LINKED
  2035. && oxu->reclaim
  2036. && HC_IS_RUNNING(oxu_to_hcd(oxu)->state)) {
  2037. struct ehci_qh *last;
  2038. for (last = oxu->reclaim;
  2039. last->reclaim;
  2040. last = last->reclaim)
  2041. continue;
  2042. qh->qh_state = QH_STATE_UNLINK_WAIT;
  2043. last->reclaim = qh;
  2044. /* bypass IAA if the hc can't care */
  2045. } else if (!HC_IS_RUNNING(oxu_to_hcd(oxu)->state) && oxu->reclaim)
  2046. end_unlink_async(oxu);
  2047. /* something else might have unlinked the qh by now */
  2048. if (qh->qh_state == QH_STATE_LINKED)
  2049. start_unlink_async(oxu, qh);
  2050. }
  2051. /*
  2052. * USB host controller methods
  2053. */
  2054. static irqreturn_t oxu210_hcd_irq(struct usb_hcd *hcd)
  2055. {
  2056. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2057. u32 status, pcd_status = 0;
  2058. int bh;
  2059. spin_lock(&oxu->lock);
  2060. status = readl(&oxu->regs->status);
  2061. /* e.g. cardbus physical eject */
  2062. if (status == ~(u32) 0) {
  2063. oxu_dbg(oxu, "device removed\n");
  2064. goto dead;
  2065. }
  2066. /* Shared IRQ? */
  2067. status &= INTR_MASK;
  2068. if (!status || unlikely(hcd->state == HC_STATE_HALT)) {
  2069. spin_unlock(&oxu->lock);
  2070. return IRQ_NONE;
  2071. }
  2072. /* clear (just) interrupts */
  2073. writel(status, &oxu->regs->status);
  2074. readl(&oxu->regs->command); /* unblock posted write */
  2075. bh = 0;
  2076. #ifdef OXU_VERBOSE_DEBUG
  2077. /* unrequested/ignored: Frame List Rollover */
  2078. dbg_status(oxu, "irq", status);
  2079. #endif
  2080. /* INT, ERR, and IAA interrupt rates can be throttled */
  2081. /* normal [4.15.1.2] or error [4.15.1.1] completion */
  2082. if (likely((status & (STS_INT|STS_ERR)) != 0))
  2083. bh = 1;
  2084. /* complete the unlinking of some qh [4.15.2.3] */
  2085. if (status & STS_IAA) {
  2086. oxu->reclaim_ready = 1;
  2087. bh = 1;
  2088. }
  2089. /* remote wakeup [4.3.1] */
  2090. if (status & STS_PCD) {
  2091. unsigned i = HCS_N_PORTS(oxu->hcs_params);
  2092. pcd_status = status;
  2093. /* resume root hub? */
  2094. if (!(readl(&oxu->regs->command) & CMD_RUN))
  2095. usb_hcd_resume_root_hub(hcd);
  2096. while (i--) {
  2097. int pstatus = readl(&oxu->regs->port_status[i]);
  2098. if (pstatus & PORT_OWNER)
  2099. continue;
  2100. if (!(pstatus & PORT_RESUME)
  2101. || oxu->reset_done[i] != 0)
  2102. continue;
  2103. /* start USB_RESUME_TIMEOUT resume signaling from this
  2104. * port, and make hub_wq collect PORT_STAT_C_SUSPEND to
  2105. * stop that signaling.
  2106. */
  2107. oxu->reset_done[i] = jiffies +
  2108. msecs_to_jiffies(USB_RESUME_TIMEOUT);
  2109. oxu_dbg(oxu, "port %d remote wakeup\n", i + 1);
  2110. mod_timer(&hcd->rh_timer, oxu->reset_done[i]);
  2111. }
  2112. }
  2113. /* PCI errors [4.15.2.4] */
  2114. if (unlikely((status & STS_FATAL) != 0)) {
  2115. /* bogus "fatal" IRQs appear on some chips... why? */
  2116. status = readl(&oxu->regs->status);
  2117. dbg_cmd(oxu, "fatal", readl(&oxu->regs->command));
  2118. dbg_status(oxu, "fatal", status);
  2119. if (status & STS_HALT) {
  2120. oxu_err(oxu, "fatal error\n");
  2121. dead:
  2122. ehci_reset(oxu);
  2123. writel(0, &oxu->regs->configured_flag);
  2124. usb_hc_died(hcd);
  2125. /* generic layer kills/unlinks all urbs, then
  2126. * uses oxu_stop to clean up the rest
  2127. */
  2128. bh = 1;
  2129. }
  2130. }
  2131. if (bh)
  2132. ehci_work(oxu);
  2133. spin_unlock(&oxu->lock);
  2134. if (pcd_status & STS_PCD)
  2135. usb_hcd_poll_rh_status(hcd);
  2136. return IRQ_HANDLED;
  2137. }
  2138. static irqreturn_t oxu_irq(struct usb_hcd *hcd)
  2139. {
  2140. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2141. int ret = IRQ_HANDLED;
  2142. u32 status = oxu_readl(hcd->regs, OXU_CHIPIRQSTATUS);
  2143. u32 enable = oxu_readl(hcd->regs, OXU_CHIPIRQEN_SET);
  2144. /* Disable all interrupt */
  2145. oxu_writel(hcd->regs, OXU_CHIPIRQEN_CLR, enable);
  2146. if ((oxu->is_otg && (status & OXU_USBOTGI)) ||
  2147. (!oxu->is_otg && (status & OXU_USBSPHI)))
  2148. oxu210_hcd_irq(hcd);
  2149. else
  2150. ret = IRQ_NONE;
  2151. /* Enable all interrupt back */
  2152. oxu_writel(hcd->regs, OXU_CHIPIRQEN_SET, enable);
  2153. return ret;
  2154. }
  2155. static void oxu_watchdog(unsigned long param)
  2156. {
  2157. struct oxu_hcd *oxu = (struct oxu_hcd *) param;
  2158. unsigned long flags;
  2159. spin_lock_irqsave(&oxu->lock, flags);
  2160. /* lost IAA irqs wedge things badly; seen with a vt8235 */
  2161. if (oxu->reclaim) {
  2162. u32 status = readl(&oxu->regs->status);
  2163. if (status & STS_IAA) {
  2164. oxu_vdbg(oxu, "lost IAA\n");
  2165. writel(STS_IAA, &oxu->regs->status);
  2166. oxu->reclaim_ready = 1;
  2167. }
  2168. }
  2169. /* stop async processing after it's idled a bit */
  2170. if (test_bit(TIMER_ASYNC_OFF, &oxu->actions))
  2171. start_unlink_async(oxu, oxu->async);
  2172. /* oxu could run by timer, without IRQs ... */
  2173. ehci_work(oxu);
  2174. spin_unlock_irqrestore(&oxu->lock, flags);
  2175. }
  2176. /* One-time init, only for memory state.
  2177. */
  2178. static int oxu_hcd_init(struct usb_hcd *hcd)
  2179. {
  2180. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2181. u32 temp;
  2182. int retval;
  2183. u32 hcc_params;
  2184. spin_lock_init(&oxu->lock);
  2185. init_timer(&oxu->watchdog);
  2186. oxu->watchdog.function = oxu_watchdog;
  2187. oxu->watchdog.data = (unsigned long) oxu;
  2188. /*
  2189. * hw default: 1K periodic list heads, one per frame.
  2190. * periodic_size can shrink by USBCMD update if hcc_params allows.
  2191. */
  2192. oxu->periodic_size = DEFAULT_I_TDPS;
  2193. retval = ehci_mem_init(oxu, GFP_KERNEL);
  2194. if (retval < 0)
  2195. return retval;
  2196. /* controllers may cache some of the periodic schedule ... */
  2197. hcc_params = readl(&oxu->caps->hcc_params);
  2198. if (HCC_ISOC_CACHE(hcc_params)) /* full frame cache */
  2199. oxu->i_thresh = 8;
  2200. else /* N microframes cached */
  2201. oxu->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  2202. oxu->reclaim = NULL;
  2203. oxu->reclaim_ready = 0;
  2204. oxu->next_uframe = -1;
  2205. /*
  2206. * dedicate a qh for the async ring head, since we couldn't unlink
  2207. * a 'real' qh without stopping the async schedule [4.8]. use it
  2208. * as the 'reclamation list head' too.
  2209. * its dummy is used in hw_alt_next of many tds, to prevent the qh
  2210. * from automatically advancing to the next td after short reads.
  2211. */
  2212. oxu->async->qh_next.qh = NULL;
  2213. oxu->async->hw_next = QH_NEXT(oxu->async->qh_dma);
  2214. oxu->async->hw_info1 = cpu_to_le32(QH_HEAD);
  2215. oxu->async->hw_token = cpu_to_le32(QTD_STS_HALT);
  2216. oxu->async->hw_qtd_next = EHCI_LIST_END;
  2217. oxu->async->qh_state = QH_STATE_LINKED;
  2218. oxu->async->hw_alt_next = QTD_NEXT(oxu->async->dummy->qtd_dma);
  2219. /* clear interrupt enables, set irq latency */
  2220. if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
  2221. log2_irq_thresh = 0;
  2222. temp = 1 << (16 + log2_irq_thresh);
  2223. if (HCC_CANPARK(hcc_params)) {
  2224. /* HW default park == 3, on hardware that supports it (like
  2225. * NVidia and ALI silicon), maximizes throughput on the async
  2226. * schedule by avoiding QH fetches between transfers.
  2227. *
  2228. * With fast usb storage devices and NForce2, "park" seems to
  2229. * make problems: throughput reduction (!), data errors...
  2230. */
  2231. if (park) {
  2232. park = min(park, (unsigned) 3);
  2233. temp |= CMD_PARK;
  2234. temp |= park << 8;
  2235. }
  2236. oxu_dbg(oxu, "park %d\n", park);
  2237. }
  2238. if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
  2239. /* periodic schedule size can be smaller than default */
  2240. temp &= ~(3 << 2);
  2241. temp |= (EHCI_TUNE_FLS << 2);
  2242. }
  2243. oxu->command = temp;
  2244. return 0;
  2245. }
  2246. /* Called during probe() after chip reset completes.
  2247. */
  2248. static int oxu_reset(struct usb_hcd *hcd)
  2249. {
  2250. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2251. int ret;
  2252. spin_lock_init(&oxu->mem_lock);
  2253. INIT_LIST_HEAD(&oxu->urb_list);
  2254. oxu->urb_len = 0;
  2255. /* FIMXE */
  2256. hcd->self.controller->dma_mask = NULL;
  2257. if (oxu->is_otg) {
  2258. oxu->caps = hcd->regs + OXU_OTG_CAP_OFFSET;
  2259. oxu->regs = hcd->regs + OXU_OTG_CAP_OFFSET + \
  2260. HC_LENGTH(readl(&oxu->caps->hc_capbase));
  2261. oxu->mem = hcd->regs + OXU_SPH_MEM;
  2262. } else {
  2263. oxu->caps = hcd->regs + OXU_SPH_CAP_OFFSET;
  2264. oxu->regs = hcd->regs + OXU_SPH_CAP_OFFSET + \
  2265. HC_LENGTH(readl(&oxu->caps->hc_capbase));
  2266. oxu->mem = hcd->regs + OXU_OTG_MEM;
  2267. }
  2268. oxu->hcs_params = readl(&oxu->caps->hcs_params);
  2269. oxu->sbrn = 0x20;
  2270. ret = oxu_hcd_init(hcd);
  2271. if (ret)
  2272. return ret;
  2273. return 0;
  2274. }
  2275. static int oxu_run(struct usb_hcd *hcd)
  2276. {
  2277. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2278. int retval;
  2279. u32 temp, hcc_params;
  2280. hcd->uses_new_polling = 1;
  2281. /* EHCI spec section 4.1 */
  2282. retval = ehci_reset(oxu);
  2283. if (retval != 0) {
  2284. ehci_mem_cleanup(oxu);
  2285. return retval;
  2286. }
  2287. writel(oxu->periodic_dma, &oxu->regs->frame_list);
  2288. writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
  2289. /* hcc_params controls whether oxu->regs->segment must (!!!)
  2290. * be used; it constrains QH/ITD/SITD and QTD locations.
  2291. * pci_pool consistent memory always uses segment zero.
  2292. * streaming mappings for I/O buffers, like pci_map_single(),
  2293. * can return segments above 4GB, if the device allows.
  2294. *
  2295. * NOTE: the dma mask is visible through dma_supported(), so
  2296. * drivers can pass this info along ... like NETIF_F_HIGHDMA,
  2297. * Scsi_Host.highmem_io, and so forth. It's readonly to all
  2298. * host side drivers though.
  2299. */
  2300. hcc_params = readl(&oxu->caps->hcc_params);
  2301. if (HCC_64BIT_ADDR(hcc_params))
  2302. writel(0, &oxu->regs->segment);
  2303. oxu->command &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE |
  2304. CMD_ASE | CMD_RESET);
  2305. oxu->command |= CMD_RUN;
  2306. writel(oxu->command, &oxu->regs->command);
  2307. dbg_cmd(oxu, "init", oxu->command);
  2308. /*
  2309. * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
  2310. * are explicitly handed to companion controller(s), so no TT is
  2311. * involved with the root hub. (Except where one is integrated,
  2312. * and there's no companion controller unless maybe for USB OTG.)
  2313. */
  2314. hcd->state = HC_STATE_RUNNING;
  2315. writel(FLAG_CF, &oxu->regs->configured_flag);
  2316. readl(&oxu->regs->command); /* unblock posted writes */
  2317. temp = HC_VERSION(readl(&oxu->caps->hc_capbase));
  2318. oxu_info(oxu, "USB %x.%x started, quasi-EHCI %x.%02x, driver %s%s\n",
  2319. ((oxu->sbrn & 0xf0)>>4), (oxu->sbrn & 0x0f),
  2320. temp >> 8, temp & 0xff, DRIVER_VERSION,
  2321. ignore_oc ? ", overcurrent ignored" : "");
  2322. writel(INTR_MASK, &oxu->regs->intr_enable); /* Turn On Interrupts */
  2323. return 0;
  2324. }
  2325. static void oxu_stop(struct usb_hcd *hcd)
  2326. {
  2327. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2328. /* Turn off port power on all root hub ports. */
  2329. ehci_port_power(oxu, 0);
  2330. /* no more interrupts ... */
  2331. del_timer_sync(&oxu->watchdog);
  2332. spin_lock_irq(&oxu->lock);
  2333. if (HC_IS_RUNNING(hcd->state))
  2334. ehci_quiesce(oxu);
  2335. ehci_reset(oxu);
  2336. writel(0, &oxu->regs->intr_enable);
  2337. spin_unlock_irq(&oxu->lock);
  2338. /* let companion controllers work when we aren't */
  2339. writel(0, &oxu->regs->configured_flag);
  2340. /* root hub is shut down separately (first, when possible) */
  2341. spin_lock_irq(&oxu->lock);
  2342. if (oxu->async)
  2343. ehci_work(oxu);
  2344. spin_unlock_irq(&oxu->lock);
  2345. ehci_mem_cleanup(oxu);
  2346. dbg_status(oxu, "oxu_stop completed", readl(&oxu->regs->status));
  2347. }
  2348. /* Kick in for silicon on any bus (not just pci, etc).
  2349. * This forcibly disables dma and IRQs, helping kexec and other cases
  2350. * where the next system software may expect clean state.
  2351. */
  2352. static void oxu_shutdown(struct usb_hcd *hcd)
  2353. {
  2354. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2355. (void) ehci_halt(oxu);
  2356. ehci_turn_off_all_ports(oxu);
  2357. /* make BIOS/etc use companion controller during reboot */
  2358. writel(0, &oxu->regs->configured_flag);
  2359. /* unblock posted writes */
  2360. readl(&oxu->regs->configured_flag);
  2361. }
  2362. /* Non-error returns are a promise to giveback() the urb later
  2363. * we drop ownership so next owner (or urb unlink) can get it
  2364. *
  2365. * urb + dev is in hcd.self.controller.urb_list
  2366. * we're queueing TDs onto software and hardware lists
  2367. *
  2368. * hcd-specific init for hcpriv hasn't been done yet
  2369. *
  2370. * NOTE: control, bulk, and interrupt share the same code to append TDs
  2371. * to a (possibly active) QH, and the same QH scanning code.
  2372. */
  2373. static int __oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  2374. gfp_t mem_flags)
  2375. {
  2376. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2377. struct list_head qtd_list;
  2378. INIT_LIST_HEAD(&qtd_list);
  2379. switch (usb_pipetype(urb->pipe)) {
  2380. case PIPE_CONTROL:
  2381. case PIPE_BULK:
  2382. default:
  2383. if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
  2384. return -ENOMEM;
  2385. return submit_async(oxu, urb, &qtd_list, mem_flags);
  2386. case PIPE_INTERRUPT:
  2387. if (!qh_urb_transaction(oxu, urb, &qtd_list, mem_flags))
  2388. return -ENOMEM;
  2389. return intr_submit(oxu, urb, &qtd_list, mem_flags);
  2390. case PIPE_ISOCHRONOUS:
  2391. if (urb->dev->speed == USB_SPEED_HIGH)
  2392. return itd_submit(oxu, urb, mem_flags);
  2393. else
  2394. return sitd_submit(oxu, urb, mem_flags);
  2395. }
  2396. }
  2397. /* This function is responsible for breaking URBs with big data size
  2398. * into smaller size and processing small urbs in sequence.
  2399. */
  2400. static int oxu_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  2401. gfp_t mem_flags)
  2402. {
  2403. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2404. int num, rem;
  2405. int transfer_buffer_length;
  2406. void *transfer_buffer;
  2407. struct urb *murb;
  2408. int i, ret;
  2409. /* If not bulk pipe just enqueue the URB */
  2410. if (!usb_pipebulk(urb->pipe))
  2411. return __oxu_urb_enqueue(hcd, urb, mem_flags);
  2412. /* Otherwise we should verify the USB transfer buffer size! */
  2413. transfer_buffer = urb->transfer_buffer;
  2414. transfer_buffer_length = urb->transfer_buffer_length;
  2415. num = urb->transfer_buffer_length / 4096;
  2416. rem = urb->transfer_buffer_length % 4096;
  2417. if (rem != 0)
  2418. num++;
  2419. /* If URB is smaller than 4096 bytes just enqueue it! */
  2420. if (num == 1)
  2421. return __oxu_urb_enqueue(hcd, urb, mem_flags);
  2422. /* Ok, we have more job to do! :) */
  2423. for (i = 0; i < num - 1; i++) {
  2424. /* Get free micro URB poll till a free urb is received */
  2425. do {
  2426. murb = (struct urb *) oxu_murb_alloc(oxu);
  2427. if (!murb)
  2428. schedule();
  2429. } while (!murb);
  2430. /* Coping the urb */
  2431. memcpy(murb, urb, sizeof(struct urb));
  2432. murb->transfer_buffer_length = 4096;
  2433. murb->transfer_buffer = transfer_buffer + i * 4096;
  2434. /* Null pointer for the encodes that this is a micro urb */
  2435. murb->complete = NULL;
  2436. ((struct oxu_murb *) murb)->main = urb;
  2437. ((struct oxu_murb *) murb)->last = 0;
  2438. /* This loop is to guarantee urb to be processed when there's
  2439. * not enough resources at a particular time by retrying.
  2440. */
  2441. do {
  2442. ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
  2443. if (ret)
  2444. schedule();
  2445. } while (ret);
  2446. }
  2447. /* Last urb requires special handling */
  2448. /* Get free micro URB poll till a free urb is received */
  2449. do {
  2450. murb = (struct urb *) oxu_murb_alloc(oxu);
  2451. if (!murb)
  2452. schedule();
  2453. } while (!murb);
  2454. /* Coping the urb */
  2455. memcpy(murb, urb, sizeof(struct urb));
  2456. murb->transfer_buffer_length = rem > 0 ? rem : 4096;
  2457. murb->transfer_buffer = transfer_buffer + (num - 1) * 4096;
  2458. /* Null pointer for the encodes that this is a micro urb */
  2459. murb->complete = NULL;
  2460. ((struct oxu_murb *) murb)->main = urb;
  2461. ((struct oxu_murb *) murb)->last = 1;
  2462. do {
  2463. ret = __oxu_urb_enqueue(hcd, murb, mem_flags);
  2464. if (ret)
  2465. schedule();
  2466. } while (ret);
  2467. return ret;
  2468. }
  2469. /* Remove from hardware lists.
  2470. * Completions normally happen asynchronously
  2471. */
  2472. static int oxu_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
  2473. {
  2474. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2475. struct ehci_qh *qh;
  2476. unsigned long flags;
  2477. spin_lock_irqsave(&oxu->lock, flags);
  2478. switch (usb_pipetype(urb->pipe)) {
  2479. case PIPE_CONTROL:
  2480. case PIPE_BULK:
  2481. default:
  2482. qh = (struct ehci_qh *) urb->hcpriv;
  2483. if (!qh)
  2484. break;
  2485. unlink_async(oxu, qh);
  2486. break;
  2487. case PIPE_INTERRUPT:
  2488. qh = (struct ehci_qh *) urb->hcpriv;
  2489. if (!qh)
  2490. break;
  2491. switch (qh->qh_state) {
  2492. case QH_STATE_LINKED:
  2493. intr_deschedule(oxu, qh);
  2494. /* FALL THROUGH */
  2495. case QH_STATE_IDLE:
  2496. qh_completions(oxu, qh);
  2497. break;
  2498. default:
  2499. oxu_dbg(oxu, "bogus qh %p state %d\n",
  2500. qh, qh->qh_state);
  2501. goto done;
  2502. }
  2503. /* reschedule QH iff another request is queued */
  2504. if (!list_empty(&qh->qtd_list)
  2505. && HC_IS_RUNNING(hcd->state)) {
  2506. int status;
  2507. status = qh_schedule(oxu, qh);
  2508. spin_unlock_irqrestore(&oxu->lock, flags);
  2509. if (status != 0) {
  2510. /* shouldn't happen often, but ...
  2511. * FIXME kill those tds' urbs
  2512. */
  2513. dev_err(hcd->self.controller,
  2514. "can't reschedule qh %p, err %d\n", qh,
  2515. status);
  2516. }
  2517. return status;
  2518. }
  2519. break;
  2520. }
  2521. done:
  2522. spin_unlock_irqrestore(&oxu->lock, flags);
  2523. return 0;
  2524. }
  2525. /* Bulk qh holds the data toggle */
  2526. static void oxu_endpoint_disable(struct usb_hcd *hcd,
  2527. struct usb_host_endpoint *ep)
  2528. {
  2529. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2530. unsigned long flags;
  2531. struct ehci_qh *qh, *tmp;
  2532. /* ASSERT: any requests/urbs are being unlinked */
  2533. /* ASSERT: nobody can be submitting urbs for this any more */
  2534. rescan:
  2535. spin_lock_irqsave(&oxu->lock, flags);
  2536. qh = ep->hcpriv;
  2537. if (!qh)
  2538. goto done;
  2539. /* endpoints can be iso streams. for now, we don't
  2540. * accelerate iso completions ... so spin a while.
  2541. */
  2542. if (qh->hw_info1 == 0) {
  2543. oxu_vdbg(oxu, "iso delay\n");
  2544. goto idle_timeout;
  2545. }
  2546. if (!HC_IS_RUNNING(hcd->state))
  2547. qh->qh_state = QH_STATE_IDLE;
  2548. switch (qh->qh_state) {
  2549. case QH_STATE_LINKED:
  2550. for (tmp = oxu->async->qh_next.qh;
  2551. tmp && tmp != qh;
  2552. tmp = tmp->qh_next.qh)
  2553. continue;
  2554. /* periodic qh self-unlinks on empty */
  2555. if (!tmp)
  2556. goto nogood;
  2557. unlink_async(oxu, qh);
  2558. /* FALL THROUGH */
  2559. case QH_STATE_UNLINK: /* wait for hw to finish? */
  2560. idle_timeout:
  2561. spin_unlock_irqrestore(&oxu->lock, flags);
  2562. schedule_timeout_uninterruptible(1);
  2563. goto rescan;
  2564. case QH_STATE_IDLE: /* fully unlinked */
  2565. if (list_empty(&qh->qtd_list)) {
  2566. qh_put(qh);
  2567. break;
  2568. }
  2569. /* else FALL THROUGH */
  2570. default:
  2571. nogood:
  2572. /* caller was supposed to have unlinked any requests;
  2573. * that's not our job. just leak this memory.
  2574. */
  2575. oxu_err(oxu, "qh %p (#%02x) state %d%s\n",
  2576. qh, ep->desc.bEndpointAddress, qh->qh_state,
  2577. list_empty(&qh->qtd_list) ? "" : "(has tds)");
  2578. break;
  2579. }
  2580. ep->hcpriv = NULL;
  2581. done:
  2582. spin_unlock_irqrestore(&oxu->lock, flags);
  2583. }
  2584. static int oxu_get_frame(struct usb_hcd *hcd)
  2585. {
  2586. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2587. return (readl(&oxu->regs->frame_index) >> 3) %
  2588. oxu->periodic_size;
  2589. }
  2590. /* Build "status change" packet (one or two bytes) from HC registers */
  2591. static int oxu_hub_status_data(struct usb_hcd *hcd, char *buf)
  2592. {
  2593. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2594. u32 temp, mask, status = 0;
  2595. int ports, i, retval = 1;
  2596. unsigned long flags;
  2597. /* if !PM_RUNTIME, root hub timers won't get shut down ... */
  2598. if (!HC_IS_RUNNING(hcd->state))
  2599. return 0;
  2600. /* init status to no-changes */
  2601. buf[0] = 0;
  2602. ports = HCS_N_PORTS(oxu->hcs_params);
  2603. if (ports > 7) {
  2604. buf[1] = 0;
  2605. retval++;
  2606. }
  2607. /* Some boards (mostly VIA?) report bogus overcurrent indications,
  2608. * causing massive log spam unless we completely ignore them. It
  2609. * may be relevant that VIA VT8235 controllers, where PORT_POWER is
  2610. * always set, seem to clear PORT_OCC and PORT_CSC when writing to
  2611. * PORT_POWER; that's surprising, but maybe within-spec.
  2612. */
  2613. if (!ignore_oc)
  2614. mask = PORT_CSC | PORT_PEC | PORT_OCC;
  2615. else
  2616. mask = PORT_CSC | PORT_PEC;
  2617. /* no hub change reports (bit 0) for now (power, ...) */
  2618. /* port N changes (bit N)? */
  2619. spin_lock_irqsave(&oxu->lock, flags);
  2620. for (i = 0; i < ports; i++) {
  2621. temp = readl(&oxu->regs->port_status[i]);
  2622. /*
  2623. * Return status information even for ports with OWNER set.
  2624. * Otherwise hub_wq wouldn't see the disconnect event when a
  2625. * high-speed device is switched over to the companion
  2626. * controller by the user.
  2627. */
  2628. if (!(temp & PORT_CONNECT))
  2629. oxu->reset_done[i] = 0;
  2630. if ((temp & mask) != 0 || ((temp & PORT_RESUME) != 0 &&
  2631. time_after_eq(jiffies, oxu->reset_done[i]))) {
  2632. if (i < 7)
  2633. buf[0] |= 1 << (i + 1);
  2634. else
  2635. buf[1] |= 1 << (i - 7);
  2636. status = STS_PCD;
  2637. }
  2638. }
  2639. /* FIXME autosuspend idle root hubs */
  2640. spin_unlock_irqrestore(&oxu->lock, flags);
  2641. return status ? retval : 0;
  2642. }
  2643. /* Returns the speed of a device attached to a port on the root hub. */
  2644. static inline unsigned int oxu_port_speed(struct oxu_hcd *oxu,
  2645. unsigned int portsc)
  2646. {
  2647. switch ((portsc >> 26) & 3) {
  2648. case 0:
  2649. return 0;
  2650. case 1:
  2651. return USB_PORT_STAT_LOW_SPEED;
  2652. case 2:
  2653. default:
  2654. return USB_PORT_STAT_HIGH_SPEED;
  2655. }
  2656. }
  2657. #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  2658. static int oxu_hub_control(struct usb_hcd *hcd, u16 typeReq,
  2659. u16 wValue, u16 wIndex, char *buf, u16 wLength)
  2660. {
  2661. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2662. int ports = HCS_N_PORTS(oxu->hcs_params);
  2663. u32 __iomem *status_reg = &oxu->regs->port_status[wIndex - 1];
  2664. u32 temp, status;
  2665. unsigned long flags;
  2666. int retval = 0;
  2667. unsigned selector;
  2668. /*
  2669. * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
  2670. * HCS_INDICATOR may say we can change LEDs to off/amber/green.
  2671. * (track current state ourselves) ... blink for diagnostics,
  2672. * power, "this is the one", etc. EHCI spec supports this.
  2673. */
  2674. spin_lock_irqsave(&oxu->lock, flags);
  2675. switch (typeReq) {
  2676. case ClearHubFeature:
  2677. switch (wValue) {
  2678. case C_HUB_LOCAL_POWER:
  2679. case C_HUB_OVER_CURRENT:
  2680. /* no hub-wide feature/status flags */
  2681. break;
  2682. default:
  2683. goto error;
  2684. }
  2685. break;
  2686. case ClearPortFeature:
  2687. if (!wIndex || wIndex > ports)
  2688. goto error;
  2689. wIndex--;
  2690. temp = readl(status_reg);
  2691. /*
  2692. * Even if OWNER is set, so the port is owned by the
  2693. * companion controller, hub_wq needs to be able to clear
  2694. * the port-change status bits (especially
  2695. * USB_PORT_STAT_C_CONNECTION).
  2696. */
  2697. switch (wValue) {
  2698. case USB_PORT_FEAT_ENABLE:
  2699. writel(temp & ~PORT_PE, status_reg);
  2700. break;
  2701. case USB_PORT_FEAT_C_ENABLE:
  2702. writel((temp & ~PORT_RWC_BITS) | PORT_PEC, status_reg);
  2703. break;
  2704. case USB_PORT_FEAT_SUSPEND:
  2705. if (temp & PORT_RESET)
  2706. goto error;
  2707. if (temp & PORT_SUSPEND) {
  2708. if ((temp & PORT_PE) == 0)
  2709. goto error;
  2710. /* resume signaling for 20 msec */
  2711. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  2712. writel(temp | PORT_RESUME, status_reg);
  2713. oxu->reset_done[wIndex] = jiffies
  2714. + msecs_to_jiffies(20);
  2715. }
  2716. break;
  2717. case USB_PORT_FEAT_C_SUSPEND:
  2718. /* we auto-clear this feature */
  2719. break;
  2720. case USB_PORT_FEAT_POWER:
  2721. if (HCS_PPC(oxu->hcs_params))
  2722. writel(temp & ~(PORT_RWC_BITS | PORT_POWER),
  2723. status_reg);
  2724. break;
  2725. case USB_PORT_FEAT_C_CONNECTION:
  2726. writel((temp & ~PORT_RWC_BITS) | PORT_CSC, status_reg);
  2727. break;
  2728. case USB_PORT_FEAT_C_OVER_CURRENT:
  2729. writel((temp & ~PORT_RWC_BITS) | PORT_OCC, status_reg);
  2730. break;
  2731. case USB_PORT_FEAT_C_RESET:
  2732. /* GetPortStatus clears reset */
  2733. break;
  2734. default:
  2735. goto error;
  2736. }
  2737. readl(&oxu->regs->command); /* unblock posted write */
  2738. break;
  2739. case GetHubDescriptor:
  2740. ehci_hub_descriptor(oxu, (struct usb_hub_descriptor *)
  2741. buf);
  2742. break;
  2743. case GetHubStatus:
  2744. /* no hub-wide feature/status flags */
  2745. memset(buf, 0, 4);
  2746. break;
  2747. case GetPortStatus:
  2748. if (!wIndex || wIndex > ports)
  2749. goto error;
  2750. wIndex--;
  2751. status = 0;
  2752. temp = readl(status_reg);
  2753. /* wPortChange bits */
  2754. if (temp & PORT_CSC)
  2755. status |= USB_PORT_STAT_C_CONNECTION << 16;
  2756. if (temp & PORT_PEC)
  2757. status |= USB_PORT_STAT_C_ENABLE << 16;
  2758. if ((temp & PORT_OCC) && !ignore_oc)
  2759. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  2760. /* whoever resumes must GetPortStatus to complete it!! */
  2761. if (temp & PORT_RESUME) {
  2762. /* Remote Wakeup received? */
  2763. if (!oxu->reset_done[wIndex]) {
  2764. /* resume signaling for 20 msec */
  2765. oxu->reset_done[wIndex] = jiffies
  2766. + msecs_to_jiffies(20);
  2767. /* check the port again */
  2768. mod_timer(&oxu_to_hcd(oxu)->rh_timer,
  2769. oxu->reset_done[wIndex]);
  2770. }
  2771. /* resume completed? */
  2772. else if (time_after_eq(jiffies,
  2773. oxu->reset_done[wIndex])) {
  2774. status |= USB_PORT_STAT_C_SUSPEND << 16;
  2775. oxu->reset_done[wIndex] = 0;
  2776. /* stop resume signaling */
  2777. temp = readl(status_reg);
  2778. writel(temp & ~(PORT_RWC_BITS | PORT_RESUME),
  2779. status_reg);
  2780. retval = handshake(oxu, status_reg,
  2781. PORT_RESUME, 0, 2000 /* 2msec */);
  2782. if (retval != 0) {
  2783. oxu_err(oxu,
  2784. "port %d resume error %d\n",
  2785. wIndex + 1, retval);
  2786. goto error;
  2787. }
  2788. temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
  2789. }
  2790. }
  2791. /* whoever resets must GetPortStatus to complete it!! */
  2792. if ((temp & PORT_RESET)
  2793. && time_after_eq(jiffies,
  2794. oxu->reset_done[wIndex])) {
  2795. status |= USB_PORT_STAT_C_RESET << 16;
  2796. oxu->reset_done[wIndex] = 0;
  2797. /* force reset to complete */
  2798. writel(temp & ~(PORT_RWC_BITS | PORT_RESET),
  2799. status_reg);
  2800. /* REVISIT: some hardware needs 550+ usec to clear
  2801. * this bit; seems too long to spin routinely...
  2802. */
  2803. retval = handshake(oxu, status_reg,
  2804. PORT_RESET, 0, 750);
  2805. if (retval != 0) {
  2806. oxu_err(oxu, "port %d reset error %d\n",
  2807. wIndex + 1, retval);
  2808. goto error;
  2809. }
  2810. /* see what we found out */
  2811. temp = check_reset_complete(oxu, wIndex, status_reg,
  2812. readl(status_reg));
  2813. }
  2814. /* transfer dedicated ports to the companion hc */
  2815. if ((temp & PORT_CONNECT) &&
  2816. test_bit(wIndex, &oxu->companion_ports)) {
  2817. temp &= ~PORT_RWC_BITS;
  2818. temp |= PORT_OWNER;
  2819. writel(temp, status_reg);
  2820. oxu_dbg(oxu, "port %d --> companion\n", wIndex + 1);
  2821. temp = readl(status_reg);
  2822. }
  2823. /*
  2824. * Even if OWNER is set, there's no harm letting hub_wq
  2825. * see the wPortStatus values (they should all be 0 except
  2826. * for PORT_POWER anyway).
  2827. */
  2828. if (temp & PORT_CONNECT) {
  2829. status |= USB_PORT_STAT_CONNECTION;
  2830. /* status may be from integrated TT */
  2831. status |= oxu_port_speed(oxu, temp);
  2832. }
  2833. if (temp & PORT_PE)
  2834. status |= USB_PORT_STAT_ENABLE;
  2835. if (temp & (PORT_SUSPEND|PORT_RESUME))
  2836. status |= USB_PORT_STAT_SUSPEND;
  2837. if (temp & PORT_OC)
  2838. status |= USB_PORT_STAT_OVERCURRENT;
  2839. if (temp & PORT_RESET)
  2840. status |= USB_PORT_STAT_RESET;
  2841. if (temp & PORT_POWER)
  2842. status |= USB_PORT_STAT_POWER;
  2843. #ifndef OXU_VERBOSE_DEBUG
  2844. if (status & ~0xffff) /* only if wPortChange is interesting */
  2845. #endif
  2846. dbg_port(oxu, "GetStatus", wIndex + 1, temp);
  2847. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  2848. break;
  2849. case SetHubFeature:
  2850. switch (wValue) {
  2851. case C_HUB_LOCAL_POWER:
  2852. case C_HUB_OVER_CURRENT:
  2853. /* no hub-wide feature/status flags */
  2854. break;
  2855. default:
  2856. goto error;
  2857. }
  2858. break;
  2859. case SetPortFeature:
  2860. selector = wIndex >> 8;
  2861. wIndex &= 0xff;
  2862. if (!wIndex || wIndex > ports)
  2863. goto error;
  2864. wIndex--;
  2865. temp = readl(status_reg);
  2866. if (temp & PORT_OWNER)
  2867. break;
  2868. temp &= ~PORT_RWC_BITS;
  2869. switch (wValue) {
  2870. case USB_PORT_FEAT_SUSPEND:
  2871. if ((temp & PORT_PE) == 0
  2872. || (temp & PORT_RESET) != 0)
  2873. goto error;
  2874. if (device_may_wakeup(&hcd->self.root_hub->dev))
  2875. temp |= PORT_WAKE_BITS;
  2876. writel(temp | PORT_SUSPEND, status_reg);
  2877. break;
  2878. case USB_PORT_FEAT_POWER:
  2879. if (HCS_PPC(oxu->hcs_params))
  2880. writel(temp | PORT_POWER, status_reg);
  2881. break;
  2882. case USB_PORT_FEAT_RESET:
  2883. if (temp & PORT_RESUME)
  2884. goto error;
  2885. /* line status bits may report this as low speed,
  2886. * which can be fine if this root hub has a
  2887. * transaction translator built in.
  2888. */
  2889. oxu_vdbg(oxu, "port %d reset\n", wIndex + 1);
  2890. temp |= PORT_RESET;
  2891. temp &= ~PORT_PE;
  2892. /*
  2893. * caller must wait, then call GetPortStatus
  2894. * usb 2.0 spec says 50 ms resets on root
  2895. */
  2896. oxu->reset_done[wIndex] = jiffies
  2897. + msecs_to_jiffies(50);
  2898. writel(temp, status_reg);
  2899. break;
  2900. /* For downstream facing ports (these): one hub port is put
  2901. * into test mode according to USB2 11.24.2.13, then the hub
  2902. * must be reset (which for root hub now means rmmod+modprobe,
  2903. * or else system reboot). See EHCI 2.3.9 and 4.14 for info
  2904. * about the EHCI-specific stuff.
  2905. */
  2906. case USB_PORT_FEAT_TEST:
  2907. if (!selector || selector > 5)
  2908. goto error;
  2909. ehci_quiesce(oxu);
  2910. ehci_halt(oxu);
  2911. temp |= selector << 16;
  2912. writel(temp, status_reg);
  2913. break;
  2914. default:
  2915. goto error;
  2916. }
  2917. readl(&oxu->regs->command); /* unblock posted writes */
  2918. break;
  2919. default:
  2920. error:
  2921. /* "stall" on error */
  2922. retval = -EPIPE;
  2923. }
  2924. spin_unlock_irqrestore(&oxu->lock, flags);
  2925. return retval;
  2926. }
  2927. #ifdef CONFIG_PM
  2928. static int oxu_bus_suspend(struct usb_hcd *hcd)
  2929. {
  2930. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2931. int port;
  2932. int mask;
  2933. oxu_dbg(oxu, "suspend root hub\n");
  2934. if (time_before(jiffies, oxu->next_statechange))
  2935. msleep(5);
  2936. port = HCS_N_PORTS(oxu->hcs_params);
  2937. spin_lock_irq(&oxu->lock);
  2938. /* stop schedules, clean any completed work */
  2939. if (HC_IS_RUNNING(hcd->state)) {
  2940. ehci_quiesce(oxu);
  2941. hcd->state = HC_STATE_QUIESCING;
  2942. }
  2943. oxu->command = readl(&oxu->regs->command);
  2944. if (oxu->reclaim)
  2945. oxu->reclaim_ready = 1;
  2946. ehci_work(oxu);
  2947. /* Unlike other USB host controller types, EHCI doesn't have
  2948. * any notion of "global" or bus-wide suspend. The driver has
  2949. * to manually suspend all the active unsuspended ports, and
  2950. * then manually resume them in the bus_resume() routine.
  2951. */
  2952. oxu->bus_suspended = 0;
  2953. while (port--) {
  2954. u32 __iomem *reg = &oxu->regs->port_status[port];
  2955. u32 t1 = readl(reg) & ~PORT_RWC_BITS;
  2956. u32 t2 = t1;
  2957. /* keep track of which ports we suspend */
  2958. if ((t1 & PORT_PE) && !(t1 & PORT_OWNER) &&
  2959. !(t1 & PORT_SUSPEND)) {
  2960. t2 |= PORT_SUSPEND;
  2961. set_bit(port, &oxu->bus_suspended);
  2962. }
  2963. /* enable remote wakeup on all ports */
  2964. if (device_may_wakeup(&hcd->self.root_hub->dev))
  2965. t2 |= PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E;
  2966. else
  2967. t2 &= ~(PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E);
  2968. if (t1 != t2) {
  2969. oxu_vdbg(oxu, "port %d, %08x -> %08x\n",
  2970. port + 1, t1, t2);
  2971. writel(t2, reg);
  2972. }
  2973. }
  2974. /* turn off now-idle HC */
  2975. del_timer_sync(&oxu->watchdog);
  2976. ehci_halt(oxu);
  2977. hcd->state = HC_STATE_SUSPENDED;
  2978. /* allow remote wakeup */
  2979. mask = INTR_MASK;
  2980. if (!device_may_wakeup(&hcd->self.root_hub->dev))
  2981. mask &= ~STS_PCD;
  2982. writel(mask, &oxu->regs->intr_enable);
  2983. readl(&oxu->regs->intr_enable);
  2984. oxu->next_statechange = jiffies + msecs_to_jiffies(10);
  2985. spin_unlock_irq(&oxu->lock);
  2986. return 0;
  2987. }
  2988. /* Caller has locked the root hub, and should reset/reinit on error */
  2989. static int oxu_bus_resume(struct usb_hcd *hcd)
  2990. {
  2991. struct oxu_hcd *oxu = hcd_to_oxu(hcd);
  2992. u32 temp;
  2993. int i;
  2994. if (time_before(jiffies, oxu->next_statechange))
  2995. msleep(5);
  2996. spin_lock_irq(&oxu->lock);
  2997. /* Ideally and we've got a real resume here, and no port's power
  2998. * was lost. (For PCI, that means Vaux was maintained.) But we
  2999. * could instead be restoring a swsusp snapshot -- so that BIOS was
  3000. * the last user of the controller, not reset/pm hardware keeping
  3001. * state we gave to it.
  3002. */
  3003. temp = readl(&oxu->regs->intr_enable);
  3004. oxu_dbg(oxu, "resume root hub%s\n", temp ? "" : " after power loss");
  3005. /* at least some APM implementations will try to deliver
  3006. * IRQs right away, so delay them until we're ready.
  3007. */
  3008. writel(0, &oxu->regs->intr_enable);
  3009. /* re-init operational registers */
  3010. writel(0, &oxu->regs->segment);
  3011. writel(oxu->periodic_dma, &oxu->regs->frame_list);
  3012. writel((u32) oxu->async->qh_dma, &oxu->regs->async_next);
  3013. /* restore CMD_RUN, framelist size, and irq threshold */
  3014. writel(oxu->command, &oxu->regs->command);
  3015. /* Some controller/firmware combinations need a delay during which
  3016. * they set up the port statuses. See Bugzilla #8190. */
  3017. mdelay(8);
  3018. /* manually resume the ports we suspended during bus_suspend() */
  3019. i = HCS_N_PORTS(oxu->hcs_params);
  3020. while (i--) {
  3021. temp = readl(&oxu->regs->port_status[i]);
  3022. temp &= ~(PORT_RWC_BITS
  3023. | PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E);
  3024. if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
  3025. oxu->reset_done[i] = jiffies + msecs_to_jiffies(20);
  3026. temp |= PORT_RESUME;
  3027. }
  3028. writel(temp, &oxu->regs->port_status[i]);
  3029. }
  3030. i = HCS_N_PORTS(oxu->hcs_params);
  3031. mdelay(20);
  3032. while (i--) {
  3033. temp = readl(&oxu->regs->port_status[i]);
  3034. if (test_bit(i, &oxu->bus_suspended) && (temp & PORT_SUSPEND)) {
  3035. temp &= ~(PORT_RWC_BITS | PORT_RESUME);
  3036. writel(temp, &oxu->regs->port_status[i]);
  3037. oxu_vdbg(oxu, "resumed port %d\n", i + 1);
  3038. }
  3039. }
  3040. (void) readl(&oxu->regs->command);
  3041. /* maybe re-activate the schedule(s) */
  3042. temp = 0;
  3043. if (oxu->async->qh_next.qh)
  3044. temp |= CMD_ASE;
  3045. if (oxu->periodic_sched)
  3046. temp |= CMD_PSE;
  3047. if (temp) {
  3048. oxu->command |= temp;
  3049. writel(oxu->command, &oxu->regs->command);
  3050. }
  3051. oxu->next_statechange = jiffies + msecs_to_jiffies(5);
  3052. hcd->state = HC_STATE_RUNNING;
  3053. /* Now we can safely re-enable irqs */
  3054. writel(INTR_MASK, &oxu->regs->intr_enable);
  3055. spin_unlock_irq(&oxu->lock);
  3056. return 0;
  3057. }
  3058. #else
  3059. static int oxu_bus_suspend(struct usb_hcd *hcd)
  3060. {
  3061. return 0;
  3062. }
  3063. static int oxu_bus_resume(struct usb_hcd *hcd)
  3064. {
  3065. return 0;
  3066. }
  3067. #endif /* CONFIG_PM */
  3068. static const struct hc_driver oxu_hc_driver = {
  3069. .description = "oxu210hp_hcd",
  3070. .product_desc = "oxu210hp HCD",
  3071. .hcd_priv_size = sizeof(struct oxu_hcd),
  3072. /*
  3073. * Generic hardware linkage
  3074. */
  3075. .irq = oxu_irq,
  3076. .flags = HCD_MEMORY | HCD_USB2,
  3077. /*
  3078. * Basic lifecycle operations
  3079. */
  3080. .reset = oxu_reset,
  3081. .start = oxu_run,
  3082. .stop = oxu_stop,
  3083. .shutdown = oxu_shutdown,
  3084. /*
  3085. * Managing i/o requests and associated device resources
  3086. */
  3087. .urb_enqueue = oxu_urb_enqueue,
  3088. .urb_dequeue = oxu_urb_dequeue,
  3089. .endpoint_disable = oxu_endpoint_disable,
  3090. /*
  3091. * Scheduling support
  3092. */
  3093. .get_frame_number = oxu_get_frame,
  3094. /*
  3095. * Root hub support
  3096. */
  3097. .hub_status_data = oxu_hub_status_data,
  3098. .hub_control = oxu_hub_control,
  3099. .bus_suspend = oxu_bus_suspend,
  3100. .bus_resume = oxu_bus_resume,
  3101. };
  3102. /*
  3103. * Module stuff
  3104. */
  3105. static void oxu_configuration(struct platform_device *pdev, void *base)
  3106. {
  3107. u32 tmp;
  3108. /* Initialize top level registers.
  3109. * First write ever
  3110. */
  3111. oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
  3112. oxu_writel(base, OXU_SOFTRESET, OXU_SRESET);
  3113. oxu_writel(base, OXU_HOSTIFCONFIG, 0x0000037D);
  3114. tmp = oxu_readl(base, OXU_PIOBURSTREADCTRL);
  3115. oxu_writel(base, OXU_PIOBURSTREADCTRL, tmp | 0x0040);
  3116. oxu_writel(base, OXU_ASO, OXU_SPHPOEN | OXU_OVRCCURPUPDEN |
  3117. OXU_COMPARATOR | OXU_ASO_OP);
  3118. tmp = oxu_readl(base, OXU_CLKCTRL_SET);
  3119. oxu_writel(base, OXU_CLKCTRL_SET, tmp | OXU_SYSCLKEN | OXU_USBOTGCLKEN);
  3120. /* Clear all top interrupt enable */
  3121. oxu_writel(base, OXU_CHIPIRQEN_CLR, 0xff);
  3122. /* Clear all top interrupt status */
  3123. oxu_writel(base, OXU_CHIPIRQSTATUS, 0xff);
  3124. /* Enable all needed top interrupt except OTG SPH core */
  3125. oxu_writel(base, OXU_CHIPIRQEN_SET, OXU_USBSPHLPWUI | OXU_USBOTGLPWUI);
  3126. }
  3127. static int oxu_verify_id(struct platform_device *pdev, void *base)
  3128. {
  3129. u32 id;
  3130. static const char * const bo[] = {
  3131. "reserved",
  3132. "128-pin LQFP",
  3133. "84-pin TFBGA",
  3134. "reserved",
  3135. };
  3136. /* Read controller signature register to find a match */
  3137. id = oxu_readl(base, OXU_DEVICEID);
  3138. dev_info(&pdev->dev, "device ID %x\n", id);
  3139. if ((id & OXU_REV_MASK) != (OXU_REV_2100 << OXU_REV_SHIFT))
  3140. return -1;
  3141. dev_info(&pdev->dev, "found device %x %s (%04x:%04x)\n",
  3142. id >> OXU_REV_SHIFT,
  3143. bo[(id & OXU_BO_MASK) >> OXU_BO_SHIFT],
  3144. (id & OXU_MAJ_REV_MASK) >> OXU_MAJ_REV_SHIFT,
  3145. (id & OXU_MIN_REV_MASK) >> OXU_MIN_REV_SHIFT);
  3146. return 0;
  3147. }
  3148. static const struct hc_driver oxu_hc_driver;
  3149. static struct usb_hcd *oxu_create(struct platform_device *pdev,
  3150. unsigned long memstart, unsigned long memlen,
  3151. void *base, int irq, int otg)
  3152. {
  3153. struct device *dev = &pdev->dev;
  3154. struct usb_hcd *hcd;
  3155. struct oxu_hcd *oxu;
  3156. int ret;
  3157. /* Set endian mode and host mode */
  3158. oxu_writel(base + (otg ? OXU_OTG_CORE_OFFSET : OXU_SPH_CORE_OFFSET),
  3159. OXU_USBMODE,
  3160. OXU_CM_HOST_ONLY | OXU_ES_LITTLE | OXU_VBPS);
  3161. hcd = usb_create_hcd(&oxu_hc_driver, dev,
  3162. otg ? "oxu210hp_otg" : "oxu210hp_sph");
  3163. if (!hcd)
  3164. return ERR_PTR(-ENOMEM);
  3165. hcd->rsrc_start = memstart;
  3166. hcd->rsrc_len = memlen;
  3167. hcd->regs = base;
  3168. hcd->irq = irq;
  3169. hcd->state = HC_STATE_HALT;
  3170. oxu = hcd_to_oxu(hcd);
  3171. oxu->is_otg = otg;
  3172. ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
  3173. if (ret < 0)
  3174. return ERR_PTR(ret);
  3175. device_wakeup_enable(hcd->self.controller);
  3176. return hcd;
  3177. }
  3178. static int oxu_init(struct platform_device *pdev,
  3179. unsigned long memstart, unsigned long memlen,
  3180. void *base, int irq)
  3181. {
  3182. struct oxu_info *info = platform_get_drvdata(pdev);
  3183. struct usb_hcd *hcd;
  3184. int ret;
  3185. /* First time configuration at start up */
  3186. oxu_configuration(pdev, base);
  3187. ret = oxu_verify_id(pdev, base);
  3188. if (ret) {
  3189. dev_err(&pdev->dev, "no devices found!\n");
  3190. return -ENODEV;
  3191. }
  3192. /* Create the OTG controller */
  3193. hcd = oxu_create(pdev, memstart, memlen, base, irq, 1);
  3194. if (IS_ERR(hcd)) {
  3195. dev_err(&pdev->dev, "cannot create OTG controller!\n");
  3196. ret = PTR_ERR(hcd);
  3197. goto error_create_otg;
  3198. }
  3199. info->hcd[0] = hcd;
  3200. /* Create the SPH host controller */
  3201. hcd = oxu_create(pdev, memstart, memlen, base, irq, 0);
  3202. if (IS_ERR(hcd)) {
  3203. dev_err(&pdev->dev, "cannot create SPH controller!\n");
  3204. ret = PTR_ERR(hcd);
  3205. goto error_create_sph;
  3206. }
  3207. info->hcd[1] = hcd;
  3208. oxu_writel(base, OXU_CHIPIRQEN_SET,
  3209. oxu_readl(base, OXU_CHIPIRQEN_SET) | 3);
  3210. return 0;
  3211. error_create_sph:
  3212. usb_remove_hcd(info->hcd[0]);
  3213. usb_put_hcd(info->hcd[0]);
  3214. error_create_otg:
  3215. return ret;
  3216. }
  3217. static int oxu_drv_probe(struct platform_device *pdev)
  3218. {
  3219. struct resource *res;
  3220. void *base;
  3221. unsigned long memstart, memlen;
  3222. int irq, ret;
  3223. struct oxu_info *info;
  3224. if (usb_disabled())
  3225. return -ENODEV;
  3226. /*
  3227. * Get the platform resources
  3228. */
  3229. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  3230. if (!res) {
  3231. dev_err(&pdev->dev,
  3232. "no IRQ! Check %s setup!\n", dev_name(&pdev->dev));
  3233. return -ENODEV;
  3234. }
  3235. irq = res->start;
  3236. dev_dbg(&pdev->dev, "IRQ resource %d\n", irq);
  3237. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  3238. base = devm_ioremap_resource(&pdev->dev, res);
  3239. if (IS_ERR(base)) {
  3240. ret = PTR_ERR(base);
  3241. goto error;
  3242. }
  3243. memstart = res->start;
  3244. memlen = resource_size(res);
  3245. ret = irq_set_irq_type(irq, IRQF_TRIGGER_FALLING);
  3246. if (ret) {
  3247. dev_err(&pdev->dev, "error setting irq type\n");
  3248. ret = -EFAULT;
  3249. goto error;
  3250. }
  3251. /* Allocate a driver data struct to hold useful info for both
  3252. * SPH & OTG devices
  3253. */
  3254. info = devm_kzalloc(&pdev->dev, sizeof(struct oxu_info), GFP_KERNEL);
  3255. if (!info) {
  3256. dev_dbg(&pdev->dev, "error allocating memory\n");
  3257. ret = -EFAULT;
  3258. goto error;
  3259. }
  3260. platform_set_drvdata(pdev, info);
  3261. ret = oxu_init(pdev, memstart, memlen, base, irq);
  3262. if (ret < 0) {
  3263. dev_dbg(&pdev->dev, "cannot init USB devices\n");
  3264. goto error;
  3265. }
  3266. dev_info(&pdev->dev, "devices enabled and running\n");
  3267. platform_set_drvdata(pdev, info);
  3268. return 0;
  3269. error:
  3270. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), ret);
  3271. return ret;
  3272. }
  3273. static void oxu_remove(struct platform_device *pdev, struct usb_hcd *hcd)
  3274. {
  3275. usb_remove_hcd(hcd);
  3276. usb_put_hcd(hcd);
  3277. }
  3278. static int oxu_drv_remove(struct platform_device *pdev)
  3279. {
  3280. struct oxu_info *info = platform_get_drvdata(pdev);
  3281. oxu_remove(pdev, info->hcd[0]);
  3282. oxu_remove(pdev, info->hcd[1]);
  3283. return 0;
  3284. }
  3285. static void oxu_drv_shutdown(struct platform_device *pdev)
  3286. {
  3287. oxu_drv_remove(pdev);
  3288. }
  3289. #if 0
  3290. /* FIXME: TODO */
  3291. static int oxu_drv_suspend(struct device *dev)
  3292. {
  3293. struct platform_device *pdev = to_platform_device(dev);
  3294. struct usb_hcd *hcd = dev_get_drvdata(dev);
  3295. return 0;
  3296. }
  3297. static int oxu_drv_resume(struct device *dev)
  3298. {
  3299. struct platform_device *pdev = to_platform_device(dev);
  3300. struct usb_hcd *hcd = dev_get_drvdata(dev);
  3301. return 0;
  3302. }
  3303. #else
  3304. #define oxu_drv_suspend NULL
  3305. #define oxu_drv_resume NULL
  3306. #endif
  3307. static struct platform_driver oxu_driver = {
  3308. .probe = oxu_drv_probe,
  3309. .remove = oxu_drv_remove,
  3310. .shutdown = oxu_drv_shutdown,
  3311. .suspend = oxu_drv_suspend,
  3312. .resume = oxu_drv_resume,
  3313. .driver = {
  3314. .name = "oxu210hp-hcd",
  3315. .bus = &platform_bus_type
  3316. }
  3317. };
  3318. module_platform_driver(oxu_driver);
  3319. MODULE_DESCRIPTION("Oxford OXU210HP HCD driver - ver. " DRIVER_VERSION);
  3320. MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
  3321. MODULE_LICENSE("GPL");