Domovská stránka Prehľadávať Pomoc
Prihlásiť sa
lechercheur123
/
Aquaris-M10-4G
1
0
Fork 0
Súbory Issues 0 Pull requesty 0 Wiki
Strom: 30697f8dd8
Branche Tagy
Aquaris-M10-4G
/
include
/
dt-bindings
/
mmc
/
mt67xx-msdc.h

mt67xx-msdc.h 7.2 KB
História Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172 
  1. /*
    2. 

  2.  * Copyright (c) 2014 MediaTek Inc.
    3. 

  3.  * Author: Shi.Ma <shi.ma@mediatek.com>
    4. 

  4.  *
    5. 

  5.  * This program is free software; you can redistribute it and/or modify
    6. 

  6.  * it under the terms of the GNU General Public License version 2 as
    7. 

  7.  * published by the Free Software Foundation.
    8. 

  8.  *
    9. 

  9.  * This program is distributed in the hope that it will be useful,
    10. 

  10.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    11. 

  11.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    12. 

  12.  * GNU General Public License for more details.
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef _DT_BINDINGS_MMC_MT65XX_H
    16. 

  16. #define _DT_BINDINGS_MMC_MT65XX_H
    17. 

  17. 

  18. #define MSDC_EMMC	(0)
    19. 

  19. #define MSDC_SD		(1)
    20. 

  20. #define MSDC_SDIO	(2)
    21. 

  21. 

  22. #define MSDC_CD_HIGH        (1)
    23. 

  23. #define MSDC_CD_LOW         (0)
    24. 

  24. 

  25. /* each PLL have different gears for select
    26. 

  26.  * software can used mux interface from clock management module to select */
    27. 

  27. #define MSDC50_CLKSRC_26MHZ        (0)
    28. 

  28. #define MSDC50_CLKSRC_800MHZ         (1)
    29. 

  29. #define MSDC50_CLKSRC_400MHZ        (2)
    30. 

  30. #define MSDC50_CLKSRC_200MHZ        (3)
    31. 

  31. #define MSDC50_CLKSRC_182MHZ        (4)
    32. 

  32. #define MSDC50_CLKSRC_136MHZ         (5)
    33. 

  33. #define MSDC50_CLKSRC_156MHZ        (6)
    34. 

  34. #define MSDC50_CLKSRC_416MHZ        (7)
    35. 

  35. #define MSDC50_CLKSRC_48MHZ        (8)
    36. 

  36. #define MSDC50_CLKSRC_91MHZ       (9)
    37. 

  37. #define MSDC50_CLKSRC_624MHZ      (10)
    38. 

  38. 

  39. #define MSDC30_CLKSRC_26MHZ       (0)
    40. 

  40. #define MSDC30_CLKSRC_208MHZ       (1)
    41. 

  41. #define MSDC30_CLKSRC_200MHZ      (2)
    42. 

  42. #define MSDC30_CLKSRC_182MHZ       (3)
    43. 

  43. #define MSDC30_CLKSRC_136MHZ       (4)
    44. 

  44. #define MSDC30_CLKSRC_156MHZ       (5)
    45. 

  45. #define MSDC30_CLKSRC_48MHZ        (6)
    46. 

  46. #define MSDC30_CLKSRC_91MHZ      (7)
    47. 

  47. 

  48. /* #define HOST_MAX_MCLK       (200000000) */ /*(104000000) */
    49. 

  49. 

  50. #define MMC_VDD_165_195	0x00000080	/* VDD voltage 1.65 - 1.95 */
    51. 

  51. #define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
    52. 

  52. #define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
    53. 

  53. #define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
    54. 

  54. #define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
    55. 

  55. #define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
    56. 

  56. #define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
    57. 

  57. #define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
    58. 

  58. #define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
    59. 

  59. #define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
    60. 

  60. #define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
    61. 

  61. #define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
    62. 

  62. #define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
    63. 

  63. #define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
    64. 

  64. #define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
    65. 

  65. #define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
    66. 

  66. #define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */
    67. 

  67. 

  68. #define MSDC_SMPL_RISING    (0)
    69. 

  69. #define MSDC_SMPL_FALLING   (1)
    70. 

  70. 

  71. /*msdc register address*/
    72. 

  72. #define OFFSET_MSDC_PATCH_BIT0					0x000000B0
    73. 

  73. #define OFFSET_MSDC_PATCH_BIT1					0x000000B4
    74. 

  74. #define OFFSET_MSDC_IOCON								0x00000004
    75. 

  75. #define OFFSET_MSDC_PAD_TUNE0						0x000000F0
    76. 

  76. #define OFFSET_MSDC_DAT_RDDLY0					0x000000F8
    77. 

  77. #define OFFSET_EMMC50_PAD_DS_TUNE				0x00000188
    78. 

  78. 

  79. /*bit mask*/
    80. 

  80. /* MSDC_PATCH_BIT0 mask */
    81. 

  81. #define MSDC_PB0_RESV1           (0x1 << 0)
    82. 

  82. #define MSDC_PB0_EN_8BITSUP      (0x1 << 1)
    83. 

  83. #define MSDC_PB0_DIS_RECMDWR     (0x1 << 2)
    84. 

  84. #define MSDC_PB0_RESV2           (0x7 << 3)
    85. 

  85. #define MSDC_PB0_DESCUP          (0x1 << 6)
    86. 

  86. #define MSDC_PB0_INT_DAT_LATCH_CK_SEL (0x7 << 7)
    87. 

  87. #define MSDC_PB0_CKGEN_MSDC_DLY_SEL   (0x1F<<10)
    88. 

  88. #define MSDC_PB0_FIFORD_DIS      (0x1 << 15)
    89. 

  89. #define MSDC_PB0_BLKNUM_SEL      (0x1 << 16)
    90. 

  90. #define MSDC_PB0_SDIO_INTCSEL    (0x1 << 17)
    91. 

  91. #define MSDC_PB0_SDC_BSYDLY      (0xf << 18)
    92. 

  92. #define MSDC_PB0_SDC_WDOD        (0xf << 22)
    93. 

  93. #define MSDC_PB0_CMDIDRTSEL      (0x1 << 26)
    94. 

  94. #define MSDC_PB0_CMDFAILSEL      (0x1 << 27)
    95. 

  95. #define MSDC_PB0_SDIO_INTDLYSEL  (0x1 << 28)
    96. 

  96. #define MSDC_PB0_SPCPUSH         (0x1 << 29)
    97. 

  97. #define MSDC_PB0_DETWR_CRCTMO    (0x1 << 30)
    98. 

  98. #define MSDC_PB0_EN_DRVRSP       (0x1UL << 31)
    99. 

  99. 

  100. /* MSDC_PATCH_BIT1 mask */
    101. 

  101. #define MSDC_PB1_WRDAT_CRCS_TA_CNTR   (0x7 << 0)
    102. 

  102. #define MSDC_PB1_CMD_RSP_TA_CNTR      (0x7 << 3)
    103. 

  103. #define MSDC_PB1_GET_BUSY_MA     (0x1 << 6)
    104. 

  104. #define MSDC_PB1_GET_CRC_MA      (0x1 << 7)
    105. 

  105. #define MSDC_PB1_BIAS_TUNE_28NM  (0xf << 8)
    106. 

  106. #define MSDC_PB1_BIAS_EN18IO_28NM (0x1 << 12)
    107. 

  107. #define MSDC_PB1_BIAS_EXT_28NM   (0x1 << 13)
    108. 

  108. #define MSDC_PB1_RESV2           (0x1 << 14)
    109. 

  109. #define MSDC_PB1_RESET_GDMA      (0x1 << 15)
    110. 

  110. #define MSDC_PB1_SINGLEBURST     (0x1 << 16)
    111. 

  111. #define MSDC_PB1_FROCE_STOP      (0x1 << 17)
    112. 

  112. #define MSDC_PB1_DCM_DEV_SEL2    (0x3 << 18)
    113. 

  113. #define MSDC_PB1_DCM_DEV_SEL1    (0x1 << 20)
    114. 

  114. #define MSDC_PB1_DCM_EN          (0x1 << 21)
    115. 

  115. #define MSDC_PB1_AXI_WRAP_CKEN   (0x1 << 22)
    116. 

  116. #define MSDC_PB1_AHBCKEN         (0x1 << 23)
    117. 

  117. #define MSDC_PB1_CKSPCEN         (0x1 << 24)
    118. 

  118. #define MSDC_PB1_CKPSCEN         (0x1 << 25)
    119. 

  119. #define MSDC_PB1_CKVOLDETEN      (0x1 << 26)
    120. 

  120. #define MSDC_PB1_CKACMDEN        (0x1 << 27)
    121. 

  121. #define MSDC_PB1_CKSDEN          (0x1 << 28)
    122. 

  122. #define MSDC_PB1_CKWCTLEN        (0x1 << 29)
    123. 

  123. #define MSDC_PB1_CKRCTLEN        (0x1 << 30)
    124. 

  124. #define MSDC_PB1_CKSHBFFEN       (0x1UL << 31)
    125. 

  125. 

  126. /* MSDC_IOCON mask */
    127. 

  127. #define MSDC_IOCON_SDR104CKS    (0x1  << 0)     /* RW */
    128. 

  128. #define MSDC_IOCON_RSPL         (0x1  << 1)     /* RW */
    129. 

  129. #define MSDC_IOCON_R_D_SMPL     (0x1  << 2)     /* RW */
    130. 

  130. #define MSDC_IOCON_DDLSEL       (0x1  << 3)     /* RW */
    131. 

  131. #define MSDC_IOCON_DDR50CKD     (0x1  << 4)     /* RW */
    132. 

  132. #define MSDC_IOCON_R_D_SMPL_SEL (0x1  << 5)     /* RW */
    133. 

  133. #define MSDC_IOCON_W_D_SMPL     (0x1  << 8)     /* RW */
    134. 

  134. #define MSDC_IOCON_W_D_SMPL_SEL (0x1  << 9)     /* RW */
    135. 

  135. #define MSDC_IOCON_W_D0SPL      (0x1  << 10)    /* RW */
    136. 

  136. #define MSDC_IOCON_W_D1SPL      (0x1  << 11)    /* RW */
    137. 

  137. #define MSDC_IOCON_W_D2SPL      (0x1  << 12)    /* RW */
    138. 

  138. #define MSDC_IOCON_W_D3SPL      (0x1  << 13)    /* RW */
    139. 

  139. #define MSDC_IOCON_R_D0SPL      (0x1  << 16)    /* RW */
    140. 

  140. #define MSDC_IOCON_R_D1SPL      (0x1  << 17)    /* RW */
    141. 

  141. #define MSDC_IOCON_R_D2SPL      (0x1  << 18)    /* RW */
    142. 

  142. #define MSDC_IOCON_R_D3SPL      (0x1  << 19)    /* RW */
    143. 

  143. #define MSDC_IOCON_R_D4SPL      (0x1  << 20)    /* RW */
    144. 

  144. #define MSDC_IOCON_R_D5SPL      (0x1  << 21)    /* RW */
    145. 

  145. #define MSDC_IOCON_R_D6SPL      (0x1  << 22)    /* RW */
    146. 

  146. #define MSDC_IOCON_R_D7SPL      (0x1  << 23)    /* RW */
    147. 

  147. 

  148. /* MSDC_PAD_TUNE0 mask */
    149. 

  149. #define MSDC_PAD_TUNE0_DATWRDLY      (0x1F <<  0)     /* RW */
    150. 

  150. #define MSDC_PAD_TUNE0_DELAYEN       (0x1  <<  7)     /* RW */
    151. 

  151. #define MSDC_PAD_TUNE0_DATRRDLY      (0x1F <<  8)     /* RW */
    152. 

  152. #define MSDC_PAD_TUNE0_DATRRDLYSEL   (0x1  << 13)     /* RW */
    153. 

  153. #define MSDC_PAD_TUNE0_RXDLYSEL      (0x1  << 15)     /* RW */
    154. 

  154. #define MSDC_PAD_TUNE0_CMDRDLY       (0x1F << 16)     /* RW */
    155. 

  155. #define MSDC_PAD_TUNE0_CMDRRDLYSEL   (0x1  << 21)     /* RW */
    156. 

  156. #define MSDC_PAD_TUNE0_CMDRRDLY      (0x1FUL << 22)   /* RW */
    157. 

  157. #define MSDC_PAD_TUNE0_CLKTXDLY      (0x1FUL << 27)   /* RW */
    158. 

  158. 

  159. /* MSDC_DAT_RDDLY0/1/2/3 mask */
    160. 

  160. #define MSDC_DAT_RDDLY0_D3      (0x1F << 0)     /* RW */
    161. 

  161. #define MSDC_DAT_RDDLY0_D2      (0x1F << 8)     /* RW */
    162. 

  162. #define MSDC_DAT_RDDLY0_D1      (0x1F << 16)    /* RW */
    163. 

  163. #define MSDC_DAT_RDDLY0_D0      (0x1FUL << 24)  /* RW */
    164. 

  164. 

  165. /* EMMC50_PAD_DS_TUNE mask */
    166. 

  166. #define MSDC_EMMC50_PAD_DS_TUNE_DLYSEL  (0x1 << 0)
    167. 

  167. #define MSDC_EMMC50_PAD_DS_TUNE_DLY2SEL (0x1 << 1)
    168. 

  168. #define MSDC_EMMC50_PAD_DS_TUNE_DLY1    (0x1f << 2)
    169. 

  169. #define MSDC_EMMC50_PAD_DS_TUNE_DLY2    (0x1f << 7)
    170. 

  170. #define MSDC_EMMC50_PAD_DS_TUNE_DLY3    (0x1F << 12)
    171. 

  171. 

  172. #endif /* _DT_BINDINGS_MMC_MT65XX_H */
    173.