cq.h 4.8 KB

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  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #ifndef MLX5_CORE_CQ_H
  33. #define MLX5_CORE_CQ_H
  34. #include <rdma/ib_verbs.h>
  35. #include <linux/mlx5/driver.h>
  36. struct mlx5_core_cq {
  37. u32 cqn;
  38. int cqe_sz;
  39. __be32 *set_ci_db;
  40. __be32 *arm_db;
  41. atomic_t refcount;
  42. struct completion free;
  43. unsigned vector;
  44. int irqn;
  45. void (*comp) (struct mlx5_core_cq *);
  46. void (*event) (struct mlx5_core_cq *, enum mlx5_event);
  47. struct mlx5_uar *uar;
  48. u32 cons_index;
  49. unsigned arm_sn;
  50. struct mlx5_rsc_debug *dbg;
  51. int pid;
  52. };
  53. enum {
  54. MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
  55. MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
  56. MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
  57. MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
  58. MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06,
  59. MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
  60. MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
  61. MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
  62. MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
  63. MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
  64. MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
  65. MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
  66. MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
  67. };
  68. enum {
  69. MLX5_CQE_OWNER_MASK = 1,
  70. MLX5_CQE_REQ = 0,
  71. MLX5_CQE_RESP_WR_IMM = 1,
  72. MLX5_CQE_RESP_SEND = 2,
  73. MLX5_CQE_RESP_SEND_IMM = 3,
  74. MLX5_CQE_RESP_SEND_INV = 4,
  75. MLX5_CQE_RESIZE_CQ = 5,
  76. MLX5_CQE_SIG_ERR = 12,
  77. MLX5_CQE_REQ_ERR = 13,
  78. MLX5_CQE_RESP_ERR = 14,
  79. MLX5_CQE_INVALID = 15,
  80. };
  81. enum {
  82. MLX5_CQ_MODIFY_PERIOD = 1 << 0,
  83. MLX5_CQ_MODIFY_COUNT = 1 << 1,
  84. MLX5_CQ_MODIFY_OVERRUN = 1 << 2,
  85. };
  86. enum {
  87. MLX5_CQ_OPMOD_RESIZE = 1,
  88. MLX5_MODIFY_CQ_MASK_LOG_SIZE = 1 << 0,
  89. MLX5_MODIFY_CQ_MASK_PG_OFFSET = 1 << 1,
  90. MLX5_MODIFY_CQ_MASK_PG_SIZE = 1 << 2,
  91. };
  92. struct mlx5_cq_modify_params {
  93. int type;
  94. union {
  95. struct {
  96. u32 page_offset;
  97. u8 log_cq_size;
  98. } resize;
  99. struct {
  100. } moder;
  101. struct {
  102. } mapping;
  103. } params;
  104. };
  105. enum {
  106. CQE_SIZE_64 = 0,
  107. CQE_SIZE_128 = 1,
  108. };
  109. static inline int cqe_sz_to_mlx_sz(u8 size)
  110. {
  111. return size == 64 ? CQE_SIZE_64 : CQE_SIZE_128;
  112. }
  113. static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq)
  114. {
  115. *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
  116. }
  117. enum {
  118. MLX5_CQ_DB_REQ_NOT_SOL = 1 << 24,
  119. MLX5_CQ_DB_REQ_NOT = 0 << 24
  120. };
  121. static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
  122. void __iomem *uar_page,
  123. spinlock_t *doorbell_lock)
  124. {
  125. __be32 doorbell[2];
  126. u32 sn;
  127. u32 ci;
  128. sn = cq->arm_sn & 3;
  129. ci = cq->cons_index & 0xffffff;
  130. *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
  131. /* Make sure that the doorbell record in host memory is
  132. * written before ringing the doorbell via PCI MMIO.
  133. */
  134. wmb();
  135. doorbell[0] = cpu_to_be32(sn << 28 | cmd | ci);
  136. doorbell[1] = cpu_to_be32(cq->cqn);
  137. mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, doorbell_lock);
  138. }
  139. int mlx5_init_cq_table(struct mlx5_core_dev *dev);
  140. void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev);
  141. int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
  142. struct mlx5_create_cq_mbox_in *in, int inlen);
  143. int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
  144. int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
  145. struct mlx5_query_cq_mbox_out *out);
  146. int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
  147. struct mlx5_modify_cq_mbox_in *in, int in_sz);
  148. int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
  149. void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
  150. #endif /* MLX5_CORE_CQ_H */