max98926.c 33 KB

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  1. /*
  2. * max98926.c -- ALSA SoC Stereo max98926 driver
  3. * Copyright 2013-15 Maxim Integrated Products
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/i2c.h>
  10. #include <linux/module.h>
  11. #include <linux/regmap.h>
  12. #include <linux/slab.h>
  13. #include <linux/cdev.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <sound/soc.h>
  19. #include <sound/tlv.h>
  20. #include "max98926.h"
  21. #define MAX98926_I2C_Channel (0)
  22. static struct i2c_client *new_client;
  23. static ssize_t max_i2c_write(const char *data, size_t count);
  24. static int max_i2c_master_send(const struct i2c_client *client, const char *buf, int count);
  25. static int max98926_WriteReg(u16 a_u2Addr, u16 a_u2Data);
  26. static int max98926_ReadReg(u16 a_u2Addr, unsigned short *a_pu2Result);
  27. static int max98926_regulator_config(struct i2c_client *i2c, bool pullup, bool on);
  28. static void max98926_set_sense_data(struct max98926_priv *max98926);
  29. static const char *const dai_text[] = {
  30. "Left", "Right", "LeftRight", "LeftRightDiv2",
  31. };
  32. static const char *const dai_input_text[] = {
  33. "Pcm", "Analog",
  34. };
  35. static const char *const pdm_1_text[] = {
  36. "Current", "Voltage",
  37. };
  38. static const char *const pdm_0_text[] = {
  39. "Current", "Voltage",
  40. };
  41. static const char *const max98926_boost_voltage_text[] = {
  42. "8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
  43. "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
  44. };
  45. static SOC_ENUM_SINGLE_DECL(max98926_boost_voltage,
  46. max98926_CONFIGURATION, M98926_BST_VOUT_SHIFT, max98926_boost_voltage_text);
  47. static const char *const hpf_text[] = {
  48. "Disable", "DC Block", "100Hz", "200Hz", "400Hz", "800Hz",
  49. };
  50. static int max98926_spk_zcd_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  51. {
  52. return 0;
  53. }
  54. static int max98926_spk_zcd_put(struct snd_kcontrol *kcontrol,
  55. struct snd_ctl_elem_value *ucontrol)
  56. {
  57. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  58. struct snd_soc_component *codec = component->codec;
  59. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  60. int ret, reg;
  61. ret = snd_soc_read(codec,
  62. max98926_DAI_CLK_DIV_N_LSBS);
  63. pr_err("%s 0x1f read 0x%x\n", __func__, ret);
  64. return 1;
  65. }
  66. static int reg_set_optimum_mode_check(struct regulator *reg, int load_uA)
  67. {
  68. return (regulator_count_voltages(reg) > 0) ?
  69. regulator_set_optimum_mode(reg, load_uA) : 0;
  70. }
  71. static int max98926_regulator_config(struct i2c_client *i2c, bool pullup, bool on)
  72. {
  73. struct regulator *max98926_vcc_i2c;
  74. int rc;
  75. #define VCC_I2C_MIN_UV 1800000
  76. #define VCC_I2C_MAX_UV 1800000
  77. #define I2C_LOAD_UA 300000
  78. pr_info("%s: enter\n", __func__);
  79. if (pullup) {
  80. pr_info("%s: I2C PULL UP.\n", __func__);
  81. max98926_vcc_i2c = regulator_get(&i2c->dev, "vcc_i2c");
  82. if (IS_ERR(max98926_vcc_i2c)) {
  83. rc = PTR_ERR(max98926_vcc_i2c);
  84. pr_info("%s: regulator get failed rc=%d\n", __func__, rc);
  85. goto error_get_vtg_i2c;
  86. }
  87. if (regulator_count_voltages(max98926_vcc_i2c) > 0) {
  88. rc = regulator_set_voltage(max98926_vcc_i2c,
  89. VCC_I2C_MIN_UV, VCC_I2C_MAX_UV);
  90. if (rc) {
  91. pr_info("%s: regulator set_vtg failed rc=%d\n", __func__, rc);
  92. goto error_set_vtg_i2c;
  93. }
  94. }
  95. rc = reg_set_optimum_mode_check(max98926_vcc_i2c, I2C_LOAD_UA);
  96. if (rc < 0) {
  97. pr_info("%s: regulator vcc_i2c set_opt failed rc=%d\n", __func__, rc);
  98. goto error_reg_opt_i2c;
  99. }
  100. rc = regulator_enable(max98926_vcc_i2c);
  101. if (rc) {
  102. pr_info("%s: regulator vcc_i2c enable failed rc=%d\n", __func__, rc);
  103. goto error_reg_en_vcc_i2c;
  104. }
  105. }
  106. return 0;
  107. error_set_vtg_i2c:
  108. regulator_put(max98926_vcc_i2c);
  109. error_get_vtg_i2c:
  110. if (regulator_count_voltages(max98926_vcc_i2c) > 0)
  111. regulator_set_voltage(max98926_vcc_i2c, 0, VCC_I2C_MAX_UV);
  112. error_reg_en_vcc_i2c:
  113. if (pullup)
  114. reg_set_optimum_mode_check(max98926_vcc_i2c, 0);
  115. error_reg_opt_i2c:
  116. regulator_disable(max98926_vcc_i2c);
  117. return rc;
  118. }
  119. static struct reg_default max98926_reg[] = {
  120. { 0x0B, 0x00 }, /* IRQ Enable0 */
  121. { 0x0C, 0x00 }, /* IRQ Enable1 */
  122. { 0x0D, 0x00 }, /* IRQ Enable2 */
  123. { 0x0E, 0x00 }, /* IRQ Clear0 */
  124. { 0x0F, 0x00 }, /* IRQ Clear1 */
  125. { 0x10, 0x00 }, /* IRQ Clear2 */
  126. { 0x11, 0xC0 }, /* Map0 */
  127. { 0x12, 0x00 }, /* Map1 */
  128. { 0x13, 0x00 }, /* Map2 */
  129. { 0x14, 0xF0 }, /* Map3 */
  130. { 0x15, 0x00 }, /* Map4 */
  131. { 0x16, 0xAB }, /* Map5 */
  132. { 0x17, 0x89 }, /* Map6 */
  133. { 0x18, 0x00 }, /* Map7 */
  134. { 0x19, 0x00 }, /* Map8 */
  135. { 0x1A, 0x06 }, /* DAI Clock Mode 1 */
  136. { 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
  137. { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
  138. { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
  139. { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
  140. { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
  141. { 0x20, 0x50 }, /* Format */
  142. { 0x21, 0x00 }, /* TDM Slot Select */
  143. { 0x22, 0x00 }, /* DOUT Configuration VMON */
  144. { 0x23, 0x00 }, /* DOUT Configuration IMON */
  145. { 0x24, 0x00 }, /* DOUT Configuration VBAT */
  146. { 0x25, 0x00 }, /* DOUT Configuration VBST */
  147. { 0x26, 0x00 }, /* DOUT Configuration FLAG */
  148. { 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
  149. { 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
  150. { 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
  151. { 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
  152. { 0x2B, 0x02 }, /* DOUT Drive Strength */
  153. { 0x2C, 0x90 }, /* Filters */
  154. { 0x2D, 0x00 }, /* Gain */
  155. { 0x2E, 0x02 }, /* Gain Ramping */
  156. { 0x2F, 0x00 }, /* Speaker Amplifier */
  157. { 0x30, 0x0A }, /* Threshold */
  158. { 0x31, 0x00 }, /* ALC Attack */
  159. { 0x32, 0x80 }, /* ALC Atten and Release */
  160. { 0x33, 0x00 }, /* ALC Infinite Hold Release */
  161. { 0x34, 0x92 }, /* ALC Configuration */
  162. { 0x35, 0x01 }, /* Boost Converter */
  163. { 0x36, 0x00 }, /* Block Enable */
  164. { 0x37, 0x00 }, /* Configuration */
  165. { 0x38, 0x00 }, /* Global Enable */
  166. { 0x3A, 0x00 }, /* Boost Limiter */
  167. };
  168. static const struct soc_enum max98926_dai_enum =
  169. SOC_ENUM_SINGLE(max98926_GAIN, 5, ARRAY_SIZE(dai_text), dai_text);
  170. static const struct soc_enum max98926_dai_input_enum =
  171. SOC_ENUM_SINGLE(max98926_SPK_AMP, 1, ARRAY_SIZE(dai_input_text), dai_input_text);
  172. static const struct soc_enum max98926_pdm_1_enum =
  173. SOC_ENUM_SINGLE(max98926_DAI_CLK_DIV_N_LSBS, 4, ARRAY_SIZE(pdm_1_text), pdm_1_text);
  174. static const struct soc_enum max98926_pdm_0_enum =
  175. SOC_ENUM_SINGLE(max98926_DAI_CLK_DIV_N_LSBS, 0, ARRAY_SIZE(pdm_0_text), pdm_0_text);
  176. static const struct soc_enum max98926_hpf_enum =
  177. SOC_ENUM_SINGLE(max98926_FILTERS, 0, ARRAY_SIZE(hpf_text), hpf_text);
  178. static const struct snd_kcontrol_new max98926_hpf_sel_mux =
  179. SOC_DAPM_ENUM("Rc Filter MUX Mux", max98926_hpf_enum);
  180. static const struct snd_kcontrol_new max98926_dai_sel_mux =
  181. SOC_DAPM_ENUM("DAI IN MUX Mux", max98926_dai_enum);
  182. static const struct snd_kcontrol_new max98926_input_sel_mux =
  183. SOC_DAPM_ENUM("INPUT SEL MUX Mux", max98926_dai_input_enum);
  184. static const struct snd_kcontrol_new max98926_pdm_1_sel_mux =
  185. SOC_DAPM_ENUM("PDM CHANNEL_1 MUX Mux", max98926_pdm_1_enum);
  186. static const struct snd_kcontrol_new max98926_pdm_0_sel_mux =
  187. SOC_DAPM_ENUM("PDM CHANNEL_0 MUX Mux", max98926_pdm_0_enum);
  188. static int max98926_get_switch_mixer(struct snd_kcontrol *kcontrol,
  189. struct snd_ctl_elem_value *ucontrol)
  190. {
  191. return 0;
  192. }
  193. static int max98926_put_switch_mixer(struct snd_kcontrol *kcontrol,
  194. struct snd_ctl_elem_value *ucontrol)
  195. {
  196. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  197. struct snd_soc_component *codec = component->codec;
  198. struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
  199. if (ucontrol->value.integer.value[0])
  200. snd_soc_dapm_mixer_update_power(widget, kcontrol, 1, NULL);
  201. else
  202. snd_soc_dapm_mixer_update_power(widget, kcontrol, 0 , NULL);
  203. return 1;
  204. }
  205. static const struct snd_kcontrol_new max98926_pdm_path_1_control =
  206. SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, 0, 1, 0, max98926_get_switch_mixer, max98926_put_switch_mixer);
  207. static const struct snd_kcontrol_new max98926_pdm_path_0_control =
  208. SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, 0, 1, 0, max98926_get_switch_mixer, max98926_put_switch_mixer);
  209. static int max98926_dac_event(struct snd_soc_dapm_widget *w,
  210. struct snd_kcontrol *kcontrol, int event)
  211. {
  212. struct snd_soc_codec *codec = w->codec;
  213. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  214. switch (event) {
  215. case SND_SOC_DAPM_PRE_PMU:
  216. snd_soc_update_bits(codec,
  217. max98926_BLOCK_ENABLE,
  218. M98926_BST_EN_MASK |
  219. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  220. M98926_BST_EN_MASK |
  221. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK);
  222. break;
  223. case SND_SOC_DAPM_POST_PMD:
  224. snd_soc_update_bits(codec,
  225. max98926_BLOCK_ENABLE, M98926_BST_EN_MASK |
  226. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK, 0);
  227. break;
  228. default:
  229. return 0;
  230. }
  231. return 0;
  232. }
  233. static int pdm_enable_channel_ev(struct snd_soc_dapm_widget *w,
  234. struct snd_kcontrol *kcontrol, int event)
  235. {
  236. struct snd_soc_codec *codec = w->codec;
  237. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  238. int ret, reg;
  239. ret = snd_soc_read(codec,
  240. max98926_DAI_CLK_DIV_N_LSBS);
  241. pr_err("%s 0x1f read 0x%x\n", __func__, ret);
  242. switch (event) {
  243. case SND_SOC_DAPM_PRE_PMU:
  244. /* enable current measurement */
  245. snd_soc_update_bits(codec,
  246. max98926_DAI_CLK_DIV_N_LSBS,
  247. max98926_PDM_CURRENT_MASK, max98926_PDM_CURRENT_MASK);
  248. /* enable voltage measurement */
  249. snd_soc_update_bits(codec,
  250. max98926_DAI_CLK_DIV_N_LSBS,
  251. max98926_PDM_VOLTAGE_MASK, max98926_PDM_VOLTAGE_MASK);
  252. break;
  253. case SND_SOC_DAPM_POST_PMD:
  254. snd_soc_update_bits(codec,
  255. max98926_DAI_CLK_DIV_N_LSBS,
  256. max98926_PDM_CURRENT_MASK, 0);
  257. snd_soc_update_bits(codec,
  258. max98926_DAI_CLK_DIV_N_LSBS,
  259. max98926_PDM_VOLTAGE_MASK, 0);
  260. break;
  261. }
  262. ret = snd_soc_read(codec,
  263. max98926_DAI_CLK_DIV_N_LSBS);
  264. pr_err("%s 0x1f read 0x%x\n", __func__, ret);
  265. return 0;
  266. }
  267. static const struct snd_soc_dapm_widget max98926_dapm_widgets[] = {
  268. SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
  269. SND_SOC_DAPM_AIF_OUT("DAI_IN", "HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
  270. SND_SOC_DAPM_MUX("DAI IN MUX", SND_SOC_NOPM, 0, 0,
  271. &max98926_dai_sel_mux),
  272. SND_SOC_DAPM_MUX("INPUT SEL MUX", SND_SOC_NOPM, 0, 0,
  273. &max98926_input_sel_mux),
  274. SND_SOC_DAPM_MUX_E("PDM CHANNEL_1 MUX", max98926_DAI_CLK_DIV_N_LSBS, 6, 0,
  275. &max98926_pdm_1_sel_mux, pdm_enable_channel_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  276. SND_SOC_DAPM_MUX_E("PDM CHANNEL_0 MUX", max98926_DAI_CLK_DIV_N_LSBS, 2, 0,
  277. &max98926_pdm_0_sel_mux, pdm_enable_channel_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  278. SND_SOC_DAPM_MUX("Rc Filter MUX", SND_SOC_NOPM, 0, 0,
  279. &max98926_hpf_sel_mux),
  280. SND_SOC_DAPM_DAC_E("Amp Enable", NULL, max98926_BLOCK_ENABLE,
  281. M98926_SPK_EN_SHIFT, 0, max98926_dac_event,
  282. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  283. SND_SOC_DAPM_SUPPLY("Global Enable", max98926_GLOBAL_ENABLE,
  284. M98926_EN_SHIFT, 0, NULL, 0),
  285. SND_SOC_DAPM_OUTPUT("BE_OUT"),
  286. SND_SOC_DAPM_INPUT("Speaker_Pdm"),
  287. };
  288. static const struct snd_soc_dapm_route max98926_audio_map[] = {
  289. {"DAI IN MUX", "Left", "DAI_OUT"},
  290. {"DAI IN MUX", "Right", "DAI_OUT"},
  291. {"DAI IN MUX", "LeftRight", "DAI_OUT"},
  292. {"DAI IN MUX", "LeftRightDiv2", "DAI_OUT"},
  293. {"Rc Filter MUX", "Disable", "DAI IN MUX"},
  294. {"Rc Filter MUX", "DC Block", "DAI IN MUX"},
  295. {"Rc Filter MUX", "100Hz", "DAI IN MUX"},
  296. {"Rc Filter MUX", "200Hz", "DAI IN MUX"},
  297. {"Rc Filter MUX", "400Hz", "DAI IN MUX"},
  298. {"Rc Filter MUX", "800Hz", "DAI IN MUX"},
  299. {"Amp Enable", NULL, "Rc Filter MUX"},
  300. {"Amp Enable", NULL, "Global Enable"},
  301. {"BE_OUT", NULL, "Amp Enable"},
  302. {"INPUT SEL MUX", "Pcm", "DAI_OUT"},
  303. {"INPUT SEL MUX", "Analog", "DAI_OUT"},
  304. {"Amp Enable", NULL, "INPUT SEL MUX"},
  305. #if 0
  306. {"PDM CHANNEL_1 MUX", "Voltage", "DAI_IN"},
  307. {"PDM CHANNEL_1 MUX", "Current", "DAI_IN"},
  308. {"PDM CHANNEL_0 MUX", "Voltage", "DAI_IN"},
  309. {"PDM CHANNEL_0 MUX", "Current", "DAI_IN"},
  310. {"PDM PATH CH_1", "Switch", "PDM CHANNEL_1 MUX"},
  311. {"PDM PATH CH_0", "Switch", "PDM CHANNEL_0 MUX"},
  312. {"Speaker_Pdm", NULL, "PDM PATH CH_1"},
  313. {"Speaker_Pdm", NULL, "PDM PATH CH_0"},
  314. #endif
  315. #if 1
  316. {"PDM CHANNEL_1 MUX", "Voltage", "DAI_OUT"},
  317. {"PDM CHANNEL_1 MUX", "Current", "DAI_OUT"},
  318. {"PDM CHANNEL_0 MUX", "Voltage", "DAI_OUT"},
  319. {"PDM CHANNEL_0 MUX", "Current", "DAI_OUT"},
  320. {"PDM PATH CH_1", "Switch", "PDM CHANNEL_1 MUX"},
  321. {"PDM PATH CH_0", "Switch", "PDM CHANNEL_0 MUX"},
  322. {"Amp Enable", NULL, "PDM PATH CH_1"},
  323. {"Amp Enable", NULL, "PDM PATH CH_0"},
  324. #endif
  325. };
  326. static bool max98926_volatile_register(struct device *dev, unsigned int reg)
  327. {
  328. switch (reg) {
  329. case max98926_VBAT_DATA:
  330. case max98926_VBST_DATA:
  331. case max98926_LIVE_STATUS0:
  332. case max98926_LIVE_STATUS1:
  333. case max98926_LIVE_STATUS2:
  334. case max98926_STATE0:
  335. case max98926_STATE1:
  336. case max98926_STATE2:
  337. case max98926_FLAG0:
  338. case max98926_FLAG1:
  339. case max98926_FLAG2:
  340. case max98926_REV_VERSION:
  341. case max98926_DAI_CLK_DIV_N_LSBS:
  342. return true;
  343. default:
  344. return false;
  345. }
  346. }
  347. static bool max98926_readable_register(struct device *dev, unsigned int reg)
  348. {
  349. switch (reg) {
  350. case max98926_IRQ_CLEAR0:
  351. case max98926_IRQ_CLEAR1:
  352. case max98926_IRQ_CLEAR2:
  353. case max98926_ALC_HOLD_RLS:
  354. return false;
  355. default:
  356. return true;
  357. }
  358. }
  359. DECLARE_TLV_DB_SCALE(max98926_spk_tlv, -600, 100, 0);
  360. static int max98926_reg_put(struct snd_kcontrol *kcontrol,
  361. struct snd_ctl_elem_value *ucontrol, unsigned int reg,
  362. unsigned int mask, unsigned int shift)
  363. {
  364. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  365. struct snd_soc_component *codec = component->codec;
  366. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  367. unsigned int sel = ucontrol->value.integer.value[0];
  368. pr_err("%s codec = %p\n", __func__, codec);
  369. snd_soc_update_bits(codec, reg, mask, sel << shift);
  370. pr_err("%s: register 0x%02X, value 0x%02X\n",
  371. __func__, reg, sel);
  372. return 0;
  373. }
  374. static int speaker_enable;
  375. static int max98926_spk_enable_get(struct snd_kcontrol *kcontrol,
  376. struct snd_ctl_elem_value *ucontrol)
  377. {
  378. pr_err("%s , speaker_enable = %d\n", __func__, speaker_enable);
  379. ucontrol->value.integer.value[0] = speaker_enable;
  380. return 0;
  381. }
  382. static int max98926_spk_enable_put(struct snd_kcontrol *kcontrol,
  383. struct snd_ctl_elem_value *ucontrol)
  384. {
  385. struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
  386. struct snd_soc_component *codec = component->codec;
  387. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  388. pr_err("%s , codec = %p\n", __func__, codec);
  389. if (ucontrol->value.integer.value[0] == 1) {
  390. snd_soc_update_bits(codec, max98926_BLOCK_ENABLE,
  391. (M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  392. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  393. M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  394. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK),
  395. (M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  396. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  397. M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  398. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK)
  399. );
  400. snd_soc_update_bits(codec, max98926_BLOCK_ENABLE,
  401. (M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  402. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  403. M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  404. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK),
  405. (M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  406. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  407. M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  408. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK)
  409. );
  410. snd_soc_update_bits(codec, max98926_GLOBAL_ENABLE,
  411. M98926_EN_MASK, M98926_EN_MASK);
  412. max98926_set_sense_data(max98926);
  413. } else if (ucontrol->value.integer.value[0] == 0) {
  414. snd_soc_update_bits(codec, max98926_BLOCK_ENABLE
  415. , M98926_SPK_EN_MASK | M98926_BST_EN_MASK |
  416. M98926_ADC_IMON_EN_MASK | M98926_ADC_VMON_EN_MASK,
  417. 0);
  418. snd_soc_update_bits(codec, max98926_GLOBAL_ENABLE,
  419. M98926_EN_MASK, 0);
  420. }
  421. speaker_enable = ucontrol->value.integer.value[0];
  422. return 1;
  423. }
  424. static const char *const spk_enable_text[] = {"Off", "On"};
  425. static const struct soc_enum max98926_global_enum[] = {
  426. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(spk_enable_text), spk_enable_text),
  427. };
  428. static const struct snd_kcontrol_new max98926_snd_controls[] = {
  429. SOC_SINGLE_TLV("Speaker Volume", max98926_GAIN,
  430. M98926_SPK_GAIN_SHIFT, (1 << M98926_SPK_GAIN_WIDTH) - 1, 0,
  431. max98926_spk_tlv),
  432. SOC_SINGLE("Ramp Switch", max98926_GAIN_RAMPING,
  433. M98926_SPK_RMP_EN_SHIFT, 1, 0),
  434. SOC_SINGLE("ZCD Switch", max98926_GAIN_RAMPING,
  435. M98926_SPK_ZCD_EN_SHIFT, 1, 0),
  436. SOC_SINGLE("ALC Switch", max98926_THRESHOLD,
  437. M98926_ALC_EN_SHIFT, 1, 0),
  438. SOC_SINGLE("ALC Threshold", max98926_THRESHOLD, M98926_ALC_TH_SHIFT,
  439. (1 << M98926_ALC_TH_WIDTH) - 1, 0),
  440. SOC_ENUM("Boost Output Voltage", max98926_boost_voltage),
  441. SOC_SINGLE_EXT("Speaker ZCD", 0, 0, 1, 0,
  442. max98926_spk_zcd_get, max98926_spk_zcd_put),
  443. SOC_ENUM_EXT("Spk_Enable", max98926_global_enum[0], max98926_spk_enable_get, max98926_spk_enable_put),
  444. };
  445. /* codec sample rate and n/m dividers parameter table */
  446. static const struct {
  447. int rate;
  448. int sr;
  449. int divisors[3][2];
  450. } rate_table[] = {
  451. {
  452. .rate = 8000,
  453. .sr = 0,
  454. .divisors = { {1, 375}, {5, 1764}, {1, 384} }
  455. },
  456. {
  457. .rate = 11025,
  458. .sr = 1,
  459. .divisors = { {147, 40000}, {1, 256}, {147, 40960} }
  460. },
  461. {
  462. .rate = 12000,
  463. .sr = 2,
  464. .divisors = { {1, 250}, {5, 1176}, {1, 256} }
  465. },
  466. {
  467. .rate = 16000,
  468. .sr = 3,
  469. .divisors = { {2, 375}, {5, 882}, {1, 192} }
  470. },
  471. {
  472. .rate = 22050,
  473. .sr = 4,
  474. .divisors = { {147, 20000}, {1, 128}, {147, 20480} }
  475. },
  476. {
  477. .rate = 24000,
  478. .sr = 5,
  479. .divisors = { {1, 125}, {5, 588}, {1, 128} }
  480. },
  481. {
  482. .rate = 32000,
  483. .sr = 6,
  484. .divisors = { {4, 375}, {5, 441}, {1, 96} }
  485. },
  486. {
  487. .rate = 44100,
  488. .sr = 7,
  489. .divisors = { {147, 10000}, {1, 64}, {147, 10240} }
  490. },
  491. {
  492. .rate = 48000,
  493. .sr = 8,
  494. .divisors = { {2, 125}, {5, 294}, {1, 64} }
  495. },
  496. };
  497. static inline int max98926_rate_value(struct snd_soc_codec *codec,
  498. int rate, int clock, int *value, int *n, int *m)
  499. {
  500. int ret = -EINVAL;
  501. int i;
  502. for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
  503. if (rate_table[i].rate >= rate) {
  504. *value = rate_table[i].sr;
  505. *n = rate_table[i].divisors[clock][0];
  506. *m = rate_table[i].divisors[clock][1];
  507. ret = 0;
  508. break;
  509. }
  510. }
  511. dev_dbg(codec->dev, "%s: sample rate is %d, returning %d\n",
  512. __func__, rate_table[i].rate, *value);
  513. return ret;
  514. }
  515. static void max98926_set_sense_data(struct max98926_priv *max98926)
  516. {
  517. struct snd_soc_codec *codec = max98926->codec;
  518. pr_err("%s %d %d\n", __func__, max98926->i_slot, max98926->v_slot);
  519. /* set VMON slots */
  520. snd_soc_update_bits(codec,
  521. max98926_DOUT_CFG_VMON,
  522. M98926_DAI_VMON_EN_MASK, M98926_DAI_VMON_EN_MASK);
  523. snd_soc_update_bits(codec,
  524. max98926_DOUT_CFG_VMON,
  525. M98926_DAI_VMON_SLOT_MASK, max98926->v_slot);
  526. /* set IMON slots */
  527. snd_soc_update_bits(codec,
  528. max98926_DOUT_CFG_IMON,
  529. M98926_DAI_IMON_EN_MASK, M98926_DAI_IMON_EN_MASK);
  530. snd_soc_update_bits(codec,
  531. max98926_DOUT_CFG_IMON,
  532. M98926_DAI_IMON_SLOT_MASK, max98926->i_slot);
  533. pr_err("%s codec = %p", __func__, codec);
  534. }
  535. static int max98926_dai_set_fmt(struct snd_soc_dai *codec_dai,
  536. unsigned int fmt)
  537. {
  538. struct snd_soc_codec *codec = codec_dai->codec;
  539. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  540. unsigned int invert = 0;
  541. dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
  542. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  543. case SND_SOC_DAIFMT_CBS_CFS:
  544. max98926_set_sense_data(max98926);
  545. break;
  546. case SND_SOC_DAIFMT_CBM_CFM:
  547. case SND_SOC_DAIFMT_CBS_CFM:
  548. case SND_SOC_DAIFMT_CBM_CFS:
  549. default:
  550. dev_err(codec->dev, "DAI clock mode unsupported");
  551. return -EINVAL;
  552. }
  553. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  554. case SND_SOC_DAIFMT_NB_NF:
  555. break;
  556. case SND_SOC_DAIFMT_NB_IF:
  557. invert = M98926_DAI_WCI_MASK;
  558. break;
  559. case SND_SOC_DAIFMT_IB_NF:
  560. invert = M98926_DAI_BCI_MASK;
  561. break;
  562. case SND_SOC_DAIFMT_IB_IF:
  563. invert = M98926_DAI_BCI_MASK | M98926_DAI_WCI_MASK;
  564. break;
  565. default:
  566. dev_err(codec->dev, "DAI invert mode unsupported");
  567. return -EINVAL;
  568. }
  569. snd_soc_update_bits(codec, max98926_FORMAT,
  570. M98926_DAI_BCI_MASK, invert);
  571. return 0;
  572. }
  573. static int max98926_set_clock(struct max98926_priv *max98926,
  574. struct snd_pcm_hw_params *params)
  575. {
  576. unsigned int dai_sr = 0, clock, n, m;
  577. struct snd_soc_codec *codec = max98926->codec;
  578. int rate = params_rate(params);
  579. /* BCLK/LRCLK ratio calculation */
  580. int blr_clk_ratio = params_channels(params) * max98926->ch_size;
  581. pr_err("%s %d %d\n", __func__, params_channels(params), max98926->ch_size);
  582. switch (blr_clk_ratio) {
  583. case 32:
  584. snd_soc_update_bits(codec,
  585. max98926_DAI_CLK_MODE2,
  586. M98926_DAI_BSEL_MASK, M98926_DAI_BSEL_32);
  587. break;
  588. case 48:
  589. snd_soc_update_bits(codec,
  590. max98926_DAI_CLK_MODE2,
  591. M98926_DAI_BSEL_MASK, M98926_DAI_BSEL_48);
  592. break;
  593. case 64:
  594. snd_soc_update_bits(codec,
  595. max98926_DAI_CLK_MODE2,
  596. M98926_DAI_BSEL_MASK, M98926_DAI_BSEL_64);
  597. break;
  598. default:
  599. return -EINVAL;
  600. }
  601. switch (max98926->sysclk) {
  602. case 6000000:
  603. clock = 0;
  604. break;
  605. case 11289600:
  606. clock = 1;
  607. break;
  608. case 12000000:
  609. clock = 0;
  610. break;
  611. case 12288000:
  612. clock = 2;
  613. break;
  614. default:
  615. pr_err("unsupported sysclk %d\n",
  616. max98926->sysclk);
  617. break;
  618. }
  619. if (max98926_rate_value(codec, rate, clock, &dai_sr, &n, &m)) {
  620. pr_err("%s return -EINVAL\n", __func__);
  621. return -EINVAL;
  622. }
  623. /* set DAI_SR to correct LRCLK frequency */
  624. snd_soc_update_bits(codec,
  625. max98926_DAI_CLK_MODE2,
  626. M98926_DAI_SR_MASK, dai_sr << M98926_DAI_SR_SHIFT);
  627. pr_err("%s return 0\n", __func__);
  628. return 0;
  629. }
  630. static int max98926_dai_hw_params(struct snd_pcm_substream *substream,
  631. struct snd_pcm_hw_params *params,
  632. struct snd_soc_dai *dai)
  633. {
  634. struct snd_soc_codec *codec = dai->codec;
  635. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  636. int ret, reg;
  637. ret = snd_soc_read(codec,
  638. max98926_DAI_CLK_DIV_N_LSBS);
  639. pr_err("%s 0x1f read 0x%x\n", __func__, ret);
  640. pr_err("%s %d\n", __func__, snd_pcm_format_width(params_format(params)));
  641. switch (snd_pcm_format_width(params_format(params))) {
  642. case 16:
  643. snd_soc_update_bits(codec,
  644. max98926_FORMAT,
  645. M98926_DAI_CHANSZ_MASK, M98926_DAI_CHANSZ_16);
  646. max98926->ch_size = 16;
  647. break;
  648. case 24:
  649. snd_soc_update_bits(codec,
  650. max98926_FORMAT,
  651. M98926_DAI_CHANSZ_MASK, M98926_DAI_CHANSZ_32);
  652. max98926->ch_size = 32;
  653. break;
  654. case 32:
  655. snd_soc_update_bits(codec,
  656. max98926_FORMAT,
  657. M98926_DAI_CHANSZ_MASK, M98926_DAI_CHANSZ_32);
  658. max98926->ch_size = 32;
  659. break;
  660. default:
  661. pr_err("%s: format unsupported %d",
  662. __func__, params_format(params));
  663. return -EINVAL;
  664. }
  665. dev_dbg(codec->dev, "%s: format supported %d",
  666. __func__, params_format(params));
  667. return max98926_set_clock(max98926, params);
  668. }
  669. static int max98926_dai_set_sysclk(struct snd_soc_dai *dai,
  670. int clk_id, unsigned int freq, int dir)
  671. {
  672. struct snd_soc_codec *codec = dai->codec;
  673. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  674. max98926->sysclk = freq;
  675. return 0;
  676. }
  677. #define max98926_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  678. static struct snd_soc_dai_ops max98926_dai_ops = {
  679. .set_sysclk = max98926_dai_set_sysclk,
  680. .set_fmt = max98926_dai_set_fmt,
  681. .hw_params = max98926_dai_hw_params,
  682. };
  683. static struct snd_soc_dai_driver max98926_dai[] = {
  684. {
  685. .name = "max98926-aif1",
  686. .playback = {
  687. .stream_name = "Speaker_PLayback",
  688. .channels_min = 1,
  689. .channels_max = 2,
  690. .rates = SNDRV_PCM_RATE_8000_48000,
  691. .formats = max98926_FORMATS,
  692. },
  693. .capture = {
  694. .stream_name = "Speaker_PLayback",
  695. .channels_min = 1,
  696. .channels_max = 2,
  697. .rates = SNDRV_PCM_RATE_8000_48000,
  698. .formats = max98926_FORMATS,
  699. },
  700. .ops = &max98926_dai_ops,
  701. }
  702. };
  703. static int max98926_probe(struct snd_soc_codec *codec)
  704. {
  705. int ret = 0;
  706. struct max98926_priv *max98926 = snd_soc_codec_get_drvdata(codec);
  707. max98926->codec = codec;
  708. codec->control_data = codec;
  709. pr_err("%s codec = %p", __func__, codec);
  710. speaker_enable = false;
  711. /*
  712. ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
  713. if (ret != 0) {
  714. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  715. return ret;
  716. }
  717. */
  718. ret = snd_soc_read(codec,
  719. max98926_REV_VERSION);
  720. if ((ret < 0) ||
  721. ((ret != max98926_VERSION) &&
  722. (ret != max98926_VERSION1))) {
  723. pr_err("device initialization error (%d )\n",
  724. ret);
  725. }
  726. pr_err("device version 0x%02X\n", ret);
  727. /* can be configured to any other value supported by this chip */
  728. max98926->sysclk = 12288000;
  729. max98926->spk_gain = 0x14;
  730. snd_soc_write(codec, max98926_GLOBAL_ENABLE, 0x00);
  731. /* It's not the default but we need to set DAI_DLY */
  732. snd_soc_write(codec,
  733. max98926_FORMAT, M98926_DAI_DLY_MASK);
  734. snd_soc_write(codec, max98926_TDM_SLOT_SELECT, 0xC8);
  735. snd_soc_write(codec, max98926_DOUT_HIZ_CFG1, 0xFF);
  736. snd_soc_write(codec, max98926_DOUT_HIZ_CFG2, 0xFF);
  737. snd_soc_write(codec, max98926_DOUT_HIZ_CFG3, 0xFF);
  738. snd_soc_write(codec, max98926_DOUT_HIZ_CFG4, 0xCC);
  739. snd_soc_write(codec, max98926_FILTERS, 0xD8);
  740. snd_soc_write(codec, max98926_ALC_CONFIGURATION, 0xF8);
  741. snd_soc_write(codec, max98926_GAIN, 0x1a);
  742. /* Disable ALC muting */
  743. snd_soc_write(codec, max98926_BOOST_LIMITER, 0xF8);
  744. if (codec->dev->of_node)
  745. dev_set_name(&codec->dev, "%s", "MAX98926_MT");
  746. return 0;
  747. }
  748. static unsigned int max98926_read(struct snd_soc_codec *codec, unsigned int addr)
  749. {
  750. unsigned short Ret = 0;
  751. max98926_ReadReg((unsigned short)addr, (unsigned short *)&Ret);
  752. return Ret;
  753. }
  754. static int max98926_write(struct snd_soc_codec *codec, unsigned int adrress, unsigned int value)
  755. {
  756. int ret = 0;
  757. ret = max98926_WriteReg(adrress , value);
  758. return ret;
  759. }
  760. static struct snd_soc_codec_driver soc_codec_dev_max98926 = {
  761. .probe = max98926_probe,
  762. .controls = max98926_snd_controls,
  763. .num_controls = ARRAY_SIZE(max98926_snd_controls),
  764. .dapm_routes = max98926_audio_map,
  765. .num_dapm_routes = ARRAY_SIZE(max98926_audio_map),
  766. .dapm_widgets = max98926_dapm_widgets,
  767. .num_dapm_widgets = ARRAY_SIZE(max98926_dapm_widgets),
  768. .read = max98926_read,
  769. .write = max98926_write,
  770. };
  771. static struct regmap_config max98926_regmap = {
  772. .reg_bits = 8,
  773. .val_bits = 8,
  774. .max_register = max98926_REV_VERSION,
  775. .reg_defaults = max98926_reg,
  776. .num_reg_defaults = ARRAY_SIZE(max98926_reg),
  777. .volatile_reg = max98926_volatile_register,
  778. .readable_reg = max98926_readable_register,
  779. .cache_type = REGCACHE_RBTREE,
  780. };
  781. static ssize_t max_i2c_write(const char *data, size_t count)
  782. {
  783. int ret;
  784. pr_err("%s count = %zu\n", __func__, count);
  785. ret = max_i2c_master_send(new_client, data, count);
  786. return ret;
  787. }
  788. static int max_i2c_master_send(const struct i2c_client *client, const char *buf, int count)
  789. {
  790. int ret;
  791. struct i2c_adapter *adap = client->adapter;
  792. struct i2c_msg msg;
  793. #ifdef CONFIG_MTK_I2C_EXTENSION
  794. if (count <= 8)
  795. msg.addr = client->addr & I2C_MASK_FLAG;
  796. else
  797. msg.addr = client->addr & I2C_MASK_FLAG | I2C_DMA_FLAG;
  798. #endif
  799. msg.flags = client->flags & I2C_M_TEN;
  800. msg.len = count;
  801. msg.buf = (char *)buf;
  802. #ifdef CONFIG_MTK_I2C_EXTENSION
  803. msg.ext_flag = client->ext_flag;
  804. #endif
  805. ret = i2c_transfer(adap, &msg, 1);
  806. /*
  807. * If everything went ok (i.e. 1 msg transmitted), return #bytes
  808. * transmitted, else error code.
  809. */
  810. return (ret == 1) ? count : ret;
  811. }
  812. static int max98926_WriteReg(u16 a_u2Addr, u16 a_u2Data)
  813. {
  814. pr_err("%s\n", __func__);
  815. int i4RetValue = 0;
  816. char puSendCmd[2] = {(char)a_u2Addr , (char)a_u2Data};
  817. #ifdef CONFIG_MTK_I2C_EXTENSION
  818. new_client->ext_flag = 0;
  819. #endif
  820. i4RetValue = i2c_master_send(new_client, puSendCmd, 2);
  821. if (i4RetValue < 0) {
  822. pr_err("max98926_WriteReg I2C send failed!!\n");
  823. return -1;
  824. }
  825. return 0;
  826. }
  827. static int max98926_ReadReg(u16 a_u2Addr, unsigned short *a_pu2Result)
  828. {
  829. int i4RetValue = 0;
  830. char pBuff;
  831. int ret;
  832. struct i2c_adapter *adap = new_client->adapter;
  833. unsigned short buffer[2];
  834. #ifdef CONFIG_MTK_I2C_EXTENSION
  835. new_client->ext_flag = ((new_client->ext_flag) & I2C_MASK_FLAG) | I2C_WR_FLAG | I2C_RS_FLAG;
  836. if (i2c_master_send(new_client, &a_u2Addr, 1 << 8 | 1) != 1)
  837. pr_err("max98926_ReadReg I2C send failed!!\n");
  838. *a_pu2Result = a_u2Addr;
  839. #else
  840. struct i2c_msg wr_msgs[2];
  841. wr_msgs[0].addr = new_client->addr;
  842. wr_msgs[0].flags = 0x00;
  843. wr_msgs[0].len = 1;
  844. wr_msgs[0].buf = &buffer[0];
  845. wr_msgs[1].addr = new_client->addr;
  846. wr_msgs[1].flags |= I2C_M_RD;
  847. wr_msgs[1].len = 1;
  848. wr_msgs[1].buf = &buffer[1];
  849. ret = i2c_transfer(adap, &wr_msgs, 2);
  850. *a_pu2Result = buffer[1];
  851. #endif
  852. return 0;
  853. }
  854. static int max98926_i2c_probe(struct i2c_client *i2c,
  855. const struct i2c_device_id *id)
  856. {
  857. pr_err("%s\n", __func__);
  858. new_client = i2c;
  859. #ifdef CONFIG_MTK_I2C_EXTENSION
  860. new_client->timing = 100;
  861. new_client->ext_flag = ((new_client->ext_flag) & I2C_MASK_FLAG) | I2C_WR_FLAG | I2C_RS_FLAG;
  862. #endif
  863. struct snd_soc_codec *codec = NULL;
  864. int ret, reg;
  865. u32 value;
  866. struct max98926_priv *max98926 = NULL;
  867. /*
  868. max98926_regulator_config(i2c, of_property_read_bool(i2c->dev.of_node,
  869. "max98926,i2c-pull-up"), 1);
  870. */
  871. max98926 = devm_kzalloc(&i2c->dev,
  872. sizeof(*max98926), GFP_KERNEL);
  873. if (!max98926)
  874. return -ENOMEM;
  875. pr_err("max98926 = %p\n", max98926);
  876. i2c_set_clientdata(i2c, max98926);
  877. /*
  878. max98926->regmap = devm_regmap_init_i2c(i2c, &max98926_regmap);
  879. if (IS_ERR(max98926->regmap))
  880. {
  881. ret = PTR_ERR(max98926->regmap);
  882. dev_err(&i2c->dev,"Failed to allocate regmap: %d\n", ret);
  883. goto err_out;
  884. }
  885. */
  886. if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
  887. if (value > M98926_DAI_VMON_SLOT_1E_1F) {
  888. dev_err(&i2c->dev, "vmon slot number is wrong:\n");
  889. return -EINVAL;
  890. }
  891. max98926->v_slot = value;
  892. } else {
  893. max98926->v_slot = 0;
  894. }
  895. if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
  896. if (value > M98926_DAI_IMON_SLOT_1E_1F) {
  897. dev_err(&i2c->dev, "imon slot number is wrong:\n");
  898. return -EINVAL;
  899. }
  900. max98926->i_slot = value;
  901. } else {
  902. max98926->i_slot = 4;
  903. }
  904. pr_err("4 %s max98926->v_slot = %d max98926->i_slot = %d\n", __func__, max98926->v_slot, max98926->i_slot);
  905. if (&i2c->dev.of_node)
  906. dev_set_name(&i2c->dev, "%s", "MAX98926_MT");
  907. ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98926,
  908. max98926_dai, ARRAY_SIZE(max98926_dai));
  909. if (ret < 0)
  910. dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
  911. pr_err("%s ret = %d\n", __func__, ret);
  912. err_out:
  913. return ret;
  914. }
  915. static int max98926_i2c_remove(struct i2c_client *client)
  916. {
  917. snd_soc_unregister_codec(&client->dev);
  918. return 0;
  919. }
  920. static const struct i2c_device_id max98926_i2c_id[] = {
  921. { "max98926L", 0 },
  922. { }
  923. };
  924. MODULE_DEVICE_TABLE(i2c, max98926_i2c_id);
  925. static const struct of_device_id max98926_of_match[] = {
  926. { .compatible = "mediatek,speaker_amp", },
  927. { }
  928. };
  929. MODULE_DEVICE_TABLE(of, max98926_of_match);
  930. static struct i2c_driver max98926_i2c_driver = {
  931. .driver = {
  932. .name = "speaker_amp",
  933. .owner = THIS_MODULE,
  934. .of_match_table = of_match_ptr(max98926_of_match),
  935. .pm = NULL,
  936. },
  937. .probe = max98926_i2c_probe,
  938. .remove = max98926_i2c_remove,
  939. .id_table = max98926_i2c_id,
  940. };
  941. /*
  942. static struct i2c_board_info __initdata max_i2c_board_info[] = {
  943. {
  944. I2C_BOARD_INFO("max98926L", 0x31), // if 0x31 is your device address_space
  945. },
  946. };
  947. */
  948. static struct platform_device *Max98926_dev;
  949. static int __init max98926_init(void)
  950. {
  951. int ret = 0;
  952. pr_err("+max98926_init\n");
  953. Max98926_dev = platform_device_alloc("max98926L", -1);
  954. if (!Max98926_dev)
  955. return -ENOMEM;
  956. ret = platform_device_add(Max98926_dev);
  957. if (ret != 0) {
  958. platform_device_put(Max98926_dev);
  959. return ret;
  960. }
  961. /*
  962. i2c_register_board_info(MAX98926_I2C_Channel, max_i2c_board_info, ARRAY_SIZE(max_i2c_board_info));
  963. */
  964. if (i2c_add_driver(&max98926_i2c_driver)) {
  965. pr_err("fail to add device into i2c");
  966. return -1;
  967. }
  968. pr_err("-max98926_init\n");
  969. return 0;
  970. }
  971. subsys_initcall(max98926_init);
  972. static void __exit max98926_exit(void)
  973. {
  974. i2c_del_driver(&max98926_i2c_driver);
  975. }
  976. module_exit(max98926_exit);
  977. /* replace with init_call and module exit.
  978. module_i2c_driver(max98926_i2c_driver)
  979. */
  980. MODULE_DESCRIPTION("ALSA SoC max98926 driver");
  981. MODULE_AUTHOR("Ralph Birt <rdbirt@gmail.com>, Anish kumar <anish.kumar@maximintegrated.com>");
  982. MODULE_LICENSE("GPL");