slicoss.c 82 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright 2000-2006 Alacritech, Inc. All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions
  7. * are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above
  12. * copyright notice, this list of conditions and the following
  13. * disclaimer in the documentation and/or other materials provided
  14. * with the distribution.
  15. *
  16. * Alternatively, this software may be distributed under the terms of the
  17. * GNU General Public License ("GPL") version 2 as published by the Free
  18. * Software Foundation.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
  21. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
  24. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  29. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  30. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31. * SUCH DAMAGE.
  32. *
  33. * The views and conclusions contained in the software and documentation
  34. * are those of the authors and should not be interpreted as representing
  35. * official policies, either expressed or implied, of Alacritech, Inc.
  36. *
  37. **************************************************************************/
  38. /*
  39. * FILENAME: slicoss.c
  40. *
  41. * The SLICOSS driver for Alacritech's IS-NIC products.
  42. *
  43. * This driver is supposed to support:
  44. *
  45. * Mojave cards (single port PCI Gigabit) both copper and fiber
  46. * Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
  47. * Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
  48. *
  49. * The driver was actually tested on Oasis and Kalahari cards.
  50. *
  51. *
  52. * NOTE: This is the standard, non-accelerated version of Alacritech's
  53. * IS-NIC driver.
  54. */
  55. #define KLUDGE_FOR_4GB_BOUNDARY 1
  56. #define DEBUG_MICROCODE 1
  57. #define DBG 1
  58. #define SLIC_INTERRUPT_PROCESS_LIMIT 1
  59. #define SLIC_OFFLOAD_IP_CHECKSUM 1
  60. #define STATS_TIMER_INTERVAL 2
  61. #define PING_TIMER_INTERVAL 1
  62. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  63. #include <linux/kernel.h>
  64. #include <linux/string.h>
  65. #include <linux/errno.h>
  66. #include <linux/ioport.h>
  67. #include <linux/slab.h>
  68. #include <linux/interrupt.h>
  69. #include <linux/timer.h>
  70. #include <linux/pci.h>
  71. #include <linux/spinlock.h>
  72. #include <linux/init.h>
  73. #include <linux/bitops.h>
  74. #include <linux/io.h>
  75. #include <linux/netdevice.h>
  76. #include <linux/crc32.h>
  77. #include <linux/etherdevice.h>
  78. #include <linux/skbuff.h>
  79. #include <linux/delay.h>
  80. #include <linux/seq_file.h>
  81. #include <linux/kthread.h>
  82. #include <linux/module.h>
  83. #include <linux/moduleparam.h>
  84. #include <linux/firmware.h>
  85. #include <linux/types.h>
  86. #include <linux/dma-mapping.h>
  87. #include <linux/mii.h>
  88. #include <linux/if_vlan.h>
  89. #include <asm/unaligned.h>
  90. #include <linux/ethtool.h>
  91. #include <linux/uaccess.h>
  92. #include "slichw.h"
  93. #include "slic.h"
  94. static uint slic_first_init = 1;
  95. static char *slic_banner = "Alacritech SLIC Technology(tm) Server "
  96. "and Storage Accelerator (Non-Accelerated)";
  97. static char *slic_proc_version = "2.0.351 2006/07/14 12:26:00";
  98. static struct base_driver slic_global = { {}, 0, 0, 0, 1, NULL, NULL };
  99. static int intagg_delay = 100;
  100. static u32 dynamic_intagg;
  101. static unsigned int rcv_count;
  102. #define DRV_NAME "slicoss"
  103. #define DRV_VERSION "2.0.1"
  104. #define DRV_AUTHOR "Alacritech, Inc. Engineering"
  105. #define DRV_DESCRIPTION "Alacritech SLIC Techonology(tm) "\
  106. "Non-Accelerated Driver"
  107. #define DRV_COPYRIGHT "Copyright 2000-2006 Alacritech, Inc. "\
  108. "All rights reserved."
  109. #define PFX DRV_NAME " "
  110. MODULE_AUTHOR(DRV_AUTHOR);
  111. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  112. MODULE_LICENSE("Dual BSD/GPL");
  113. module_param(dynamic_intagg, int, 0);
  114. MODULE_PARM_DESC(dynamic_intagg, "Dynamic Interrupt Aggregation Setting");
  115. module_param(intagg_delay, int, 0);
  116. MODULE_PARM_DESC(intagg_delay, "uSec Interrupt Aggregation Delay");
  117. static const struct pci_device_id slic_pci_tbl[] = {
  118. { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_1GB_DEVICE_ID) },
  119. { PCI_DEVICE(PCI_VENDOR_ID_ALACRITECH, SLIC_2GB_DEVICE_ID) },
  120. { 0 }
  121. };
  122. MODULE_DEVICE_TABLE(pci, slic_pci_tbl);
  123. static inline void slic_reg32_write(void __iomem *reg, u32 value, bool flush)
  124. {
  125. writel(value, reg);
  126. if (flush)
  127. mb();
  128. }
  129. static inline void slic_reg64_write(struct adapter *adapter, void __iomem *reg,
  130. u32 value, void __iomem *regh, u32 paddrh,
  131. bool flush)
  132. {
  133. spin_lock_irqsave(&adapter->bit64reglock.lock,
  134. adapter->bit64reglock.flags);
  135. if (paddrh != adapter->curaddrupper) {
  136. adapter->curaddrupper = paddrh;
  137. writel(paddrh, regh);
  138. }
  139. writel(value, reg);
  140. if (flush)
  141. mb();
  142. spin_unlock_irqrestore(&adapter->bit64reglock.lock,
  143. adapter->bit64reglock.flags);
  144. }
  145. static void slic_mcast_set_bit(struct adapter *adapter, char *address)
  146. {
  147. unsigned char crcpoly;
  148. /* Get the CRC polynomial for the mac address */
  149. /* we use bits 1-8 (lsb), bitwise reversed,
  150. * msb (= lsb bit 0 before bitrev) is automatically discarded */
  151. crcpoly = (ether_crc(ETH_ALEN, address)>>23);
  152. /* We only have space on the SLIC for 64 entries. Lop
  153. * off the top two bits. (2^6 = 64)
  154. */
  155. crcpoly &= 0x3F;
  156. /* OR in the new bit into our 64 bit mask. */
  157. adapter->mcastmask |= (u64) 1 << crcpoly;
  158. }
  159. static void slic_mcast_set_mask(struct adapter *adapter)
  160. {
  161. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  162. if (adapter->macopts & (MAC_ALLMCAST | MAC_PROMISC)) {
  163. /* Turn on all multicast addresses. We have to do this for
  164. * promiscuous mode as well as ALLMCAST mode. It saves the
  165. * Microcode from having to keep state about the MAC
  166. * configuration.
  167. */
  168. slic_reg32_write(&slic_regs->slic_mcastlow, 0xFFFFFFFF, FLUSH);
  169. slic_reg32_write(&slic_regs->slic_mcasthigh, 0xFFFFFFFF,
  170. FLUSH);
  171. } else {
  172. /* Commit our multicast mast to the SLIC by writing to the
  173. * multicast address mask registers
  174. */
  175. slic_reg32_write(&slic_regs->slic_mcastlow,
  176. (u32)(adapter->mcastmask & 0xFFFFFFFF), FLUSH);
  177. slic_reg32_write(&slic_regs->slic_mcasthigh,
  178. (u32)((adapter->mcastmask >> 32) & 0xFFFFFFFF), FLUSH);
  179. }
  180. }
  181. static void slic_timer_ping(ulong dev)
  182. {
  183. struct adapter *adapter;
  184. struct sliccard *card;
  185. adapter = netdev_priv((struct net_device *)dev);
  186. card = adapter->card;
  187. adapter->pingtimer.expires = jiffies + (PING_TIMER_INTERVAL * HZ);
  188. add_timer(&adapter->pingtimer);
  189. }
  190. static void slic_unmap_mmio_space(struct adapter *adapter)
  191. {
  192. if (adapter->slic_regs)
  193. iounmap(adapter->slic_regs);
  194. adapter->slic_regs = NULL;
  195. }
  196. /*
  197. * slic_link_config
  198. *
  199. * Write phy control to configure link duplex/speed
  200. *
  201. */
  202. static void slic_link_config(struct adapter *adapter,
  203. u32 linkspeed, u32 linkduplex)
  204. {
  205. u32 __iomem *wphy;
  206. u32 speed;
  207. u32 duplex;
  208. u32 phy_config;
  209. u32 phy_advreg;
  210. u32 phy_gctlreg;
  211. if (adapter->state != ADAPT_UP)
  212. return;
  213. if (linkspeed > LINK_1000MB)
  214. linkspeed = LINK_AUTOSPEED;
  215. if (linkduplex > LINK_AUTOD)
  216. linkduplex = LINK_AUTOD;
  217. wphy = &adapter->slic_regs->slic_wphy;
  218. if ((linkspeed == LINK_AUTOSPEED) || (linkspeed == LINK_1000MB)) {
  219. if (adapter->flags & ADAPT_FLAGS_FIBERMEDIA) {
  220. /* We've got a fiber gigabit interface, and register
  221. * 4 is different in fiber mode than in copper mode
  222. */
  223. /* advertise FD only @1000 Mb */
  224. phy_advreg = (MIICR_REG_4 | (PAR_ADV1000XFD));
  225. /* enable PAUSE frames */
  226. phy_advreg |= PAR_ASYMPAUSE_FIBER;
  227. slic_reg32_write(wphy, phy_advreg, FLUSH);
  228. if (linkspeed == LINK_AUTOSPEED) {
  229. /* reset phy, enable auto-neg */
  230. phy_config =
  231. (MIICR_REG_PCR |
  232. (PCR_RESET | PCR_AUTONEG |
  233. PCR_AUTONEG_RST));
  234. slic_reg32_write(wphy, phy_config, FLUSH);
  235. } else { /* forced 1000 Mb FD*/
  236. /* power down phy to break link
  237. this may not work) */
  238. phy_config = (MIICR_REG_PCR | PCR_POWERDOWN);
  239. slic_reg32_write(wphy, phy_config, FLUSH);
  240. /* wait, Marvell says 1 sec,
  241. try to get away with 10 ms */
  242. mdelay(10);
  243. /* disable auto-neg, set speed/duplex,
  244. soft reset phy, powerup */
  245. phy_config =
  246. (MIICR_REG_PCR |
  247. (PCR_RESET | PCR_SPEED_1000 |
  248. PCR_DUPLEX_FULL));
  249. slic_reg32_write(wphy, phy_config, FLUSH);
  250. }
  251. } else { /* copper gigabit */
  252. /* Auto-Negotiate or 1000 Mb must be auto negotiated
  253. * We've got a copper gigabit interface, and
  254. * register 4 is different in copper mode than
  255. * in fiber mode
  256. */
  257. if (linkspeed == LINK_AUTOSPEED) {
  258. /* advertise 10/100 Mb modes */
  259. phy_advreg =
  260. (MIICR_REG_4 |
  261. (PAR_ADV100FD | PAR_ADV100HD | PAR_ADV10FD
  262. | PAR_ADV10HD));
  263. } else {
  264. /* linkspeed == LINK_1000MB -
  265. don't advertise 10/100 Mb modes */
  266. phy_advreg = MIICR_REG_4;
  267. }
  268. /* enable PAUSE frames */
  269. phy_advreg |= PAR_ASYMPAUSE;
  270. /* required by the Cicada PHY */
  271. phy_advreg |= PAR_802_3;
  272. slic_reg32_write(wphy, phy_advreg, FLUSH);
  273. /* advertise FD only @1000 Mb */
  274. phy_gctlreg = (MIICR_REG_9 | (PGC_ADV1000FD));
  275. slic_reg32_write(wphy, phy_gctlreg, FLUSH);
  276. if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
  277. /* if a Marvell PHY
  278. enable auto crossover */
  279. phy_config =
  280. (MIICR_REG_16 | (MRV_REG16_XOVERON));
  281. slic_reg32_write(wphy, phy_config, FLUSH);
  282. /* reset phy, enable auto-neg */
  283. phy_config =
  284. (MIICR_REG_PCR |
  285. (PCR_RESET | PCR_AUTONEG |
  286. PCR_AUTONEG_RST));
  287. slic_reg32_write(wphy, phy_config, FLUSH);
  288. } else { /* it's a Cicada PHY */
  289. /* enable and restart auto-neg (don't reset) */
  290. phy_config =
  291. (MIICR_REG_PCR |
  292. (PCR_AUTONEG | PCR_AUTONEG_RST));
  293. slic_reg32_write(wphy, phy_config, FLUSH);
  294. }
  295. }
  296. } else {
  297. /* Forced 10/100 */
  298. if (linkspeed == LINK_10MB)
  299. speed = 0;
  300. else
  301. speed = PCR_SPEED_100;
  302. if (linkduplex == LINK_HALFD)
  303. duplex = 0;
  304. else
  305. duplex = PCR_DUPLEX_FULL;
  306. if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
  307. /* if a Marvell PHY
  308. disable auto crossover */
  309. phy_config = (MIICR_REG_16 | (MRV_REG16_XOVEROFF));
  310. slic_reg32_write(wphy, phy_config, FLUSH);
  311. }
  312. /* power down phy to break link (this may not work) */
  313. phy_config = (MIICR_REG_PCR | (PCR_POWERDOWN | speed | duplex));
  314. slic_reg32_write(wphy, phy_config, FLUSH);
  315. /* wait, Marvell says 1 sec, try to get away with 10 ms */
  316. mdelay(10);
  317. if (adapter->subsysid != SLIC_1GB_CICADA_SUBSYS_ID) {
  318. /* if a Marvell PHY
  319. disable auto-neg, set speed,
  320. soft reset phy, powerup */
  321. phy_config =
  322. (MIICR_REG_PCR | (PCR_RESET | speed | duplex));
  323. slic_reg32_write(wphy, phy_config, FLUSH);
  324. } else { /* it's a Cicada PHY */
  325. /* disable auto-neg, set speed, powerup */
  326. phy_config = (MIICR_REG_PCR | (speed | duplex));
  327. slic_reg32_write(wphy, phy_config, FLUSH);
  328. }
  329. }
  330. }
  331. static int slic_card_download_gbrcv(struct adapter *adapter)
  332. {
  333. const struct firmware *fw;
  334. const char *file = "";
  335. int ret;
  336. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  337. u32 codeaddr;
  338. u32 instruction;
  339. int index = 0;
  340. u32 rcvucodelen = 0;
  341. switch (adapter->devid) {
  342. case SLIC_2GB_DEVICE_ID:
  343. file = "slicoss/oasisrcvucode.sys";
  344. break;
  345. case SLIC_1GB_DEVICE_ID:
  346. file = "slicoss/gbrcvucode.sys";
  347. break;
  348. default:
  349. return -ENOENT;
  350. }
  351. ret = request_firmware(&fw, file, &adapter->pcidev->dev);
  352. if (ret) {
  353. dev_err(&adapter->pcidev->dev,
  354. "Failed to load firmware %s\n", file);
  355. return ret;
  356. }
  357. rcvucodelen = *(u32 *)(fw->data + index);
  358. index += 4;
  359. switch (adapter->devid) {
  360. case SLIC_2GB_DEVICE_ID:
  361. if (rcvucodelen != OasisRcvUCodeLen) {
  362. release_firmware(fw);
  363. return -EINVAL;
  364. }
  365. break;
  366. case SLIC_1GB_DEVICE_ID:
  367. if (rcvucodelen != GBRcvUCodeLen) {
  368. release_firmware(fw);
  369. return -EINVAL;
  370. }
  371. break;
  372. }
  373. /* start download */
  374. slic_reg32_write(&slic_regs->slic_rcv_wcs, SLIC_RCVWCS_BEGIN, FLUSH);
  375. /* download the rcv sequencer ucode */
  376. for (codeaddr = 0; codeaddr < rcvucodelen; codeaddr++) {
  377. /* write out instruction address */
  378. slic_reg32_write(&slic_regs->slic_rcv_wcs, codeaddr, FLUSH);
  379. instruction = *(u32 *)(fw->data + index);
  380. index += 4;
  381. /* write out the instruction data low addr */
  382. slic_reg32_write(&slic_regs->slic_rcv_wcs, instruction, FLUSH);
  383. instruction = *(u8 *)(fw->data + index);
  384. index++;
  385. /* write out the instruction data high addr */
  386. slic_reg32_write(&slic_regs->slic_rcv_wcs, (u8)instruction,
  387. FLUSH);
  388. }
  389. /* download finished */
  390. release_firmware(fw);
  391. slic_reg32_write(&slic_regs->slic_rcv_wcs, SLIC_RCVWCS_FINISH, FLUSH);
  392. return 0;
  393. }
  394. MODULE_FIRMWARE("slicoss/oasisrcvucode.sys");
  395. MODULE_FIRMWARE("slicoss/gbrcvucode.sys");
  396. static int slic_card_download(struct adapter *adapter)
  397. {
  398. const struct firmware *fw;
  399. const char *file = "";
  400. int ret;
  401. u32 section;
  402. int thissectionsize;
  403. int codeaddr;
  404. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  405. u32 instruction;
  406. u32 baseaddress;
  407. u32 i;
  408. u32 numsects = 0;
  409. u32 sectsize[3];
  410. u32 sectstart[3];
  411. int ucode_start, index = 0;
  412. switch (adapter->devid) {
  413. case SLIC_2GB_DEVICE_ID:
  414. file = "slicoss/oasisdownload.sys";
  415. break;
  416. case SLIC_1GB_DEVICE_ID:
  417. file = "slicoss/gbdownload.sys";
  418. break;
  419. default:
  420. return -ENOENT;
  421. }
  422. ret = request_firmware(&fw, file, &adapter->pcidev->dev);
  423. if (ret) {
  424. dev_err(&adapter->pcidev->dev,
  425. "Failed to load firmware %s\n", file);
  426. return ret;
  427. }
  428. numsects = *(u32 *)(fw->data + index);
  429. index += 4;
  430. for (i = 0; i < numsects; i++) {
  431. sectsize[i] = *(u32 *)(fw->data + index);
  432. index += 4;
  433. }
  434. for (i = 0; i < numsects; i++) {
  435. sectstart[i] = *(u32 *)(fw->data + index);
  436. index += 4;
  437. }
  438. ucode_start = index;
  439. instruction = *(u32 *)(fw->data + index);
  440. index += 4;
  441. for (section = 0; section < numsects; section++) {
  442. baseaddress = sectstart[section];
  443. thissectionsize = sectsize[section] >> 3;
  444. for (codeaddr = 0; codeaddr < thissectionsize; codeaddr++) {
  445. /* Write out instruction address */
  446. slic_reg32_write(&slic_regs->slic_wcs,
  447. baseaddress + codeaddr, FLUSH);
  448. /* Write out instruction to low addr */
  449. slic_reg32_write(&slic_regs->slic_wcs, instruction, FLUSH);
  450. instruction = *(u32 *)(fw->data + index);
  451. index += 4;
  452. /* Write out instruction to high addr */
  453. slic_reg32_write(&slic_regs->slic_wcs, instruction, FLUSH);
  454. instruction = *(u32 *)(fw->data + index);
  455. index += 4;
  456. }
  457. }
  458. index = ucode_start;
  459. for (section = 0; section < numsects; section++) {
  460. instruction = *(u32 *)(fw->data + index);
  461. baseaddress = sectstart[section];
  462. if (baseaddress < 0x8000)
  463. continue;
  464. thissectionsize = sectsize[section] >> 3;
  465. for (codeaddr = 0; codeaddr < thissectionsize; codeaddr++) {
  466. /* Write out instruction address */
  467. slic_reg32_write(&slic_regs->slic_wcs,
  468. SLIC_WCS_COMPARE | (baseaddress + codeaddr),
  469. FLUSH);
  470. /* Write out instruction to low addr */
  471. slic_reg32_write(&slic_regs->slic_wcs, instruction,
  472. FLUSH);
  473. instruction = *(u32 *)(fw->data + index);
  474. index += 4;
  475. /* Write out instruction to high addr */
  476. slic_reg32_write(&slic_regs->slic_wcs, instruction,
  477. FLUSH);
  478. instruction = *(u32 *)(fw->data + index);
  479. index += 4;
  480. /* Check SRAM location zero. If it is non-zero. Abort.*/
  481. /* failure = readl((u32 __iomem *)&slic_regs->slic_reset);
  482. if (failure) {
  483. release_firmware(fw);
  484. return -EIO;
  485. }*/
  486. }
  487. }
  488. release_firmware(fw);
  489. /* Everything OK, kick off the card */
  490. mdelay(10);
  491. slic_reg32_write(&slic_regs->slic_wcs, SLIC_WCS_START, FLUSH);
  492. /* stall for 20 ms, long enough for ucode to init card
  493. and reach mainloop */
  494. mdelay(20);
  495. return 0;
  496. }
  497. MODULE_FIRMWARE("slicoss/oasisdownload.sys");
  498. MODULE_FIRMWARE("slicoss/gbdownload.sys");
  499. static void slic_adapter_set_hwaddr(struct adapter *adapter)
  500. {
  501. struct sliccard *card = adapter->card;
  502. if ((adapter->card) && (card->config_set)) {
  503. memcpy(adapter->macaddr,
  504. card->config.MacInfo[adapter->functionnumber].macaddrA,
  505. sizeof(struct slic_config_mac));
  506. if (is_zero_ether_addr(adapter->currmacaddr))
  507. memcpy(adapter->currmacaddr, adapter->macaddr,
  508. ETH_ALEN);
  509. if (adapter->netdev)
  510. memcpy(adapter->netdev->dev_addr, adapter->currmacaddr,
  511. ETH_ALEN);
  512. }
  513. }
  514. static void slic_intagg_set(struct adapter *adapter, u32 value)
  515. {
  516. slic_reg32_write(&adapter->slic_regs->slic_intagg, value, FLUSH);
  517. adapter->card->loadlevel_current = value;
  518. }
  519. static void slic_soft_reset(struct adapter *adapter)
  520. {
  521. if (adapter->card->state == CARD_UP) {
  522. slic_reg32_write(&adapter->slic_regs->slic_quiesce, 0, FLUSH);
  523. mdelay(1);
  524. }
  525. slic_reg32_write(&adapter->slic_regs->slic_reset, SLIC_RESET_MAGIC,
  526. FLUSH);
  527. mdelay(1);
  528. }
  529. static void slic_mac_address_config(struct adapter *adapter)
  530. {
  531. u32 value;
  532. u32 value2;
  533. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  534. value = *(u32 *) &adapter->currmacaddr[2];
  535. value = ntohl(value);
  536. slic_reg32_write(&slic_regs->slic_wraddral, value, FLUSH);
  537. slic_reg32_write(&slic_regs->slic_wraddrbl, value, FLUSH);
  538. value2 = (u32) ((adapter->currmacaddr[0] << 8 |
  539. adapter->currmacaddr[1]) & 0xFFFF);
  540. slic_reg32_write(&slic_regs->slic_wraddrah, value2, FLUSH);
  541. slic_reg32_write(&slic_regs->slic_wraddrbh, value2, FLUSH);
  542. /* Write our multicast mask out to the card. This is done */
  543. /* here in addition to the slic_mcast_addr_set routine */
  544. /* because ALL_MCAST may have been enabled or disabled */
  545. slic_mcast_set_mask(adapter);
  546. }
  547. static void slic_mac_config(struct adapter *adapter)
  548. {
  549. u32 value;
  550. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  551. /* Setup GMAC gaps */
  552. if (adapter->linkspeed == LINK_1000MB) {
  553. value = ((GMCR_GAPBB_1000 << GMCR_GAPBB_SHIFT) |
  554. (GMCR_GAPR1_1000 << GMCR_GAPR1_SHIFT) |
  555. (GMCR_GAPR2_1000 << GMCR_GAPR2_SHIFT));
  556. } else {
  557. value = ((GMCR_GAPBB_100 << GMCR_GAPBB_SHIFT) |
  558. (GMCR_GAPR1_100 << GMCR_GAPR1_SHIFT) |
  559. (GMCR_GAPR2_100 << GMCR_GAPR2_SHIFT));
  560. }
  561. /* enable GMII */
  562. if (adapter->linkspeed == LINK_1000MB)
  563. value |= GMCR_GBIT;
  564. /* enable fullduplex */
  565. if ((adapter->linkduplex == LINK_FULLD)
  566. || (adapter->macopts & MAC_LOOPBACK)) {
  567. value |= GMCR_FULLD;
  568. }
  569. /* write mac config */
  570. slic_reg32_write(&slic_regs->slic_wmcfg, value, FLUSH);
  571. /* setup mac addresses */
  572. slic_mac_address_config(adapter);
  573. }
  574. static void slic_config_set(struct adapter *adapter, bool linkchange)
  575. {
  576. u32 value;
  577. u32 RcrReset;
  578. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  579. if (linkchange) {
  580. /* Setup MAC */
  581. slic_mac_config(adapter);
  582. RcrReset = GRCR_RESET;
  583. } else {
  584. slic_mac_address_config(adapter);
  585. RcrReset = 0;
  586. }
  587. if (adapter->linkduplex == LINK_FULLD) {
  588. /* setup xmtcfg */
  589. value = (GXCR_RESET | /* Always reset */
  590. GXCR_XMTEN | /* Enable transmit */
  591. GXCR_PAUSEEN); /* Enable pause */
  592. slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
  593. /* Setup rcvcfg last */
  594. value = (RcrReset | /* Reset, if linkchange */
  595. GRCR_CTLEN | /* Enable CTL frames */
  596. GRCR_ADDRAEN | /* Address A enable */
  597. GRCR_RCVBAD | /* Rcv bad frames */
  598. (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
  599. } else {
  600. /* setup xmtcfg */
  601. value = (GXCR_RESET | /* Always reset */
  602. GXCR_XMTEN); /* Enable transmit */
  603. slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
  604. /* Setup rcvcfg last */
  605. value = (RcrReset | /* Reset, if linkchange */
  606. GRCR_ADDRAEN | /* Address A enable */
  607. GRCR_RCVBAD | /* Rcv bad frames */
  608. (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
  609. }
  610. if (adapter->state != ADAPT_DOWN) {
  611. /* Only enable receive if we are restarting or running */
  612. value |= GRCR_RCVEN;
  613. }
  614. if (adapter->macopts & MAC_PROMISC)
  615. value |= GRCR_RCVALL;
  616. slic_reg32_write(&slic_regs->slic_wrcfg, value, FLUSH);
  617. }
  618. /*
  619. * Turn off RCV and XMT, power down PHY
  620. */
  621. static void slic_config_clear(struct adapter *adapter)
  622. {
  623. u32 value;
  624. u32 phy_config;
  625. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  626. /* Setup xmtcfg */
  627. value = (GXCR_RESET | /* Always reset */
  628. GXCR_PAUSEEN); /* Enable pause */
  629. slic_reg32_write(&slic_regs->slic_wxcfg, value, FLUSH);
  630. value = (GRCR_RESET | /* Always reset */
  631. GRCR_CTLEN | /* Enable CTL frames */
  632. GRCR_ADDRAEN | /* Address A enable */
  633. (GRCR_HASHSIZE << GRCR_HASHSIZE_SHIFT));
  634. slic_reg32_write(&slic_regs->slic_wrcfg, value, FLUSH);
  635. /* power down phy */
  636. phy_config = (MIICR_REG_PCR | (PCR_POWERDOWN));
  637. slic_reg32_write(&slic_regs->slic_wphy, phy_config, FLUSH);
  638. }
  639. static bool slic_mac_filter(struct adapter *adapter,
  640. struct ether_header *ether_frame)
  641. {
  642. struct net_device *netdev = adapter->netdev;
  643. u32 opts = adapter->macopts;
  644. if (opts & MAC_PROMISC)
  645. return true;
  646. if (is_broadcast_ether_addr(ether_frame->ether_dhost)) {
  647. if (opts & MAC_BCAST) {
  648. adapter->rcv_broadcasts++;
  649. return true;
  650. }
  651. return false;
  652. }
  653. if (is_multicast_ether_addr(ether_frame->ether_dhost)) {
  654. if (opts & MAC_ALLMCAST) {
  655. adapter->rcv_multicasts++;
  656. netdev->stats.multicast++;
  657. return true;
  658. }
  659. if (opts & MAC_MCAST) {
  660. struct mcast_address *mcaddr = adapter->mcastaddrs;
  661. while (mcaddr) {
  662. if (ether_addr_equal(mcaddr->address,
  663. ether_frame->ether_dhost)) {
  664. adapter->rcv_multicasts++;
  665. netdev->stats.multicast++;
  666. return true;
  667. }
  668. mcaddr = mcaddr->next;
  669. }
  670. return false;
  671. }
  672. return false;
  673. }
  674. if (opts & MAC_DIRECTED) {
  675. adapter->rcv_unicasts++;
  676. return true;
  677. }
  678. return false;
  679. }
  680. static int slic_mac_set_address(struct net_device *dev, void *ptr)
  681. {
  682. struct adapter *adapter = netdev_priv(dev);
  683. struct sockaddr *addr = ptr;
  684. if (netif_running(dev))
  685. return -EBUSY;
  686. if (!adapter)
  687. return -EBUSY;
  688. if (!is_valid_ether_addr(addr->sa_data))
  689. return -EINVAL;
  690. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  691. memcpy(adapter->currmacaddr, addr->sa_data, dev->addr_len);
  692. slic_config_set(adapter, true);
  693. return 0;
  694. }
  695. static void slic_timer_load_check(ulong cardaddr)
  696. {
  697. struct sliccard *card = (struct sliccard *)cardaddr;
  698. struct adapter *adapter = card->master;
  699. u32 __iomem *intagg;
  700. u32 load = card->events;
  701. u32 level = 0;
  702. if ((adapter) && (adapter->state == ADAPT_UP) &&
  703. (card->state == CARD_UP) && (slic_global.dynamic_intagg)) {
  704. intagg = &adapter->slic_regs->slic_intagg;
  705. if (adapter->devid == SLIC_1GB_DEVICE_ID) {
  706. if (adapter->linkspeed == LINK_1000MB)
  707. level = 100;
  708. else {
  709. if (load > SLIC_LOAD_5)
  710. level = SLIC_INTAGG_5;
  711. else if (load > SLIC_LOAD_4)
  712. level = SLIC_INTAGG_4;
  713. else if (load > SLIC_LOAD_3)
  714. level = SLIC_INTAGG_3;
  715. else if (load > SLIC_LOAD_2)
  716. level = SLIC_INTAGG_2;
  717. else if (load > SLIC_LOAD_1)
  718. level = SLIC_INTAGG_1;
  719. else
  720. level = SLIC_INTAGG_0;
  721. }
  722. if (card->loadlevel_current != level) {
  723. card->loadlevel_current = level;
  724. slic_reg32_write(intagg, level, FLUSH);
  725. }
  726. } else {
  727. if (load > SLIC_LOAD_5)
  728. level = SLIC_INTAGG_5;
  729. else if (load > SLIC_LOAD_4)
  730. level = SLIC_INTAGG_4;
  731. else if (load > SLIC_LOAD_3)
  732. level = SLIC_INTAGG_3;
  733. else if (load > SLIC_LOAD_2)
  734. level = SLIC_INTAGG_2;
  735. else if (load > SLIC_LOAD_1)
  736. level = SLIC_INTAGG_1;
  737. else
  738. level = SLIC_INTAGG_0;
  739. if (card->loadlevel_current != level) {
  740. card->loadlevel_current = level;
  741. slic_reg32_write(intagg, level, FLUSH);
  742. }
  743. }
  744. }
  745. card->events = 0;
  746. card->loadtimer.expires = jiffies + (SLIC_LOADTIMER_PERIOD * HZ);
  747. add_timer(&card->loadtimer);
  748. }
  749. static int slic_upr_queue_request(struct adapter *adapter,
  750. u32 upr_request,
  751. u32 upr_data,
  752. u32 upr_data_h,
  753. u32 upr_buffer, u32 upr_buffer_h)
  754. {
  755. struct slic_upr *upr;
  756. struct slic_upr *uprqueue;
  757. upr = kmalloc(sizeof(struct slic_upr), GFP_ATOMIC);
  758. if (!upr)
  759. return -ENOMEM;
  760. upr->adapter = adapter->port;
  761. upr->upr_request = upr_request;
  762. upr->upr_data = upr_data;
  763. upr->upr_buffer = upr_buffer;
  764. upr->upr_data_h = upr_data_h;
  765. upr->upr_buffer_h = upr_buffer_h;
  766. upr->next = NULL;
  767. if (adapter->upr_list) {
  768. uprqueue = adapter->upr_list;
  769. while (uprqueue->next)
  770. uprqueue = uprqueue->next;
  771. uprqueue->next = upr;
  772. } else {
  773. adapter->upr_list = upr;
  774. }
  775. return 0;
  776. }
  777. static void slic_upr_start(struct adapter *adapter)
  778. {
  779. struct slic_upr *upr;
  780. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  781. /*
  782. char * ptr1;
  783. char * ptr2;
  784. uint cmdoffset;
  785. */
  786. upr = adapter->upr_list;
  787. if (!upr)
  788. return;
  789. if (adapter->upr_busy)
  790. return;
  791. adapter->upr_busy = 1;
  792. switch (upr->upr_request) {
  793. case SLIC_UPR_STATS:
  794. if (upr->upr_data_h == 0) {
  795. slic_reg32_write(&slic_regs->slic_stats, upr->upr_data,
  796. FLUSH);
  797. } else {
  798. slic_reg64_write(adapter, &slic_regs->slic_stats64,
  799. upr->upr_data,
  800. &slic_regs->slic_addr_upper,
  801. upr->upr_data_h, FLUSH);
  802. }
  803. break;
  804. case SLIC_UPR_RLSR:
  805. slic_reg64_write(adapter, &slic_regs->slic_rlsr, upr->upr_data,
  806. &slic_regs->slic_addr_upper, upr->upr_data_h,
  807. FLUSH);
  808. break;
  809. case SLIC_UPR_RCONFIG:
  810. slic_reg64_write(adapter, &slic_regs->slic_rconfig,
  811. upr->upr_data, &slic_regs->slic_addr_upper,
  812. upr->upr_data_h, FLUSH);
  813. break;
  814. case SLIC_UPR_PING:
  815. slic_reg32_write(&slic_regs->slic_ping, 1, FLUSH);
  816. break;
  817. }
  818. }
  819. static int slic_upr_request(struct adapter *adapter,
  820. u32 upr_request,
  821. u32 upr_data,
  822. u32 upr_data_h,
  823. u32 upr_buffer, u32 upr_buffer_h)
  824. {
  825. int rc;
  826. spin_lock_irqsave(&adapter->upr_lock.lock, adapter->upr_lock.flags);
  827. rc = slic_upr_queue_request(adapter,
  828. upr_request,
  829. upr_data,
  830. upr_data_h, upr_buffer, upr_buffer_h);
  831. if (rc)
  832. goto err_unlock_irq;
  833. slic_upr_start(adapter);
  834. err_unlock_irq:
  835. spin_unlock_irqrestore(&adapter->upr_lock.lock,
  836. adapter->upr_lock.flags);
  837. return rc;
  838. }
  839. static void slic_link_upr_complete(struct adapter *adapter, u32 isr)
  840. {
  841. u32 linkstatus = adapter->pshmem->linkstatus;
  842. uint linkup;
  843. unsigned char linkspeed;
  844. unsigned char linkduplex;
  845. if ((isr & ISR_UPCERR) || (isr & ISR_UPCBSY)) {
  846. struct slic_shmem *pshmem;
  847. pshmem = (struct slic_shmem *)(unsigned long)
  848. adapter->phys_shmem;
  849. #if BITS_PER_LONG == 64
  850. slic_upr_queue_request(adapter,
  851. SLIC_UPR_RLSR,
  852. SLIC_GET_ADDR_LOW(&pshmem->linkstatus),
  853. SLIC_GET_ADDR_HIGH(&pshmem->linkstatus),
  854. 0, 0);
  855. #else
  856. slic_upr_queue_request(adapter,
  857. SLIC_UPR_RLSR,
  858. (u32) &pshmem->linkstatus,
  859. SLIC_GET_ADDR_HIGH(pshmem), 0, 0);
  860. #endif
  861. return;
  862. }
  863. if (adapter->state != ADAPT_UP)
  864. return;
  865. linkup = linkstatus & GIG_LINKUP ? LINK_UP : LINK_DOWN;
  866. if (linkstatus & GIG_SPEED_1000)
  867. linkspeed = LINK_1000MB;
  868. else if (linkstatus & GIG_SPEED_100)
  869. linkspeed = LINK_100MB;
  870. else
  871. linkspeed = LINK_10MB;
  872. if (linkstatus & GIG_FULLDUPLEX)
  873. linkduplex = LINK_FULLD;
  874. else
  875. linkduplex = LINK_HALFD;
  876. if ((adapter->linkstate == LINK_DOWN) && (linkup == LINK_DOWN))
  877. return;
  878. /* link up event, but nothing has changed */
  879. if ((adapter->linkstate == LINK_UP) &&
  880. (linkup == LINK_UP) &&
  881. (adapter->linkspeed == linkspeed) &&
  882. (adapter->linkduplex == linkduplex))
  883. return;
  884. /* link has changed at this point */
  885. /* link has gone from up to down */
  886. if (linkup == LINK_DOWN) {
  887. adapter->linkstate = LINK_DOWN;
  888. return;
  889. }
  890. /* link has gone from down to up */
  891. adapter->linkspeed = linkspeed;
  892. adapter->linkduplex = linkduplex;
  893. if (adapter->linkstate != LINK_UP) {
  894. /* setup the mac */
  895. slic_config_set(adapter, true);
  896. adapter->linkstate = LINK_UP;
  897. netif_start_queue(adapter->netdev);
  898. }
  899. }
  900. static void slic_upr_request_complete(struct adapter *adapter, u32 isr)
  901. {
  902. struct sliccard *card = adapter->card;
  903. struct slic_upr *upr;
  904. spin_lock_irqsave(&adapter->upr_lock.lock, adapter->upr_lock.flags);
  905. upr = adapter->upr_list;
  906. if (!upr) {
  907. spin_unlock_irqrestore(&adapter->upr_lock.lock,
  908. adapter->upr_lock.flags);
  909. return;
  910. }
  911. adapter->upr_list = upr->next;
  912. upr->next = NULL;
  913. adapter->upr_busy = 0;
  914. switch (upr->upr_request) {
  915. case SLIC_UPR_STATS:
  916. {
  917. struct slic_stats *slicstats =
  918. (struct slic_stats *) &adapter->pshmem->inicstats;
  919. struct slic_stats *newstats = slicstats;
  920. struct slic_stats *old = &adapter->inicstats_prev;
  921. struct slicnet_stats *stst = &adapter->slic_stats;
  922. if (isr & ISR_UPCERR) {
  923. dev_err(&adapter->netdev->dev,
  924. "SLIC_UPR_STATS command failed isr[%x]\n",
  925. isr);
  926. break;
  927. }
  928. UPDATE_STATS_GB(stst->tcp.xmit_tcp_segs,
  929. newstats->xmit_tcp_segs_gb,
  930. old->xmit_tcp_segs_gb);
  931. UPDATE_STATS_GB(stst->tcp.xmit_tcp_bytes,
  932. newstats->xmit_tcp_bytes_gb,
  933. old->xmit_tcp_bytes_gb);
  934. UPDATE_STATS_GB(stst->tcp.rcv_tcp_segs,
  935. newstats->rcv_tcp_segs_gb,
  936. old->rcv_tcp_segs_gb);
  937. UPDATE_STATS_GB(stst->tcp.rcv_tcp_bytes,
  938. newstats->rcv_tcp_bytes_gb,
  939. old->rcv_tcp_bytes_gb);
  940. UPDATE_STATS_GB(stst->iface.xmt_bytes,
  941. newstats->xmit_bytes_gb,
  942. old->xmit_bytes_gb);
  943. UPDATE_STATS_GB(stst->iface.xmt_ucast,
  944. newstats->xmit_unicasts_gb,
  945. old->xmit_unicasts_gb);
  946. UPDATE_STATS_GB(stst->iface.rcv_bytes,
  947. newstats->rcv_bytes_gb,
  948. old->rcv_bytes_gb);
  949. UPDATE_STATS_GB(stst->iface.rcv_ucast,
  950. newstats->rcv_unicasts_gb,
  951. old->rcv_unicasts_gb);
  952. UPDATE_STATS_GB(stst->iface.xmt_errors,
  953. newstats->xmit_collisions_gb,
  954. old->xmit_collisions_gb);
  955. UPDATE_STATS_GB(stst->iface.xmt_errors,
  956. newstats->xmit_excess_collisions_gb,
  957. old->xmit_excess_collisions_gb);
  958. UPDATE_STATS_GB(stst->iface.xmt_errors,
  959. newstats->xmit_other_error_gb,
  960. old->xmit_other_error_gb);
  961. UPDATE_STATS_GB(stst->iface.rcv_errors,
  962. newstats->rcv_other_error_gb,
  963. old->rcv_other_error_gb);
  964. UPDATE_STATS_GB(stst->iface.rcv_discards,
  965. newstats->rcv_drops_gb,
  966. old->rcv_drops_gb);
  967. if (newstats->rcv_drops_gb > old->rcv_drops_gb) {
  968. adapter->rcv_drops +=
  969. (newstats->rcv_drops_gb -
  970. old->rcv_drops_gb);
  971. }
  972. memcpy(old, newstats, sizeof(struct slic_stats));
  973. break;
  974. }
  975. case SLIC_UPR_RLSR:
  976. slic_link_upr_complete(adapter, isr);
  977. break;
  978. case SLIC_UPR_RCONFIG:
  979. break;
  980. case SLIC_UPR_PING:
  981. card->pingstatus |= (isr & ISR_PINGDSMASK);
  982. break;
  983. }
  984. kfree(upr);
  985. slic_upr_start(adapter);
  986. spin_unlock_irqrestore(&adapter->upr_lock.lock,
  987. adapter->upr_lock.flags);
  988. }
  989. static int slic_config_get(struct adapter *adapter, u32 config, u32 config_h)
  990. {
  991. return slic_upr_request(adapter, SLIC_UPR_RCONFIG, config, config_h,
  992. 0, 0);
  993. }
  994. /*
  995. * Compute a checksum of the EEPROM according to RFC 1071.
  996. */
  997. static u16 slic_eeprom_cksum(void *eeprom, unsigned len)
  998. {
  999. u16 *wp = eeprom;
  1000. u32 checksum = 0;
  1001. while (len > 1) {
  1002. checksum += *(wp++);
  1003. len -= 2;
  1004. }
  1005. if (len > 0)
  1006. checksum += *(u8 *) wp;
  1007. while (checksum >> 16)
  1008. checksum = (checksum & 0xFFFF) + ((checksum >> 16) & 0xFFFF);
  1009. return ~checksum;
  1010. }
  1011. static void slic_rspqueue_free(struct adapter *adapter)
  1012. {
  1013. int i;
  1014. struct slic_rspqueue *rspq = &adapter->rspqueue;
  1015. for (i = 0; i < rspq->num_pages; i++) {
  1016. if (rspq->vaddr[i]) {
  1017. pci_free_consistent(adapter->pcidev, PAGE_SIZE,
  1018. rspq->vaddr[i], rspq->paddr[i]);
  1019. }
  1020. rspq->vaddr[i] = NULL;
  1021. rspq->paddr[i] = 0;
  1022. }
  1023. rspq->offset = 0;
  1024. rspq->pageindex = 0;
  1025. rspq->rspbuf = NULL;
  1026. }
  1027. static int slic_rspqueue_init(struct adapter *adapter)
  1028. {
  1029. int i;
  1030. struct slic_rspqueue *rspq = &adapter->rspqueue;
  1031. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  1032. u32 paddrh = 0;
  1033. memset(rspq, 0, sizeof(struct slic_rspqueue));
  1034. rspq->num_pages = SLIC_RSPQ_PAGES_GB;
  1035. for (i = 0; i < rspq->num_pages; i++) {
  1036. rspq->vaddr[i] = pci_zalloc_consistent(adapter->pcidev,
  1037. PAGE_SIZE,
  1038. &rspq->paddr[i]);
  1039. if (!rspq->vaddr[i]) {
  1040. dev_err(&adapter->pcidev->dev,
  1041. "pci_alloc_consistent failed\n");
  1042. slic_rspqueue_free(adapter);
  1043. return -ENOMEM;
  1044. }
  1045. if (paddrh == 0) {
  1046. slic_reg32_write(&slic_regs->slic_rbar,
  1047. (rspq->paddr[i] | SLIC_RSPQ_BUFSINPAGE),
  1048. DONT_FLUSH);
  1049. } else {
  1050. slic_reg64_write(adapter, &slic_regs->slic_rbar64,
  1051. (rspq->paddr[i] | SLIC_RSPQ_BUFSINPAGE),
  1052. &slic_regs->slic_addr_upper,
  1053. paddrh, DONT_FLUSH);
  1054. }
  1055. }
  1056. rspq->offset = 0;
  1057. rspq->pageindex = 0;
  1058. rspq->rspbuf = (struct slic_rspbuf *)rspq->vaddr[0];
  1059. return 0;
  1060. }
  1061. static struct slic_rspbuf *slic_rspqueue_getnext(struct adapter *adapter)
  1062. {
  1063. struct slic_rspqueue *rspq = &adapter->rspqueue;
  1064. struct slic_rspbuf *buf;
  1065. if (!(rspq->rspbuf->status))
  1066. return NULL;
  1067. buf = rspq->rspbuf;
  1068. if (++rspq->offset < SLIC_RSPQ_BUFSINPAGE) {
  1069. rspq->rspbuf++;
  1070. } else {
  1071. slic_reg64_write(adapter, &adapter->slic_regs->slic_rbar64,
  1072. (rspq->paddr[rspq->pageindex] | SLIC_RSPQ_BUFSINPAGE),
  1073. &adapter->slic_regs->slic_addr_upper, 0, DONT_FLUSH);
  1074. rspq->pageindex = (rspq->pageindex + 1) % rspq->num_pages;
  1075. rspq->offset = 0;
  1076. rspq->rspbuf = (struct slic_rspbuf *)
  1077. rspq->vaddr[rspq->pageindex];
  1078. }
  1079. return buf;
  1080. }
  1081. static void slic_cmdqmem_free(struct adapter *adapter)
  1082. {
  1083. struct slic_cmdqmem *cmdqmem = &adapter->cmdqmem;
  1084. int i;
  1085. for (i = 0; i < SLIC_CMDQ_MAXPAGES; i++) {
  1086. if (cmdqmem->pages[i]) {
  1087. pci_free_consistent(adapter->pcidev,
  1088. PAGE_SIZE,
  1089. (void *) cmdqmem->pages[i],
  1090. cmdqmem->dma_pages[i]);
  1091. }
  1092. }
  1093. memset(cmdqmem, 0, sizeof(struct slic_cmdqmem));
  1094. }
  1095. static u32 *slic_cmdqmem_addpage(struct adapter *adapter)
  1096. {
  1097. struct slic_cmdqmem *cmdqmem = &adapter->cmdqmem;
  1098. u32 *pageaddr;
  1099. if (cmdqmem->pagecnt >= SLIC_CMDQ_MAXPAGES)
  1100. return NULL;
  1101. pageaddr = pci_alloc_consistent(adapter->pcidev,
  1102. PAGE_SIZE,
  1103. &cmdqmem->dma_pages[cmdqmem->pagecnt]);
  1104. if (!pageaddr)
  1105. return NULL;
  1106. cmdqmem->pages[cmdqmem->pagecnt] = pageaddr;
  1107. cmdqmem->pagecnt++;
  1108. return pageaddr;
  1109. }
  1110. static void slic_cmdq_free(struct adapter *adapter)
  1111. {
  1112. struct slic_hostcmd *cmd;
  1113. cmd = adapter->cmdq_all.head;
  1114. while (cmd) {
  1115. if (cmd->busy) {
  1116. struct sk_buff *tempskb;
  1117. tempskb = cmd->skb;
  1118. if (tempskb) {
  1119. cmd->skb = NULL;
  1120. dev_kfree_skb_irq(tempskb);
  1121. }
  1122. }
  1123. cmd = cmd->next_all;
  1124. }
  1125. memset(&adapter->cmdq_all, 0, sizeof(struct slic_cmdqueue));
  1126. memset(&adapter->cmdq_free, 0, sizeof(struct slic_cmdqueue));
  1127. memset(&adapter->cmdq_done, 0, sizeof(struct slic_cmdqueue));
  1128. slic_cmdqmem_free(adapter);
  1129. }
  1130. static void slic_cmdq_addcmdpage(struct adapter *adapter, u32 *page)
  1131. {
  1132. struct slic_hostcmd *cmd;
  1133. struct slic_hostcmd *prev;
  1134. struct slic_hostcmd *tail;
  1135. struct slic_cmdqueue *cmdq;
  1136. int cmdcnt;
  1137. void *cmdaddr;
  1138. ulong phys_addr;
  1139. u32 phys_addrl;
  1140. u32 phys_addrh;
  1141. struct slic_handle *pslic_handle;
  1142. cmdaddr = page;
  1143. cmd = (struct slic_hostcmd *)cmdaddr;
  1144. cmdcnt = 0;
  1145. phys_addr = virt_to_bus((void *)page);
  1146. phys_addrl = SLIC_GET_ADDR_LOW(phys_addr);
  1147. phys_addrh = SLIC_GET_ADDR_HIGH(phys_addr);
  1148. prev = NULL;
  1149. tail = cmd;
  1150. while ((cmdcnt < SLIC_CMDQ_CMDSINPAGE) &&
  1151. (adapter->slic_handle_ix < 256)) {
  1152. /* Allocate and initialize a SLIC_HANDLE for this command */
  1153. spin_lock_irqsave(&adapter->handle_lock.lock,
  1154. adapter->handle_lock.flags);
  1155. pslic_handle = adapter->pfree_slic_handles;
  1156. adapter->pfree_slic_handles = pslic_handle->next;
  1157. spin_unlock_irqrestore(&adapter->handle_lock.lock,
  1158. adapter->handle_lock.flags);
  1159. pslic_handle->type = SLIC_HANDLE_CMD;
  1160. pslic_handle->address = (void *) cmd;
  1161. pslic_handle->offset = (ushort) adapter->slic_handle_ix++;
  1162. pslic_handle->other_handle = NULL;
  1163. pslic_handle->next = NULL;
  1164. cmd->pslic_handle = pslic_handle;
  1165. cmd->cmd64.hosthandle = pslic_handle->token.handle_token;
  1166. cmd->busy = false;
  1167. cmd->paddrl = phys_addrl;
  1168. cmd->paddrh = phys_addrh;
  1169. cmd->next_all = prev;
  1170. cmd->next = prev;
  1171. prev = cmd;
  1172. phys_addrl += SLIC_HOSTCMD_SIZE;
  1173. cmdaddr += SLIC_HOSTCMD_SIZE;
  1174. cmd = (struct slic_hostcmd *)cmdaddr;
  1175. cmdcnt++;
  1176. }
  1177. cmdq = &adapter->cmdq_all;
  1178. cmdq->count += cmdcnt; /* SLIC_CMDQ_CMDSINPAGE; mooktodo */
  1179. tail->next_all = cmdq->head;
  1180. cmdq->head = prev;
  1181. cmdq = &adapter->cmdq_free;
  1182. spin_lock_irqsave(&cmdq->lock.lock, cmdq->lock.flags);
  1183. cmdq->count += cmdcnt; /* SLIC_CMDQ_CMDSINPAGE; mooktodo */
  1184. tail->next = cmdq->head;
  1185. cmdq->head = prev;
  1186. spin_unlock_irqrestore(&cmdq->lock.lock, cmdq->lock.flags);
  1187. }
  1188. static int slic_cmdq_init(struct adapter *adapter)
  1189. {
  1190. int i;
  1191. u32 *pageaddr;
  1192. memset(&adapter->cmdq_all, 0, sizeof(struct slic_cmdqueue));
  1193. memset(&adapter->cmdq_free, 0, sizeof(struct slic_cmdqueue));
  1194. memset(&adapter->cmdq_done, 0, sizeof(struct slic_cmdqueue));
  1195. spin_lock_init(&adapter->cmdq_all.lock.lock);
  1196. spin_lock_init(&adapter->cmdq_free.lock.lock);
  1197. spin_lock_init(&adapter->cmdq_done.lock.lock);
  1198. memset(&adapter->cmdqmem, 0, sizeof(struct slic_cmdqmem));
  1199. adapter->slic_handle_ix = 1;
  1200. for (i = 0; i < SLIC_CMDQ_INITPAGES; i++) {
  1201. pageaddr = slic_cmdqmem_addpage(adapter);
  1202. if (!pageaddr) {
  1203. slic_cmdq_free(adapter);
  1204. return -ENOMEM;
  1205. }
  1206. slic_cmdq_addcmdpage(adapter, pageaddr);
  1207. }
  1208. adapter->slic_handle_ix = 1;
  1209. return 0;
  1210. }
  1211. static void slic_cmdq_reset(struct adapter *adapter)
  1212. {
  1213. struct slic_hostcmd *hcmd;
  1214. struct sk_buff *skb;
  1215. u32 outstanding;
  1216. spin_lock_irqsave(&adapter->cmdq_free.lock.lock,
  1217. adapter->cmdq_free.lock.flags);
  1218. spin_lock_irqsave(&adapter->cmdq_done.lock.lock,
  1219. adapter->cmdq_done.lock.flags);
  1220. outstanding = adapter->cmdq_all.count - adapter->cmdq_done.count;
  1221. outstanding -= adapter->cmdq_free.count;
  1222. hcmd = adapter->cmdq_all.head;
  1223. while (hcmd) {
  1224. if (hcmd->busy) {
  1225. skb = hcmd->skb;
  1226. hcmd->busy = 0;
  1227. hcmd->skb = NULL;
  1228. dev_kfree_skb_irq(skb);
  1229. }
  1230. hcmd = hcmd->next_all;
  1231. }
  1232. adapter->cmdq_free.count = 0;
  1233. adapter->cmdq_free.head = NULL;
  1234. adapter->cmdq_free.tail = NULL;
  1235. adapter->cmdq_done.count = 0;
  1236. adapter->cmdq_done.head = NULL;
  1237. adapter->cmdq_done.tail = NULL;
  1238. adapter->cmdq_free.head = adapter->cmdq_all.head;
  1239. hcmd = adapter->cmdq_all.head;
  1240. while (hcmd) {
  1241. adapter->cmdq_free.count++;
  1242. hcmd->next = hcmd->next_all;
  1243. hcmd = hcmd->next_all;
  1244. }
  1245. if (adapter->cmdq_free.count != adapter->cmdq_all.count) {
  1246. dev_err(&adapter->netdev->dev,
  1247. "free_count %d != all count %d\n",
  1248. adapter->cmdq_free.count, adapter->cmdq_all.count);
  1249. }
  1250. spin_unlock_irqrestore(&adapter->cmdq_done.lock.lock,
  1251. adapter->cmdq_done.lock.flags);
  1252. spin_unlock_irqrestore(&adapter->cmdq_free.lock.lock,
  1253. adapter->cmdq_free.lock.flags);
  1254. }
  1255. static void slic_cmdq_getdone(struct adapter *adapter)
  1256. {
  1257. struct slic_cmdqueue *done_cmdq = &adapter->cmdq_done;
  1258. struct slic_cmdqueue *free_cmdq = &adapter->cmdq_free;
  1259. spin_lock_irqsave(&done_cmdq->lock.lock, done_cmdq->lock.flags);
  1260. free_cmdq->head = done_cmdq->head;
  1261. free_cmdq->count = done_cmdq->count;
  1262. done_cmdq->head = NULL;
  1263. done_cmdq->tail = NULL;
  1264. done_cmdq->count = 0;
  1265. spin_unlock_irqrestore(&done_cmdq->lock.lock, done_cmdq->lock.flags);
  1266. }
  1267. static struct slic_hostcmd *slic_cmdq_getfree(struct adapter *adapter)
  1268. {
  1269. struct slic_cmdqueue *cmdq = &adapter->cmdq_free;
  1270. struct slic_hostcmd *cmd = NULL;
  1271. lock_and_retry:
  1272. spin_lock_irqsave(&cmdq->lock.lock, cmdq->lock.flags);
  1273. retry:
  1274. cmd = cmdq->head;
  1275. if (cmd) {
  1276. cmdq->head = cmd->next;
  1277. cmdq->count--;
  1278. spin_unlock_irqrestore(&cmdq->lock.lock, cmdq->lock.flags);
  1279. } else {
  1280. slic_cmdq_getdone(adapter);
  1281. cmd = cmdq->head;
  1282. if (cmd) {
  1283. goto retry;
  1284. } else {
  1285. u32 *pageaddr;
  1286. spin_unlock_irqrestore(&cmdq->lock.lock,
  1287. cmdq->lock.flags);
  1288. pageaddr = slic_cmdqmem_addpage(adapter);
  1289. if (pageaddr) {
  1290. slic_cmdq_addcmdpage(adapter, pageaddr);
  1291. goto lock_and_retry;
  1292. }
  1293. }
  1294. }
  1295. return cmd;
  1296. }
  1297. static void slic_cmdq_putdone_irq(struct adapter *adapter,
  1298. struct slic_hostcmd *cmd)
  1299. {
  1300. struct slic_cmdqueue *cmdq = &adapter->cmdq_done;
  1301. spin_lock(&cmdq->lock.lock);
  1302. cmd->busy = 0;
  1303. cmd->next = cmdq->head;
  1304. cmdq->head = cmd;
  1305. cmdq->count++;
  1306. if ((adapter->xmitq_full) && (cmdq->count > 10))
  1307. netif_wake_queue(adapter->netdev);
  1308. spin_unlock(&cmdq->lock.lock);
  1309. }
  1310. static int slic_rcvqueue_fill(struct adapter *adapter)
  1311. {
  1312. void *paddr;
  1313. u32 paddrl;
  1314. u32 paddrh;
  1315. struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
  1316. int i = 0;
  1317. struct device *dev = &adapter->netdev->dev;
  1318. while (i < SLIC_RCVQ_FILLENTRIES) {
  1319. struct slic_rcvbuf *rcvbuf;
  1320. struct sk_buff *skb;
  1321. #ifdef KLUDGE_FOR_4GB_BOUNDARY
  1322. retry_rcvqfill:
  1323. #endif
  1324. skb = alloc_skb(SLIC_RCVQ_RCVBUFSIZE, GFP_ATOMIC);
  1325. if (skb) {
  1326. paddr = (void *)(unsigned long)
  1327. pci_map_single(adapter->pcidev,
  1328. skb->data,
  1329. SLIC_RCVQ_RCVBUFSIZE,
  1330. PCI_DMA_FROMDEVICE);
  1331. paddrl = SLIC_GET_ADDR_LOW(paddr);
  1332. paddrh = SLIC_GET_ADDR_HIGH(paddr);
  1333. skb->len = SLIC_RCVBUF_HEADSIZE;
  1334. rcvbuf = (struct slic_rcvbuf *)skb->head;
  1335. rcvbuf->status = 0;
  1336. skb->next = NULL;
  1337. #ifdef KLUDGE_FOR_4GB_BOUNDARY
  1338. if (paddrl == 0) {
  1339. dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
  1340. __func__);
  1341. dev_err(dev, "skb[%p] PROBLEM\n", skb);
  1342. dev_err(dev, " skbdata[%p]\n", skb->data);
  1343. dev_err(dev, " skblen[%x]\n", skb->len);
  1344. dev_err(dev, " paddr[%p]\n", paddr);
  1345. dev_err(dev, " paddrl[%x]\n", paddrl);
  1346. dev_err(dev, " paddrh[%x]\n", paddrh);
  1347. dev_err(dev, " rcvq->head[%p]\n", rcvq->head);
  1348. dev_err(dev, " rcvq->tail[%p]\n", rcvq->tail);
  1349. dev_err(dev, " rcvq->count[%x]\n", rcvq->count);
  1350. dev_err(dev, "SKIP THIS SKB!!!!!!!!\n");
  1351. goto retry_rcvqfill;
  1352. }
  1353. #else
  1354. if (paddrl == 0) {
  1355. dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
  1356. __func__);
  1357. dev_err(dev, "skb[%p] PROBLEM\n", skb);
  1358. dev_err(dev, " skbdata[%p]\n", skb->data);
  1359. dev_err(dev, " skblen[%x]\n", skb->len);
  1360. dev_err(dev, " paddr[%p]\n", paddr);
  1361. dev_err(dev, " paddrl[%x]\n", paddrl);
  1362. dev_err(dev, " paddrh[%x]\n", paddrh);
  1363. dev_err(dev, " rcvq->head[%p]\n", rcvq->head);
  1364. dev_err(dev, " rcvq->tail[%p]\n", rcvq->tail);
  1365. dev_err(dev, " rcvq->count[%x]\n", rcvq->count);
  1366. dev_err(dev, "GIVE TO CARD ANYWAY\n");
  1367. }
  1368. #endif
  1369. if (paddrh == 0) {
  1370. slic_reg32_write(&adapter->slic_regs->slic_hbar,
  1371. (u32)paddrl, DONT_FLUSH);
  1372. } else {
  1373. slic_reg64_write(adapter,
  1374. &adapter->slic_regs->slic_hbar64,
  1375. paddrl,
  1376. &adapter->slic_regs->slic_addr_upper,
  1377. paddrh, DONT_FLUSH);
  1378. }
  1379. if (rcvq->head)
  1380. rcvq->tail->next = skb;
  1381. else
  1382. rcvq->head = skb;
  1383. rcvq->tail = skb;
  1384. rcvq->count++;
  1385. i++;
  1386. } else {
  1387. dev_err(&adapter->netdev->dev,
  1388. "slic_rcvqueue_fill could only get [%d] skbuffs\n",
  1389. i);
  1390. break;
  1391. }
  1392. }
  1393. return i;
  1394. }
  1395. static void slic_rcvqueue_free(struct adapter *adapter)
  1396. {
  1397. struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
  1398. struct sk_buff *skb;
  1399. while (rcvq->head) {
  1400. skb = rcvq->head;
  1401. rcvq->head = rcvq->head->next;
  1402. dev_kfree_skb(skb);
  1403. }
  1404. rcvq->tail = NULL;
  1405. rcvq->head = NULL;
  1406. rcvq->count = 0;
  1407. }
  1408. static int slic_rcvqueue_init(struct adapter *adapter)
  1409. {
  1410. int i, count;
  1411. struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
  1412. rcvq->tail = NULL;
  1413. rcvq->head = NULL;
  1414. rcvq->size = SLIC_RCVQ_ENTRIES;
  1415. rcvq->errors = 0;
  1416. rcvq->count = 0;
  1417. i = (SLIC_RCVQ_ENTRIES / SLIC_RCVQ_FILLENTRIES);
  1418. count = 0;
  1419. while (i) {
  1420. count += slic_rcvqueue_fill(adapter);
  1421. i--;
  1422. }
  1423. if (rcvq->count < SLIC_RCVQ_MINENTRIES) {
  1424. slic_rcvqueue_free(adapter);
  1425. return -ENOMEM;
  1426. }
  1427. return 0;
  1428. }
  1429. static struct sk_buff *slic_rcvqueue_getnext(struct adapter *adapter)
  1430. {
  1431. struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
  1432. struct sk_buff *skb;
  1433. struct slic_rcvbuf *rcvbuf;
  1434. int count;
  1435. if (rcvq->count) {
  1436. skb = rcvq->head;
  1437. rcvbuf = (struct slic_rcvbuf *)skb->head;
  1438. if (rcvbuf->status & IRHDDR_SVALID) {
  1439. rcvq->head = rcvq->head->next;
  1440. skb->next = NULL;
  1441. rcvq->count--;
  1442. } else {
  1443. skb = NULL;
  1444. }
  1445. } else {
  1446. dev_err(&adapter->netdev->dev,
  1447. "RcvQ Empty!! rcvq[%p] count[%x]\n", rcvq, rcvq->count);
  1448. skb = NULL;
  1449. }
  1450. while (rcvq->count < SLIC_RCVQ_FILLTHRESH) {
  1451. count = slic_rcvqueue_fill(adapter);
  1452. if (!count)
  1453. break;
  1454. }
  1455. if (skb)
  1456. rcvq->errors = 0;
  1457. return skb;
  1458. }
  1459. static u32 slic_rcvqueue_reinsert(struct adapter *adapter, struct sk_buff *skb)
  1460. {
  1461. struct slic_rcvqueue *rcvq = &adapter->rcvqueue;
  1462. void *paddr;
  1463. u32 paddrl;
  1464. u32 paddrh;
  1465. struct slic_rcvbuf *rcvbuf = (struct slic_rcvbuf *)skb->head;
  1466. struct device *dev;
  1467. paddr = (void *)(unsigned long)
  1468. pci_map_single(adapter->pcidev, skb->head,
  1469. SLIC_RCVQ_RCVBUFSIZE, PCI_DMA_FROMDEVICE);
  1470. rcvbuf->status = 0;
  1471. skb->next = NULL;
  1472. paddrl = SLIC_GET_ADDR_LOW(paddr);
  1473. paddrh = SLIC_GET_ADDR_HIGH(paddr);
  1474. if (paddrl == 0) {
  1475. dev = &adapter->netdev->dev;
  1476. dev_err(dev, "%s: LOW 32bits PHYSICAL ADDRESS == 0\n",
  1477. __func__);
  1478. dev_err(dev, "skb[%p] PROBLEM\n", skb);
  1479. dev_err(dev, " skbdata[%p]\n", skb->data);
  1480. dev_err(dev, " skblen[%x]\n", skb->len);
  1481. dev_err(dev, " paddr[%p]\n", paddr);
  1482. dev_err(dev, " paddrl[%x]\n", paddrl);
  1483. dev_err(dev, " paddrh[%x]\n", paddrh);
  1484. dev_err(dev, " rcvq->head[%p]\n", rcvq->head);
  1485. dev_err(dev, " rcvq->tail[%p]\n", rcvq->tail);
  1486. dev_err(dev, " rcvq->count[%x]\n", rcvq->count);
  1487. }
  1488. if (paddrh == 0) {
  1489. slic_reg32_write(&adapter->slic_regs->slic_hbar, (u32)paddrl,
  1490. DONT_FLUSH);
  1491. } else {
  1492. slic_reg64_write(adapter, &adapter->slic_regs->slic_hbar64,
  1493. paddrl, &adapter->slic_regs->slic_addr_upper,
  1494. paddrh, DONT_FLUSH);
  1495. }
  1496. if (rcvq->head)
  1497. rcvq->tail->next = skb;
  1498. else
  1499. rcvq->head = skb;
  1500. rcvq->tail = skb;
  1501. rcvq->count++;
  1502. return rcvq->count;
  1503. }
  1504. /*
  1505. * slic_link_event_handler -
  1506. *
  1507. * Initiate a link configuration sequence. The link configuration begins
  1508. * by issuing a READ_LINK_STATUS command to the Utility Processor on the
  1509. * SLIC. Since the command finishes asynchronously, the slic_upr_comlete
  1510. * routine will follow it up witha UP configuration write command, which
  1511. * will also complete asynchronously.
  1512. *
  1513. */
  1514. static void slic_link_event_handler(struct adapter *adapter)
  1515. {
  1516. int status;
  1517. struct slic_shmem *pshmem;
  1518. if (adapter->state != ADAPT_UP) {
  1519. /* Adapter is not operational. Ignore. */
  1520. return;
  1521. }
  1522. pshmem = (struct slic_shmem *)(unsigned long)adapter->phys_shmem;
  1523. #if BITS_PER_LONG == 64
  1524. status = slic_upr_request(adapter,
  1525. SLIC_UPR_RLSR,
  1526. SLIC_GET_ADDR_LOW(&pshmem->linkstatus),
  1527. SLIC_GET_ADDR_HIGH(&pshmem->linkstatus),
  1528. 0, 0);
  1529. #else
  1530. status = slic_upr_request(adapter, SLIC_UPR_RLSR,
  1531. (u32) &pshmem->linkstatus, /* no 4GB wrap guaranteed */
  1532. 0, 0, 0);
  1533. #endif
  1534. }
  1535. static void slic_init_cleanup(struct adapter *adapter)
  1536. {
  1537. if (adapter->intrregistered) {
  1538. adapter->intrregistered = 0;
  1539. free_irq(adapter->netdev->irq, adapter->netdev);
  1540. }
  1541. if (adapter->pshmem) {
  1542. pci_free_consistent(adapter->pcidev,
  1543. sizeof(struct slic_shmem),
  1544. adapter->pshmem, adapter->phys_shmem);
  1545. adapter->pshmem = NULL;
  1546. adapter->phys_shmem = (dma_addr_t)(unsigned long)NULL;
  1547. }
  1548. if (adapter->pingtimerset) {
  1549. adapter->pingtimerset = 0;
  1550. del_timer(&adapter->pingtimer);
  1551. }
  1552. slic_rspqueue_free(adapter);
  1553. slic_cmdq_free(adapter);
  1554. slic_rcvqueue_free(adapter);
  1555. }
  1556. /*
  1557. * Allocate a mcast_address structure to hold the multicast address.
  1558. * Link it in.
  1559. */
  1560. static int slic_mcast_add_list(struct adapter *adapter, char *address)
  1561. {
  1562. struct mcast_address *mcaddr, *mlist;
  1563. /* Check to see if it already exists */
  1564. mlist = adapter->mcastaddrs;
  1565. while (mlist) {
  1566. if (ether_addr_equal(mlist->address, address))
  1567. return 0;
  1568. mlist = mlist->next;
  1569. }
  1570. /* Doesn't already exist. Allocate a structure to hold it */
  1571. mcaddr = kmalloc(sizeof(struct mcast_address), GFP_ATOMIC);
  1572. if (mcaddr == NULL)
  1573. return 1;
  1574. memcpy(mcaddr->address, address, ETH_ALEN);
  1575. mcaddr->next = adapter->mcastaddrs;
  1576. adapter->mcastaddrs = mcaddr;
  1577. return 0;
  1578. }
  1579. static void slic_mcast_set_list(struct net_device *dev)
  1580. {
  1581. struct adapter *adapter = netdev_priv(dev);
  1582. int status = 0;
  1583. char *addresses;
  1584. struct netdev_hw_addr *ha;
  1585. netdev_for_each_mc_addr(ha, dev) {
  1586. addresses = (char *) &ha->addr;
  1587. status = slic_mcast_add_list(adapter, addresses);
  1588. if (status != 0)
  1589. break;
  1590. slic_mcast_set_bit(adapter, addresses);
  1591. }
  1592. if (adapter->devflags_prev != dev->flags) {
  1593. adapter->macopts = MAC_DIRECTED;
  1594. if (dev->flags) {
  1595. if (dev->flags & IFF_BROADCAST)
  1596. adapter->macopts |= MAC_BCAST;
  1597. if (dev->flags & IFF_PROMISC)
  1598. adapter->macopts |= MAC_PROMISC;
  1599. if (dev->flags & IFF_ALLMULTI)
  1600. adapter->macopts |= MAC_ALLMCAST;
  1601. if (dev->flags & IFF_MULTICAST)
  1602. adapter->macopts |= MAC_MCAST;
  1603. }
  1604. adapter->devflags_prev = dev->flags;
  1605. slic_config_set(adapter, true);
  1606. } else {
  1607. if (status == 0)
  1608. slic_mcast_set_mask(adapter);
  1609. }
  1610. }
  1611. #define XMIT_FAIL_LINK_STATE 1
  1612. #define XMIT_FAIL_ZERO_LENGTH 2
  1613. #define XMIT_FAIL_HOSTCMD_FAIL 3
  1614. static void slic_xmit_build_request(struct adapter *adapter,
  1615. struct slic_hostcmd *hcmd, struct sk_buff *skb)
  1616. {
  1617. struct slic_host64_cmd *ihcmd;
  1618. ulong phys_addr;
  1619. ihcmd = &hcmd->cmd64;
  1620. ihcmd->flags = (adapter->port << IHFLG_IFSHFT);
  1621. ihcmd->command = IHCMD_XMT_REQ;
  1622. ihcmd->u.slic_buffers.totlen = skb->len;
  1623. phys_addr = pci_map_single(adapter->pcidev, skb->data, skb->len,
  1624. PCI_DMA_TODEVICE);
  1625. ihcmd->u.slic_buffers.bufs[0].paddrl = SLIC_GET_ADDR_LOW(phys_addr);
  1626. ihcmd->u.slic_buffers.bufs[0].paddrh = SLIC_GET_ADDR_HIGH(phys_addr);
  1627. ihcmd->u.slic_buffers.bufs[0].length = skb->len;
  1628. #if BITS_PER_LONG == 64
  1629. hcmd->cmdsize = (u32) ((((u64)&ihcmd->u.slic_buffers.bufs[1] -
  1630. (u64) hcmd) + 31) >> 5);
  1631. #else
  1632. hcmd->cmdsize = ((((u32) &ihcmd->u.slic_buffers.bufs[1] -
  1633. (u32) hcmd) + 31) >> 5);
  1634. #endif
  1635. }
  1636. static void slic_xmit_fail(struct adapter *adapter,
  1637. struct sk_buff *skb,
  1638. void *cmd, u32 skbtype, u32 status)
  1639. {
  1640. if (adapter->xmitq_full)
  1641. netif_stop_queue(adapter->netdev);
  1642. if ((cmd == NULL) && (status <= XMIT_FAIL_HOSTCMD_FAIL)) {
  1643. switch (status) {
  1644. case XMIT_FAIL_LINK_STATE:
  1645. dev_err(&adapter->netdev->dev,
  1646. "reject xmit skb[%p: %x] linkstate[%s] adapter[%s:%d] card[%s:%d]\n",
  1647. skb, skb->pkt_type,
  1648. SLIC_LINKSTATE(adapter->linkstate),
  1649. SLIC_ADAPTER_STATE(adapter->state),
  1650. adapter->state,
  1651. SLIC_CARD_STATE(adapter->card->state),
  1652. adapter->card->state);
  1653. break;
  1654. case XMIT_FAIL_ZERO_LENGTH:
  1655. dev_err(&adapter->netdev->dev,
  1656. "xmit_start skb->len == 0 skb[%p] type[%x]\n",
  1657. skb, skb->pkt_type);
  1658. break;
  1659. case XMIT_FAIL_HOSTCMD_FAIL:
  1660. dev_err(&adapter->netdev->dev,
  1661. "xmit_start skb[%p] type[%x] No host commands available\n", skb, skb->pkt_type);
  1662. break;
  1663. }
  1664. }
  1665. dev_kfree_skb(skb);
  1666. adapter->netdev->stats.tx_dropped++;
  1667. }
  1668. static void slic_rcv_handle_error(struct adapter *adapter,
  1669. struct slic_rcvbuf *rcvbuf)
  1670. {
  1671. struct slic_hddr_wds *hdr = (struct slic_hddr_wds *)rcvbuf->data;
  1672. struct net_device *netdev = adapter->netdev;
  1673. if (adapter->devid != SLIC_1GB_DEVICE_ID) {
  1674. if (hdr->frame_status14 & VRHSTAT_802OE)
  1675. adapter->if_events.oflow802++;
  1676. if (hdr->frame_status14 & VRHSTAT_TPOFLO)
  1677. adapter->if_events.Tprtoflow++;
  1678. if (hdr->frame_status_b14 & VRHSTATB_802UE)
  1679. adapter->if_events.uflow802++;
  1680. if (hdr->frame_status_b14 & VRHSTATB_RCVE) {
  1681. adapter->if_events.rcvearly++;
  1682. netdev->stats.rx_fifo_errors++;
  1683. }
  1684. if (hdr->frame_status_b14 & VRHSTATB_BUFF) {
  1685. adapter->if_events.Bufov++;
  1686. netdev->stats.rx_over_errors++;
  1687. }
  1688. if (hdr->frame_status_b14 & VRHSTATB_CARRE) {
  1689. adapter->if_events.Carre++;
  1690. netdev->stats.tx_carrier_errors++;
  1691. }
  1692. if (hdr->frame_status_b14 & VRHSTATB_LONGE)
  1693. adapter->if_events.Longe++;
  1694. if (hdr->frame_status_b14 & VRHSTATB_PREA)
  1695. adapter->if_events.Invp++;
  1696. if (hdr->frame_status_b14 & VRHSTATB_CRC) {
  1697. adapter->if_events.Crc++;
  1698. netdev->stats.rx_crc_errors++;
  1699. }
  1700. if (hdr->frame_status_b14 & VRHSTATB_DRBL)
  1701. adapter->if_events.Drbl++;
  1702. if (hdr->frame_status_b14 & VRHSTATB_CODE)
  1703. adapter->if_events.Code++;
  1704. if (hdr->frame_status_b14 & VRHSTATB_TPCSUM)
  1705. adapter->if_events.TpCsum++;
  1706. if (hdr->frame_status_b14 & VRHSTATB_TPHLEN)
  1707. adapter->if_events.TpHlen++;
  1708. if (hdr->frame_status_b14 & VRHSTATB_IPCSUM)
  1709. adapter->if_events.IpCsum++;
  1710. if (hdr->frame_status_b14 & VRHSTATB_IPLERR)
  1711. adapter->if_events.IpLen++;
  1712. if (hdr->frame_status_b14 & VRHSTATB_IPHERR)
  1713. adapter->if_events.IpHlen++;
  1714. } else {
  1715. if (hdr->frame_statusGB & VGBSTAT_XPERR) {
  1716. u32 xerr = hdr->frame_statusGB >> VGBSTAT_XERRSHFT;
  1717. if (xerr == VGBSTAT_XCSERR)
  1718. adapter->if_events.TpCsum++;
  1719. if (xerr == VGBSTAT_XUFLOW)
  1720. adapter->if_events.Tprtoflow++;
  1721. if (xerr == VGBSTAT_XHLEN)
  1722. adapter->if_events.TpHlen++;
  1723. }
  1724. if (hdr->frame_statusGB & VGBSTAT_NETERR) {
  1725. u32 nerr =
  1726. (hdr->
  1727. frame_statusGB >> VGBSTAT_NERRSHFT) &
  1728. VGBSTAT_NERRMSK;
  1729. if (nerr == VGBSTAT_NCSERR)
  1730. adapter->if_events.IpCsum++;
  1731. if (nerr == VGBSTAT_NUFLOW)
  1732. adapter->if_events.IpLen++;
  1733. if (nerr == VGBSTAT_NHLEN)
  1734. adapter->if_events.IpHlen++;
  1735. }
  1736. if (hdr->frame_statusGB & VGBSTAT_LNKERR) {
  1737. u32 lerr = hdr->frame_statusGB & VGBSTAT_LERRMSK;
  1738. if (lerr == VGBSTAT_LDEARLY)
  1739. adapter->if_events.rcvearly++;
  1740. if (lerr == VGBSTAT_LBOFLO)
  1741. adapter->if_events.Bufov++;
  1742. if (lerr == VGBSTAT_LCODERR)
  1743. adapter->if_events.Code++;
  1744. if (lerr == VGBSTAT_LDBLNBL)
  1745. adapter->if_events.Drbl++;
  1746. if (lerr == VGBSTAT_LCRCERR)
  1747. adapter->if_events.Crc++;
  1748. if (lerr == VGBSTAT_LOFLO)
  1749. adapter->if_events.oflow802++;
  1750. if (lerr == VGBSTAT_LUFLO)
  1751. adapter->if_events.uflow802++;
  1752. }
  1753. }
  1754. }
  1755. #define TCP_OFFLOAD_FRAME_PUSHFLAG 0x10000000
  1756. #define M_FAST_PATH 0x0040
  1757. static void slic_rcv_handler(struct adapter *adapter)
  1758. {
  1759. struct net_device *netdev = adapter->netdev;
  1760. struct sk_buff *skb;
  1761. struct slic_rcvbuf *rcvbuf;
  1762. u32 frames = 0;
  1763. while ((skb = slic_rcvqueue_getnext(adapter))) {
  1764. u32 rx_bytes;
  1765. rcvbuf = (struct slic_rcvbuf *)skb->head;
  1766. adapter->card->events++;
  1767. if (rcvbuf->status & IRHDDR_ERR) {
  1768. adapter->rx_errors++;
  1769. slic_rcv_handle_error(adapter, rcvbuf);
  1770. slic_rcvqueue_reinsert(adapter, skb);
  1771. continue;
  1772. }
  1773. if (!slic_mac_filter(adapter, (struct ether_header *)
  1774. rcvbuf->data)) {
  1775. slic_rcvqueue_reinsert(adapter, skb);
  1776. continue;
  1777. }
  1778. skb_pull(skb, SLIC_RCVBUF_HEADSIZE);
  1779. rx_bytes = (rcvbuf->length & IRHDDR_FLEN_MSK);
  1780. skb_put(skb, rx_bytes);
  1781. netdev->stats.rx_packets++;
  1782. netdev->stats.rx_bytes += rx_bytes;
  1783. #if SLIC_OFFLOAD_IP_CHECKSUM
  1784. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1785. #endif
  1786. skb->dev = adapter->netdev;
  1787. skb->protocol = eth_type_trans(skb, skb->dev);
  1788. netif_rx(skb);
  1789. ++frames;
  1790. #if SLIC_INTERRUPT_PROCESS_LIMIT
  1791. if (frames >= SLIC_RCVQ_MAX_PROCESS_ISR) {
  1792. adapter->rcv_interrupt_yields++;
  1793. break;
  1794. }
  1795. #endif
  1796. }
  1797. adapter->max_isr_rcvs = max(adapter->max_isr_rcvs, frames);
  1798. }
  1799. static void slic_xmit_complete(struct adapter *adapter)
  1800. {
  1801. struct slic_hostcmd *hcmd;
  1802. struct slic_rspbuf *rspbuf;
  1803. u32 frames = 0;
  1804. struct slic_handle_word slic_handle_word;
  1805. do {
  1806. rspbuf = slic_rspqueue_getnext(adapter);
  1807. if (!rspbuf)
  1808. break;
  1809. adapter->xmit_completes++;
  1810. adapter->card->events++;
  1811. /*
  1812. Get the complete host command buffer
  1813. */
  1814. slic_handle_word.handle_token = rspbuf->hosthandle;
  1815. hcmd =
  1816. (struct slic_hostcmd *)
  1817. adapter->slic_handles[slic_handle_word.handle_index].
  1818. address;
  1819. /* hcmd = (struct slic_hostcmd *) rspbuf->hosthandle; */
  1820. if (hcmd->type == SLIC_CMD_DUMB) {
  1821. if (hcmd->skb)
  1822. dev_kfree_skb_irq(hcmd->skb);
  1823. slic_cmdq_putdone_irq(adapter, hcmd);
  1824. }
  1825. rspbuf->status = 0;
  1826. rspbuf->hosthandle = 0;
  1827. frames++;
  1828. } while (1);
  1829. adapter->max_isr_xmits = max(adapter->max_isr_xmits, frames);
  1830. }
  1831. static void slic_interrupt_card_up(u32 isr, struct adapter *adapter,
  1832. struct net_device *dev)
  1833. {
  1834. if (isr & ~ISR_IO) {
  1835. if (isr & ISR_ERR) {
  1836. adapter->error_interrupts++;
  1837. if (isr & ISR_RMISS) {
  1838. int count;
  1839. int pre_count;
  1840. int errors;
  1841. struct slic_rcvqueue *rcvq =
  1842. &adapter->rcvqueue;
  1843. adapter->error_rmiss_interrupts++;
  1844. if (!rcvq->errors)
  1845. rcv_count = rcvq->count;
  1846. pre_count = rcvq->count;
  1847. errors = rcvq->errors;
  1848. while (rcvq->count < SLIC_RCVQ_FILLTHRESH) {
  1849. count = slic_rcvqueue_fill(adapter);
  1850. if (!count)
  1851. break;
  1852. }
  1853. } else if (isr & ISR_XDROP) {
  1854. dev_err(&dev->dev,
  1855. "isr & ISR_ERR [%x] ISR_XDROP\n", isr);
  1856. } else {
  1857. dev_err(&dev->dev,
  1858. "isr & ISR_ERR [%x]\n",
  1859. isr);
  1860. }
  1861. }
  1862. if (isr & ISR_LEVENT) {
  1863. adapter->linkevent_interrupts++;
  1864. slic_link_event_handler(adapter);
  1865. }
  1866. if ((isr & ISR_UPC) || (isr & ISR_UPCERR) ||
  1867. (isr & ISR_UPCBSY)) {
  1868. adapter->upr_interrupts++;
  1869. slic_upr_request_complete(adapter, isr);
  1870. }
  1871. }
  1872. if (isr & ISR_RCV) {
  1873. adapter->rcv_interrupts++;
  1874. slic_rcv_handler(adapter);
  1875. }
  1876. if (isr & ISR_CMD) {
  1877. adapter->xmit_interrupts++;
  1878. slic_xmit_complete(adapter);
  1879. }
  1880. }
  1881. static irqreturn_t slic_interrupt(int irq, void *dev_id)
  1882. {
  1883. struct net_device *dev = (struct net_device *)dev_id;
  1884. struct adapter *adapter = netdev_priv(dev);
  1885. u32 isr;
  1886. if ((adapter->pshmem) && (adapter->pshmem->isr)) {
  1887. slic_reg32_write(&adapter->slic_regs->slic_icr,
  1888. ICR_INT_MASK, FLUSH);
  1889. isr = adapter->isrcopy = adapter->pshmem->isr;
  1890. adapter->pshmem->isr = 0;
  1891. adapter->num_isrs++;
  1892. switch (adapter->card->state) {
  1893. case CARD_UP:
  1894. slic_interrupt_card_up(isr, adapter, dev);
  1895. break;
  1896. case CARD_DOWN:
  1897. if ((isr & ISR_UPC) ||
  1898. (isr & ISR_UPCERR) || (isr & ISR_UPCBSY)) {
  1899. adapter->upr_interrupts++;
  1900. slic_upr_request_complete(adapter, isr);
  1901. }
  1902. break;
  1903. }
  1904. adapter->isrcopy = 0;
  1905. adapter->all_reg_writes += 2;
  1906. adapter->isr_reg_writes++;
  1907. slic_reg32_write(&adapter->slic_regs->slic_isr, 0, FLUSH);
  1908. } else {
  1909. adapter->false_interrupts++;
  1910. }
  1911. return IRQ_HANDLED;
  1912. }
  1913. #define NORMAL_ETHFRAME 0
  1914. static netdev_tx_t slic_xmit_start(struct sk_buff *skb, struct net_device *dev)
  1915. {
  1916. struct sliccard *card;
  1917. struct adapter *adapter = netdev_priv(dev);
  1918. struct slic_hostcmd *hcmd = NULL;
  1919. u32 status = 0;
  1920. void *offloadcmd = NULL;
  1921. card = adapter->card;
  1922. if ((adapter->linkstate != LINK_UP) ||
  1923. (adapter->state != ADAPT_UP) || (card->state != CARD_UP)) {
  1924. status = XMIT_FAIL_LINK_STATE;
  1925. goto xmit_fail;
  1926. } else if (skb->len == 0) {
  1927. status = XMIT_FAIL_ZERO_LENGTH;
  1928. goto xmit_fail;
  1929. }
  1930. hcmd = slic_cmdq_getfree(adapter);
  1931. if (!hcmd) {
  1932. adapter->xmitq_full = 1;
  1933. status = XMIT_FAIL_HOSTCMD_FAIL;
  1934. goto xmit_fail;
  1935. }
  1936. hcmd->skb = skb;
  1937. hcmd->busy = 1;
  1938. hcmd->type = SLIC_CMD_DUMB;
  1939. slic_xmit_build_request(adapter, hcmd, skb);
  1940. dev->stats.tx_packets++;
  1941. dev->stats.tx_bytes += skb->len;
  1942. #ifdef DEBUG_DUMP
  1943. if (adapter->kill_card) {
  1944. struct slic_host64_cmd ihcmd;
  1945. ihcmd = &hcmd->cmd64;
  1946. ihcmd->flags |= 0x40;
  1947. adapter->kill_card = 0; /* only do this once */
  1948. }
  1949. #endif
  1950. if (hcmd->paddrh == 0) {
  1951. slic_reg32_write(&adapter->slic_regs->slic_cbar,
  1952. (hcmd->paddrl | hcmd->cmdsize), DONT_FLUSH);
  1953. } else {
  1954. slic_reg64_write(adapter, &adapter->slic_regs->slic_cbar64,
  1955. (hcmd->paddrl | hcmd->cmdsize),
  1956. &adapter->slic_regs->slic_addr_upper,
  1957. hcmd->paddrh, DONT_FLUSH);
  1958. }
  1959. xmit_done:
  1960. return NETDEV_TX_OK;
  1961. xmit_fail:
  1962. slic_xmit_fail(adapter, skb, offloadcmd, NORMAL_ETHFRAME, status);
  1963. goto xmit_done;
  1964. }
  1965. static void slic_adapter_freeresources(struct adapter *adapter)
  1966. {
  1967. slic_init_cleanup(adapter);
  1968. adapter->error_interrupts = 0;
  1969. adapter->rcv_interrupts = 0;
  1970. adapter->xmit_interrupts = 0;
  1971. adapter->linkevent_interrupts = 0;
  1972. adapter->upr_interrupts = 0;
  1973. adapter->num_isrs = 0;
  1974. adapter->xmit_completes = 0;
  1975. adapter->rcv_broadcasts = 0;
  1976. adapter->rcv_multicasts = 0;
  1977. adapter->rcv_unicasts = 0;
  1978. }
  1979. static int slic_adapter_allocresources(struct adapter *adapter)
  1980. {
  1981. if (!adapter->intrregistered) {
  1982. int retval;
  1983. spin_unlock_irqrestore(&slic_global.driver_lock.lock,
  1984. slic_global.driver_lock.flags);
  1985. retval = request_irq(adapter->netdev->irq,
  1986. &slic_interrupt,
  1987. IRQF_SHARED,
  1988. adapter->netdev->name, adapter->netdev);
  1989. spin_lock_irqsave(&slic_global.driver_lock.lock,
  1990. slic_global.driver_lock.flags);
  1991. if (retval) {
  1992. dev_err(&adapter->netdev->dev,
  1993. "request_irq (%s) FAILED [%x]\n",
  1994. adapter->netdev->name, retval);
  1995. return retval;
  1996. }
  1997. adapter->intrregistered = 1;
  1998. }
  1999. return 0;
  2000. }
  2001. /*
  2002. * slic_if_init
  2003. *
  2004. * Perform initialization of our slic interface.
  2005. *
  2006. */
  2007. static int slic_if_init(struct adapter *adapter)
  2008. {
  2009. struct sliccard *card = adapter->card;
  2010. struct net_device *dev = adapter->netdev;
  2011. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  2012. struct slic_shmem *pshmem;
  2013. int rc;
  2014. /* adapter should be down at this point */
  2015. if (adapter->state != ADAPT_DOWN) {
  2016. dev_err(&dev->dev, "%s: adapter->state != ADAPT_DOWN\n",
  2017. __func__);
  2018. rc = -EIO;
  2019. goto err;
  2020. }
  2021. adapter->devflags_prev = dev->flags;
  2022. adapter->macopts = MAC_DIRECTED;
  2023. if (dev->flags) {
  2024. if (dev->flags & IFF_BROADCAST)
  2025. adapter->macopts |= MAC_BCAST;
  2026. if (dev->flags & IFF_PROMISC)
  2027. adapter->macopts |= MAC_PROMISC;
  2028. if (dev->flags & IFF_ALLMULTI)
  2029. adapter->macopts |= MAC_ALLMCAST;
  2030. if (dev->flags & IFF_MULTICAST)
  2031. adapter->macopts |= MAC_MCAST;
  2032. }
  2033. rc = slic_adapter_allocresources(adapter);
  2034. if (rc) {
  2035. dev_err(&dev->dev,
  2036. "%s: slic_adapter_allocresources FAILED %x\n",
  2037. __func__, rc);
  2038. slic_adapter_freeresources(adapter);
  2039. goto err;
  2040. }
  2041. if (!adapter->queues_initialized) {
  2042. rc = slic_rspqueue_init(adapter);
  2043. if (rc)
  2044. goto err;
  2045. rc = slic_cmdq_init(adapter);
  2046. if (rc)
  2047. goto err;
  2048. rc = slic_rcvqueue_init(adapter);
  2049. if (rc)
  2050. goto err;
  2051. adapter->queues_initialized = 1;
  2052. }
  2053. slic_reg32_write(&slic_regs->slic_icr, ICR_INT_OFF, FLUSH);
  2054. mdelay(1);
  2055. if (!adapter->isp_initialized) {
  2056. pshmem = (struct slic_shmem *)(unsigned long)
  2057. adapter->phys_shmem;
  2058. spin_lock_irqsave(&adapter->bit64reglock.lock,
  2059. adapter->bit64reglock.flags);
  2060. #if BITS_PER_LONG == 64
  2061. slic_reg32_write(&slic_regs->slic_addr_upper,
  2062. SLIC_GET_ADDR_HIGH(&pshmem->isr), DONT_FLUSH);
  2063. slic_reg32_write(&slic_regs->slic_isp,
  2064. SLIC_GET_ADDR_LOW(&pshmem->isr), FLUSH);
  2065. #else
  2066. slic_reg32_write(&slic_regs->slic_addr_upper, 0, DONT_FLUSH);
  2067. slic_reg32_write(&slic_regs->slic_isp, (u32)&pshmem->isr, FLUSH);
  2068. #endif
  2069. spin_unlock_irqrestore(&adapter->bit64reglock.lock,
  2070. adapter->bit64reglock.flags);
  2071. adapter->isp_initialized = 1;
  2072. }
  2073. adapter->state = ADAPT_UP;
  2074. if (!card->loadtimerset) {
  2075. init_timer(&card->loadtimer);
  2076. card->loadtimer.expires =
  2077. jiffies + (SLIC_LOADTIMER_PERIOD * HZ);
  2078. card->loadtimer.data = (ulong) card;
  2079. card->loadtimer.function = &slic_timer_load_check;
  2080. add_timer(&card->loadtimer);
  2081. card->loadtimerset = 1;
  2082. }
  2083. if (!adapter->pingtimerset) {
  2084. init_timer(&adapter->pingtimer);
  2085. adapter->pingtimer.expires =
  2086. jiffies + (PING_TIMER_INTERVAL * HZ);
  2087. adapter->pingtimer.data = (ulong) dev;
  2088. adapter->pingtimer.function = &slic_timer_ping;
  2089. add_timer(&adapter->pingtimer);
  2090. adapter->pingtimerset = 1;
  2091. adapter->card->pingstatus = ISR_PINGMASK;
  2092. }
  2093. /*
  2094. * clear any pending events, then enable interrupts
  2095. */
  2096. adapter->isrcopy = 0;
  2097. adapter->pshmem->isr = 0;
  2098. slic_reg32_write(&slic_regs->slic_isr, 0, FLUSH);
  2099. slic_reg32_write(&slic_regs->slic_icr, ICR_INT_ON, FLUSH);
  2100. slic_link_config(adapter, LINK_AUTOSPEED, LINK_AUTOD);
  2101. slic_link_event_handler(adapter);
  2102. err:
  2103. return rc;
  2104. }
  2105. static int slic_entry_open(struct net_device *dev)
  2106. {
  2107. struct adapter *adapter = netdev_priv(dev);
  2108. struct sliccard *card = adapter->card;
  2109. int status;
  2110. netif_stop_queue(adapter->netdev);
  2111. spin_lock_irqsave(&slic_global.driver_lock.lock,
  2112. slic_global.driver_lock.flags);
  2113. if (!adapter->activated) {
  2114. card->adapters_activated++;
  2115. slic_global.num_slic_ports_active++;
  2116. adapter->activated = 1;
  2117. }
  2118. status = slic_if_init(adapter);
  2119. if (status != 0) {
  2120. if (adapter->activated) {
  2121. card->adapters_activated--;
  2122. slic_global.num_slic_ports_active--;
  2123. adapter->activated = 0;
  2124. }
  2125. goto spin_unlock;
  2126. }
  2127. if (!card->master)
  2128. card->master = adapter;
  2129. spin_unlock:
  2130. spin_unlock_irqrestore(&slic_global.driver_lock.lock,
  2131. slic_global.driver_lock.flags);
  2132. return status;
  2133. }
  2134. static void slic_card_cleanup(struct sliccard *card)
  2135. {
  2136. if (card->loadtimerset) {
  2137. card->loadtimerset = 0;
  2138. del_timer_sync(&card->loadtimer);
  2139. }
  2140. kfree(card);
  2141. }
  2142. static void slic_entry_remove(struct pci_dev *pcidev)
  2143. {
  2144. struct net_device *dev = pci_get_drvdata(pcidev);
  2145. struct adapter *adapter = netdev_priv(dev);
  2146. struct sliccard *card;
  2147. struct mcast_address *mcaddr, *mlist;
  2148. unregister_netdev(dev);
  2149. slic_adapter_freeresources(adapter);
  2150. slic_unmap_mmio_space(adapter);
  2151. /* free multicast addresses */
  2152. mlist = adapter->mcastaddrs;
  2153. while (mlist) {
  2154. mcaddr = mlist;
  2155. mlist = mlist->next;
  2156. kfree(mcaddr);
  2157. }
  2158. card = adapter->card;
  2159. card->adapters_allocated--;
  2160. adapter->allocated = 0;
  2161. if (!card->adapters_allocated) {
  2162. struct sliccard *curr_card = slic_global.slic_card;
  2163. if (curr_card == card) {
  2164. slic_global.slic_card = card->next;
  2165. } else {
  2166. while (curr_card->next != card)
  2167. curr_card = curr_card->next;
  2168. curr_card->next = card->next;
  2169. }
  2170. slic_global.num_slic_cards--;
  2171. slic_card_cleanup(card);
  2172. }
  2173. free_netdev(dev);
  2174. pci_release_regions(pcidev);
  2175. pci_disable_device(pcidev);
  2176. }
  2177. static int slic_entry_halt(struct net_device *dev)
  2178. {
  2179. struct adapter *adapter = netdev_priv(dev);
  2180. struct sliccard *card = adapter->card;
  2181. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  2182. spin_lock_irqsave(&slic_global.driver_lock.lock,
  2183. slic_global.driver_lock.flags);
  2184. netif_stop_queue(adapter->netdev);
  2185. adapter->state = ADAPT_DOWN;
  2186. adapter->linkstate = LINK_DOWN;
  2187. adapter->upr_list = NULL;
  2188. adapter->upr_busy = 0;
  2189. adapter->devflags_prev = 0;
  2190. slic_reg32_write(&slic_regs->slic_icr, ICR_INT_OFF, FLUSH);
  2191. adapter->all_reg_writes++;
  2192. adapter->icr_reg_writes++;
  2193. slic_config_clear(adapter);
  2194. if (adapter->activated) {
  2195. card->adapters_activated--;
  2196. slic_global.num_slic_ports_active--;
  2197. adapter->activated = 0;
  2198. }
  2199. #ifdef AUTOMATIC_RESET
  2200. slic_reg32_write(&slic_regs->slic_reset_iface, 0, FLUSH);
  2201. #endif
  2202. /*
  2203. * Reset the adapter's cmd queues
  2204. */
  2205. slic_cmdq_reset(adapter);
  2206. #ifdef AUTOMATIC_RESET
  2207. if (!card->adapters_activated)
  2208. slic_card_init(card, adapter);
  2209. #endif
  2210. spin_unlock_irqrestore(&slic_global.driver_lock.lock,
  2211. slic_global.driver_lock.flags);
  2212. return 0;
  2213. }
  2214. static struct net_device_stats *slic_get_stats(struct net_device *dev)
  2215. {
  2216. struct adapter *adapter = netdev_priv(dev);
  2217. dev->stats.collisions = adapter->slic_stats.iface.xmit_collisions;
  2218. dev->stats.rx_errors = adapter->slic_stats.iface.rcv_errors;
  2219. dev->stats.tx_errors = adapter->slic_stats.iface.xmt_errors;
  2220. dev->stats.rx_missed_errors = adapter->slic_stats.iface.rcv_discards;
  2221. dev->stats.tx_heartbeat_errors = 0;
  2222. dev->stats.tx_aborted_errors = 0;
  2223. dev->stats.tx_window_errors = 0;
  2224. dev->stats.tx_fifo_errors = 0;
  2225. dev->stats.rx_frame_errors = 0;
  2226. dev->stats.rx_length_errors = 0;
  2227. return &dev->stats;
  2228. }
  2229. static int slic_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  2230. {
  2231. struct adapter *adapter = netdev_priv(dev);
  2232. struct ethtool_cmd edata;
  2233. struct ethtool_cmd ecmd;
  2234. u32 data[7];
  2235. u32 intagg;
  2236. switch (cmd) {
  2237. case SIOCSLICSETINTAGG:
  2238. if (copy_from_user(data, rq->ifr_data, 28))
  2239. return -EFAULT;
  2240. intagg = data[0];
  2241. dev_err(&dev->dev, "%s: set interrupt aggregation to %d\n",
  2242. __func__, intagg);
  2243. slic_intagg_set(adapter, intagg);
  2244. return 0;
  2245. #ifdef SLIC_TRACE_DUMP_ENABLED
  2246. case SIOCSLICTRACEDUMP:
  2247. {
  2248. u32 value;
  2249. DBG_IOCTL("slic_ioctl SIOCSLIC_TRACE_DUMP\n");
  2250. if (copy_from_user(data, rq->ifr_data, 28)) {
  2251. PRINT_ERROR
  2252. ("slic: copy_from_user FAILED getting initial simba param\n");
  2253. return -EFAULT;
  2254. }
  2255. value = data[0];
  2256. if (tracemon_request == SLIC_DUMP_DONE) {
  2257. PRINT_ERROR
  2258. ("ATK Diagnostic Trace Dump Requested\n");
  2259. tracemon_request = SLIC_DUMP_REQUESTED;
  2260. tracemon_request_type = value;
  2261. tracemon_timestamp = jiffies;
  2262. } else if ((tracemon_request == SLIC_DUMP_REQUESTED) ||
  2263. (tracemon_request ==
  2264. SLIC_DUMP_IN_PROGRESS)) {
  2265. PRINT_ERROR
  2266. ("ATK Diagnostic Trace Dump Requested but already in progress... ignore\n");
  2267. } else {
  2268. PRINT_ERROR
  2269. ("ATK Diagnostic Trace Dump Requested\n");
  2270. tracemon_request = SLIC_DUMP_REQUESTED;
  2271. tracemon_request_type = value;
  2272. tracemon_timestamp = jiffies;
  2273. }
  2274. return 0;
  2275. }
  2276. #endif
  2277. case SIOCETHTOOL:
  2278. if (copy_from_user(&ecmd, rq->ifr_data, sizeof(ecmd)))
  2279. return -EFAULT;
  2280. if (ecmd.cmd == ETHTOOL_GSET) {
  2281. memset(&edata, 0, sizeof(edata));
  2282. edata.supported = (SUPPORTED_10baseT_Half |
  2283. SUPPORTED_10baseT_Full |
  2284. SUPPORTED_100baseT_Half |
  2285. SUPPORTED_100baseT_Full |
  2286. SUPPORTED_Autoneg | SUPPORTED_MII);
  2287. edata.port = PORT_MII;
  2288. edata.transceiver = XCVR_INTERNAL;
  2289. edata.phy_address = 0;
  2290. if (adapter->linkspeed == LINK_100MB)
  2291. edata.speed = SPEED_100;
  2292. else if (adapter->linkspeed == LINK_10MB)
  2293. edata.speed = SPEED_10;
  2294. else
  2295. edata.speed = 0;
  2296. if (adapter->linkduplex == LINK_FULLD)
  2297. edata.duplex = DUPLEX_FULL;
  2298. else
  2299. edata.duplex = DUPLEX_HALF;
  2300. edata.autoneg = AUTONEG_ENABLE;
  2301. edata.maxtxpkt = 1;
  2302. edata.maxrxpkt = 1;
  2303. if (copy_to_user(rq->ifr_data, &edata, sizeof(edata)))
  2304. return -EFAULT;
  2305. } else if (ecmd.cmd == ETHTOOL_SSET) {
  2306. if (!capable(CAP_NET_ADMIN))
  2307. return -EPERM;
  2308. if (adapter->linkspeed == LINK_100MB)
  2309. edata.speed = SPEED_100;
  2310. else if (adapter->linkspeed == LINK_10MB)
  2311. edata.speed = SPEED_10;
  2312. else
  2313. edata.speed = 0;
  2314. if (adapter->linkduplex == LINK_FULLD)
  2315. edata.duplex = DUPLEX_FULL;
  2316. else
  2317. edata.duplex = DUPLEX_HALF;
  2318. edata.autoneg = AUTONEG_ENABLE;
  2319. edata.maxtxpkt = 1;
  2320. edata.maxrxpkt = 1;
  2321. if ((ecmd.speed != edata.speed) ||
  2322. (ecmd.duplex != edata.duplex)) {
  2323. u32 speed;
  2324. u32 duplex;
  2325. if (ecmd.speed == SPEED_10)
  2326. speed = 0;
  2327. else
  2328. speed = PCR_SPEED_100;
  2329. if (ecmd.duplex == DUPLEX_FULL)
  2330. duplex = PCR_DUPLEX_FULL;
  2331. else
  2332. duplex = 0;
  2333. slic_link_config(adapter, speed, duplex);
  2334. slic_link_event_handler(adapter);
  2335. }
  2336. }
  2337. return 0;
  2338. default:
  2339. return -EOPNOTSUPP;
  2340. }
  2341. }
  2342. static void slic_config_pci(struct pci_dev *pcidev)
  2343. {
  2344. u16 pci_command;
  2345. u16 new_command;
  2346. pci_read_config_word(pcidev, PCI_COMMAND, &pci_command);
  2347. new_command = pci_command | PCI_COMMAND_MASTER
  2348. | PCI_COMMAND_MEMORY
  2349. | PCI_COMMAND_INVALIDATE
  2350. | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
  2351. if (pci_command != new_command)
  2352. pci_write_config_word(pcidev, PCI_COMMAND, new_command);
  2353. }
  2354. static int slic_card_init(struct sliccard *card, struct adapter *adapter)
  2355. {
  2356. __iomem struct slic_regs *slic_regs = adapter->slic_regs;
  2357. struct slic_eeprom *peeprom;
  2358. struct oslic_eeprom *pOeeprom;
  2359. dma_addr_t phys_config;
  2360. u32 phys_configh;
  2361. u32 phys_configl;
  2362. u32 i = 0;
  2363. struct slic_shmem *pshmem;
  2364. int status;
  2365. uint macaddrs = card->card_size;
  2366. ushort eecodesize;
  2367. ushort dramsize;
  2368. ushort ee_chksum;
  2369. ushort calc_chksum;
  2370. struct slic_config_mac *pmac;
  2371. unsigned char fruformat;
  2372. unsigned char oemfruformat;
  2373. struct atk_fru *patkfru;
  2374. union oemfru *poemfru;
  2375. /* Reset everything except PCI configuration space */
  2376. slic_soft_reset(adapter);
  2377. /* Download the microcode */
  2378. status = slic_card_download(adapter);
  2379. if (status)
  2380. return status;
  2381. if (!card->config_set) {
  2382. peeprom = pci_alloc_consistent(adapter->pcidev,
  2383. sizeof(struct slic_eeprom),
  2384. &phys_config);
  2385. phys_configl = SLIC_GET_ADDR_LOW(phys_config);
  2386. phys_configh = SLIC_GET_ADDR_HIGH(phys_config);
  2387. if (!peeprom) {
  2388. dev_err(&adapter->pcidev->dev,
  2389. "Failed to allocate DMA memory for EEPROM.\n");
  2390. return -ENOMEM;
  2391. }
  2392. memset(peeprom, 0, sizeof(struct slic_eeprom));
  2393. slic_reg32_write(&slic_regs->slic_icr, ICR_INT_OFF, FLUSH);
  2394. mdelay(1);
  2395. pshmem = (struct slic_shmem *)(unsigned long)
  2396. adapter->phys_shmem;
  2397. spin_lock_irqsave(&adapter->bit64reglock.lock,
  2398. adapter->bit64reglock.flags);
  2399. slic_reg32_write(&slic_regs->slic_addr_upper,
  2400. SLIC_GET_ADDR_HIGH(&pshmem->isr), DONT_FLUSH);
  2401. slic_reg32_write(&slic_regs->slic_isp,
  2402. SLIC_GET_ADDR_LOW(&pshmem->isr), FLUSH);
  2403. spin_unlock_irqrestore(&adapter->bit64reglock.lock,
  2404. adapter->bit64reglock.flags);
  2405. status = slic_config_get(adapter, phys_configl, phys_configh);
  2406. if (status) {
  2407. dev_err(&adapter->pcidev->dev,
  2408. "Failed to fetch config data from device.\n");
  2409. goto card_init_err;
  2410. }
  2411. for (;;) {
  2412. if (adapter->pshmem->isr) {
  2413. if (adapter->pshmem->isr & ISR_UPC) {
  2414. adapter->pshmem->isr = 0;
  2415. slic_reg64_write(adapter,
  2416. &slic_regs->slic_isp, 0,
  2417. &slic_regs->slic_addr_upper,
  2418. 0, FLUSH);
  2419. slic_reg32_write(&slic_regs->slic_isr,
  2420. 0, FLUSH);
  2421. slic_upr_request_complete(adapter, 0);
  2422. break;
  2423. }
  2424. adapter->pshmem->isr = 0;
  2425. slic_reg32_write(&slic_regs->slic_isr,
  2426. 0, FLUSH);
  2427. } else {
  2428. mdelay(1);
  2429. i++;
  2430. if (i > 5000) {
  2431. dev_err(&adapter->pcidev->dev,
  2432. "Fetch of config data timed out.\n");
  2433. slic_reg64_write(adapter,
  2434. &slic_regs->slic_isp, 0,
  2435. &slic_regs->slic_addr_upper,
  2436. 0, FLUSH);
  2437. status = -EINVAL;
  2438. goto card_init_err;
  2439. }
  2440. }
  2441. }
  2442. switch (adapter->devid) {
  2443. /* Oasis card */
  2444. case SLIC_2GB_DEVICE_ID:
  2445. /* extract EEPROM data and pointers to EEPROM data */
  2446. pOeeprom = (struct oslic_eeprom *) peeprom;
  2447. eecodesize = pOeeprom->EecodeSize;
  2448. dramsize = pOeeprom->DramSize;
  2449. pmac = pOeeprom->MacInfo;
  2450. fruformat = pOeeprom->FruFormat;
  2451. patkfru = &pOeeprom->AtkFru;
  2452. oemfruformat = pOeeprom->OemFruFormat;
  2453. poemfru = &pOeeprom->OemFru;
  2454. macaddrs = 2;
  2455. /* Minor kludge for Oasis card
  2456. get 2 MAC addresses from the
  2457. EEPROM to ensure that function 1
  2458. gets the Port 1 MAC address */
  2459. break;
  2460. default:
  2461. /* extract EEPROM data and pointers to EEPROM data */
  2462. eecodesize = peeprom->EecodeSize;
  2463. dramsize = peeprom->DramSize;
  2464. pmac = peeprom->u2.mac.MacInfo;
  2465. fruformat = peeprom->FruFormat;
  2466. patkfru = &peeprom->AtkFru;
  2467. oemfruformat = peeprom->OemFruFormat;
  2468. poemfru = &peeprom->OemFru;
  2469. break;
  2470. }
  2471. card->config.EepromValid = false;
  2472. /* see if the EEPROM is valid by checking it's checksum */
  2473. if ((eecodesize <= MAX_EECODE_SIZE) &&
  2474. (eecodesize >= MIN_EECODE_SIZE)) {
  2475. ee_chksum =
  2476. *(u16 *) ((char *) peeprom + (eecodesize - 2));
  2477. /*
  2478. calculate the EEPROM checksum
  2479. */
  2480. calc_chksum = slic_eeprom_cksum(peeprom,
  2481. eecodesize - 2);
  2482. /*
  2483. if the ucdoe chksum flag bit worked,
  2484. we wouldn't need this
  2485. */
  2486. if (ee_chksum == calc_chksum)
  2487. card->config.EepromValid = true;
  2488. }
  2489. /* copy in the DRAM size */
  2490. card->config.DramSize = dramsize;
  2491. /* copy in the MAC address(es) */
  2492. for (i = 0; i < macaddrs; i++) {
  2493. memcpy(&card->config.MacInfo[i],
  2494. &pmac[i], sizeof(struct slic_config_mac));
  2495. }
  2496. /* copy the Alacritech FRU information */
  2497. card->config.FruFormat = fruformat;
  2498. memcpy(&card->config.AtkFru, patkfru,
  2499. sizeof(struct atk_fru));
  2500. pci_free_consistent(adapter->pcidev,
  2501. sizeof(struct slic_eeprom),
  2502. peeprom, phys_config);
  2503. if (!card->config.EepromValid) {
  2504. slic_reg64_write(adapter, &slic_regs->slic_isp, 0,
  2505. &slic_regs->slic_addr_upper,
  2506. 0, FLUSH);
  2507. dev_err(&adapter->pcidev->dev, "EEPROM invalid.\n");
  2508. return -EINVAL;
  2509. }
  2510. card->config_set = 1;
  2511. }
  2512. status = slic_card_download_gbrcv(adapter);
  2513. if (status)
  2514. return status;
  2515. if (slic_global.dynamic_intagg)
  2516. slic_intagg_set(adapter, 0);
  2517. else
  2518. slic_intagg_set(adapter, intagg_delay);
  2519. /*
  2520. * Initialize ping status to "ok"
  2521. */
  2522. card->pingstatus = ISR_PINGMASK;
  2523. /*
  2524. * Lastly, mark our card state as up and return success
  2525. */
  2526. card->state = CARD_UP;
  2527. card->reset_in_progress = 0;
  2528. return 0;
  2529. card_init_err:
  2530. pci_free_consistent(adapter->pcidev, sizeof(struct slic_eeprom),
  2531. peeprom, phys_config);
  2532. return status;
  2533. }
  2534. static void slic_init_driver(void)
  2535. {
  2536. if (slic_first_init) {
  2537. slic_first_init = 0;
  2538. spin_lock_init(&slic_global.driver_lock.lock);
  2539. }
  2540. }
  2541. static void slic_init_adapter(struct net_device *netdev,
  2542. struct pci_dev *pcidev,
  2543. const struct pci_device_id *pci_tbl_entry,
  2544. void __iomem *memaddr, int chip_idx)
  2545. {
  2546. ushort index;
  2547. struct slic_handle *pslic_handle;
  2548. struct adapter *adapter = netdev_priv(netdev);
  2549. /* adapter->pcidev = pcidev;*/
  2550. adapter->vendid = pci_tbl_entry->vendor;
  2551. adapter->devid = pci_tbl_entry->device;
  2552. adapter->subsysid = pci_tbl_entry->subdevice;
  2553. adapter->busnumber = pcidev->bus->number;
  2554. adapter->slotnumber = ((pcidev->devfn >> 3) & 0x1F);
  2555. adapter->functionnumber = (pcidev->devfn & 0x7);
  2556. adapter->slic_regs = (__iomem struct slic_regs *)memaddr;
  2557. adapter->irq = pcidev->irq;
  2558. /* adapter->netdev = netdev;*/
  2559. adapter->chipid = chip_idx;
  2560. adapter->port = 0; /*adapter->functionnumber;*/
  2561. adapter->cardindex = adapter->port;
  2562. spin_lock_init(&adapter->upr_lock.lock);
  2563. spin_lock_init(&adapter->bit64reglock.lock);
  2564. spin_lock_init(&adapter->adapter_lock.lock);
  2565. spin_lock_init(&adapter->reset_lock.lock);
  2566. spin_lock_init(&adapter->handle_lock.lock);
  2567. adapter->card_size = 1;
  2568. /*
  2569. Initialize slic_handle array
  2570. */
  2571. /*
  2572. Start with 1. 0 is an invalid host handle.
  2573. */
  2574. for (index = 1, pslic_handle = &adapter->slic_handles[1];
  2575. index < SLIC_CMDQ_MAXCMDS; index++, pslic_handle++) {
  2576. pslic_handle->token.handle_index = index;
  2577. pslic_handle->type = SLIC_HANDLE_FREE;
  2578. pslic_handle->next = adapter->pfree_slic_handles;
  2579. adapter->pfree_slic_handles = pslic_handle;
  2580. }
  2581. adapter->pshmem = (struct slic_shmem *)
  2582. pci_alloc_consistent(adapter->pcidev,
  2583. sizeof(struct slic_shmem),
  2584. &adapter->
  2585. phys_shmem);
  2586. if (adapter->pshmem)
  2587. memset(adapter->pshmem, 0, sizeof(struct slic_shmem));
  2588. }
  2589. static const struct net_device_ops slic_netdev_ops = {
  2590. .ndo_open = slic_entry_open,
  2591. .ndo_stop = slic_entry_halt,
  2592. .ndo_start_xmit = slic_xmit_start,
  2593. .ndo_do_ioctl = slic_ioctl,
  2594. .ndo_set_mac_address = slic_mac_set_address,
  2595. .ndo_get_stats = slic_get_stats,
  2596. .ndo_set_rx_mode = slic_mcast_set_list,
  2597. .ndo_validate_addr = eth_validate_addr,
  2598. .ndo_change_mtu = eth_change_mtu,
  2599. };
  2600. static u32 slic_card_locate(struct adapter *adapter)
  2601. {
  2602. struct sliccard *card = slic_global.slic_card;
  2603. struct physcard *physcard = slic_global.phys_card;
  2604. ushort card_hostid;
  2605. u16 __iomem *hostid_reg;
  2606. uint i;
  2607. uint rdhostid_offset = 0;
  2608. switch (adapter->devid) {
  2609. case SLIC_2GB_DEVICE_ID:
  2610. rdhostid_offset = SLIC_RDHOSTID_2GB;
  2611. break;
  2612. case SLIC_1GB_DEVICE_ID:
  2613. rdhostid_offset = SLIC_RDHOSTID_1GB;
  2614. break;
  2615. default:
  2616. return -ENODEV;
  2617. }
  2618. hostid_reg =
  2619. (u16 __iomem *) (((u8 __iomem *) (adapter->slic_regs)) +
  2620. rdhostid_offset);
  2621. /* read the 16 bit hostid from SRAM */
  2622. card_hostid = (ushort) readw(hostid_reg);
  2623. /* Initialize a new card structure if need be */
  2624. if (card_hostid == SLIC_HOSTID_DEFAULT) {
  2625. card = kzalloc(sizeof(struct sliccard), GFP_KERNEL);
  2626. if (card == NULL)
  2627. return -ENOMEM;
  2628. card->next = slic_global.slic_card;
  2629. slic_global.slic_card = card;
  2630. card->busnumber = adapter->busnumber;
  2631. card->slotnumber = adapter->slotnumber;
  2632. /* Find an available cardnum */
  2633. for (i = 0; i < SLIC_MAX_CARDS; i++) {
  2634. if (slic_global.cardnuminuse[i] == 0) {
  2635. slic_global.cardnuminuse[i] = 1;
  2636. card->cardnum = i;
  2637. break;
  2638. }
  2639. }
  2640. slic_global.num_slic_cards++;
  2641. } else {
  2642. /* Card exists, find the card this adapter belongs to */
  2643. while (card) {
  2644. if (card->cardnum == card_hostid)
  2645. break;
  2646. card = card->next;
  2647. }
  2648. }
  2649. if (!card)
  2650. return -ENXIO;
  2651. /* Put the adapter in the card's adapter list */
  2652. if (!card->adapter[adapter->port]) {
  2653. card->adapter[adapter->port] = adapter;
  2654. adapter->card = card;
  2655. }
  2656. card->card_size = 1; /* one port per *logical* card */
  2657. while (physcard) {
  2658. for (i = 0; i < SLIC_MAX_PORTS; i++) {
  2659. if (physcard->adapter[i])
  2660. break;
  2661. }
  2662. if (i == SLIC_MAX_PORTS)
  2663. break;
  2664. if (physcard->adapter[i]->slotnumber == adapter->slotnumber)
  2665. break;
  2666. physcard = physcard->next;
  2667. }
  2668. if (!physcard) {
  2669. /* no structure allocated for this physical card yet */
  2670. physcard = kzalloc(sizeof(struct physcard), GFP_ATOMIC);
  2671. if (!physcard) {
  2672. if (card_hostid == SLIC_HOSTID_DEFAULT)
  2673. kfree(card);
  2674. return -ENOMEM;
  2675. }
  2676. physcard->next = slic_global.phys_card;
  2677. slic_global.phys_card = physcard;
  2678. physcard->adapters_allocd = 1;
  2679. } else {
  2680. physcard->adapters_allocd++;
  2681. }
  2682. /* Note - this is ZERO relative */
  2683. adapter->physport = physcard->adapters_allocd - 1;
  2684. physcard->adapter[adapter->physport] = adapter;
  2685. adapter->physcard = physcard;
  2686. return 0;
  2687. }
  2688. static int slic_entry_probe(struct pci_dev *pcidev,
  2689. const struct pci_device_id *pci_tbl_entry)
  2690. {
  2691. static int cards_found;
  2692. static int did_version;
  2693. int err = -ENODEV;
  2694. struct net_device *netdev;
  2695. struct adapter *adapter;
  2696. void __iomem *memmapped_ioaddr = NULL;
  2697. ulong mmio_start = 0;
  2698. ulong mmio_len = 0;
  2699. struct sliccard *card = NULL;
  2700. int pci_using_dac = 0;
  2701. slic_global.dynamic_intagg = dynamic_intagg;
  2702. err = pci_enable_device(pcidev);
  2703. if (err)
  2704. return err;
  2705. if (did_version++ == 0) {
  2706. dev_info(&pcidev->dev, "%s\n", slic_banner);
  2707. dev_info(&pcidev->dev, "%s\n", slic_proc_version);
  2708. }
  2709. if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  2710. pci_using_dac = 1;
  2711. err = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
  2712. if (err) {
  2713. dev_err(&pcidev->dev, "unable to obtain 64-bit DMA for consistent allocations\n");
  2714. goto err_out_disable_pci;
  2715. }
  2716. } else {
  2717. err = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
  2718. if (err) {
  2719. dev_err(&pcidev->dev, "no usable DMA configuration\n");
  2720. goto err_out_disable_pci;
  2721. }
  2722. pci_using_dac = 0;
  2723. pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  2724. }
  2725. err = pci_request_regions(pcidev, DRV_NAME);
  2726. if (err) {
  2727. dev_err(&pcidev->dev, "can't obtain PCI resources\n");
  2728. goto err_out_disable_pci;
  2729. }
  2730. pci_set_master(pcidev);
  2731. netdev = alloc_etherdev(sizeof(struct adapter));
  2732. if (!netdev) {
  2733. err = -ENOMEM;
  2734. goto err_out_exit_slic_probe;
  2735. }
  2736. SET_NETDEV_DEV(netdev, &pcidev->dev);
  2737. pci_set_drvdata(pcidev, netdev);
  2738. adapter = netdev_priv(netdev);
  2739. adapter->netdev = netdev;
  2740. adapter->pcidev = pcidev;
  2741. if (pci_using_dac)
  2742. netdev->features |= NETIF_F_HIGHDMA;
  2743. mmio_start = pci_resource_start(pcidev, 0);
  2744. mmio_len = pci_resource_len(pcidev, 0);
  2745. /* memmapped_ioaddr = (u32)ioremap_nocache(mmio_start, mmio_len);*/
  2746. memmapped_ioaddr = ioremap(mmio_start, mmio_len);
  2747. if (!memmapped_ioaddr) {
  2748. dev_err(&pcidev->dev, "cannot remap MMIO region %lx @ %lx\n",
  2749. mmio_len, mmio_start);
  2750. err = -ENOMEM;
  2751. goto err_out_free_netdev;
  2752. }
  2753. slic_config_pci(pcidev);
  2754. slic_init_driver();
  2755. slic_init_adapter(netdev,
  2756. pcidev, pci_tbl_entry, memmapped_ioaddr, cards_found);
  2757. err = slic_card_locate(adapter);
  2758. if (err) {
  2759. dev_err(&pcidev->dev, "cannot locate card\n");
  2760. goto err_out_unmap;
  2761. }
  2762. card = adapter->card;
  2763. if (!adapter->allocated) {
  2764. card->adapters_allocated++;
  2765. adapter->allocated = 1;
  2766. }
  2767. err = slic_card_init(card, adapter);
  2768. if (err)
  2769. goto err_out_unmap;
  2770. slic_adapter_set_hwaddr(adapter);
  2771. netdev->base_addr = (unsigned long) memmapped_ioaddr;
  2772. netdev->irq = adapter->irq;
  2773. netdev->netdev_ops = &slic_netdev_ops;
  2774. strcpy(netdev->name, "eth%d");
  2775. err = register_netdev(netdev);
  2776. if (err) {
  2777. dev_err(&pcidev->dev, "Cannot register net device, aborting.\n");
  2778. goto err_out_unmap;
  2779. }
  2780. cards_found++;
  2781. return 0;
  2782. err_out_unmap:
  2783. iounmap(memmapped_ioaddr);
  2784. err_out_free_netdev:
  2785. free_netdev(netdev);
  2786. err_out_exit_slic_probe:
  2787. pci_release_regions(pcidev);
  2788. err_out_disable_pci:
  2789. pci_disable_device(pcidev);
  2790. return err;
  2791. }
  2792. static struct pci_driver slic_driver = {
  2793. .name = DRV_NAME,
  2794. .id_table = slic_pci_tbl,
  2795. .probe = slic_entry_probe,
  2796. .remove = slic_entry_remove,
  2797. };
  2798. static int __init slic_module_init(void)
  2799. {
  2800. slic_init_driver();
  2801. return pci_register_driver(&slic_driver);
  2802. }
  2803. static void __exit slic_module_cleanup(void)
  2804. {
  2805. pci_unregister_driver(&slic_driver);
  2806. }
  2807. module_init(slic_module_init);
  2808. module_exit(slic_module_cleanup);