g1011.dts 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898
  1. /dts-v1/;
  2. #include "mt6753.dtsi"
  3. #include <dt-bindings/lcm/r63417_fhd_dsi_cmd_truly_nt50358.dtsi>
  4. #include "g1011_bat_setting.dtsi"
  5. / {
  6. memory@00000000 {
  7. device_type = "memory";
  8. reg = <0 0x40000000 0 0x3F000000>;
  9. };
  10. bus {
  11. compatible = "simple-bus";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. ranges = <0 0 0 0xffffffff>;
  15. MTKFB@5e200000 {
  16. compatible = "mediatek,MTKFB";
  17. reg = <0x7F000000 0x1000000>;
  18. };
  19. };
  20. led0:led@0 {
  21. compatible = "mediatek,red";
  22. led_mode = <0>;
  23. data = <1>;
  24. pwm_config = <0 0 0 0 0>;
  25. };
  26. led1:led@1 {
  27. compatible = "mediatek,green";
  28. led_mode = <0>;
  29. data = <1>;
  30. pwm_config = <0 0 0 0 0>;
  31. };
  32. led2:led@2 {
  33. compatible = "mediatek,blue";
  34. led_mode = <0>;
  35. data = <1>;
  36. pwm_config = <0 0 0 0 0>;
  37. };
  38. led3:led@3 {
  39. compatible = "mediatek,jogball-backlight";
  40. led_mode = <0>;
  41. data = <1>;
  42. pwm_config = <0 0 0 0 0>;
  43. };
  44. led4:led@4 {
  45. compatible = "mediatek,keyboard-backlight";
  46. led_mode = <0>;
  47. data = <1>;
  48. pwm_config = <0 0 0 0 0>;
  49. };
  50. led5:led@5 {
  51. compatible = "mediatek,button-backlight";
  52. led_mode = <0>;
  53. data = <1>;
  54. pwm_config = <0 0 0 0 0>;
  55. };
  56. led6:led@6 {
  57. compatible = "mediatek,lcd-backlight";
  58. led_mode = <5>;
  59. data = <1>;
  60. pwm_config = <0 0 0 0 0>;
  61. };
  62. vibrator0:vibrator@0 {
  63. compatible = "mediatek,vibrator";
  64. vib_timer = <25>;
  65. vib_limit = <9>;
  66. vib_vol= <6>;
  67. };
  68. /* sensor standardization */
  69. cust_accel@0 {
  70. compatible = "mediatek,bma255";
  71. i2c_num = <2>;
  72. i2c_addr = <0x10 0 0 0>;
  73. direction = <7>;
  74. power_id = <0xffff>;
  75. power_vol = <0>;
  76. firlen = <0>;
  77. is_batch_supported = <0>;
  78. };
  79. cust_alsps@0 {
  80. compatible = "mediatek,ltr303_new";
  81. i2c_num = <2>;
  82. i2c_addr = <0x29 0 0 0>;
  83. polling_mode_ps = <0>;
  84. polling_mode_als = <1>;
  85. power_id = <0xffff>;
  86. power_vol = <0>;
  87. als_level = <10 35 70 100 150 250 300 350 400 600 800 1000 1200 1600 2000>;
  88. als_value = <0 40 70 90 120 140 160 200 250 300 400 600 800 2000 10240 10240>;
  89. ps_threshold_high = <90>;
  90. ps_threshold_low = <70>;
  91. is_batch_supported_ps = <0>;
  92. is_batch_supported_als = <0>;
  93. interrupt-parent = <&pio>;
  94. interrupts = <65 IRQ_TYPE_EDGE_FALLING>;
  95. debounce = <8 0>;
  96. };
  97. cust_mag@0 {
  98. compatible = "mediatek,bmm150";
  99. i2c_num = <2>;
  100. i2c_addr = <0x12 0 0 0>;
  101. direction = <7>;
  102. power_id = <0xffff>;
  103. power_vol = <0>;
  104. is_batch_supported = <0>;
  105. };
  106. cust_gyro@0 {
  107. compatible = "mediatek,mpu6050gy";
  108. i2c_num = <2>;
  109. i2c_addr = <0x69 0 0 0>;
  110. direction = <4>;
  111. power_id = <0xffff>;
  112. power_vol = <0>;
  113. firlen = <0>;
  114. is_batch_supported = <0>;
  115. };
  116. cap_touch@5D {
  117. compatible = "mediatek,cap_touch";
  118. reg = <0x5D>;
  119. interrupt-parent = <&pio>;
  120. interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
  121. int-gpio = <&pio 10 0>;
  122. rst-gpio = <&pio 62 0>;
  123. };
  124. mt8193hdmi: mt8193hdmi@0 {//add line 1
  125. compatible = "mediatek,mt8193-hdmi";//add line 2
  126. };//add line 3
  127. };
  128. /* sensor gpio standization */
  129. &pio {
  130. alsps_intpin_cfg: alspspincfg {
  131. pins_cmd_dat {
  132. pins = <PINMUX_GPIO65__FUNC_GPIO65>;
  133. slew-rate = <0>;
  134. bias-pull-up = <00>;
  135. };
  136. };
  137. alsps_intpin_default: alspsdefaultcfg {
  138. pins_cmd_dat {
  139. pins = <PINMUX_GPIO65__FUNC_GPIO65>;
  140. slew-rate = <0>;
  141. bias-pull-up = <00>;
  142. };
  143. };
  144. gyro_intpin_cfg: gyropincfg {
  145. pins_cmd_dat {
  146. pins = <PINMUX_GPIO67__FUNC_GPIO67>;
  147. slew-rate = <0>;
  148. bias-pull-down = <00>;
  149. };
  150. };
  151. gyro_intpin_default: gyrodefaultcfg {
  152. };
  153. };
  154. &alsps {
  155. pinctrl-names = "pin_default", "pin_cfg";
  156. pinctrl-0 = <&alsps_intpin_default>;
  157. pinctrl-1 = <&alsps_intpin_cfg>;
  158. status = "okay";
  159. };
  160. &gyro {
  161. pinctrl-names = "pin_default", "pin_cfg";
  162. pinctrl-0 = <&gyro_intpin_default>;
  163. pinctrl-1 = <&gyro_intpin_cfg>;
  164. status = "okay";
  165. };
  166. /* sensor end */
  167. /*ACCDET GPIO standardization */
  168. &accdet {
  169. interrupt-parent = <&eintc>;
  170. interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
  171. eint-debounce = <256>;
  172. accdet-gpio = <&pio 12 0>;
  173. accdet-mic-vol = <7>;
  174. headset-mode-setting = <0x500 0x200 1 0x1f0 0x800 0x800 0x20>;
  175. accdet-plugout-debounce = <20>;
  176. /*1:ACC mode, 2:low cost without in bias, 6:low cost with in bias*/
  177. accdet-mic-mode = <1>;
  178. /*0--MD_MAX--UP_MAX--DW_MAX*/
  179. headset-three-key-threshold = <0 80 220 500>;
  180. /*0--MD_MAX--VOICE_MAX--UP_MAX--DW_MAX*/
  181. headset-four-key-threshold = <0 58 121 192 450>;
  182. pinctrl-names = "default", "state_eint_as_int";
  183. pinctrl-0 = <&accdet_pins_default>;
  184. pinctrl-1 = <&accdet_pins_eint_as_int>;
  185. status = "okay";
  186. };
  187. &pio{
  188. accdet_pins_default: eint86default {
  189. };
  190. accdet_pins_eint_as_int: eint12 {
  191. pins_cmd_dat {
  192. pins = <PINMUX_GPIO12__FUNC_GPIO12>;
  193. bias-disable;
  194. };
  195. };
  196. };
  197. /*ACCDET end*/
  198. /*TOUCH GPIO standardization */
  199. &touch {
  200. tpd-resolution = <1920 1200>;
  201. use-tpd-button = <1>;
  202. tpd-key-num = <1>;
  203. tpd-key-local= <172 0 0 0>;
  204. tpd-key-dim-local = <2000 2000 40 40 0 0 0 0 0 0 0 0 0 0 0 0>;
  205. tpd-max-touch-num = <10>;
  206. tpd-filter-enable = <1>;
  207. tpd-filter-pixel-density = <186>;
  208. tpd-filter-custom-prameters = <0 0 0 0 0 0 0 0 0 0 0 0>;
  209. tpd-filter-custom-speed = <0 0 0>;
  210. pinctrl-names = "default", "state_eint_as_int", "state_eint_output0", "state_eint_output1",
  211. "state_rst_output0", "state_rst_output1";
  212. pinctrl-0 = <&CTP_pins_default>;
  213. pinctrl-1 = <&CTP_pins_eint_as_int>;
  214. pinctrl-2 = <&CTP_pins_eint_output0>;
  215. pinctrl-3 = <&CTP_pins_eint_output1>;
  216. pinctrl-4 = <&CTP_pins_rst_output0>;
  217. pinctrl-5 = <&CTP_pins_rst_output1>;
  218. status = "okay";
  219. };
  220. &pio {
  221. CTP_pins_default: eint0default {
  222. };
  223. CTP_pins_eint_as_int: eint@0 {
  224. pins_cmd_dat {
  225. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  226. slew-rate = <0>;
  227. bias-disable;
  228. };
  229. };
  230. CTP_pins_eint_output0: eintoutput0 {
  231. pins_cmd_dat {
  232. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  233. slew-rate = <1>;
  234. output-low;
  235. };
  236. };
  237. CTP_pins_eint_output1: eintoutput1 {
  238. pins_cmd_dat {
  239. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  240. slew-rate = <1>;
  241. output-high;
  242. };
  243. };
  244. CTP_pins_rst_output0: rstoutput0 {
  245. pins_cmd_dat {
  246. pins = <PINMUX_GPIO62__FUNC_GPIO62>;
  247. slew-rate = <1>;
  248. output-low;
  249. };
  250. };
  251. CTP_pins_rst_output1: rstoutput1 {
  252. pins_cmd_dat {
  253. pins = <PINMUX_GPIO62__FUNC_GPIO62>;
  254. slew-rate = <1>;
  255. output-high;
  256. };
  257. };
  258. };
  259. /* TOUCH end */
  260. /* CAMERA GPIO standardization */
  261. &pio {
  262. camera_pins_cam0_rst0: cam0@0 {
  263. pins_cmd_dat {
  264. pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST_PIN*/
  265. slew-rate = <1>; /*direction 0:in, 1:out*/
  266. output-low;/*direction out used only. output_low or high*/
  267. };
  268. };
  269. camera_pins_cam0_rst1: cam0@1 {
  270. pins_cmd_dat {
  271. pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST_PIN*/
  272. slew-rate = <1>;
  273. output-high;
  274. };
  275. };
  276. camera_pins_cam0_pnd0: cam0@2 {
  277. pins_cmd_dat {
  278. pins = <PINMUX_GPIO82__FUNC_GPIO82>;/*GPIO_CAMERA_CMPDN_PIN*/
  279. slew-rate = <1>;
  280. output-low;
  281. };
  282. };
  283. camera_pins_cam0_pnd1: cam0@3 {
  284. pins_cmd_dat {
  285. pins = <PINMUX_GPIO82__FUNC_GPIO82>;/*GPIO_CAMERA_CMPDN_PIN*/
  286. slew-rate = <1>;
  287. output-high;
  288. };
  289. };
  290. camera_pins_cam1_rst0: cam1@0 {
  291. pins_cmd_dat {
  292. pins = <PINMUX_GPIO76__FUNC_GPIO76>;/*GPIO_CAMERA_CMRST1_PIN*/
  293. slew-rate = <1>; /*direction 0:in, 1:out*/
  294. output-low;/*direction out used only. output_low or high*/
  295. };
  296. };
  297. camera_pins_cam1_rst1: cam1@1 {
  298. pins_cmd_dat {
  299. pins = <PINMUX_GPIO76__FUNC_GPIO76>;/*GPIO_CAMERA_CMRST1_PIN*/
  300. slew-rate = <1>;
  301. output-high;
  302. };
  303. };
  304. camera_pins_cam1_pnd0: cam1@2 {
  305. pins_cmd_dat {
  306. pins = <PINMUX_GPIO86__FUNC_GPIO86>;/*GPIO_CAMERA_CMPDN1_PIN*/
  307. slew-rate = <1>;
  308. output-low;
  309. };
  310. };
  311. camera_pins_cam1_pnd1: cam1@3 {
  312. pins_cmd_dat {
  313. pins = <PINMUX_GPIO86__FUNC_GPIO86>;/*GPIO_CAMERA_CMPDN1_PIN*/
  314. slew-rate = <1>;
  315. output-high;
  316. };
  317. };
  318. camera_pins_cam_ldo0_0: cam@0 {
  319. pins_cmd_dat {
  320. pins = <PINMUX_GPIO63__FUNC_GPIO63>;
  321. slew-rate = <1>;
  322. output-low;
  323. };
  324. };
  325. camera_pins_cam_ldo0_1: cam@1 {
  326. pins_cmd_dat {
  327. pins = <PINMUX_GPIO63__FUNC_GPIO63>;
  328. slew-rate = <1>;
  329. output-high;
  330. };
  331. };
  332. camera_pins_default: camdefault {
  333. };
  334. };
  335. &mt8193_bridge{
  336. pinctrl-names = "default";
  337. pinctrl-0 = <&dpi_pins_default>;
  338. status = "okay";
  339. };
  340. &pio{
  341. dpi_pins_default:hdmi_dpi_pins{
  342. pins_cmd_dat {
  343. pins = <PINMUX_GPIO0__FUNC_DPI_D4>,
  344. <PINMUX_GPIO1__FUNC_DPI_D5>,
  345. <PINMUX_GPIO2__FUNC_DPI_D6>,
  346. <PINMUX_GPIO3__FUNC_DPI_D7>,
  347. <PINMUX_GPIO4__FUNC_DPI_D8>,
  348. <PINMUX_GPIO5__FUNC_DPI_D9>,
  349. <PINMUX_GPIO6__FUNC_DPI_D10>,
  350. <PINMUX_GPIO7__FUNC_DPI_D11>,
  351. <PINMUX_GPIO59__FUNC_DPI_CK0>;
  352. };
  353. };
  354. };
  355. &mt8193hdmi{
  356. pinctrl-names = "default";
  357. pinctrl-0 = <&mt8193hdmi_pins_default>;
  358. hdmi_power_gpios = <&pio 87 0>;
  359. status = "okay";
  360. };
  361. &pio{
  362. mt8193hdmi_pins_default:8193hdmi_dpi_pins{
  363. pins_cmd_dat {
  364. pins = <PINMUX_GPIO87__FUNC_GPIO87>;
  365. slew-rate = <1>;
  366. bias-pull-up =<00>;
  367. output-low;
  368. };
  369. };
  370. };
  371. &kd_camera_hw1 {
  372. pinctrl-names = "default", "cam0_rst0", "cam0_rst1", "cam0_pnd0", "cam0_pnd1",
  373. "cam1_rst0", "cam1_rst1", "cam1_pnd0", "cam1_pnd1",
  374. "cam_ldo0_0", "cam_ldo0_1";
  375. pinctrl-0 = <&camera_pins_default>;
  376. pinctrl-1 = <&camera_pins_cam0_rst0>;
  377. pinctrl-2 = <&camera_pins_cam0_rst1>;
  378. pinctrl-3 = <&camera_pins_cam0_pnd0>;
  379. pinctrl-4 = <&camera_pins_cam0_pnd1>;
  380. pinctrl-5 = <&camera_pins_cam1_rst0>;
  381. pinctrl-6 = <&camera_pins_cam1_rst1>;
  382. pinctrl-7 = <&camera_pins_cam1_pnd0>;
  383. pinctrl-8 = <&camera_pins_cam1_pnd1>;
  384. pinctrl-9 = <&camera_pins_cam_ldo0_0>;
  385. pinctrl-10 = <&camera_pins_cam_ldo0_1>;
  386. status = "okay";
  387. };
  388. /* CAMERA GPIO end */
  389. /* CONSYS GPIO standardization */
  390. &pio {
  391. consys_pins_default: default {
  392. };
  393. gpslna_pins_init: gpslna@0 {
  394. pins_cmd_dat {
  395. pins = <PINMUX_GPIO77__FUNC_GPIO77>;
  396. slew-rate = <0>;
  397. bias-disable;
  398. output-low;
  399. };
  400. };
  401. gpslna_pins_oh: gpslna@1 {
  402. pins_cmd_dat {
  403. pins = <PINMUX_GPIO77__FUNC_GPIO77>;
  404. slew-rate = <1>;
  405. bias-pull-up = <00>;
  406. output-high;
  407. };
  408. };
  409. gpslna_pins_ol: gpslna@2 {
  410. pins_cmd_dat {
  411. pins = <PINMUX_GPIO77__FUNC_GPIO77>;
  412. slew-rate = <1>;
  413. bias-pull-up = <00>;
  414. output-low;
  415. };
  416. };
  417. };
  418. &consys {
  419. pinctrl-names = "default", "gps_lna_state_init", "gps_lna_state_oh", "gps_lna_state_ol";
  420. pinctrl-0 = <&consys_pins_default>;
  421. pinctrl-1 = <&gpslna_pins_init>;
  422. pinctrl-2 = <&gpslna_pins_oh>;
  423. pinctrl-3 = <&gpslna_pins_ol>;
  424. status = "okay";
  425. };
  426. /* CONSYS end */
  427. /* mmc start */
  428. &mmc0 {
  429. clk_src = /bits/ 8 <MSDC50_CLKSRC_400MHZ>;
  430. bus-width = <8>;
  431. max-frequency = <200000000>;
  432. cap-mmc-highspeed;
  433. msdc-sys-suspend;
  434. mmc-ddr-1_8v;
  435. mmc-hs200-1_8v;
  436. mmc-hs400-1_8v;
  437. non-removable;
  438. pinctl = <&mmc0_pins_default>;
  439. register_setting = <&mmc0_register_setting_default>;
  440. host_function = /bits/ 8 <MSDC_EMMC>;
  441. bootable;
  442. status = "okay";
  443. };
  444. &mmc1 {
  445. clk_src = /bits/ 8 <MSDC30_CLKSRC_200MHZ>;
  446. bus-width = <4>;
  447. max-frequency = <200000000>;
  448. msdc-sys-suspend;
  449. sd_need_power;
  450. cap-sd-highspeed;
  451. sd-uhs-sdr12;
  452. sd-uhs-sdr25;
  453. sd-uhs-sdr50;
  454. sd-uhs-sdr104;
  455. sd-uhs-ddr50;
  456. pinctl = <&mmc1_pins_default>;
  457. pinctl_sdr104 = <&mmc1_pins_sdr104>;
  458. pinctl_sdr50 = <&mmc1_pins_sdr50>;
  459. pinctl_ddr50 = <&mmc1_pins_ddr50>;
  460. register_setting = <&mmc1_register_setting_default>;
  461. host_function = /bits/ 8 <MSDC_SD>;
  462. cd_level = /bits/ 8 <MSDC_CD_LOW>;
  463. cd-gpios = <&pio 11 0>;
  464. status = "okay";
  465. };
  466. &mmc2 {
  467. clk_src = /bits/ 8 <MSDC30_CLKSRC_200MHZ>;
  468. bus-width = <4>;
  469. max-frequency = <200000000>;
  470. cap-sd-highspeed;
  471. sd-uhs-sdr12;
  472. sd-uhs-sdr25;
  473. sd-uhs-sdr50;
  474. sd-uhs-sdr104;
  475. sd-uhs-ddr50;
  476. non-removable;
  477. host_function = /bits/ 8 <MSDC_SDIO>;
  478. status = "okay";
  479. };
  480. &pio {
  481. mmc0_pins_default: mmc0@default {
  482. pins_cmd {
  483. drive-strength = /bits/ 8 <2>;
  484. };
  485. pins_dat {
  486. drive-strength = /bits/ 8 <2>;
  487. };
  488. pins_clk {
  489. drive-strength = /bits/ 8 <2>;
  490. };
  491. pins_rst {
  492. drive-strength = /bits/ 8 <2>;
  493. };
  494. pins_ds {
  495. drive-strength = /bits/ 8 <2>;
  496. };
  497. };
  498. mmc0_register_setting_default: mmc0@register_default {
  499. dat0rddly = /bits/ 8 <0>;
  500. dat1rddly = /bits/ 8 <0>;
  501. dat2rddly = /bits/ 8 <0>;
  502. dat3rddly = /bits/ 8 <0>;
  503. dat4rddly = /bits/ 8 <0>;
  504. dat5rddly = /bits/ 8 <0>;
  505. dat6rddly = /bits/ 8 <0>;
  506. dat7rddly = /bits/ 8 <0>;
  507. datwrddly = /bits/ 8 <0>;
  508. cmdrrddly = /bits/ 8 <0>;
  509. cmdrddly = /bits/ 8 <0>;
  510. cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  511. rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  512. wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  513. ett-hs200-cells = <12>;
  514. ett-hs200-default = <OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_INT_DAT_LATCH_CK_SEL 0x0
  515. OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_CKGEN_MSDC_DLY_SEL 0x0
  516. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_CMD_RSP_TA_CNTR 0x1
  517. OFFSET_MSDC_IOCON MSDC_IOCON_RSPL 0x1
  518. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRDLY 0xf
  519. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRRDLY 0x0
  520. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_WRDAT_CRCS_TA_CNTR 0x1
  521. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_DATWRDLY 0xf
  522. OFFSET_MSDC_IOCON MSDC_IOCON_W_D0SPL 0x1
  523. OFFSET_MSDC_DAT_RDDLY0 MSDC_DAT_RDDLY0_D0 0xf
  524. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_DATRRDLY 0x16
  525. OFFSET_MSDC_IOCON MSDC_IOCON_R_D_SMPL 0x0>;
  526. ett-hs400-cells = <8>;
  527. ett-hs400-default = <OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_INT_DAT_LATCH_CK_SEL 0x0
  528. OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_CKGEN_MSDC_DLY_SEL 0x0
  529. OFFSET_EMMC50_PAD_DS_TUNE MSDC_EMMC50_PAD_DS_TUNE_DLY1 0x2
  530. OFFSET_EMMC50_PAD_DS_TUNE MSDC_EMMC50_PAD_DS_TUNE_DLY3 0xe
  531. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_CMD_RSP_TA_CNTR 0x1
  532. OFFSET_MSDC_IOCON MSDC_IOCON_RSPL 0x0
  533. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRDLY 0xf
  534. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRRDLY 0xd>;
  535. };
  536. mmc1_pins_default: mmc1@default {
  537. pins_cmd {
  538. drive-strength = /bits/ 8 <3>;
  539. };
  540. pins_dat {
  541. drive-strength = /bits/ 8 <3>;
  542. };
  543. pins_clk {
  544. drive-strength = /bits/ 8 <3>;
  545. };
  546. };
  547. mmc1_pins_sdr104: mmc1@sdr104 {
  548. pins_cmd {
  549. drive-strength = /bits/ 8 <2>;
  550. };
  551. pins_dat {
  552. drive-strength = /bits/ 8 <2>;
  553. };
  554. pins_clk {
  555. drive-strength = /bits/ 8 <3>;
  556. };
  557. };
  558. mmc1_pins_sdr50: mmc1@sdr50 {
  559. pins_cmd {
  560. drive-strength = /bits/ 8 <2>;
  561. };
  562. pins_dat {
  563. drive-strength = /bits/ 8 <2>;
  564. };
  565. pins_clk {
  566. drive-strength = /bits/ 8 <3>;
  567. };
  568. };
  569. mmc1_pins_ddr50: mmc1@ddr50 {
  570. pins_cmd {
  571. drive-strength = /bits/ 8 <2>;
  572. };
  573. pins_dat {
  574. drive-strength = /bits/ 8 <2>;
  575. };
  576. pins_clk {
  577. drive-strength = /bits/ 8 <3>;
  578. };
  579. };
  580. mmc1_register_setting_default: mmc1@register_default {
  581. dat0rddly = /bits/ 8 <0>;
  582. dat1rddly = /bits/ 8 <0>;
  583. dat2rddly = /bits/ 8 <0>;
  584. dat3rddly = /bits/ 8 <0>;
  585. datwrddly = /bits/ 8 <0>;
  586. cmdrrddly = /bits/ 8 <0>;
  587. cmdrddly = /bits/ 8 <0>;
  588. cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  589. rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  590. wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  591. };
  592. };
  593. /* mmc end */
  594. /* USB GPIO Kernal Standardization start */
  595. &pio {
  596. usb_default: usb_default {
  597. };
  598. gpio67_mode5_iddig: iddig_irq_init {
  599. pins_cmd_dat {
  600. pins = <PINMUX_GPIO67__FUNC_IDDIG>;
  601. slew-rate = <0>;
  602. bias-pull-up = <00>;
  603. };
  604. };
  605. gpio83_mode2_drvvbus: drvvbus_init {
  606. pins_cmd_dat {
  607. pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
  608. slew-rate = <1>;
  609. bias-pull-up = <00>;
  610. };
  611. };
  612. gpio83_mode2_drvvbus_low: drvvbus_low {
  613. pins_cmd_dat {
  614. pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
  615. slew-rate = <1>;
  616. output-low;
  617. };
  618. };
  619. gpio83_mode2_drvvbus_high: drvvbus_high {
  620. pins_cmd_dat {
  621. pins = <PINMUX_GPIO83__FUNC_USB_DRVVBUS>;
  622. slew-rate = <1>;
  623. output-high;
  624. };
  625. };
  626. };
  627. &usb0 {
  628. iddig_gpio = <67 1>;
  629. pinctrl-names = "usb_default", "iddig_irq_init", "drvvbus_init", "drvvbus_low", "drvvbus_high";
  630. pinctrl-0 = <&usb_default>;
  631. pinctrl-1 = <&gpio67_mode5_iddig>;
  632. pinctrl-2 = <&gpio83_mode2_drvvbus>;
  633. pinctrl-3 = <&gpio83_mode2_drvvbus_low>;
  634. pinctrl-4 = <&gpio83_mode2_drvvbus_high>;
  635. status = "okay";
  636. };
  637. /* USB GPIO Kernal Standardization end */
  638. /* AUDIO GPIO standardization */
  639. &mt_soc_dl1_pcm {
  640. pinctrl-names = "default", "audpmicclk-mode0", "audpmicclk-mode1", "audi2s1-mode0", "audi2s1-mode1", "extamp-pullhigh", "extamp-pulllow", "rcvspk-pullhigh", "rcvspk-pulllow";
  641. pinctrl-0 = <&aud_pins_default>;
  642. pinctrl-1 = <&aud_pins_pmicclk_mode0>;
  643. pinctrl-2 = <&aud_pins_pmicclk_mode1>;
  644. pinctrl-3 = <&aud_pins_i2s1_mode0>;
  645. pinctrl-4 = <&aud_pins_i2s1_mode1>;
  646. pinctrl-5 = <&aud_pins_extamp_high>;
  647. pinctrl-6 = <&aud_pins_extamp_low>;
  648. pinctrl-7 = <&aud_pins_rcvspk_high>;
  649. pinctrl-8 = <&aud_pins_rcvspk_low>;
  650. status = "okay";
  651. };
  652. &pio {
  653. aud_pins_default: audiodefault {
  654. audio_i2s1_hdmi {//add line 1
  655. pins = <PINMUX_GPIO78__FUNC_I2S1_DO>,//add line 2
  656. <PINMUX_GPIO79__FUNC_I2S1_LRCK>,//add line 3
  657. <PINMUX_GPIO80__FUNC_I2S1_BCK>;//add line 4
  658. };//add line 5
  659. };
  660. aud_pins_pmicclk_mode0: pmicclkmode0 {
  661. pins_cmd0_dat {
  662. pins = <PINMUX_GPIO143__FUNC_GPIO143>;
  663. };
  664. pins_cmd1_dat {
  665. pins = <PINMUX_GPIO144__FUNC_GPIO144>;
  666. };
  667. pins_cmd2_dat {
  668. pins = <PINMUX_GPIO145__FUNC_GPIO145>;
  669. };
  670. };
  671. aud_pins_pmicclk_mode1: pmicclkmode1 {
  672. pins_cmd0_dat {
  673. pins = <PINMUX_GPIO143__FUNC_AUD_CLK_MOSI>;
  674. };
  675. pins_cmd1_dat {
  676. pins = <PINMUX_GPIO144__FUNC_AUD_DAT_MISO>;
  677. };
  678. pins_cmd2_dat {
  679. pins = <PINMUX_GPIO145__FUNC_AUD_DAT_MOSI>;
  680. };
  681. };
  682. aud_pins_i2s1_mode0: audi2s1mode0 {
  683. pins_cmd0_dat {
  684. pins = <PINMUX_GPIO78__FUNC_GPIO78>;
  685. };
  686. pins_cmd1_dat {
  687. pins = <PINMUX_GPIO79__FUNC_GPIO79>;
  688. };
  689. pins_cmd2_dat {
  690. pins = <PINMUX_GPIO80__FUNC_GPIO80>;
  691. };
  692. };
  693. aud_pins_i2s1_mode1: audi2s1mode1 {
  694. pins_cmd0_dat {
  695. pins = <PINMUX_GPIO78__FUNC_I2S1_DO>;
  696. };
  697. pins_cmd1_dat {
  698. pins = <PINMUX_GPIO79__FUNC_I2S1_LRCK>;
  699. };
  700. pins_cmd2_dat {
  701. pins = <PINMUX_GPIO80__FUNC_I2S1_BCK>;
  702. };
  703. };
  704. aud_pins_extamp_high: audexamphigh {
  705. pins_cmd_dat {
  706. pins = <PINMUX_GPIO64__FUNC_GPIO64>;
  707. slew-rate = <1>;
  708. output-high;
  709. };
  710. };
  711. aud_pins_extamp_low: audexamplow {
  712. pins_cmd_dat {
  713. pins = <PINMUX_GPIO64__FUNC_GPIO64>;
  714. slew-rate = <1>;
  715. output-low;
  716. };
  717. };
  718. aud_pins_rcvspk_high: audrcvspkhigh {
  719. pins_cmd_dat {
  720. pins = <PINMUX_GPIO120__FUNC_GPIO120>;
  721. slew-rate = <1>;
  722. output-low; /*set low for receiver out*/
  723. };
  724. };
  725. aud_pins_rcvspk_low: audrcvspklow {
  726. pins_cmd_dat {
  727. pins = <PINMUX_GPIO120__FUNC_GPIO120>;
  728. slew-rate = <1>;
  729. output-high; /*set high for speaker out*/
  730. };
  731. };
  732. };
  733. /* AUDIO end */
  734. /* LCM GPIO Kernal Standardization start */
  735. &pio {
  736. lcm_mode_default: lcm_mode_default {
  737. pins_cmd_dat {
  738. pins = <PINMUX_GPIO80__FUNC_GPIO80>;
  739. };
  740. };
  741. lcm_mode_00: lcm_mode@0 {
  742. pins_cmd_dat {
  743. pins = <PINMUX_GPIO80__FUNC_GPIO80>;
  744. };
  745. };
  746. lcm_mode_01: lcm_mode@1 {
  747. pins_cmd_dat {
  748. pins = <PINMUX_GPIO80__FUNC_I2S0_BCK>;
  749. };
  750. };
  751. lcm_mode_02: lcm_mode@2 {
  752. pins_cmd_dat {
  753. pins = <PINMUX_GPIO80__FUNC_PCM1_CLK_1>;
  754. };
  755. };
  756. lcm_mode_03: lcm_mode@3 {
  757. pins_cmd_dat {
  758. pins = <PINMUX_GPIO80__FUNC_I2S3_BCK>;
  759. };
  760. };
  761. lcm_mode_04: lcm_mode@4 {
  762. pins_cmd_dat {
  763. pins = <PINMUX_GPIO80__FUNC_I2S1_BCK>;
  764. };
  765. };
  766. lcm_mode_05: lcm_mode@5 {
  767. pins_cmd_dat {
  768. pins = <PINMUX_GPIO80__FUNC_PWM4>;
  769. };
  770. };
  771. lcm_mode_06: lcm_mode@6 {
  772. pins_cmd_dat {
  773. pins = <PINMUX_GPIO80__FUNC_I2S2_BCK>;
  774. };
  775. };
  776. lcm_mode_07: lcm_mode@7 {
  777. pins_cmd_dat {
  778. pins = <PINMUX_GPIO80__FUNC_DBG_MON_A28>;
  779. };
  780. };
  781. };
  782. &lcm {
  783. gpio_lcm_pwr_en = <&pio 57 0>;
  784. gpio_lcm_rst_en = <&pio 146 0>;
  785. lcm_bl_gpio = <&pio 3 0>;
  786. lcm_bias_enp_gpio= <&pio 58 0>;
  787. lcm_id_gpio= <&pio 19 0>;
  788. };
  789. &lcm_mode {
  790. pinctrl-names = "default", "lcm_mode_00", "lcm_mode_01", "lcm_mode_02", "lcm_mode_03", "lcm_mode_04",
  791. "lcm_mode_05", "lcm_mode_06", "lcm_mode_07";
  792. pinctrl-0 = <&lcm_mode_default>;
  793. pinctrl-1 = <&lcm_mode_00>;
  794. pinctrl-2 = <&lcm_mode_01>;
  795. pinctrl-3 = <&lcm_mode_02>;
  796. pinctrl-4 = <&lcm_mode_03>;
  797. pinctrl-5 = <&lcm_mode_04>;
  798. pinctrl-6 = <&lcm_mode_05>;
  799. pinctrl-7 = <&lcm_mode_06>;
  800. pinctrl-8 = <&lcm_mode_07>;
  801. lcm_power_gpio = <&pio 80 0>;
  802. lcm_bl_gpio = <&pio 129 0>;
  803. status = "okay";
  804. };
  805. /* LCM GPIO Kernal Standardization end */
  806. /* i2c start */
  807. &i2c3 {
  808. bq24296@6b {
  809. status = "okay";
  810. compatible = "bq24296";
  811. reg = <0x6b>;
  812. };
  813. };
  814. &i2c2 {
  815. tpa6130a2@60 {
  816. compatible = "ti,tpa6130a2";
  817. reg = <0x60>;
  818. power-gpio = <&pio 20 0>;
  819. };
  820. };
  821. /* i2c end */