ahci-platform.txt 2.1 KB

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  1. * AHCI SATA Controller
  2. SATA nodes are defined to describe on-chip Serial ATA controllers.
  3. Each SATA controller should have its own node.
  4. It is possible, but not required, to represent each port as a sub-node.
  5. It allows to enable each port independently when dealing with multiple
  6. PHYs.
  7. Required properties:
  8. - compatible : compatible string, one of:
  9. - "allwinner,sun4i-a10-ahci"
  10. - "hisilicon,hisi-ahci"
  11. - "ibm,476gtr-ahci"
  12. - "marvell,armada-380-ahci"
  13. - "snps,dwc-ahci"
  14. - "snps,exynos5440-ahci"
  15. - "snps,spear-ahci"
  16. - "generic-ahci"
  17. - interrupts : <interrupt mapping for SATA IRQ>
  18. - reg : <registers mapping>
  19. Please note that when using "generic-ahci" you must also specify a SoC specific
  20. compatible:
  21. compatible = "manufacturer,soc-model-ahci", "generic-ahci";
  22. Optional properties:
  23. - dma-coherent : Present if dma operations are coherent
  24. - clocks : a list of phandle + clock specifier pairs
  25. - target-supply : regulator for SATA target power
  26. - phys : reference to the SATA PHY node
  27. - phy-names : must be "sata-phy"
  28. Required properties when using sub-nodes:
  29. - #address-cells : number of cells to encode an address
  30. - #size-cells : number of cells representing the size of an address
  31. Sub-nodes required properties:
  32. - reg : the port number
  33. - phys : reference to the SATA PHY node
  34. Examples:
  35. sata@ffe08000 {
  36. compatible = "snps,spear-ahci";
  37. reg = <0xffe08000 0x1000>;
  38. interrupts = <115>;
  39. };
  40. ahci: sata@01c18000 {
  41. compatible = "allwinner,sun4i-a10-ahci";
  42. reg = <0x01c18000 0x1000>;
  43. interrupts = <56>;
  44. clocks = <&pll6 0>, <&ahb_gates 25>;
  45. target-supply = <&reg_ahci_5v>;
  46. };
  47. With sub-nodes:
  48. sata@f7e90000 {
  49. compatible = "marvell,berlin2q-achi", "generic-ahci";
  50. reg = <0xe90000 0x1000>;
  51. interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  52. clocks = <&chip CLKID_SATA>;
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. sata0: sata-port@0 {
  56. reg = <0>;
  57. phys = <&sata_phy 0>;
  58. };
  59. sata1: sata-port@1 {
  60. reg = <1>;
  61. phys = <&sata_phy 1>;
  62. };
  63. };