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- Freescale L2 Cache Controller
- L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
- The cache bindings explained below are ePAPR compliant
- Required Properties:
- - compatible : Should include "fsl,chip-l2-cache-controller" and "cache"
- where chip is the processor (bsc9132, npc8572 etc.)
- - reg : Address and size of L2 cache controller registers
- - cache-size : Size of the entire L2 cache
- - interrupts : Error interrupt of L2 controller
- - cache-line-size : Size of L2 cache lines
- Example:
- L2: l2-cache-controller@20000 {
- compatible = "fsl,bsc9132-l2-cache-controller", "cache";
- reg = <0x20000 0x1000>;
- cache-line-size = <32>; // 32 bytes
- cache-size = <0x40000>; // L2,256K
- interrupts = <16 2 1 0>;
- };
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