qcom,gsbi.txt 2.3 KB

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  1. QCOM GSBI (General Serial Bus Interface) Driver
  2. The GSBI controller is modeled as a node with zero or more child nodes, each
  3. representing a serial sub-node device that is mux'd as part of the GSBI
  4. configuration settings. The mode setting will govern the input/output mode of
  5. the 4 GSBI IOs.
  6. Required properties:
  7. - compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
  8. - reg: Address range for GSBI registers
  9. - clocks: required clock
  10. - clock-names: must contain "iface" entry
  11. - qcom,mode : indicates MUX value for configuration of the serial interface.
  12. Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
  13. Optional properties:
  14. - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
  15. dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
  16. Required properties if child node exists:
  17. - #address-cells: Must be 1
  18. - #size-cells: Must be 1
  19. - ranges: Must be present
  20. Properties for children:
  21. A GSBI controller node can contain 0 or more child nodes representing serial
  22. devices. These serial devices can be a QCOM UART, I2C controller, spi
  23. controller, or some combination of aforementioned devices.
  24. See the following for child node definitions:
  25. Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
  26. Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  27. Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
  28. Example for APQ8064:
  29. #include <dt-bindings/soc/qcom,gsbi.h>
  30. gsbi4@16300000 {
  31. compatible = "qcom,gsbi-v1.0.0";
  32. reg = <0x16300000 0x100>;
  33. clocks = <&gcc GSBI4_H_CLK>;
  34. clock-names = "iface";
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. ranges;
  38. qcom,mode = <GSBI_PROT_I2C_UART>;
  39. qcom,crci = <GSBI_CRCI_QUP>;
  40. /* child nodes go under here */
  41. i2c_qup4: i2c@16380000 {
  42. compatible = "qcom,i2c-qup-v1.1.1";
  43. reg = <0x16380000 0x1000>;
  44. interrupts = <0 153 0>;
  45. clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
  46. clock-names = "core", "iface";
  47. clock-frequency = <200000>;
  48. #address-cells = <1>;
  49. #size-cells = <0>;
  50. };
  51. uart4: serial@16340000 {
  52. compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  53. reg = <0x16340000 0x1000>,
  54. <0x16300000 0x1000>;
  55. interrupts = <0 152 0x0>;
  56. clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
  57. clock-names = "core", "iface";
  58. status = "ok";
  59. };
  60. };