qcom,spmi-pmic-arb.txt 2.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061
  1. Qualcomm SPMI Controller (PMIC Arbiter)
  2. The SPMI PMIC Arbiter is found on the Snapdragon 800 Series. It is an SPMI
  3. controller with wrapping arbitration logic to allow for multiple on-chip
  4. devices to control a single SPMI master.
  5. The PMIC Arbiter can also act as an interrupt controller, providing interrupts
  6. to slave devices.
  7. See spmi.txt for the generic SPMI controller binding requirements for child
  8. nodes.
  9. See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
  10. generic interrupt controller binding documentation.
  11. Required properties:
  12. - compatible : should be "qcom,spmi-pmic-arb".
  13. - reg-names : must contain:
  14. "core" - core registers
  15. "intr" - interrupt controller registers
  16. "cnfg" - configuration registers
  17. - reg : address + size pairs describing the PMIC arb register sets; order must
  18. correspond with the order of entries in reg-names
  19. - #address-cells : must be set to 2
  20. - #size-cells : must be set to 0
  21. - qcom,ee : indicates the active Execution Environment identifier (0-5)
  22. - qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
  23. - interrupts : interrupt list for the PMIC Arb controller, must contain a
  24. single interrupt entry for the peripheral interrupt
  25. - interrupt-names : corresponding interrupt names for the interrupts
  26. listed in the 'interrupts' property, must contain:
  27. "periph_irq" - summary interrupt for PMIC peripherals
  28. - interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
  29. - #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
  30. cell 1: slave ID for the requested interrupt (0-15)
  31. cell 2: peripheral ID for requested interrupt (0-255)
  32. cell 3: the requested peripheral interrupt (0-7)
  33. cell 4: interrupt flags indicating level-sense information, as defined in
  34. dt-bindings/interrupt-controller/irq.h
  35. Example:
  36. spmi {
  37. compatible = "qcom,spmi-pmic-arb";
  38. reg-names = "core", "intr", "cnfg";
  39. reg = <0xfc4cf000 0x1000>,
  40. <0xfc4cb000 0x1000>,
  41. <0xfc4ca000 0x1000>;
  42. interrupt-names = "periph_irq";
  43. interrupts = <0 190 0>;
  44. qcom,ee = <0>;
  45. qcom,channel = <0>;
  46. #address-cells = <2>;
  47. #size-cells = <0>;
  48. interrupt-controller;
  49. #interrupt-cells = <4>;
  50. };