Aquaris-M10-4G/Documentation/devicetree/bindings/media/mediatek-videocodec.txt

* Mediatek Video Codec Driver

This document describes the binding for the mediatek video codec.

Required properties:
- compatible:
   - "mediatek,mt6735-vdec_gcon", "mediatek,mt6735-vdec", for video decoder,
   - "mediatek,mt6735-venc_gcon", "mediatek,mt6735-venc", for video encoder,
   - "mediatek,mt6735-vencsys", "mediatek,mt6735-vdecsys", for video clock management,
   for MT6735 SoCs
- interrupts: IRQ for video codec in SOC
- reg: The base address of the video codec register
- clocks: device clocks
- clock-name: Should be the names of the clocks
   - "MT_CG_DISP0_SMI_COMMON" for Display SMI
   - "MT_CG_VDEC0_VDEC" for Video Decoder
   - "MT_CG_VDEC1_LARB" for Video Decoder Larb
   - "MT_CG_VENC_VENC" for Video Encoder
   - "MT_CG_VENC_LARB" for Video Encoder Larb
   - "MT_CG_TOP_MUX_VDEC" for Video Decoder Mux for MMDVFS
   - "MT_CG_TOP_SYSPLL1_D2" for MMDVFS higher frequency
   - "MT_CG_TOP_SYSPLL1_D4" for MMDVFS lower frequency
   - "MT_SCP_SYS_VDE" for Video Decoder MTCMOS
   - "MT_SCP_SYS_VEN" for Video Encoder MTCMOS
   - "MT_SCP_SYS_DIS" for Display MTCMOS

Example:

		vdecsys: vdecsys@0x16000000 {
			compatible = "mediatek,mt6735-vdecsys";
			reg = <0x16000000 0x1000>;
			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>;
			#clock-cells = <1>;
		};

		vencsys: vencsys@0x17000000 {
			compatible = "mediatek,mt6735-vencsys";
			reg = <0x17000000 0x1000>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
			#clock-cells = <1>;
		};

		vdec_gcon: vdec_gcon@16000000 {
			compatible = "mediatek,mt6735-vdec_gcon";
			reg = <0x16000000 0x1000>;
			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>;
			clocks =
			<&mmsys MM_DISP0_SMI_COMMON>,
			<&vdecsys VDEC0_VDEC>,
			<&vdecsys VDEC1_LARB>,
			<&vencsys VENC_VENC>,
			<&vencsys VENC_LARB>,
			<&topckgen TOP_MUX_VDEC>,
			<&topckgen TOP_SYSPLL1_D2>,
			<&topckgen TOP_SYSPLL1_D4>,
			<&scpsys SCP_SYS_VDE>,
			<&scpsys SCP_SYS_VEN>,
			<&scpsys SCP_SYS_DIS>;
			clock-names =
			"MT_CG_DISP0_SMI_COMMON",
			"MT_CG_VDEC0_VDEC",
			"MT_CG_VDEC1_LARB",
			"MT_CG_VENC_VENC",
			"MT_CG_VENC_LARB",
			"MT_CG_TOP_MUX_VDEC",
			"MT_CG_TOP_SYSPLL1_D2",
			"MT_CG_TOP_SYSPLL1_D4",
			"MT_SCP_SYS_VDE",
			"MT_SCP_SYS_VEN",
			"MT_SCP_SYS_DIS";
		};

		vdec: vdec@16020000 {
			compatible = "mediatek,mt6735-vdec";
			reg = <0x16020000 0x10000>;
			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>;
		};

		venc_gcon: venc_gcon@17000000 {
			compatible = "mediatek,mt6735-venc_gcon";
			reg = <0x17000000 0x1000>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
		};

		venc: venc@17002000 {
			compatible = "mediatek,mt6735-venc";
			reg = <0x17002000 0x1000>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
		};
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