sst-haswell-ipc.c 46 KB

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  1. /*
  2. * Intel SST Haswell/Broadwell IPC Support
  3. *
  4. * Copyright (C) 2013, Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License version
  8. * 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/device.h>
  20. #include <linux/wait.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/workqueue.h>
  23. #include <linux/export.h>
  24. #include <linux/slab.h>
  25. #include <linux/delay.h>
  26. #include <linux/sched.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/kthread.h>
  29. #include <linux/firmware.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/debugfs.h>
  32. #include "sst-haswell-ipc.h"
  33. #include "sst-dsp.h"
  34. #include "sst-dsp-priv.h"
  35. /* Global Message - Generic */
  36. #define IPC_GLB_TYPE_SHIFT 24
  37. #define IPC_GLB_TYPE_MASK (0x1f << IPC_GLB_TYPE_SHIFT)
  38. #define IPC_GLB_TYPE(x) (x << IPC_GLB_TYPE_SHIFT)
  39. /* Global Message - Reply */
  40. #define IPC_GLB_REPLY_SHIFT 0
  41. #define IPC_GLB_REPLY_MASK (0x1f << IPC_GLB_REPLY_SHIFT)
  42. #define IPC_GLB_REPLY_TYPE(x) (x << IPC_GLB_REPLY_TYPE_SHIFT)
  43. /* Stream Message - Generic */
  44. #define IPC_STR_TYPE_SHIFT 20
  45. #define IPC_STR_TYPE_MASK (0xf << IPC_STR_TYPE_SHIFT)
  46. #define IPC_STR_TYPE(x) (x << IPC_STR_TYPE_SHIFT)
  47. #define IPC_STR_ID_SHIFT 16
  48. #define IPC_STR_ID_MASK (0xf << IPC_STR_ID_SHIFT)
  49. #define IPC_STR_ID(x) (x << IPC_STR_ID_SHIFT)
  50. /* Stream Message - Reply */
  51. #define IPC_STR_REPLY_SHIFT 0
  52. #define IPC_STR_REPLY_MASK (0x1f << IPC_STR_REPLY_SHIFT)
  53. /* Stream Stage Message - Generic */
  54. #define IPC_STG_TYPE_SHIFT 12
  55. #define IPC_STG_TYPE_MASK (0xf << IPC_STG_TYPE_SHIFT)
  56. #define IPC_STG_TYPE(x) (x << IPC_STG_TYPE_SHIFT)
  57. #define IPC_STG_ID_SHIFT 10
  58. #define IPC_STG_ID_MASK (0x3 << IPC_STG_ID_SHIFT)
  59. #define IPC_STG_ID(x) (x << IPC_STG_ID_SHIFT)
  60. /* Stream Stage Message - Reply */
  61. #define IPC_STG_REPLY_SHIFT 0
  62. #define IPC_STG_REPLY_MASK (0x1f << IPC_STG_REPLY_SHIFT)
  63. /* Debug Log Message - Generic */
  64. #define IPC_LOG_OP_SHIFT 20
  65. #define IPC_LOG_OP_MASK (0xf << IPC_LOG_OP_SHIFT)
  66. #define IPC_LOG_OP_TYPE(x) (x << IPC_LOG_OP_SHIFT)
  67. #define IPC_LOG_ID_SHIFT 16
  68. #define IPC_LOG_ID_MASK (0xf << IPC_LOG_ID_SHIFT)
  69. #define IPC_LOG_ID(x) (x << IPC_LOG_ID_SHIFT)
  70. /* IPC message timeout (msecs) */
  71. #define IPC_TIMEOUT_MSECS 300
  72. #define IPC_BOOT_MSECS 200
  73. #define IPC_MSG_WAIT 0
  74. #define IPC_MSG_NOWAIT 1
  75. /* Firmware Ready Message */
  76. #define IPC_FW_READY (0x1 << 29)
  77. #define IPC_STATUS_MASK (0x3 << 30)
  78. #define IPC_EMPTY_LIST_SIZE 8
  79. #define IPC_MAX_STREAMS 4
  80. /* Mailbox */
  81. #define IPC_MAX_MAILBOX_BYTES 256
  82. /* Global Message - Types and Replies */
  83. enum ipc_glb_type {
  84. IPC_GLB_GET_FW_VERSION = 0, /* Retrieves firmware version */
  85. IPC_GLB_PERFORMANCE_MONITOR = 1, /* Performance monitoring actions */
  86. IPC_GLB_ALLOCATE_STREAM = 3, /* Request to allocate new stream */
  87. IPC_GLB_FREE_STREAM = 4, /* Request to free stream */
  88. IPC_GLB_GET_FW_CAPABILITIES = 5, /* Retrieves firmware capabilities */
  89. IPC_GLB_STREAM_MESSAGE = 6, /* Message directed to stream or its stages */
  90. /* Request to store firmware context during D0->D3 transition */
  91. IPC_GLB_REQUEST_DUMP = 7,
  92. /* Request to restore firmware context during D3->D0 transition */
  93. IPC_GLB_RESTORE_CONTEXT = 8,
  94. IPC_GLB_GET_DEVICE_FORMATS = 9, /* Set device format */
  95. IPC_GLB_SET_DEVICE_FORMATS = 10, /* Get device format */
  96. IPC_GLB_SHORT_REPLY = 11,
  97. IPC_GLB_ENTER_DX_STATE = 12,
  98. IPC_GLB_GET_MIXER_STREAM_INFO = 13, /* Request mixer stream params */
  99. IPC_GLB_DEBUG_LOG_MESSAGE = 14, /* Message to or from the debug logger. */
  100. IPC_GLB_REQUEST_TRANSFER = 16, /* < Request Transfer for host */
  101. IPC_GLB_MAX_IPC_MESSAGE_TYPE = 17, /* Maximum message number */
  102. };
  103. enum ipc_glb_reply {
  104. IPC_GLB_REPLY_SUCCESS = 0, /* The operation was successful. */
  105. IPC_GLB_REPLY_ERROR_INVALID_PARAM = 1, /* Invalid parameter was passed. */
  106. IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE = 2, /* Uknown message type was resceived. */
  107. IPC_GLB_REPLY_OUT_OF_RESOURCES = 3, /* No resources to satisfy the request. */
  108. IPC_GLB_REPLY_BUSY = 4, /* The system or resource is busy. */
  109. IPC_GLB_REPLY_PENDING = 5, /* The action was scheduled for processing. */
  110. IPC_GLB_REPLY_FAILURE = 6, /* Critical error happened. */
  111. IPC_GLB_REPLY_INVALID_REQUEST = 7, /* Request can not be completed. */
  112. IPC_GLB_REPLY_STAGE_UNINITIALIZED = 8, /* Processing stage was uninitialized. */
  113. IPC_GLB_REPLY_NOT_FOUND = 9, /* Required resource can not be found. */
  114. IPC_GLB_REPLY_SOURCE_NOT_STARTED = 10, /* Source was not started. */
  115. };
  116. /* Stream Message - Types */
  117. enum ipc_str_operation {
  118. IPC_STR_RESET = 0,
  119. IPC_STR_PAUSE = 1,
  120. IPC_STR_RESUME = 2,
  121. IPC_STR_STAGE_MESSAGE = 3,
  122. IPC_STR_NOTIFICATION = 4,
  123. IPC_STR_MAX_MESSAGE
  124. };
  125. /* Stream Stage Message Types */
  126. enum ipc_stg_operation {
  127. IPC_STG_GET_VOLUME = 0,
  128. IPC_STG_SET_VOLUME,
  129. IPC_STG_SET_WRITE_POSITION,
  130. IPC_STG_SET_FX_ENABLE,
  131. IPC_STG_SET_FX_DISABLE,
  132. IPC_STG_SET_FX_GET_PARAM,
  133. IPC_STG_SET_FX_SET_PARAM,
  134. IPC_STG_SET_FX_GET_INFO,
  135. IPC_STG_MUTE_LOOPBACK,
  136. IPC_STG_MAX_MESSAGE
  137. };
  138. /* Stream Stage Message Types For Notification*/
  139. enum ipc_stg_operation_notify {
  140. IPC_POSITION_CHANGED = 0,
  141. IPC_STG_GLITCH,
  142. IPC_STG_MAX_NOTIFY
  143. };
  144. enum ipc_glitch_type {
  145. IPC_GLITCH_UNDERRUN = 1,
  146. IPC_GLITCH_DECODER_ERROR,
  147. IPC_GLITCH_DOUBLED_WRITE_POS,
  148. IPC_GLITCH_MAX
  149. };
  150. /* Debug Control */
  151. enum ipc_debug_operation {
  152. IPC_DEBUG_ENABLE_LOG = 0,
  153. IPC_DEBUG_DISABLE_LOG = 1,
  154. IPC_DEBUG_REQUEST_LOG_DUMP = 2,
  155. IPC_DEBUG_NOTIFY_LOG_DUMP = 3,
  156. IPC_DEBUG_MAX_DEBUG_LOG
  157. };
  158. /* Firmware Ready */
  159. struct sst_hsw_ipc_fw_ready {
  160. u32 inbox_offset;
  161. u32 outbox_offset;
  162. u32 inbox_size;
  163. u32 outbox_size;
  164. u32 fw_info_size;
  165. u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
  166. } __attribute__((packed));
  167. struct ipc_message {
  168. struct list_head list;
  169. u32 header;
  170. /* direction wrt host CPU */
  171. char tx_data[IPC_MAX_MAILBOX_BYTES];
  172. size_t tx_size;
  173. char rx_data[IPC_MAX_MAILBOX_BYTES];
  174. size_t rx_size;
  175. wait_queue_head_t waitq;
  176. bool pending;
  177. bool complete;
  178. bool wait;
  179. int errno;
  180. };
  181. struct sst_hsw_stream;
  182. struct sst_hsw;
  183. /* Stream infomation */
  184. struct sst_hsw_stream {
  185. /* configuration */
  186. struct sst_hsw_ipc_stream_alloc_req request;
  187. struct sst_hsw_ipc_stream_alloc_reply reply;
  188. struct sst_hsw_ipc_stream_free_req free_req;
  189. /* Mixer info */
  190. u32 mute_volume[SST_HSW_NO_CHANNELS];
  191. u32 mute[SST_HSW_NO_CHANNELS];
  192. /* runtime info */
  193. struct sst_hsw *hsw;
  194. int host_id;
  195. bool commited;
  196. bool running;
  197. /* Notification work */
  198. struct work_struct notify_work;
  199. u32 header;
  200. /* Position info from DSP */
  201. struct sst_hsw_ipc_stream_set_position wpos;
  202. struct sst_hsw_ipc_stream_get_position rpos;
  203. struct sst_hsw_ipc_stream_glitch_position glitch;
  204. /* Volume info */
  205. struct sst_hsw_ipc_volume_req vol_req;
  206. /* driver callback */
  207. u32 (*notify_position)(struct sst_hsw_stream *stream, void *data);
  208. void *pdata;
  209. struct list_head node;
  210. };
  211. /* FW log ring information */
  212. struct sst_hsw_log_stream {
  213. dma_addr_t dma_addr;
  214. unsigned char *dma_area;
  215. unsigned char *ring_descr;
  216. int pages;
  217. int size;
  218. /* Notification work */
  219. struct work_struct notify_work;
  220. wait_queue_head_t readers_wait_q;
  221. struct mutex rw_mutex;
  222. u32 last_pos;
  223. u32 curr_pos;
  224. u32 reader_pos;
  225. /* fw log config */
  226. u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
  227. struct sst_hsw *hsw;
  228. };
  229. /* SST Haswell IPC data */
  230. struct sst_hsw {
  231. struct device *dev;
  232. struct sst_dsp *dsp;
  233. struct platform_device *pdev_pcm;
  234. /* FW config */
  235. struct sst_hsw_ipc_fw_ready fw_ready;
  236. struct sst_hsw_ipc_fw_version version;
  237. struct sst_module *scratch;
  238. bool fw_done;
  239. /* stream */
  240. struct list_head stream_list;
  241. /* global mixer */
  242. struct sst_hsw_ipc_stream_info_reply mixer_info;
  243. enum sst_hsw_volume_curve curve_type;
  244. u32 curve_duration;
  245. u32 mute[SST_HSW_NO_CHANNELS];
  246. u32 mute_volume[SST_HSW_NO_CHANNELS];
  247. /* DX */
  248. struct sst_hsw_ipc_dx_reply dx;
  249. /* boot */
  250. wait_queue_head_t boot_wait;
  251. bool boot_complete;
  252. bool shutdown;
  253. /* IPC messaging */
  254. struct list_head tx_list;
  255. struct list_head rx_list;
  256. struct list_head empty_list;
  257. wait_queue_head_t wait_txq;
  258. struct task_struct *tx_thread;
  259. struct kthread_worker kworker;
  260. struct kthread_work kwork;
  261. bool pending;
  262. struct ipc_message *msg;
  263. /* FW log stream */
  264. struct sst_hsw_log_stream log_stream;
  265. };
  266. #define CREATE_TRACE_POINTS
  267. #include <trace/events/hswadsp.h>
  268. static inline u32 msg_get_global_type(u32 msg)
  269. {
  270. return (msg & IPC_GLB_TYPE_MASK) >> IPC_GLB_TYPE_SHIFT;
  271. }
  272. static inline u32 msg_get_global_reply(u32 msg)
  273. {
  274. return (msg & IPC_GLB_REPLY_MASK) >> IPC_GLB_REPLY_SHIFT;
  275. }
  276. static inline u32 msg_get_stream_type(u32 msg)
  277. {
  278. return (msg & IPC_STR_TYPE_MASK) >> IPC_STR_TYPE_SHIFT;
  279. }
  280. static inline u32 msg_get_stage_type(u32 msg)
  281. {
  282. return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
  283. }
  284. static inline u32 msg_set_stage_type(u32 msg, u32 type)
  285. {
  286. return (msg & ~IPC_STG_TYPE_MASK) +
  287. (type << IPC_STG_TYPE_SHIFT);
  288. }
  289. static inline u32 msg_get_stream_id(u32 msg)
  290. {
  291. return (msg & IPC_STR_ID_MASK) >> IPC_STR_ID_SHIFT;
  292. }
  293. static inline u32 msg_get_notify_reason(u32 msg)
  294. {
  295. return (msg & IPC_STG_TYPE_MASK) >> IPC_STG_TYPE_SHIFT;
  296. }
  297. u32 create_channel_map(enum sst_hsw_channel_config config)
  298. {
  299. switch (config) {
  300. case SST_HSW_CHANNEL_CONFIG_MONO:
  301. return (0xFFFFFFF0 | SST_HSW_CHANNEL_CENTER);
  302. case SST_HSW_CHANNEL_CONFIG_STEREO:
  303. return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
  304. | (SST_HSW_CHANNEL_RIGHT << 4));
  305. case SST_HSW_CHANNEL_CONFIG_2_POINT_1:
  306. return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
  307. | (SST_HSW_CHANNEL_RIGHT << 4)
  308. | (SST_HSW_CHANNEL_LFE << 8 ));
  309. case SST_HSW_CHANNEL_CONFIG_3_POINT_0:
  310. return (0xFFFFF000 | SST_HSW_CHANNEL_LEFT
  311. | (SST_HSW_CHANNEL_CENTER << 4)
  312. | (SST_HSW_CHANNEL_RIGHT << 8));
  313. case SST_HSW_CHANNEL_CONFIG_3_POINT_1:
  314. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  315. | (SST_HSW_CHANNEL_CENTER << 4)
  316. | (SST_HSW_CHANNEL_RIGHT << 8)
  317. | (SST_HSW_CHANNEL_LFE << 12));
  318. case SST_HSW_CHANNEL_CONFIG_QUATRO:
  319. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  320. | (SST_HSW_CHANNEL_RIGHT << 4)
  321. | (SST_HSW_CHANNEL_LEFT_SURROUND << 8)
  322. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 12));
  323. case SST_HSW_CHANNEL_CONFIG_4_POINT_0:
  324. return (0xFFFF0000 | SST_HSW_CHANNEL_LEFT
  325. | (SST_HSW_CHANNEL_CENTER << 4)
  326. | (SST_HSW_CHANNEL_RIGHT << 8)
  327. | (SST_HSW_CHANNEL_CENTER_SURROUND << 12));
  328. case SST_HSW_CHANNEL_CONFIG_5_POINT_0:
  329. return (0xFFF00000 | SST_HSW_CHANNEL_LEFT
  330. | (SST_HSW_CHANNEL_CENTER << 4)
  331. | (SST_HSW_CHANNEL_RIGHT << 8)
  332. | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
  333. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16));
  334. case SST_HSW_CHANNEL_CONFIG_5_POINT_1:
  335. return (0xFF000000 | SST_HSW_CHANNEL_CENTER
  336. | (SST_HSW_CHANNEL_LEFT << 4)
  337. | (SST_HSW_CHANNEL_RIGHT << 8)
  338. | (SST_HSW_CHANNEL_LEFT_SURROUND << 12)
  339. | (SST_HSW_CHANNEL_RIGHT_SURROUND << 16)
  340. | (SST_HSW_CHANNEL_LFE << 20));
  341. case SST_HSW_CHANNEL_CONFIG_DUAL_MONO:
  342. return (0xFFFFFF00 | SST_HSW_CHANNEL_LEFT
  343. | (SST_HSW_CHANNEL_LEFT << 4));
  344. default:
  345. return 0xFFFFFFFF;
  346. }
  347. }
  348. static struct sst_hsw_stream *get_stream_by_id(struct sst_hsw *hsw,
  349. int stream_id)
  350. {
  351. struct sst_hsw_stream *stream;
  352. list_for_each_entry(stream, &hsw->stream_list, node) {
  353. if (stream->reply.stream_hw_id == stream_id)
  354. return stream;
  355. }
  356. return NULL;
  357. }
  358. static void ipc_shim_dbg(struct sst_hsw *hsw, const char *text)
  359. {
  360. struct sst_dsp *sst = hsw->dsp;
  361. u32 isr, ipcd, imrx, ipcx;
  362. ipcx = sst_dsp_shim_read_unlocked(sst, SST_IPCX);
  363. isr = sst_dsp_shim_read_unlocked(sst, SST_ISRX);
  364. ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  365. imrx = sst_dsp_shim_read_unlocked(sst, SST_IMRX);
  366. dev_err(hsw->dev, "ipc: --%s-- ipcx 0x%8.8x isr 0x%8.8x ipcd 0x%8.8x imrx 0x%8.8x\n",
  367. text, ipcx, isr, ipcd, imrx);
  368. }
  369. /* locks held by caller */
  370. static struct ipc_message *msg_get_empty(struct sst_hsw *hsw)
  371. {
  372. struct ipc_message *msg = NULL;
  373. if (!list_empty(&hsw->empty_list)) {
  374. msg = list_first_entry(&hsw->empty_list, struct ipc_message,
  375. list);
  376. list_del(&msg->list);
  377. }
  378. return msg;
  379. }
  380. static void ipc_tx_msgs(struct kthread_work *work)
  381. {
  382. struct sst_hsw *hsw =
  383. container_of(work, struct sst_hsw, kwork);
  384. struct ipc_message *msg;
  385. unsigned long flags;
  386. u32 ipcx;
  387. spin_lock_irqsave(&hsw->dsp->spinlock, flags);
  388. if (list_empty(&hsw->tx_list) || hsw->pending) {
  389. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  390. return;
  391. }
  392. /* if the DSP is busy, we will TX messages after IRQ.
  393. * also postpone if we are in the middle of procesing completion irq*/
  394. ipcx = sst_dsp_shim_read_unlocked(hsw->dsp, SST_IPCX);
  395. if (ipcx & (SST_IPCX_BUSY | SST_IPCX_DONE)) {
  396. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  397. return;
  398. }
  399. msg = list_first_entry(&hsw->tx_list, struct ipc_message, list);
  400. list_move(&msg->list, &hsw->rx_list);
  401. /* send the message */
  402. sst_dsp_outbox_write(hsw->dsp, msg->tx_data, msg->tx_size);
  403. sst_dsp_ipc_msg_tx(hsw->dsp, msg->header | SST_IPCX_BUSY);
  404. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  405. }
  406. /* locks held by caller */
  407. static void tx_msg_reply_complete(struct sst_hsw *hsw, struct ipc_message *msg)
  408. {
  409. msg->complete = true;
  410. trace_ipc_reply("completed", msg->header);
  411. if (!msg->wait)
  412. list_add_tail(&msg->list, &hsw->empty_list);
  413. else
  414. wake_up(&msg->waitq);
  415. }
  416. static int tx_wait_done(struct sst_hsw *hsw, struct ipc_message *msg,
  417. void *rx_data)
  418. {
  419. unsigned long flags;
  420. int ret;
  421. /* wait for DSP completion (in all cases atm inc pending) */
  422. ret = wait_event_timeout(msg->waitq, msg->complete,
  423. msecs_to_jiffies(IPC_TIMEOUT_MSECS));
  424. spin_lock_irqsave(&hsw->dsp->spinlock, flags);
  425. if (ret == 0) {
  426. ipc_shim_dbg(hsw, "message timeout");
  427. trace_ipc_error("error message timeout for", msg->header);
  428. list_del(&msg->list);
  429. ret = -ETIMEDOUT;
  430. } else {
  431. /* copy the data returned from DSP */
  432. if (msg->rx_size)
  433. memcpy(rx_data, msg->rx_data, msg->rx_size);
  434. ret = msg->errno;
  435. }
  436. list_add_tail(&msg->list, &hsw->empty_list);
  437. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  438. return ret;
  439. }
  440. static int ipc_tx_message(struct sst_hsw *hsw, u32 header, void *tx_data,
  441. size_t tx_bytes, void *rx_data, size_t rx_bytes, int wait)
  442. {
  443. struct ipc_message *msg;
  444. unsigned long flags;
  445. spin_lock_irqsave(&hsw->dsp->spinlock, flags);
  446. msg = msg_get_empty(hsw);
  447. if (msg == NULL) {
  448. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  449. return -EBUSY;
  450. }
  451. if (tx_bytes)
  452. memcpy(msg->tx_data, tx_data, tx_bytes);
  453. msg->header = header;
  454. msg->tx_size = tx_bytes;
  455. msg->rx_size = rx_bytes;
  456. msg->wait = wait;
  457. msg->errno = 0;
  458. msg->pending = false;
  459. msg->complete = false;
  460. list_add_tail(&msg->list, &hsw->tx_list);
  461. spin_unlock_irqrestore(&hsw->dsp->spinlock, flags);
  462. queue_kthread_work(&hsw->kworker, &hsw->kwork);
  463. if (wait)
  464. return tx_wait_done(hsw, msg, rx_data);
  465. else
  466. return 0;
  467. }
  468. static inline int ipc_tx_message_wait(struct sst_hsw *hsw, u32 header,
  469. void *tx_data, size_t tx_bytes, void *rx_data, size_t rx_bytes)
  470. {
  471. return ipc_tx_message(hsw, header, tx_data, tx_bytes, rx_data,
  472. rx_bytes, 1);
  473. }
  474. static inline int ipc_tx_message_nowait(struct sst_hsw *hsw, u32 header,
  475. void *tx_data, size_t tx_bytes)
  476. {
  477. return ipc_tx_message(hsw, header, tx_data, tx_bytes, NULL, 0, 0);
  478. }
  479. static void hsw_fw_ready(struct sst_hsw *hsw, u32 header)
  480. {
  481. struct sst_hsw_ipc_fw_ready fw_ready;
  482. u32 offset;
  483. u8 fw_info[IPC_MAX_MAILBOX_BYTES - 5 * sizeof(u32)];
  484. char *tmp[5], *pinfo;
  485. int i = 0;
  486. offset = (header & 0x1FFFFFFF) << 3;
  487. dev_dbg(hsw->dev, "ipc: DSP is ready 0x%8.8x offset %d\n",
  488. header, offset);
  489. /* copy data from the DSP FW ready offset */
  490. sst_dsp_read(hsw->dsp, &fw_ready, offset, sizeof(fw_ready));
  491. sst_dsp_mailbox_init(hsw->dsp, fw_ready.inbox_offset,
  492. fw_ready.inbox_size, fw_ready.outbox_offset,
  493. fw_ready.outbox_size);
  494. hsw->boot_complete = true;
  495. wake_up(&hsw->boot_wait);
  496. dev_dbg(hsw->dev, " mailbox upstream 0x%x - size 0x%x\n",
  497. fw_ready.inbox_offset, fw_ready.inbox_size);
  498. dev_dbg(hsw->dev, " mailbox downstream 0x%x - size 0x%x\n",
  499. fw_ready.outbox_offset, fw_ready.outbox_size);
  500. if (fw_ready.fw_info_size < sizeof(fw_ready.fw_info)) {
  501. fw_ready.fw_info[fw_ready.fw_info_size] = 0;
  502. dev_dbg(hsw->dev, " Firmware info: %s \n", fw_ready.fw_info);
  503. /* log the FW version info got from the mailbox here. */
  504. memcpy(fw_info, fw_ready.fw_info, fw_ready.fw_info_size);
  505. pinfo = &fw_info[0];
  506. for (i = 0; i < sizeof(tmp) / sizeof(char *); i++)
  507. tmp[i] = strsep(&pinfo, " ");
  508. dev_info(hsw->dev, "FW loaded, mailbox readback FW info: type %s, - "
  509. "version: %s.%s, build %s, source commit id: %s\n",
  510. tmp[0], tmp[1], tmp[2], tmp[3], tmp[4]);
  511. }
  512. }
  513. static void hsw_notification_work(struct work_struct *work)
  514. {
  515. struct sst_hsw_stream *stream = container_of(work,
  516. struct sst_hsw_stream, notify_work);
  517. struct sst_hsw_ipc_stream_glitch_position *glitch = &stream->glitch;
  518. struct sst_hsw_ipc_stream_get_position *pos = &stream->rpos;
  519. struct sst_hsw *hsw = stream->hsw;
  520. u32 reason;
  521. reason = msg_get_notify_reason(stream->header);
  522. switch (reason) {
  523. case IPC_STG_GLITCH:
  524. trace_ipc_notification("DSP stream under/overrun",
  525. stream->reply.stream_hw_id);
  526. sst_dsp_inbox_read(hsw->dsp, glitch, sizeof(*glitch));
  527. dev_err(hsw->dev, "glitch %d pos 0x%x write pos 0x%x\n",
  528. glitch->glitch_type, glitch->present_pos,
  529. glitch->write_pos);
  530. break;
  531. case IPC_POSITION_CHANGED:
  532. trace_ipc_notification("DSP stream position changed for",
  533. stream->reply.stream_hw_id);
  534. sst_dsp_inbox_read(hsw->dsp, pos, sizeof(*pos));
  535. if (stream->notify_position)
  536. stream->notify_position(stream, stream->pdata);
  537. break;
  538. default:
  539. dev_err(hsw->dev, "error: unknown notification 0x%x\n",
  540. stream->header);
  541. break;
  542. }
  543. /* tell DSP that notification has been handled */
  544. sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IPCD,
  545. SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
  546. /* unmask busy interrupt */
  547. sst_dsp_shim_update_bits_unlocked(hsw->dsp, SST_IMRX, SST_IMRX_BUSY, 0);
  548. }
  549. static struct ipc_message *reply_find_msg(struct sst_hsw *hsw, u32 header)
  550. {
  551. struct ipc_message *msg;
  552. /* clear reply bits & status bits */
  553. header &= ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
  554. if (list_empty(&hsw->rx_list)) {
  555. dev_err(hsw->dev, "error: rx list empty but received 0x%x\n",
  556. header);
  557. return NULL;
  558. }
  559. list_for_each_entry(msg, &hsw->rx_list, list) {
  560. if (msg->header == header)
  561. return msg;
  562. }
  563. return NULL;
  564. }
  565. static void hsw_stream_update(struct sst_hsw *hsw, struct ipc_message *msg)
  566. {
  567. struct sst_hsw_stream *stream;
  568. u32 header = msg->header & ~(IPC_STATUS_MASK | IPC_GLB_REPLY_MASK);
  569. u32 stream_id = msg_get_stream_id(header);
  570. u32 stream_msg = msg_get_stream_type(header);
  571. stream = get_stream_by_id(hsw, stream_id);
  572. if (stream == NULL)
  573. return;
  574. switch (stream_msg) {
  575. case IPC_STR_STAGE_MESSAGE:
  576. case IPC_STR_NOTIFICATION:
  577. break;
  578. case IPC_STR_RESET:
  579. trace_ipc_notification("stream reset", stream->reply.stream_hw_id);
  580. break;
  581. case IPC_STR_PAUSE:
  582. stream->running = false;
  583. trace_ipc_notification("stream paused",
  584. stream->reply.stream_hw_id);
  585. break;
  586. case IPC_STR_RESUME:
  587. stream->running = true;
  588. trace_ipc_notification("stream running",
  589. stream->reply.stream_hw_id);
  590. break;
  591. }
  592. }
  593. static int hsw_process_reply(struct sst_hsw *hsw, u32 header)
  594. {
  595. struct ipc_message *msg;
  596. u32 reply = msg_get_global_reply(header);
  597. trace_ipc_reply("processing -->", header);
  598. msg = reply_find_msg(hsw, header);
  599. if (msg == NULL) {
  600. trace_ipc_error("error: can't find message header", header);
  601. return -EIO;
  602. }
  603. /* first process the header */
  604. switch (reply) {
  605. case IPC_GLB_REPLY_PENDING:
  606. trace_ipc_pending_reply("received", header);
  607. msg->pending = true;
  608. hsw->pending = true;
  609. return 1;
  610. case IPC_GLB_REPLY_SUCCESS:
  611. if (msg->pending) {
  612. trace_ipc_pending_reply("completed", header);
  613. sst_dsp_inbox_read(hsw->dsp, msg->rx_data,
  614. msg->rx_size);
  615. hsw->pending = false;
  616. } else {
  617. /* copy data from the DSP */
  618. sst_dsp_outbox_read(hsw->dsp, msg->rx_data,
  619. msg->rx_size);
  620. }
  621. break;
  622. /* these will be rare - but useful for debug */
  623. case IPC_GLB_REPLY_UNKNOWN_MESSAGE_TYPE:
  624. trace_ipc_error("error: unknown message type", header);
  625. msg->errno = -EBADMSG;
  626. break;
  627. case IPC_GLB_REPLY_OUT_OF_RESOURCES:
  628. trace_ipc_error("error: out of resources", header);
  629. msg->errno = -ENOMEM;
  630. break;
  631. case IPC_GLB_REPLY_BUSY:
  632. trace_ipc_error("error: reply busy", header);
  633. msg->errno = -EBUSY;
  634. break;
  635. case IPC_GLB_REPLY_FAILURE:
  636. trace_ipc_error("error: reply failure", header);
  637. msg->errno = -EINVAL;
  638. break;
  639. case IPC_GLB_REPLY_STAGE_UNINITIALIZED:
  640. trace_ipc_error("error: stage uninitialized", header);
  641. msg->errno = -EINVAL;
  642. break;
  643. case IPC_GLB_REPLY_NOT_FOUND:
  644. trace_ipc_error("error: reply not found", header);
  645. msg->errno = -EINVAL;
  646. break;
  647. case IPC_GLB_REPLY_SOURCE_NOT_STARTED:
  648. trace_ipc_error("error: source not started", header);
  649. msg->errno = -EINVAL;
  650. break;
  651. case IPC_GLB_REPLY_INVALID_REQUEST:
  652. trace_ipc_error("error: invalid request", header);
  653. msg->errno = -EINVAL;
  654. break;
  655. case IPC_GLB_REPLY_ERROR_INVALID_PARAM:
  656. trace_ipc_error("error: invalid parameter", header);
  657. msg->errno = -EINVAL;
  658. break;
  659. default:
  660. trace_ipc_error("error: unknown reply", header);
  661. msg->errno = -EINVAL;
  662. break;
  663. }
  664. /* update any stream states */
  665. if (msg_get_global_type(header) == IPC_GLB_STREAM_MESSAGE)
  666. hsw_stream_update(hsw, msg);
  667. /* wake up and return the error if we have waiters on this message ? */
  668. list_del(&msg->list);
  669. tx_msg_reply_complete(hsw, msg);
  670. return 1;
  671. }
  672. static int hsw_stream_message(struct sst_hsw *hsw, u32 header)
  673. {
  674. u32 stream_msg, stream_id, stage_type;
  675. struct sst_hsw_stream *stream;
  676. int handled = 0;
  677. stream_msg = msg_get_stream_type(header);
  678. stream_id = msg_get_stream_id(header);
  679. stage_type = msg_get_stage_type(header);
  680. stream = get_stream_by_id(hsw, stream_id);
  681. if (stream == NULL)
  682. return handled;
  683. stream->header = header;
  684. switch (stream_msg) {
  685. case IPC_STR_STAGE_MESSAGE:
  686. dev_err(hsw->dev, "error: stage msg not implemented 0x%8.8x\n",
  687. header);
  688. break;
  689. case IPC_STR_NOTIFICATION:
  690. schedule_work(&stream->notify_work);
  691. break;
  692. default:
  693. /* handle pending message complete request */
  694. handled = hsw_process_reply(hsw, header);
  695. break;
  696. }
  697. return handled;
  698. }
  699. static int hsw_log_message(struct sst_hsw *hsw, u32 header)
  700. {
  701. u32 operation = (header & IPC_LOG_OP_MASK) >> IPC_LOG_OP_SHIFT;
  702. struct sst_hsw_log_stream *stream = &hsw->log_stream;
  703. int ret = 1;
  704. if (operation != IPC_DEBUG_REQUEST_LOG_DUMP) {
  705. dev_err(hsw->dev,
  706. "error: log msg not implemented 0x%8.8x\n", header);
  707. return 0;
  708. }
  709. mutex_lock(&stream->rw_mutex);
  710. stream->last_pos = stream->curr_pos;
  711. sst_dsp_inbox_read(
  712. hsw->dsp, &stream->curr_pos, sizeof(stream->curr_pos));
  713. mutex_unlock(&stream->rw_mutex);
  714. schedule_work(&stream->notify_work);
  715. return ret;
  716. }
  717. static int hsw_process_notification(struct sst_hsw *hsw)
  718. {
  719. struct sst_dsp *sst = hsw->dsp;
  720. u32 type, header;
  721. int handled = 1;
  722. header = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  723. type = msg_get_global_type(header);
  724. trace_ipc_request("processing -->", header);
  725. /* FW Ready is a special case */
  726. if (!hsw->boot_complete && header & IPC_FW_READY) {
  727. hsw_fw_ready(hsw, header);
  728. return handled;
  729. }
  730. switch (type) {
  731. case IPC_GLB_GET_FW_VERSION:
  732. case IPC_GLB_ALLOCATE_STREAM:
  733. case IPC_GLB_FREE_STREAM:
  734. case IPC_GLB_GET_FW_CAPABILITIES:
  735. case IPC_GLB_REQUEST_DUMP:
  736. case IPC_GLB_GET_DEVICE_FORMATS:
  737. case IPC_GLB_SET_DEVICE_FORMATS:
  738. case IPC_GLB_ENTER_DX_STATE:
  739. case IPC_GLB_GET_MIXER_STREAM_INFO:
  740. case IPC_GLB_MAX_IPC_MESSAGE_TYPE:
  741. case IPC_GLB_RESTORE_CONTEXT:
  742. case IPC_GLB_SHORT_REPLY:
  743. dev_err(hsw->dev, "error: message type %d header 0x%x\n",
  744. type, header);
  745. break;
  746. case IPC_GLB_STREAM_MESSAGE:
  747. handled = hsw_stream_message(hsw, header);
  748. break;
  749. case IPC_GLB_DEBUG_LOG_MESSAGE:
  750. handled = hsw_log_message(hsw, header);
  751. break;
  752. default:
  753. dev_err(hsw->dev, "error: unexpected type %d hdr 0x%8.8x\n",
  754. type, header);
  755. break;
  756. }
  757. return handled;
  758. }
  759. static irqreturn_t hsw_irq_thread(int irq, void *context)
  760. {
  761. struct sst_dsp *sst = (struct sst_dsp *) context;
  762. struct sst_hsw *hsw = sst_dsp_get_thread_context(sst);
  763. u32 ipcx, ipcd;
  764. int handled;
  765. unsigned long flags;
  766. spin_lock_irqsave(&sst->spinlock, flags);
  767. ipcx = sst_dsp_ipc_msg_rx(hsw->dsp);
  768. ipcd = sst_dsp_shim_read_unlocked(sst, SST_IPCD);
  769. /* reply message from DSP */
  770. if (ipcx & SST_IPCX_DONE) {
  771. /* Handle Immediate reply from DSP Core */
  772. handled = hsw_process_reply(hsw, ipcx);
  773. if (handled > 0) {
  774. /* clear DONE bit - tell DSP we have completed */
  775. sst_dsp_shim_update_bits_unlocked(sst, SST_IPCX,
  776. SST_IPCX_DONE, 0);
  777. /* unmask Done interrupt */
  778. sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
  779. SST_IMRX_DONE, 0);
  780. }
  781. }
  782. /* new message from DSP */
  783. if (ipcd & SST_IPCD_BUSY) {
  784. /* Handle Notification and Delayed reply from DSP Core */
  785. handled = hsw_process_notification(hsw);
  786. /* clear BUSY bit and set DONE bit - accept new messages */
  787. if (handled > 0) {
  788. sst_dsp_shim_update_bits_unlocked(sst, SST_IPCD,
  789. SST_IPCD_BUSY | SST_IPCD_DONE, SST_IPCD_DONE);
  790. /* unmask busy interrupt */
  791. sst_dsp_shim_update_bits_unlocked(sst, SST_IMRX,
  792. SST_IMRX_BUSY, 0);
  793. }
  794. }
  795. spin_unlock_irqrestore(&sst->spinlock, flags);
  796. /* continue to send any remaining messages... */
  797. queue_kthread_work(&hsw->kworker, &hsw->kwork);
  798. return IRQ_HANDLED;
  799. }
  800. int sst_hsw_fw_get_version(struct sst_hsw *hsw,
  801. struct sst_hsw_ipc_fw_version *version)
  802. {
  803. int ret;
  804. ret = ipc_tx_message_wait(hsw, IPC_GLB_TYPE(IPC_GLB_GET_FW_VERSION),
  805. NULL, 0, version, sizeof(*version));
  806. if (ret < 0)
  807. dev_err(hsw->dev, "error: get version failed\n");
  808. return ret;
  809. }
  810. /* Mixer Controls */
  811. int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  812. u32 stage_id, u32 channel)
  813. {
  814. int ret;
  815. ret = sst_hsw_stream_get_volume(hsw, stream, stage_id, channel,
  816. &stream->mute_volume[channel]);
  817. if (ret < 0)
  818. return ret;
  819. ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel, 0);
  820. if (ret < 0) {
  821. dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
  822. stream->reply.stream_hw_id, channel);
  823. return ret;
  824. }
  825. stream->mute[channel] = 1;
  826. return 0;
  827. }
  828. int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  829. u32 stage_id, u32 channel)
  830. {
  831. int ret;
  832. stream->mute[channel] = 0;
  833. ret = sst_hsw_stream_set_volume(hsw, stream, stage_id, channel,
  834. stream->mute_volume[channel]);
  835. if (ret < 0) {
  836. dev_err(hsw->dev, "error: can't unmute stream %d channel %d\n",
  837. stream->reply.stream_hw_id, channel);
  838. return ret;
  839. }
  840. return 0;
  841. }
  842. int sst_hsw_stream_get_volume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  843. u32 stage_id, u32 channel, u32 *volume)
  844. {
  845. if (channel > 1)
  846. return -EINVAL;
  847. sst_dsp_read(hsw->dsp, volume,
  848. stream->reply.volume_register_address[channel],
  849. sizeof(*volume));
  850. return 0;
  851. }
  852. int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
  853. struct sst_hsw_stream *stream, u64 curve_duration,
  854. enum sst_hsw_volume_curve curve)
  855. {
  856. /* curve duration in steps of 100ns */
  857. stream->vol_req.curve_duration = curve_duration;
  858. stream->vol_req.curve_type = curve;
  859. return 0;
  860. }
  861. /* stream volume */
  862. int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
  863. struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume)
  864. {
  865. struct sst_hsw_ipc_volume_req *req;
  866. u32 header;
  867. int ret;
  868. trace_ipc_request("set stream volume", stream->reply.stream_hw_id);
  869. if (channel > 1)
  870. return -EINVAL;
  871. if (stream->mute[channel]) {
  872. stream->mute_volume[channel] = volume;
  873. return 0;
  874. }
  875. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
  876. IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
  877. header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
  878. header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
  879. header |= (stage_id << IPC_STG_ID_SHIFT);
  880. req = &stream->vol_req;
  881. req->channel = channel;
  882. req->target_volume = volume;
  883. ret = ipc_tx_message_wait(hsw, header, req, sizeof(*req), NULL, 0);
  884. if (ret < 0) {
  885. dev_err(hsw->dev, "error: set stream volume failed\n");
  886. return ret;
  887. }
  888. return 0;
  889. }
  890. int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
  891. {
  892. int ret;
  893. ret = sst_hsw_mixer_get_volume(hsw, stage_id, channel,
  894. &hsw->mute_volume[channel]);
  895. if (ret < 0)
  896. return ret;
  897. ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel, 0);
  898. if (ret < 0) {
  899. dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
  900. channel);
  901. return ret;
  902. }
  903. hsw->mute[channel] = 1;
  904. return 0;
  905. }
  906. int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel)
  907. {
  908. int ret;
  909. ret = sst_hsw_mixer_set_volume(hsw, stage_id, channel,
  910. hsw->mixer_info.volume_register_address[channel]);
  911. if (ret < 0) {
  912. dev_err(hsw->dev, "error: failed to unmute mixer channel %d\n",
  913. channel);
  914. return ret;
  915. }
  916. hsw->mute[channel] = 0;
  917. return 0;
  918. }
  919. int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
  920. u32 *volume)
  921. {
  922. if (channel > 1)
  923. return -EINVAL;
  924. sst_dsp_read(hsw->dsp, volume,
  925. hsw->mixer_info.volume_register_address[channel],
  926. sizeof(*volume));
  927. return 0;
  928. }
  929. int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
  930. u64 curve_duration, enum sst_hsw_volume_curve curve)
  931. {
  932. /* curve duration in steps of 100ns */
  933. hsw->curve_duration = curve_duration;
  934. hsw->curve_type = curve;
  935. return 0;
  936. }
  937. /* global mixer volume */
  938. int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
  939. u32 volume)
  940. {
  941. struct sst_hsw_ipc_volume_req req;
  942. u32 header;
  943. int ret;
  944. trace_ipc_request("set mixer volume", volume);
  945. /* set both at same time ? */
  946. if (channel == 2) {
  947. if (hsw->mute[0] && hsw->mute[1]) {
  948. hsw->mute_volume[0] = hsw->mute_volume[1] = volume;
  949. return 0;
  950. } else if (hsw->mute[0])
  951. req.channel = 1;
  952. else if (hsw->mute[1])
  953. req.channel = 0;
  954. else
  955. req.channel = 0xffffffff;
  956. } else {
  957. /* set only 1 channel */
  958. if (hsw->mute[channel]) {
  959. hsw->mute_volume[channel] = volume;
  960. return 0;
  961. }
  962. req.channel = channel;
  963. }
  964. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
  965. IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
  966. header |= (hsw->mixer_info.mixer_hw_id << IPC_STR_ID_SHIFT);
  967. header |= (IPC_STG_SET_VOLUME << IPC_STG_TYPE_SHIFT);
  968. header |= (stage_id << IPC_STG_ID_SHIFT);
  969. req.curve_duration = hsw->curve_duration;
  970. req.curve_type = hsw->curve_type;
  971. req.target_volume = volume;
  972. ret = ipc_tx_message_wait(hsw, header, &req, sizeof(req), NULL, 0);
  973. if (ret < 0) {
  974. dev_err(hsw->dev, "error: set mixer volume failed\n");
  975. return ret;
  976. }
  977. return 0;
  978. }
  979. /* Stream API */
  980. struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
  981. u32 (*notify_position)(struct sst_hsw_stream *stream, void *data),
  982. void *data)
  983. {
  984. struct sst_hsw_stream *stream;
  985. struct sst_dsp *sst = hsw->dsp;
  986. unsigned long flags;
  987. stream = kzalloc(sizeof(*stream), GFP_KERNEL);
  988. if (stream == NULL)
  989. return NULL;
  990. spin_lock_irqsave(&sst->spinlock, flags);
  991. list_add(&stream->node, &hsw->stream_list);
  992. stream->notify_position = notify_position;
  993. stream->pdata = data;
  994. stream->hsw = hsw;
  995. stream->host_id = id;
  996. /* work to process notification messages */
  997. INIT_WORK(&stream->notify_work, hsw_notification_work);
  998. spin_unlock_irqrestore(&sst->spinlock, flags);
  999. return stream;
  1000. }
  1001. int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  1002. {
  1003. u32 header;
  1004. int ret = 0;
  1005. struct sst_dsp *sst = hsw->dsp;
  1006. unsigned long flags;
  1007. /* dont free DSP streams that are not commited */
  1008. if (!stream->commited)
  1009. goto out;
  1010. trace_ipc_request("stream free", stream->host_id);
  1011. stream->free_req.stream_id = stream->reply.stream_hw_id;
  1012. header = IPC_GLB_TYPE(IPC_GLB_FREE_STREAM);
  1013. ret = ipc_tx_message_wait(hsw, header, &stream->free_req,
  1014. sizeof(stream->free_req), NULL, 0);
  1015. if (ret < 0) {
  1016. dev_err(hsw->dev, "error: free stream %d failed\n",
  1017. stream->free_req.stream_id);
  1018. return -EAGAIN;
  1019. }
  1020. trace_hsw_stream_free_req(stream, &stream->free_req);
  1021. out:
  1022. cancel_work_sync(&stream->notify_work);
  1023. spin_lock_irqsave(&sst->spinlock, flags);
  1024. list_del(&stream->node);
  1025. kfree(stream);
  1026. spin_unlock_irqrestore(&sst->spinlock, flags);
  1027. return ret;
  1028. }
  1029. int sst_hsw_stream_set_bits(struct sst_hsw *hsw,
  1030. struct sst_hsw_stream *stream, enum sst_hsw_bitdepth bits)
  1031. {
  1032. if (stream->commited) {
  1033. dev_err(hsw->dev, "error: stream committed for set bits\n");
  1034. return -EINVAL;
  1035. }
  1036. stream->request.format.bitdepth = bits;
  1037. return 0;
  1038. }
  1039. int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
  1040. struct sst_hsw_stream *stream, int channels)
  1041. {
  1042. if (stream->commited) {
  1043. dev_err(hsw->dev, "error: stream committed for set channels\n");
  1044. return -EINVAL;
  1045. }
  1046. /* stereo is only supported atm */
  1047. if (channels != 2)
  1048. return -EINVAL;
  1049. stream->request.format.ch_num = channels;
  1050. return 0;
  1051. }
  1052. int sst_hsw_stream_set_rate(struct sst_hsw *hsw,
  1053. struct sst_hsw_stream *stream, int rate)
  1054. {
  1055. if (stream->commited) {
  1056. dev_err(hsw->dev, "error: stream committed for set rate\n");
  1057. return -EINVAL;
  1058. }
  1059. stream->request.format.frequency = rate;
  1060. return 0;
  1061. }
  1062. int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
  1063. struct sst_hsw_stream *stream, u32 map,
  1064. enum sst_hsw_channel_config config)
  1065. {
  1066. if (stream->commited) {
  1067. dev_err(hsw->dev, "error: stream committed for set map\n");
  1068. return -EINVAL;
  1069. }
  1070. stream->request.format.map = map;
  1071. stream->request.format.config = config;
  1072. return 0;
  1073. }
  1074. int sst_hsw_stream_set_style(struct sst_hsw *hsw,
  1075. struct sst_hsw_stream *stream, enum sst_hsw_interleaving style)
  1076. {
  1077. if (stream->commited) {
  1078. dev_err(hsw->dev, "error: stream committed for set style\n");
  1079. return -EINVAL;
  1080. }
  1081. stream->request.format.style = style;
  1082. return 0;
  1083. }
  1084. int sst_hsw_stream_set_valid(struct sst_hsw *hsw,
  1085. struct sst_hsw_stream *stream, u32 bits)
  1086. {
  1087. if (stream->commited) {
  1088. dev_err(hsw->dev, "error: stream committed for set valid bits\n");
  1089. return -EINVAL;
  1090. }
  1091. stream->request.format.valid_bit = bits;
  1092. return 0;
  1093. }
  1094. /* Stream Configuration */
  1095. int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1096. enum sst_hsw_stream_path_id path_id,
  1097. enum sst_hsw_stream_type stream_type,
  1098. enum sst_hsw_stream_format format_id)
  1099. {
  1100. if (stream->commited) {
  1101. dev_err(hsw->dev, "error: stream committed for set format\n");
  1102. return -EINVAL;
  1103. }
  1104. stream->request.path_id = path_id;
  1105. stream->request.stream_type = stream_type;
  1106. stream->request.format_id = format_id;
  1107. trace_hsw_stream_alloc_request(stream, &stream->request);
  1108. return 0;
  1109. }
  1110. int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1111. u32 ring_pt_address, u32 num_pages,
  1112. u32 ring_size, u32 ring_offset, u32 ring_first_pfn)
  1113. {
  1114. if (stream->commited) {
  1115. dev_err(hsw->dev, "error: stream committed for buffer\n");
  1116. return -EINVAL;
  1117. }
  1118. stream->request.ringinfo.ring_pt_address = ring_pt_address;
  1119. stream->request.ringinfo.num_pages = num_pages;
  1120. stream->request.ringinfo.ring_size = ring_size;
  1121. stream->request.ringinfo.ring_offset = ring_offset;
  1122. stream->request.ringinfo.ring_first_pfn = ring_first_pfn;
  1123. trace_hsw_stream_buffer(stream);
  1124. return 0;
  1125. }
  1126. int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
  1127. struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id,
  1128. u32 entry_point)
  1129. {
  1130. struct sst_hsw_module_map *map = &stream->request.map;
  1131. if (stream->commited) {
  1132. dev_err(hsw->dev, "error: stream committed for set module\n");
  1133. return -EINVAL;
  1134. }
  1135. /* only support initial module atm */
  1136. map->module_entries_count = 1;
  1137. map->module_entries[0].module_id = module_id;
  1138. map->module_entries[0].entry_point = entry_point;
  1139. return 0;
  1140. }
  1141. int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
  1142. struct sst_hsw_stream *stream, u32 offset, u32 size)
  1143. {
  1144. if (stream->commited) {
  1145. dev_err(hsw->dev, "error: stream committed for set pmem\n");
  1146. return -EINVAL;
  1147. }
  1148. stream->request.persistent_mem.offset = offset;
  1149. stream->request.persistent_mem.size = size;
  1150. return 0;
  1151. }
  1152. int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
  1153. struct sst_hsw_stream *stream, u32 offset, u32 size)
  1154. {
  1155. if (stream->commited) {
  1156. dev_err(hsw->dev, "error: stream committed for set smem\n");
  1157. return -EINVAL;
  1158. }
  1159. stream->request.scratch_mem.offset = offset;
  1160. stream->request.scratch_mem.size = size;
  1161. return 0;
  1162. }
  1163. int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  1164. {
  1165. struct sst_hsw_ipc_stream_alloc_req *str_req = &stream->request;
  1166. struct sst_hsw_ipc_stream_alloc_reply *reply = &stream->reply;
  1167. u32 header;
  1168. int ret;
  1169. trace_ipc_request("stream alloc", stream->host_id);
  1170. header = IPC_GLB_TYPE(IPC_GLB_ALLOCATE_STREAM);
  1171. ret = ipc_tx_message_wait(hsw, header, str_req, sizeof(*str_req),
  1172. reply, sizeof(*reply));
  1173. if (ret < 0) {
  1174. dev_err(hsw->dev, "error: stream commit failed\n");
  1175. return ret;
  1176. }
  1177. stream->commited = 1;
  1178. trace_hsw_stream_alloc_reply(stream);
  1179. return 0;
  1180. }
  1181. /* Stream Information - these calls could be inline but we want the IPC
  1182. ABI to be opaque to client PCM drivers to cope with any future ABI changes */
  1183. int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
  1184. struct sst_hsw_stream *stream)
  1185. {
  1186. return stream->reply.stream_hw_id;
  1187. }
  1188. int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
  1189. struct sst_hsw_stream *stream)
  1190. {
  1191. return stream->reply.mixer_hw_id;
  1192. }
  1193. u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
  1194. struct sst_hsw_stream *stream)
  1195. {
  1196. return stream->reply.read_position_register_address;
  1197. }
  1198. u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
  1199. struct sst_hsw_stream *stream)
  1200. {
  1201. return stream->reply.presentation_position_register_address;
  1202. }
  1203. u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
  1204. struct sst_hsw_stream *stream, u32 channel)
  1205. {
  1206. if (channel >= 2)
  1207. return 0;
  1208. return stream->reply.peak_meter_register_address[channel];
  1209. }
  1210. u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
  1211. struct sst_hsw_stream *stream, u32 channel)
  1212. {
  1213. if (channel >= 2)
  1214. return 0;
  1215. return stream->reply.volume_register_address[channel];
  1216. }
  1217. int sst_hsw_mixer_get_info(struct sst_hsw *hsw)
  1218. {
  1219. struct sst_hsw_ipc_stream_info_reply *reply;
  1220. u32 header;
  1221. int ret;
  1222. reply = &hsw->mixer_info;
  1223. header = IPC_GLB_TYPE(IPC_GLB_GET_MIXER_STREAM_INFO);
  1224. trace_ipc_request("get global mixer info", 0);
  1225. ret = ipc_tx_message_wait(hsw, header, NULL, 0, reply, sizeof(*reply));
  1226. if (ret < 0) {
  1227. dev_err(hsw->dev, "error: get stream info failed\n");
  1228. return ret;
  1229. }
  1230. trace_hsw_mixer_info_reply(reply);
  1231. return 0;
  1232. }
  1233. /* Send stream command */
  1234. static int sst_hsw_stream_operations(struct sst_hsw *hsw, int type,
  1235. int stream_id, int wait)
  1236. {
  1237. u32 header;
  1238. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) | IPC_STR_TYPE(type);
  1239. header |= (stream_id << IPC_STR_ID_SHIFT);
  1240. if (wait)
  1241. return ipc_tx_message_wait(hsw, header, NULL, 0, NULL, 0);
  1242. else
  1243. return ipc_tx_message_nowait(hsw, header, NULL, 0);
  1244. }
  1245. /* Stream ALSA trigger operations */
  1246. int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1247. int wait)
  1248. {
  1249. int ret;
  1250. trace_ipc_request("stream pause", stream->reply.stream_hw_id);
  1251. ret = sst_hsw_stream_operations(hsw, IPC_STR_PAUSE,
  1252. stream->reply.stream_hw_id, wait);
  1253. if (ret < 0)
  1254. dev_err(hsw->dev, "error: failed to pause stream %d\n",
  1255. stream->reply.stream_hw_id);
  1256. return ret;
  1257. }
  1258. int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
  1259. int wait)
  1260. {
  1261. int ret;
  1262. trace_ipc_request("stream resume", stream->reply.stream_hw_id);
  1263. ret = sst_hsw_stream_operations(hsw, IPC_STR_RESUME,
  1264. stream->reply.stream_hw_id, wait);
  1265. if (ret < 0)
  1266. dev_err(hsw->dev, "error: failed to resume stream %d\n",
  1267. stream->reply.stream_hw_id);
  1268. return ret;
  1269. }
  1270. int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream)
  1271. {
  1272. int ret, tries = 10;
  1273. /* dont reset streams that are not commited */
  1274. if (!stream->commited)
  1275. return 0;
  1276. /* wait for pause to complete before we reset the stream */
  1277. while (stream->running && tries--)
  1278. msleep(1);
  1279. if (!tries) {
  1280. dev_err(hsw->dev, "error: reset stream %d still running\n",
  1281. stream->reply.stream_hw_id);
  1282. return -EINVAL;
  1283. }
  1284. trace_ipc_request("stream reset", stream->reply.stream_hw_id);
  1285. ret = sst_hsw_stream_operations(hsw, IPC_STR_RESET,
  1286. stream->reply.stream_hw_id, 1);
  1287. if (ret < 0)
  1288. dev_err(hsw->dev, "error: failed to reset stream %d\n",
  1289. stream->reply.stream_hw_id);
  1290. return ret;
  1291. }
  1292. /* Stream pointer positions */
  1293. u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
  1294. struct sst_hsw_stream *stream)
  1295. {
  1296. u32 rpos;
  1297. sst_dsp_read(hsw->dsp, &rpos,
  1298. stream->reply.read_position_register_address, sizeof(rpos));
  1299. return rpos;
  1300. }
  1301. /* Stream presentation (monotonic) positions */
  1302. u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
  1303. struct sst_hsw_stream *stream)
  1304. {
  1305. u64 ppos;
  1306. sst_dsp_read(hsw->dsp, &ppos,
  1307. stream->reply.presentation_position_register_address,
  1308. sizeof(ppos));
  1309. return ppos;
  1310. }
  1311. int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
  1312. struct sst_hsw_stream *stream, u32 stage_id, u32 position)
  1313. {
  1314. u32 header;
  1315. int ret;
  1316. trace_stream_write_position(stream->reply.stream_hw_id, position);
  1317. header = IPC_GLB_TYPE(IPC_GLB_STREAM_MESSAGE) |
  1318. IPC_STR_TYPE(IPC_STR_STAGE_MESSAGE);
  1319. header |= (stream->reply.stream_hw_id << IPC_STR_ID_SHIFT);
  1320. header |= (IPC_STG_SET_WRITE_POSITION << IPC_STG_TYPE_SHIFT);
  1321. header |= (stage_id << IPC_STG_ID_SHIFT);
  1322. stream->wpos.position = position;
  1323. ret = ipc_tx_message_nowait(hsw, header, &stream->wpos,
  1324. sizeof(stream->wpos));
  1325. if (ret < 0)
  1326. dev_err(hsw->dev, "error: stream %d set position %d failed\n",
  1327. stream->reply.stream_hw_id, position);
  1328. return ret;
  1329. }
  1330. /* physical BE config */
  1331. int sst_hsw_device_set_config(struct sst_hsw *hsw,
  1332. enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
  1333. enum sst_hsw_device_mode mode, u32 clock_divider)
  1334. {
  1335. struct sst_hsw_ipc_device_config_req config;
  1336. u32 header;
  1337. int ret;
  1338. trace_ipc_request("set device config", dev);
  1339. config.ssp_interface = dev;
  1340. config.clock_frequency = mclk;
  1341. config.mode = mode;
  1342. config.clock_divider = clock_divider;
  1343. trace_hsw_device_config_req(&config);
  1344. header = IPC_GLB_TYPE(IPC_GLB_SET_DEVICE_FORMATS);
  1345. ret = ipc_tx_message_wait(hsw, header, &config, sizeof(config),
  1346. NULL, 0);
  1347. if (ret < 0)
  1348. dev_err(hsw->dev, "error: set device formats failed\n");
  1349. return ret;
  1350. }
  1351. EXPORT_SYMBOL_GPL(sst_hsw_device_set_config);
  1352. /* DX Config */
  1353. int sst_hsw_dx_set_state(struct sst_hsw *hsw,
  1354. enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx)
  1355. {
  1356. u32 header, state_;
  1357. int ret, item;
  1358. header = IPC_GLB_TYPE(IPC_GLB_ENTER_DX_STATE);
  1359. state_ = state;
  1360. trace_ipc_request("PM enter Dx state", state);
  1361. ret = ipc_tx_message_wait(hsw, header, &state_, sizeof(state_),
  1362. dx, sizeof(*dx));
  1363. if (ret < 0) {
  1364. dev_err(hsw->dev, "ipc: error set dx state %d failed\n", state);
  1365. return ret;
  1366. }
  1367. for (item = 0; item < dx->entries_no; item++) {
  1368. dev_dbg(hsw->dev,
  1369. "Item[%d] offset[%x] - size[%x] - source[%x]\n",
  1370. item, dx->mem_info[item].offset,
  1371. dx->mem_info[item].size,
  1372. dx->mem_info[item].source);
  1373. }
  1374. dev_dbg(hsw->dev, "ipc: got %d entry numbers for state %d\n",
  1375. dx->entries_no, state);
  1376. memcpy(&hsw->dx, dx, sizeof(*dx));
  1377. return 0;
  1378. }
  1379. /* Used to save state into hsw->dx_reply */
  1380. int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
  1381. u32 *offset, u32 *size, u32 *source)
  1382. {
  1383. struct sst_hsw_ipc_dx_memory_item *dx_mem;
  1384. struct sst_hsw_ipc_dx_reply *dx_reply;
  1385. int entry_no;
  1386. dx_reply = &hsw->dx;
  1387. entry_no = dx_reply->entries_no;
  1388. trace_ipc_request("PM get Dx state", entry_no);
  1389. if (item >= entry_no)
  1390. return -EINVAL;
  1391. dx_mem = &dx_reply->mem_info[item];
  1392. *offset = dx_mem->offset;
  1393. *size = dx_mem->size;
  1394. *source = dx_mem->source;
  1395. return 0;
  1396. }
  1397. static int msg_empty_list_init(struct sst_hsw *hsw)
  1398. {
  1399. int i;
  1400. hsw->msg = kzalloc(sizeof(struct ipc_message) *
  1401. IPC_EMPTY_LIST_SIZE, GFP_KERNEL);
  1402. if (hsw->msg == NULL)
  1403. return -ENOMEM;
  1404. for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
  1405. init_waitqueue_head(&hsw->msg[i].waitq);
  1406. list_add(&hsw->msg[i].list, &hsw->empty_list);
  1407. }
  1408. return 0;
  1409. }
  1410. void sst_hsw_set_scratch_module(struct sst_hsw *hsw,
  1411. struct sst_module *scratch)
  1412. {
  1413. hsw->scratch = scratch;
  1414. }
  1415. struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw)
  1416. {
  1417. return hsw->dsp;
  1418. }
  1419. static struct sst_dsp_device hsw_dev = {
  1420. .thread = hsw_irq_thread,
  1421. .ops = &haswell_ops,
  1422. };
  1423. int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata)
  1424. {
  1425. struct sst_hsw_ipc_fw_version version;
  1426. struct sst_hsw *hsw;
  1427. struct sst_fw *hsw_sst_fw;
  1428. int ret;
  1429. dev_dbg(dev, "initialising Audio DSP IPC\n");
  1430. hsw = devm_kzalloc(dev, sizeof(*hsw), GFP_KERNEL);
  1431. if (hsw == NULL)
  1432. return -ENOMEM;
  1433. hsw->dev = dev;
  1434. INIT_LIST_HEAD(&hsw->stream_list);
  1435. INIT_LIST_HEAD(&hsw->tx_list);
  1436. INIT_LIST_HEAD(&hsw->rx_list);
  1437. INIT_LIST_HEAD(&hsw->empty_list);
  1438. init_waitqueue_head(&hsw->boot_wait);
  1439. init_waitqueue_head(&hsw->wait_txq);
  1440. ret = msg_empty_list_init(hsw);
  1441. if (ret < 0)
  1442. return -ENOMEM;
  1443. /* start the IPC message thread */
  1444. init_kthread_worker(&hsw->kworker);
  1445. hsw->tx_thread = kthread_run(kthread_worker_fn,
  1446. &hsw->kworker, "%s",
  1447. dev_name(hsw->dev));
  1448. if (IS_ERR(hsw->tx_thread)) {
  1449. ret = PTR_ERR(hsw->tx_thread);
  1450. dev_err(hsw->dev, "error: failed to create message TX task\n");
  1451. goto err_free_msg;
  1452. }
  1453. init_kthread_work(&hsw->kwork, ipc_tx_msgs);
  1454. hsw_dev.thread_context = hsw;
  1455. /* init SST shim */
  1456. hsw->dsp = sst_dsp_new(dev, &hsw_dev, pdata);
  1457. if (hsw->dsp == NULL) {
  1458. ret = -ENODEV;
  1459. goto dsp_err;
  1460. }
  1461. /* keep the DSP in reset state for base FW loading */
  1462. sst_dsp_reset(hsw->dsp);
  1463. hsw_sst_fw = sst_fw_new(hsw->dsp, pdata->fw, hsw);
  1464. if (hsw_sst_fw == NULL) {
  1465. ret = -ENODEV;
  1466. dev_err(dev, "error: failed to load firmware\n");
  1467. goto fw_err;
  1468. }
  1469. /* wait for DSP boot completion */
  1470. sst_dsp_boot(hsw->dsp);
  1471. ret = wait_event_timeout(hsw->boot_wait, hsw->boot_complete,
  1472. msecs_to_jiffies(IPC_BOOT_MSECS));
  1473. if (ret == 0) {
  1474. ret = -EIO;
  1475. dev_err(hsw->dev, "error: ADSP boot timeout\n");
  1476. goto boot_err;
  1477. }
  1478. /* get the FW version */
  1479. sst_hsw_fw_get_version(hsw, &version);
  1480. /* get the globalmixer */
  1481. ret = sst_hsw_mixer_get_info(hsw);
  1482. if (ret < 0) {
  1483. dev_err(hsw->dev, "error: failed to get stream info\n");
  1484. goto boot_err;
  1485. }
  1486. pdata->dsp = hsw;
  1487. return 0;
  1488. boot_err:
  1489. sst_dsp_reset(hsw->dsp);
  1490. sst_fw_free(hsw_sst_fw);
  1491. fw_err:
  1492. sst_dsp_free(hsw->dsp);
  1493. dsp_err:
  1494. kthread_stop(hsw->tx_thread);
  1495. err_free_msg:
  1496. kfree(hsw->msg);
  1497. return ret;
  1498. }
  1499. EXPORT_SYMBOL_GPL(sst_hsw_dsp_init);
  1500. void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata)
  1501. {
  1502. struct sst_hsw *hsw = pdata->dsp;
  1503. sst_dsp_reset(hsw->dsp);
  1504. sst_fw_free_all(hsw->dsp);
  1505. sst_dsp_free(hsw->dsp);
  1506. kfree(hsw->scratch);
  1507. kthread_stop(hsw->tx_thread);
  1508. kfree(hsw->msg);
  1509. }
  1510. EXPORT_SYMBOL_GPL(sst_hsw_dsp_free);