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Aquaris-M10-4G
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drivers
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misc
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mediatek
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eccci
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mt6735
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cldma_reg.h

cldma_reg.h 19 KB
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  1. #ifndef __CLDMA_REG_H__
    2. 

  2. #define __CLDMA_REG_H__
    3. 

  3. 

  4. #include <mt-plat/sync_write.h>
    5. 

  5. #define INFRA_RST0_REG (0x0030)	/* rgu reset cldma reg */
    6. 

  6. #define INFRA_RST1_REG (0x0034)	/* rgu clear cldma reset reg */
    7. 

  7. #define CLDMA_AO_RST_MASK (1<<8)
    8. 

  8. #define CLDMA_PD_RST_MASK (1<<26)
    9. 

  9. /*===========================CLDMA_AO_INDMA: 1000A804-1000A844==================================*/
    10. 

  10. #define CLDMA_AP_UL_START_ADDR_BK_0      (0x0804)
    11. 

  11. 	/* The start address of first TGPD descriptor for power-down back-up. */
    12. 

  12. #define CLDMA_AP_UL_START_ADDR_BK_1      (0x0808)
    13. 

  13. #define CLDMA_AP_UL_START_ADDR_BK_2      (0x080C)
    14. 

  14. #define CLDMA_AP_UL_START_ADDR_BK_3      (0x0810)
    15. 

  15. #define CLDMA_AP_UL_START_ADDR_BK_4      (0x0814)
    16. 

  16. #define CLDMA_AP_UL_START_ADDR_BK_5      (0x0818)
    17. 

  17. #define CLDMA_AP_UL_START_ADDR_BK_6      (0x081C)
    18. 

  18. #define CLDMA_AP_UL_START_ADDR_BK_7      (0x0820)
    19. 

  19. #define CLDMA_AP_UL_CURRENT_ADDR_BK_0    (0x0828)
    20. 

  20. 	/* The address of current processing TGPD descriptor for power-down back-up. */
    21. 

  21. #define CLDMA_AP_UL_CURRENT_ADDR_BK_1    (0x082C)
    22. 

  22. #define CLDMA_AP_UL_CURRENT_ADDR_BK_2    (0x0830)
    23. 

  23. #define CLDMA_AP_UL_CURRENT_ADDR_BK_3    (0x0834)
    24. 

  24. #define CLDMA_AP_UL_CURRENT_ADDR_BK_4    (0x0838)
    25. 

  25. #define CLDMA_AP_UL_CURRENT_ADDR_BK_5    (0x083C)
    26. 

  26. #define CLDMA_AP_UL_CURRENT_ADDR_BK_6    (0x0840)
    27. 

  27. #define CLDMA_AP_UL_CURRENT_ADDR_BK_7    (0x0844)
    28. 

  28. /*===========================CLDMA_AO_OUTDMA:1000AA04-1000AAC8==================================*/
    29. 

  29. #define CLDMA_AP_SO_CFG                     (0x0A04)	/* Operation Configuration */
    30. 

  30. #define CLDMA_AP_SO_DUMMY_2                 (0x0A10)	/* Dummy Register 2 */
    31. 

  31. #define CLDMA_AP_SO_DUMMY_3                 (0x0A14)	/* Dummy Register 3 */
    32. 

  32. #define CLDMA_AP_SO_CHECKSUM_CHANNEL_ENABLE (0x0A74)	/* Per-channel checksum checking function enable */
    33. 

  33. #define CLDMA_AP_SO_START_ADDR_0            (0x0A78)	/* The start address of first RGPD descriptor */
    34. 

  34. #define CLDMA_AP_SO_START_ADDR_1            (0x0A7C)	/* The start address of first RGPD descriptor */
    35. 

  35. #define CLDMA_AP_SO_START_ADDR_2            (0x0A80)	/* The start address of first RGPD descriptor */
    36. 

  36. #define CLDMA_AP_SO_START_ADDR_3            (0x0A84)	/* The start address of first RGPD descriptor */
    37. 

  37. #define CLDMA_AP_SO_START_ADDR_4            (0x0A88)	/* The start address of first RGPD descriptor */
    38. 

  38. #define CLDMA_AP_SO_START_ADDR_5            (0x0A8C)	/* The start address of first RGPD descriptor */
    39. 

  39. #define CLDMA_AP_SO_START_ADDR_6            (0x0A90)	/* The start address of first RGPD descriptor */
    40. 

  40. #define CLDMA_AP_SO_START_ADDR_7            (0x0A94)	/* The start address of first RGPD descriptor */
    41. 

  41. #define CLDMA_AP_SO_CURRENT_ADDR_0          (0x0A98)	/* The address of current processing RGPD descriptor. */
    42. 

  42. #define CLDMA_AP_SO_CURRENT_ADDR_1          (0x0A9C)	/* The address of current processing RGPD descriptor. */
    43. 

  43. #define CLDMA_AP_SO_CURRENT_ADDR_2          (0x0AA0)	/* The address of current processing RGPD descriptor. */
    44. 

  44. #define CLDMA_AP_SO_CURRENT_ADDR_3          (0x0AA4)	/* The address of current processing RGPD descriptor. */
    45. 

  45. #define CLDMA_AP_SO_CURRENT_ADDR_4          (0x0AA8)	/* The address of current processing RGPD descriptor. */
    46. 

  46. #define CLDMA_AP_SO_CURRENT_ADDR_5          (0x0AAC)	/* The address of current processing RGPD descriptor. */
    47. 

  47. #define CLDMA_AP_SO_CURRENT_ADDR_6          (0x0AB0)	/* The address of current processing RGPD descriptor. */
    48. 

  48. #define CLDMA_AP_SO_CURRENT_ADDR_7          (0x0AB4)	/* The address of current processing RGPD descriptor. */
    49. 

  49. #define CLDMA_AP_SO_STATUS                  (0x0AB8)	/* SME OUT SBDMA operation status. */
    50. 

  50. #define CLDMA_AP_DEBUG_ID_EN                (0x0AC8)	/* DEBUG_ID Enable */
    51. 

  51. /*=======================CLDMA_AO_MISC:  1000AC58-1000AD50==================================*/
    52. 

  52. #define CLDMA_AP_L2RIMR0                    (0x0C58)	/* Level 2 Interrupt Mask Register (RX Part) */
    53. 

  53. #define CLDMA_AP_L2RIMR1                    (0x0C5C)	/* Level 2 Interrupt Mask Register (RX Part) */
    54. 

  54. #define CLDMA_AP_L2RIMCR0                   (0x0C60)	/* Level 2 Interrupt Mask Clear Register (RX Part) */
    55. 

  55. #define CLDMA_AP_L2RIMCR1                   (0x0C64)	/* Level 2 Interrupt Mask Clear Register (RX Part) */
    56. 

  56. #define CLDMA_AP_L2RIMSR0                   (0x0C68)	/* Level 2 Interrupt Mask Set Register (RX Part) */
    57. 

  57. #define CLDMA_AP_L2RIMSR1                   (0x0C6C)	/* Level 2 Interrupt Mask Set Register (RX Part) */
    58. 

  58. #define CLDMA_AP_BUS_CFG                    (0x0C90)	/* LTEL2_BUS_INTF configuration register */
    59. 

  59. #define CLDMA_AP_CHNL_DISABLE               (0x0C94)	/* Dma channel disable register */
    60. 

  60. #define CLDMA_AP_HIGH_PRIORITY              (0x0C98)	/* Dma channel high priority register */
    61. 

  61. #define CLDMA_AP_ADDR_REMAP_FROM            (0x0D44)	/* Address Remap From Which Bank */
    62. 

  62. #define CLDMA_AP_ADDR_REMAP_TO              (0x0D48)	/* Address Remap To Which Bank */
    63. 

  63. #define CLDMA_AP_ADDR_REMAP_MASK            (0x0D4C)	/* Address Remap Mask */
    64. 

  64. #define CLDMA_AP_DUMMY                      (0x0D50)	/* Dummy Register */
    65. 

  65. /*=======================CLDMA_PD_INDMA: 1021A000-1021A140==================================*/
    66. 

  66. #define CLDMA_AP_UL_SBDMA_CODA_VERSION      (0x0000)	/* ULSBDMA Version Control Register */
    67. 

  67. #define CLDMA_AP_UL_START_ADDR_0            (0x0004)	/* The start address of first TGPD descriptor */
    68. 

  68. #define CLDMA_AP_UL_START_ADDR_1            (0x0008)	/* The start address of first TGPD descriptor */
    69. 

  69. #define CLDMA_AP_UL_START_ADDR_2            (0x000C)	/* The start address of first TGPD descriptor */
    70. 

  70. #define CLDMA_AP_UL_START_ADDR_3            (0x0010)	/* The start address of first TGPD descriptor */
    71. 

  71. #define CLDMA_AP_UL_START_ADDR_4            (0x0014)	/* The start address of first TGPD descriptor */
    72. 

  72. #define CLDMA_AP_UL_START_ADDR_5            (0x0018)	/* The start address of first TGPD descriptor */
    73. 

  73. #define CLDMA_AP_UL_START_ADDR_6            (0x001C)	/* The start address of first TGPD descriptor */
    74. 

  74. #define CLDMA_AP_UL_START_ADDR_7            (0x0020)	/* The start address of first TGPD descriptor */
    75. 

  75. #define CLDMA_AP_UL_CURRENT_ADDR_0          (0x0028)	/* The address of current processing TGPD descriptor. */
    76. 

  76. #define CLDMA_AP_UL_CURRENT_ADDR_1          (0x002C)	/* The address of current processing TGPD descriptor. */
    77. 

  77. #define CLDMA_AP_UL_CURRENT_ADDR_2          (0x0030)	/* The address of current processing TGPD descriptor. */
    78. 

  78. #define CLDMA_AP_UL_CURRENT_ADDR_3          (0x0034)	/* The address of current processing TGPD descriptor. */
    79. 

  79. #define CLDMA_AP_UL_CURRENT_ADDR_4          (0x0038)	/* The address of current processing TGPD descriptor. */
    80. 

  80. #define CLDMA_AP_UL_CURRENT_ADDR_5          (0x003C)	/* The address of current processing TGPD descriptor. */
    81. 

  81. #define CLDMA_AP_UL_CURRENT_ADDR_6          (0x0040)	/* The address of current processing TGPD descriptor. */
    82. 

  82. #define CLDMA_AP_UL_CURRENT_ADDR_7          (0x0044)	/* The address of current processing TGPD descriptor. */
    83. 

  83. #define CLDMA_AP_UL_STATUS                  (0x0050)	/* UL SBDMA operation status. */
    84. 

  84. #define CLDMA_AP_UL_START_CMD               (0x0054)	/* UL START SBDMA command. */
    85. 

  85. #define CLDMA_AP_UL_RESUME_CMD              (0x0058)	/* UL RESUME SBDMA command. */
    86. 

  86. #define CLDMA_AP_UL_STOP_CMD                (0x005C)	/* UL STOP SBDMA command. */
    87. 

  87. #define CLDMA_AP_UL_ERROR                   (0x0060)	/* ERROR */
    88. 

  88. #define CLDMA_AP_UL_CFG                     (0x0074)	/* Operation Configuration */
    89. 

  89. #define CLDMA_AP_UL_DUMMY_0                 (0x0080)	/* Dummy Register 0 */
    90. 

  90. #define CLDMA_AP_UL_DUMMY_1                 (0x0084)	/* Dummy Register 1 */
    91. 

  91. #define CLDMA_AP_UL_DUMMY_2                 (0x0088)	/* Dummy Register 2 */
    92. 

  92. #define CLDMA_AP_UL_DUMMY_3                 (0x008C)	/* Dummy Register 3 */
    93. 

  93. #define CLDMA_AP_UL_DEBUG_REG_LCMU_0        (0x0090)	/* Debug Register 0 */
    94. 

  94. #define CLDMA_AP_UL_DEBUG_REG_LCMU_1        (0x0094)	/* Debug Register 1 */
    95. 

  95. #define CLDMA_AP_UL_DEBUG_REG_LCMU_2        (0x0098)	/* Debug Register 2 */
    96. 

  96. #define CLDMA_AP_UL_DEBUG_REG_LCMU_3        (0x009C)	/* Debug Register 3 */
    97. 

  97. #define CLDMA_AP_UL_DEBUG_REG_LCMU_4        (0x00A0)	/* Debug Register 4 */
    98. 

  98. #define CLDMA_AP_UL_DEBUG_REG_LCMU_5        (0x00A4)	/* Debug Register 5 */
    99. 

  99. #define CLDMA_AP_UL_DEBUG_REG_LCMU_6        (0x00A8)	/* Debug Register 6 */
    100. 

  100. #define CLDMA_AP_UL_DEBUG_REG_LCMU_7        (0x00AC)	/* Debug Register 7 */
    101. 

  101. #define CLDMA_AP_UL_DEBUG_REG_LCMU_8        (0x00B0)	/* Debug Register 8 */
    102. 

  102. #define CLDMA_AP_UL_DEBUG_REG_LDMU_0        (0x00B4)	/* Debug Register 0 */
    103. 

  103. #define CLDMA_AP_UL_DEBUG_REG_LDMU_1        (0x00B8)	/* Debug Register 1 */
    104. 

  104. #define CLDMA_AP_UL_DEBUG_REG_LDMU_2        (0x00BC)	/* Debug Register 2 */
    105. 

  105. #define CLDMA_AP_UL_DEBUG_REG_LDMU_3        (0x00C0)	/* Debug Register 3 */
    106. 

  106. #define CLDMA_AP_UL_DEBUG_REG_LDMU_4        (0x00C4)	/* Debug Register 4 */
    107. 

  107. #define CLDMA_AP_UL_DEBUG_REG_LDMU_5        (0x00C8)	/* Debug Register 5 */
    108. 

  108. #define CLDMA_AP_UL_DEBUG_REG_LDMU_6        (0x00CC)	/* Debug Register 6 */
    109. 

  109. #define CLDMA_AP_UL_DEBUG_REG_LDMU_7        (0x00D0)	/* Debug Register 7 */
    110. 

  110. #define CLDMA_AP_UL_DEBUG_REG_LDMU_8        (0x00D4)	/* Debug Register 8 */
    111. 

  111. #define CLDMA_AP_UL_DEBUG_REG_LDMU_9        (0x00D8)	/* Debug Register 9 */
    112. 

  112. #define CLDMA_AP_UL_DEBUG_REG_LDMU_10       (0x00DC)	/* Debug Register 10 */
    113. 

  113. #define CLDMA_AP_UL_DEBUG_REG_LDMU_11       (0x00E0)	/* Debug Register 11 */
    114. 

  114. #define CLDMA_AP_UL_DEBUG_REG_LDMU_12       (0x00E4)	/* Debug Register 12 */
    115. 

  115. #define CLDMA_AP_UL_DEBUG_REG_LDMU_13       (0x00E8)	/* Debug Register 13 */
    116. 

  116. #define CLDMA_AP_UL_DEBUG_REG_LDMU_14       (0x00EC)	/* Debug Register 14 */
    117. 

  117. #define CLDMA_AP_UL_DEBUG_REG_LDMU_15       (0x00F0)	/* Debug Register 15 */
    118. 

  118. #define CLDMA_AP_UL_DEBUG_REG_LDMA_0        (0x00F4)	/* Debug Register 0 */
    119. 

  119. #define CLDMA_AP_UL_DEBUG_REG_LDMA_1        (0x00F8)	/* Debug Register 1 */
    120. 

  120. #define CLDMA_AP_UL_DEBUG_REG_LDMA_2        (0x00FC)	/* Debug Register 2 */
    121. 

  121. #define CLDMA_AP_UL_DEBUG_REG_REG_CTL_0     (0x0100)	/* Debug Register 0 */
    122. 

  122. #define CLDMA_AP_UL_DEBUG_REG_REG_CTL_1     (0x0104)	/* Debug Register 1 */
    123. 

  123. #define CLDMA_AP_UL_DEBUG_REG_REG_CTL_2     (0x0108)	/* Debug Register 2 */
    124. 

  124. #define CLDMA_AP_UL_DEBUG_REG_REG_CTL_3     (0x010C)	/* Debug Register 3 */
    125. 

  125. #define CLDMA_AP_HPQTCR                     (0x0110)	/* High priority queue traffic control value */
    126. 

  126. #define CLDMA_AP_LPQTCR                     (0x0114)	/* Low priority queue traffic control value */
    127. 

  127. #define CLDMA_AP_HPQR                       (0x0118)	/* High priority queue register */
    128. 

  128. #define CLDMA_AP_TCR0                       (0x011C)	/* Traffic control value for TX queue 0 */
    129. 

  129. #define CLDMA_AP_TCR1                       (0x0120)	/* Traffic control value for TX queue 1 */
    130. 

  130. #define CLDMA_AP_TCR2                       (0x0124)	/* Traffic control value for TX queue 2 */
    131. 

  131. #define CLDMA_AP_TCR3                       (0x0128)	/* Traffic control value for TX queue 3 */
    132. 

  132. #define CLDMA_AP_TCR4                       (0x012C)	/* Traffic control value for TX queue 4 */
    133. 

  133. #define CLDMA_AP_TCR5                       (0x0130)	/* Traffic control value for TX queue 5 */
    134. 

  134. #define CLDMA_AP_TCR6                       (0x0134)	/* Traffic control value for TX queue 6 */
    135. 

  135. #define CLDMA_AP_TCR7                       (0x0138)	/* Traffic control value for TX queue 7 */
    136. 

  136. #define CLDMA_AP_TCR_CMD                    (0x013C)	/* Traffic control command register */
    137. 

  137. #define CLDMA_AP_UL_CHECKSUM_CHANNEL_ENABLE (0x0140)	/* Per-channel checksum checking function enable */
    138. 

  138. /*========================CLDMA_PD_OUTDMA:1021A200-1021A3C4==================================*/
    139. 

  139. #define CLDMA_AP_SO_OUTDMA_CODA_VERSION     (0x0200)	/* SOOUTDMA Version Control Register */
    140. 

  140. #define CLDMA_AP_SO_ERROR                   (0x0300)	/* ERROR */
    141. 

  141. #define CLDMA_AP_SO_DUMMY_0                 (0x0308)	/* Dummy Register 0 */
    142. 

  142. #define CLDMA_AP_SO_DUMMY_1                 (0x030C)	/* Dummy Register 1 */
    143. 

  143. #define CLDMA_AP_SO_DEBUG_REG_LDMU_0        (0x0318)	/* Debug Register 0 */
    144. 

  144. #define CLDMA_AP_SO_DEBUG_REG_LDMU_1        (0x031C)	/* Debug Register 1 */
    145. 

  145. #define CLDMA_AP_SO_DEBUG_REG_LDMU_2        (0x0320)	/* Debug Register 2 */
    146. 

  146. #define CLDMA_AP_SO_DEBUG_REG_LDMU_3        (0x0324)	/* Debug Register 3 */
    147. 

  147. #define CLDMA_AP_SO_DEBUG_REG_LDMU_4        (0x0328)	/* Debug Register 4 */
    148. 

  148. #define CLDMA_AP_SO_DEBUG_REG_LDMU_5        (0x032C)	/* Debug Register 5 */
    149. 

  149. #define CLDMA_AP_SO_DEBUG_REG_LDMU_6        (0x0330)	/* Debug Register 6 */
    150. 

  150. #define CLDMA_AP_SO_DEBUG_REG_LDMU_7        (0x0334)	/* Debug Register 7 */
    151. 

  151. #define CLDMA_AP_SO_DEBUG_REG_LDMU_8        (0x0338)	/* Debug Register 8 */
    152. 

  152. #define CLDMA_AP_SO_DEBUG_REG_LDMU_9        (0x033C)	/* Debug Register 9 */
    153. 

  153. #define CLDMA_AP_SO_DEBUG_REG_LDMU_10       (0x0340)	/* Debug Register 10 */
    154. 

  154. #define CLDMA_AP_SO_DEBUG_REG_LDMU_11       (0x0344)	/* Debug Register 11 */
    155. 

  155. #define CLDMA_AP_SO_DEBUG_REG_LDMU_12       (0x0348)	/* Debug Register 12 */
    156. 

  156. #define CLDMA_AP_SO_DEBUG_REG_LDMA_0        (0x034C)	/* Debug Register 0 */
    157. 

  157. #define CLDMA_AP_SO_DEBUG_REG_LDMA_1        (0x0350)	/* Debug Register 1 */
    158. 

  158. #define CLDMA_AP_SO_DEBUG_REG_LDMA_2        (0x0354)	/* Debug Register 2 */
    159. 

  159. #define CLDMA_AP_SO_DEBUG_REG_LDMA_3        (0x0358)	/* Debug Register 3 */
    160. 

  160. #define CLDMA_AP_SO_DEBUG_REG_LDMA_4        (0x035C)	/* Debug Register 4 */
    161. 

  161. #define CLDMA_AP_SO_DEBUG_REG_LDMA_5        (0x0360)	/* Debug Register 5 */
    162. 

  162. #define CLDMA_AP_SO_DEBUG_REG_LDMA_6        (0x0364)	/* Debug Register 6 */
    163. 

  163. #define CLDMA_AP_SO_DEBUG_REG_LDMA_7        (0x0368)	/* Debug Register 7 */
    164. 

  164. #define CLDMA_AP_SO_DEBUG_REG_REG_CTL_0     (0x036C)	/* Debug Register 0 */
    165. 

  165. #define CLDMA_AP_SO_DEBUG_REG_REG_CTL_1     (0x0370)	/* Debug Register 1 */
    166. 

  166. #define CLDMA_AP_SO_START_CMD               (0x03BC)	/* SME OUT SBDMA START command. */
    167. 

  167. #define CLDMA_AP_SO_RESUME_CMD              (0x03C0)	/* SO OUTDMA RESUME command. */
    168. 

  168. #define CLDMA_AP_SO_STOP_CMD                (0x03C4)	/* SO OUTDMA STOP command. */
    169. 

  169. /*===========================CLDMA_PD_MISC:  1021A400-1021A4B4================================*/
    170. 

  170. #define CLDMA_AP_CLDMA_CODA_VERSION	(0x0400) /* CLDMAVersion Control Register */
    171. 

  171. #define CLDMA_AP_L2TISAR0		(0x0410) /* Level 2 Interrupt Status and Acknowledgment Register (TX Part) */
    172. 

  172. #define CLDMA_AP_L2TISAR1		(0x0414) /* Level 2 Interrupt Status and Acknowledgment Register (TX Part) */
    173. 

  173. #define CLDMA_AP_L2TIMR0		(0x0418) /* Level 2 Interrupt Mask Register (TX Part) */
    174. 

  174. #define CLDMA_AP_L2TIMR1		(0x041C) /* Level 2 Interrupt Mask Register (TX Part) */
    175. 

  175. #define CLDMA_AP_L2TIMCR0		(0x0420) /* Level 2 Interrupt Mask Clear Register (TX Part) */
    176. 

  176. #define CLDMA_AP_L2TIMCR1		(0x0424) /* Level 2 Interrupt Mask Clear Register (TX Part) */
    177. 

  177. #define CLDMA_AP_L2TIMSR0		(0x0428) /* Level 2 Interrupt Mask Set Register (TX Part) */
    178. 

  178. #define CLDMA_AP_L2TIMSR1		(0x042C) /* Level 2 Interrupt Mask Set Register (TX Part) */
    179. 

  179. #define CLDMA_AP_L3TISAR0		(0x0430) /* Level 3 Interrupt Status and Acknowledgment Register (TX Part) */
    180. 

  180. #define CLDMA_AP_L3TISAR1		(0x0434) /* Level 3 Interrupt Status and Acknowledgment Register (TX Part) */
    181. 

  181. #define CLDMA_AP_L3TIMR0		(0x0438) /* Level 3 Interrupt Mask Register (TX Part) */
    182. 

  182. #define CLDMA_AP_L3TIMR1		(0x043C) /* Level 3 Interrupt Mask Register (TX Part) */
    183. 

  183. #define CLDMA_AP_L3TIMCR0		(0x0440) /* Level 3 Interrupt Mask Clear Register (TX Part) */
    184. 

  184. #define CLDMA_AP_L3TIMCR1		(0x0444) /* Level 3 Interrupt Mask Clear Register (TX Part) */
    185. 

  185. #define CLDMA_AP_L3TIMSR0		(0x0448) /* Level 3 Interrupt Mask Set Register (TX Part) */
    186. 

  186. #define CLDMA_AP_L3TIMSR1		(0x044C) /* Level 3 Interrupt Mask Set Register (TX Part) */
    187. 

  187. #define CLDMA_AP_L2RISAR0		(0x0450) /* Level 2 Interrupt Status and Acknowledgment Register (RX Part) */
    188. 

  188. #define CLDMA_AP_L2RISAR1		(0x0454) /* Level 2 Interrupt Status and Acknowledgment Register (RX Part) */
    189. 

  189. #define CLDMA_AP_L3RISAR0		(0x0470) /* Level 3 Interrupt Status and Acknowledgment Register (RX Part) */
    190. 

  190. #define CLDMA_AP_L3RISAR1		(0x0474) /* Level 3 Interrupt Status and Acknowledgment Register (RX Part) */
    191. 

  191. #define CLDMA_AP_L3RIMR0		(0x0478) /* Level 3 Interrupt Mask Register (RX Part) */
    192. 

  192. #define CLDMA_AP_L3RIMR1		(0x047C) /* Level 3 Interrupt Mask Register (RX Part) */
    193. 

  193. #define CLDMA_AP_L3RIMCR0		(0x0480) /* Level 3 Interrupt Mask Clear Register (RX Part) */
    194. 

  194. #define CLDMA_AP_L3RIMCR1		(0x0484) /* Level 3 Interrupt Mask Clear Register (RX Part) */
    195. 

  195. #define CLDMA_AP_L3RIMSR0		(0x0488) /* Level 3 Interrupt MaskSet Register (RX Part) */
    196. 

  196. #define CLDMA_AP_L3RIMSR1		(0x048C) /* Level 3 Interrupt Mask Set Register (RX Part) */
    197. 

  197. #define CLDMA_AP_BUS_STA		(0x049C) /* LTEL2_BUS_INTF status register */
    198. 

  198. #define CLDMA_AP_BUS_DBG		(0x04A0) /* Debug information of ltel2_axi_master */
    199. 

  199. #define CLDMA_AP_DBG_RDATA		(0x04A4) /* Debug information (rdata) of ltel2_axi_master */
    200. 

  200. #define CLDMA_AP_DBG_WADDR		(0x04A8) /* Debug information (waddr) of ltel2_axi_master */
    201. 

  201. #define CLDMA_AP_DBG_WDATA		(0x04AC) /* Debug information (wdata) of ltel2_axi_master */
    202. 

  202. #define CLDMA_AP_CHNL_IDLE		(0x04B0) /* Dma channel idle */
    203. 

  203. #define CLDMA_AP_CLDMA_IP_BUSY		(0x04B4) /* Half DMA busy status */
    204. 

  204. 

  205. /*assistant macros*/
    206. 

  206. #define CLDMA_AP_TQSAR(i)  (CLDMA_AP_UL_START_ADDR_0   + (4 * (i)))
    207. 

  207. #define CLDMA_AP_TQCPR(i)  (CLDMA_AP_UL_CURRENT_ADDR_0 + (4 * (i)))
    208. 

  208. #define CLDMA_AP_RQSAR(i)  (CLDMA_AP_SO_START_ADDR_0   + (4 * (i)))
    209. 

  209. #define CLDMA_AP_RQCPR(i)  (CLDMA_AP_SO_CURRENT_ADDR_0 + (4 * (i)))
    210. 

  210. #define CLDMA_AP_TQTCR(i)  (CLDMA_AP_TCR0 + (4 * (i)))
    211. 

  211. #define CLDMA_AP_TQSABAK(i)  (CLDMA_AP_UL_START_ADDR_BK_0 + (4 * (i)))
    212. 

  212. #define CLDMA_AP_TQCPBAK(i)  (CLDMA_AP_UL_CURRENT_ADDR_BK_0 + (4 * (i)))
    213. 

  213. 

  214. #define cldma_write32(b, a, v)			mt_reg_sync_writel(v, (b)+(a))
    215. 

  215. #define cldma_write16(b, a, v)			mt_reg_sync_writew(v, (b)+(a))
    216. 

  216. #define cldma_write8(b, a, v)			mt_reg_sync_writeb(v, (b)+(a))
    217. 

  217. 

  218. #define cldma_read32(b, a)				ioread32((void __iomem *)((b)+(a)))
    219. 

  219. #define cldma_read16(b, a)				ioread16((void __iomem *)((b)+(a)))
    220. 

  220. #define cldma_read8(b, a)				ioread8((void __iomem *)((b)+(a)))
    221. 

  221. 

  222. /*bitmap*/
    223. 

  223. #define CLDMA_BM_INT_ALL			0xFFFFFFFF
    224. 

  224. /* L2 interrupt */
    225. 

  225. #define CLDMA_BM_INT_ACTIVE_START	0xFF000000 /* trigger start command on one active queue */
    226. 

  226. #define CLDMA_BM_INT_ERROR		0x00FF0000
    227. 

  227. 	/* error occurred on the specified queue, check L3 interrupt register for detail */
    228. 

  228. #define CLDMA_BM_INT_QUEUE_EMPTY	0x0000FF00 /* when there is no GPD to be transmitted on the specified queue */
    229. 

  229. #define CLDMA_BM_INT_DONE		0x000000FF /* when the transmission if the GPD on the specified queue is done */
    230. 

  230. #define CLDMA_BM_INT_ACTIVE_LD_TC	0x000000FF /* modify TC register when one Tx channel is active */
    231. 

  231. #define CLDMA_BM_INT_INACTIVE_ERR	0x000000FF /* asserted when a specified Rx queue is inactive */
    232. 

  232. /* L3 interrupt */
    233. 

  233. #define CLDMA_BM_INT_BD_LEN_ERR		0xFF000000 /* asserted when a length fild in BD is not configured correctly */
    234. 

  234. #define CLDMA_BM_INT_GPD_LEN_ERR	0x00FF0000 /* asserted when a length fild in GPD is not configured correctly */
    235. 

  235. #define CLDMA_BM_INT_BD_CSERR		0x0000FF00 /* asserted when the BD checksum error happen */
    236. 

  236. #define CLDMA_BM_INT_GPD_CSERR		0x000000FF /* asserted when the GPD checksum error happen */
    237. 

  237. #define CLDMA_BM_INT_DATA_LEN_MIS	0x00FF0000 /* TGPD data length mismatch error happen */
    238. 

  238. #define CLDMA_BM_INT_BD_64KERR		0x0000FF00 /* asserted when the TBD length is more than 64K */
    239. 

  239. #define CLDMA_BM_INT_GPD_64KERR		0x000000FF /* asserted when the TGPD length is more than 64K */
    240. 

  240. #define CLDMA_BM_INT_RBIDX_ERR		0x80000000 /* internal error for Rx queue */
    241. 

  241. #define CLDMA_BM_INT_FIFO_LEN_MIS	0x0000FF00 /* internal error for Rx queue */
    242. 

  242. #define CLDMA_BM_INT_ALLEN			0x000000FF
    243. 

  243. 	/* asserted when the RGPD/RBD allow data buffer length is not enough */
    244. 

  244. 

  245. #define CLDMA_BM_ALL_QUEUE 0x7F	/* all 7 queues */
    246. 

  246. 

  247. #endif				/* __CLDMA_REG_H__ */
    248.