hdmi_drv.c 35 KB

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  1. /*----------------------------------------------------------------------------*/
  2. #ifdef HDMI_MT8193_SUPPORT
  3. #include <linux/interrupt.h>
  4. #include <linux/i2c.h>
  5. #include <linux/slab.h>
  6. #include <linux/irq.h>
  7. #include <linux/miscdevice.h>
  8. #include <asm/uaccess.h>
  9. #include <linux/delay.h>
  10. #include <linux/input.h>
  11. #include <linux/workqueue.h>
  12. #include <linux/kobject.h>
  13. #ifdef CONFIG_HAS_EARLYSUSPEND
  14. #include <linux/earlysuspend.h>
  15. #endif
  16. #include <linux/platform_device.h>
  17. #include <asm/atomic.h>
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/sched.h>
  21. #include <linux/kthread.h>
  22. #include <linux/bitops.h>
  23. #include <linux/kernel.h>
  24. #include <linux/byteorder/generic.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/time.h>
  27. #include <linux/rtpm_prio.h>
  28. #include <linux/dma-mapping.h>
  29. #include <linux/syscalls.h>
  30. #include <linux/reboot.h>
  31. #include <linux/vmalloc.h>
  32. #include <linux/fs.h>
  33. #include <linux/string.h>
  34. #include <linux/completion.h>
  35. #include <linux/debugfs.h>
  36. #include <linux/of_platform.h>
  37. #include <linux/of_irq.h>
  38. #include <linux/of_address.h>
  39. #include <linux/clk.h>
  40. #include <linux/of_gpio.h>
  41. #include <linux/gpio.h>
  42. #include <linux/uaccess.h>
  43. #include <linux/types.h>
  44. #include <mt-plat/mt_gpio.h>
  45. #include "mt8193_ctrl.h"
  46. #include "mt8193ddc.h"
  47. #include "mt8193hdcp.h"
  48. #include "hdmi_drv.h"
  49. #include "mt8193_iic.h"
  50. #include "mt8193avd.h"
  51. #include "mt8193hdmicmd.h"
  52. #include "extd_factory.h"
  53. #include "ddp_hal.h"
  54. #include "extd_hdmi.h"
  55. #include "mt_boot_common.h"
  56. /*----------------------------------------------------------------------------*/
  57. /* Debug message defination */
  58. /*----------------------------------------------------------------------------*/
  59. /*----------------------------------------------------------------------------*/
  60. /* HDMI Timer */
  61. /*----------------------------------------------------------------------------*/
  62. static struct timer_list r_hdmi_timer;
  63. static struct timer_list r_cec_timer;
  64. static uint32_t gHDMI_CHK_INTERVAL = 10;
  65. static uint32_t gCEC_CHK_INTERVAL = 20;
  66. unsigned int mt8193_log_on = hdmideflog;
  67. unsigned int mt8193_cec_on = 0;
  68. unsigned int mt8193_cec_interrupt = 0;
  69. unsigned int mt8193_cecinit = 0;
  70. unsigned char mt8193_hdmiinit = 0;
  71. unsigned char mt8193_hotinit = 0;
  72. unsigned char hdmi_powerenable = 0xff;
  73. unsigned char is_hdmi_plug_out_flag = 0;
  74. unsigned char mt8193_hdmipoweroninit = 0;
  75. size_t mt8193_TmrValue[MAX_HDMI_TMR_NUMBER] = { 0 };
  76. size_t mt8193_hdmiCmd = 0xff;
  77. size_t mt8193_rxcecmode = CEC_NORMAL_MODE;
  78. HDMI_CTRL_STATE_T e_hdmi_ctrl_state = HDMI_STATE_IDLE;
  79. HDCP_CTRL_STATE_T e_hdcp_ctrl_state = HDCP_RECEIVER_NOT_READY;
  80. unsigned int mt8193_hotplugstate = HDMI_STATE_HOT_PLUG_OUT;
  81. #if defined(CONFIG_HAS_EARLYSUSPEND)
  82. size_t mt8193_hdmiearlysuspend = 1;
  83. #endif
  84. static struct task_struct *hdmi_timer_task;
  85. wait_queue_head_t hdmi_timer_wq;
  86. atomic_t hdmi_timer_event = ATOMIC_INIT(0);
  87. static struct task_struct *cec_timer_task;
  88. wait_queue_head_t cec_timer_wq;
  89. atomic_t cec_timer_event = ATOMIC_INIT(0);
  90. static struct task_struct *mt8193_nlh_task;
  91. wait_queue_head_t mt8193_nlh_wq; /* NFI, LVDS, HDMI */
  92. atomic_t mt8193_nlh_event = ATOMIC_INIT(0);
  93. static struct HDMI_UTIL_FUNCS hdmi_util = { 0 };
  94. static int hdmi_timer_kthread(void *data);
  95. static int cec_timer_kthread(void *data);
  96. static int mt8193_nlh_kthread(void *data);
  97. void (*mt8193_hdmi_factory_callback)(enum HDMI_STATE state);
  98. void (*mt8193_hdmi_unfactory_callback)(enum HDMI_STATE state);
  99. static void vInitAvInfoVar(void)
  100. {
  101. _stAvdAVInfo.e_resolution = HDMI_VIDEO_1280x720p_60Hz;
  102. _stAvdAVInfo.fgHdmiOutEnable = TRUE;
  103. _stAvdAVInfo.fgHdmiTmdsEnable = TRUE;
  104. _stAvdAVInfo.bMuteHdmiAudio = FALSE;
  105. _stAvdAVInfo.e_video_color_space = HDMI_RGB;
  106. _stAvdAVInfo.e_deep_color_bit = HDMI_NO_DEEP_COLOR;
  107. _stAvdAVInfo.ui1_aud_out_ch_number = 2;
  108. _stAvdAVInfo.e_hdmi_fs = HDMI_FS_44K;
  109. _stAvdAVInfo.bhdmiRChstatus[0] = 0x00;
  110. _stAvdAVInfo.bhdmiRChstatus[1] = 0x00;
  111. _stAvdAVInfo.bhdmiRChstatus[2] = 0x02;
  112. _stAvdAVInfo.bhdmiRChstatus[3] = 0x00;
  113. _stAvdAVInfo.bhdmiRChstatus[4] = 0x00;
  114. _stAvdAVInfo.bhdmiRChstatus[5] = 0x00;
  115. _stAvdAVInfo.bhdmiLChstatus[0] = 0x00;
  116. _stAvdAVInfo.bhdmiLChstatus[1] = 0x00;
  117. _stAvdAVInfo.bhdmiLChstatus[2] = 0x02;
  118. _stAvdAVInfo.bhdmiLChstatus[3] = 0x00;
  119. _stAvdAVInfo.bhdmiLChstatus[4] = 0x00;
  120. _stAvdAVInfo.bhdmiLChstatus[5] = 0x00;
  121. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS, HDMI_PLUG_OUT);
  122. }
  123. void vSetHDMIMdiTimeOut(unsigned int i4_count)
  124. {
  125. MT8193_DRV_FUNC();
  126. mt8193_TmrValue[HDMI_PLUG_DETECT_CMD] = i4_count;
  127. }
  128. /*----------------------------------------------------------------------------*/
  129. static void mt8193_set_util_funcs(const struct HDMI_UTIL_FUNCS *util)
  130. {
  131. memcpy(&hdmi_util, util, sizeof(struct HDMI_UTIL_FUNCS));
  132. }
  133. /*----------------------------------------------------------------------------*/
  134. static void mt8193_get_params(struct HDMI_PARAMS *params)
  135. {
  136. enum HDMI_VIDEO_RESOLUTION input_resolution;
  137. input_resolution = params->init_config.vformat;
  138. memset(params, 0, sizeof(struct HDMI_PARAMS));
  139. switch (input_resolution) {
  140. case HDMI_VIDEO_720x480p_60Hz:
  141. params->clk_pol = HDMI_POLARITY_FALLING;
  142. params->de_pol = HDMI_POLARITY_RISING;
  143. params->hsync_pol = HDMI_POLARITY_RISING;
  144. params->vsync_pol = HDMI_POLARITY_RISING;
  145. params->hsync_pulse_width = 62;
  146. params->hsync_back_porch = 60;
  147. params->hsync_front_porch = 16;
  148. params->vsync_pulse_width = 6;
  149. params->vsync_back_porch = 30;
  150. params->vsync_front_porch = 9;
  151. params->width = 720;
  152. params->height = 480;
  153. params->input_clock = 27027;
  154. params->init_config.vformat = HDMI_VIDEO_720x480p_60Hz;
  155. break;
  156. case HDMI_VIDEO_1280x720p_60Hz:
  157. params->clk_pol = HDMI_POLARITY_FALLING;
  158. params->de_pol = HDMI_POLARITY_RISING;
  159. params->hsync_pol = HDMI_POLARITY_FALLING;
  160. params->vsync_pol = HDMI_POLARITY_FALLING;
  161. params->hsync_pulse_width = 40;
  162. params->hsync_back_porch = 220;
  163. params->hsync_front_porch = 110;
  164. params->vsync_pulse_width = 5;
  165. params->vsync_back_porch = 20;
  166. params->vsync_front_porch = 5;
  167. params->width = 1280;
  168. params->height = 720;
  169. params->input_clock = 74250;
  170. params->init_config.vformat = HDMI_VIDEO_1280x720p_60Hz;
  171. break;
  172. case HDMI_VIDEO_1920x1080p_30Hz:
  173. params->clk_pol = HDMI_POLARITY_FALLING;
  174. params->de_pol = HDMI_POLARITY_RISING;
  175. params->hsync_pol = HDMI_POLARITY_FALLING;
  176. params->vsync_pol = HDMI_POLARITY_FALLING;
  177. params->hsync_pulse_width = 44;
  178. params->hsync_back_porch = 148;
  179. params->hsync_front_porch = 88;
  180. params->vsync_pulse_width = 5;
  181. params->vsync_back_porch = 36;
  182. params->vsync_front_porch = 4;
  183. params->width = 1920;
  184. params->height = 1080;
  185. params->input_clock = 74250;
  186. params->init_config.vformat = HDMI_VIDEO_1920x1080p_30Hz;
  187. break;
  188. case HDMI_VIDEO_1920x1080p_60Hz:
  189. params->clk_pol = HDMI_POLARITY_FALLING;
  190. params->de_pol = HDMI_POLARITY_RISING;
  191. params->hsync_pol = HDMI_POLARITY_FALLING;
  192. params->vsync_pol = HDMI_POLARITY_FALLING;
  193. params->hsync_pulse_width = 44;
  194. params->hsync_back_porch = 148;
  195. params->hsync_front_porch = 88;
  196. params->vsync_pulse_width = 5;
  197. params->vsync_back_porch = 36;
  198. params->vsync_front_porch = 4;
  199. params->width = 1920;
  200. params->height = 1080;
  201. params->input_clock = 148500;
  202. params->init_config.vformat = HDMI_VIDEO_1920x1080p_60Hz;
  203. break;
  204. default:
  205. HDMI_DEF_LOG("Unknown support resolution\n");
  206. break;
  207. }
  208. params->init_config.aformat = HDMI_AUDIO_44K_2CH;
  209. params->rgb_order = HDMI_COLOR_ORDER_RGB;
  210. params->io_driving_current = IO_DRIVING_CURRENT_2MA;
  211. params->intermediat_buffer_num = 4;
  212. params->scaling_factor = 0;
  213. params->cabletype = 0;
  214. params->HDCPSupported = 0;
  215. params->is_force_awake = 1;
  216. }
  217. static int mt8193_enter(void)
  218. {
  219. MT8193_DRV_FUNC();
  220. return 0;
  221. }
  222. static int mt8193_exit(void)
  223. {
  224. MT8193_DRV_FUNC();
  225. return 0;
  226. }
  227. /*----------------------------------------------------------------------------*/
  228. static void mt8193_suspend(void)
  229. {
  230. MT8193_DRV_FUNC();
  231. _stAvdAVInfo.fgHdmiTmdsEnable = 0;
  232. av_hdmiset(HDMI_SET_TURN_OFF_TMDS, &_stAvdAVInfo, 1);
  233. }
  234. /*----------------------------------------------------------------------------*/
  235. static void mt8193_resume(void)
  236. {
  237. MT8193_DRV_FUNC();
  238. }
  239. /*----------------------------------------------------------------------------*/
  240. static int mt8193_video_config(enum HDMI_VIDEO_RESOLUTION vformat, enum HDMI_VIDEO_INPUT_FORMAT vin,
  241. enum HDMI_VIDEO_OUTPUT_FORMAT vout)
  242. {
  243. HDMI_DEF_LOG("[hdmi]mt8193_video_config:%d\n", vformat);
  244. _stAvdAVInfo.e_resolution = vformat;
  245. vSetHDMITxPLLTrigger();
  246. vResetHDMIPLL();
  247. _stAvdAVInfo.fgHdmiTmdsEnable = 0;
  248. av_hdmiset(HDMI_SET_TURN_OFF_TMDS, &_stAvdAVInfo, 1);
  249. av_hdmiset(HDMI_SET_VPLL, &_stAvdAVInfo, 1);
  250. av_hdmiset(HDMI_SET_SOFT_NCTS, &_stAvdAVInfo, 1);
  251. av_hdmiset(HDMI_SET_VIDEO_RES_CHG, &_stAvdAVInfo, 1);
  252. if (get_boot_mode() != FACTORY_BOOT)
  253. av_hdmiset(HDMI_SET_HDCP_INITIAL_AUTH, &_stAvdAVInfo, 1);
  254. mt8193_hdmiinit = 1;
  255. return 0;
  256. }
  257. /*----------------------------------------------------------------------------*/
  258. static int mt8193_audio_config(enum HDMI_AUDIO_FORMAT aformat, int bitWidth)
  259. {
  260. MT8193_DRV_FUNC();
  261. if (aformat == HDMI_AUDIO_32K_2CH) {
  262. HDMI_DEF_LOG("[hdmi]HDMI_AUDIO_32K_2CH\n");
  263. _stAvdAVInfo.e_hdmi_fs = HDMI_FS_32K;
  264. } else if (aformat == HDMI_AUDIO_44K_2CH) {
  265. HDMI_DEF_LOG("[hdmi]HDMI_AUDIO_44K_2CH\n");
  266. _stAvdAVInfo.e_hdmi_fs = HDMI_FS_44K;
  267. } else if (aformat == HDMI_AUDIO_48K_2CH) {
  268. HDMI_DEF_LOG("[hdmi]HDMI_AUDIO_48K_2CH\n");
  269. _stAvdAVInfo.e_hdmi_fs = HDMI_FS_48K;
  270. } else {
  271. HDMI_DEF_LOG("[hdmi]not support audio format, force to HDMI_AUDIO_44K_2CH\n");
  272. _stAvdAVInfo.e_hdmi_fs = HDMI_FS_44K;
  273. }
  274. av_hdmiset(HDMI_SET_AUDIO_CHG_SETTING, &_stAvdAVInfo, 1);
  275. return 0;
  276. }
  277. /*----------------------------------------------------------------------------*/
  278. static int mt8193_video_enable(bool enable)
  279. {
  280. MT8193_DRV_FUNC();
  281. return 0;
  282. }
  283. /*----------------------------------------------------------------------------*/
  284. static int mt8193_audio_enable(bool enable)
  285. {
  286. MT8193_DRV_FUNC();
  287. if (enable)
  288. hdmi_user_mute_audio(0);
  289. else
  290. hdmi_user_mute_audio(1);
  291. return 0;
  292. }
  293. /*----------------------------------------------------------------------------*/
  294. /*----------------------------------------------------------------------------*/
  295. void mt8193_set_mode(unsigned char ucMode)
  296. {
  297. MT8193_DRV_FUNC();
  298. vSetClk();
  299. }
  300. /*----------------------------------------------------------------------------*/
  301. int mt8193_power_on(void)
  302. {
  303. struct device_node *dn;
  304. int bus_switch_pin;
  305. HDMI_DEF_LOG("[hdmi]mt8193_power_on_\n");
  306. if (hdmi_powerenable == 1) {
  307. HDMI_DEF_LOG("[hdmi]already power on, return\n");
  308. return 0;
  309. }
  310. hdmi_powerenable = 1;
  311. #if defined(CONFIG_HAS_EARLYSUSPEND)
  312. if (mt8193_hdmiearlysuspend == 0)
  313. return 0;
  314. #endif
  315. mt8193_hotinit = 0;
  316. mt8193_hotplugstate = HDMI_STATE_HOT_PLUG_OUT;
  317. is_hdmi_plug_out_flag = 0;
  318. #ifdef GPIO_HDMI_POWER_CONTROL
  319. mt_set_gpio_mode(GPIO_HDMI_POWER_CONTROL, GPIO_MODE_00);
  320. mt_set_gpio_dir(GPIO_HDMI_POWER_CONTROL, GPIO_DIR_OUT);
  321. mt_set_gpio_out(GPIO_HDMI_POWER_CONTROL, GPIO_OUT_ONE);
  322. HDMI_DEF_LOG("[hdmi]hdmi_5v_on\n");
  323. #endif
  324. dn = of_find_compatible_node(NULL, NULL, "mediatek,mt8193-hdmi");
  325. bus_switch_pin = of_get_named_gpio(dn, "hdmi_power_gpios", 0);
  326. gpio_direction_output(bus_switch_pin, 1);
  327. vWriteHdmiSYSMsk(HDMI_PWR_CTRL, hdmi_power_turnon, hdmi_power_turnon);
  328. vWriteHdmiSYSMsk(HDMI_SYS_PWR_RST_B, hdmi_pwr_sys_sw_unreset, hdmi_pwr_sys_sw_unreset);
  329. vWriteHdmiSYSMsk(HDMI_PWR_CTRL, hdmi_iso_dis, hdmi_iso_en);
  330. vWriteHdmiSYSMsk(HDMI_PWR_CTRL, hdmi_clock_on, hdmi_clock_off);
  331. vWriteHdmiSYSMsk(HDMI_SYS_CFG1C, ANLG_ON | HDMI_ON, ANLG_ON | HDMI_ON);
  332. mt8193_i2c_write(0x1500, 0x20);
  333. vHotPlugPinInit();
  334. vInitHdcpKeyGetMethod(NON_HOST_ACCESS_FROM_EEPROM);
  335. vWriteHdmiIntMask(0xFF);
  336. mod_timer(&r_hdmi_timer, jiffies + gHDMI_CHK_INTERVAL / (1000 / HZ));
  337. mod_timer(&r_cec_timer, jiffies + gCEC_CHK_INTERVAL / (1000 / HZ));
  338. return 0;
  339. }
  340. /*----------------------------------------------------------------------------*/
  341. void mt8193_power_off(void)
  342. {
  343. struct device_node *dn;
  344. int bus_switch_pin;
  345. HDMI_DEF_LOG("[hdmi]mt8193_power_off\n");
  346. if (hdmi_powerenable == 0) {
  347. HDMI_DEF_LOG("[hdmi]already power off, return\n");
  348. return;
  349. }
  350. hdmi_powerenable = 0;
  351. is_hdmi_plug_out_flag = 1;
  352. mt8193_hotinit = 1;
  353. mt8193_hotplugstate = HDMI_STATE_HOT_PLUG_OUT;
  354. #if defined(CONFIG_HAS_EARLYSUSPEND)
  355. if (mt8193_hdmiearlysuspend == 1)
  356. is_hdmi_plug_out_flag = 1;
  357. else
  358. is_hdmi_plug_out_flag = 0;
  359. #endif
  360. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS, HDMI_PLUG_OUT);
  361. vWriteHdmiIntMask(0xFF);
  362. vWriteHdmiSYSMsk(HDMI_SYS_CFG1C, 0, ANLG_ON | HDMI_ON);
  363. #ifdef GPIO_HDMI_POWER_CONTROL
  364. mt_set_gpio_mode(GPIO_HDMI_POWER_CONTROL, GPIO_MODE_00);
  365. mt_set_gpio_dir(GPIO_HDMI_POWER_CONTROL, GPIO_DIR_OUT);
  366. mt_set_gpio_out(GPIO_HDMI_POWER_CONTROL, GPIO_OUT_ZERO);
  367. HDMI_DEF_LOG("[hdmi]hdmi_5v_off\n");
  368. #endif
  369. dn = of_find_compatible_node(NULL, NULL, "mediatek,mt8193-hdmi");
  370. bus_switch_pin = of_get_named_gpio(dn, "hdmi_power_gpios", 0);
  371. gpio_direction_output(bus_switch_pin, 0);
  372. vWriteHdmiSYSMsk(HDMI_PWR_CTRL, hdmi_clock_off, hdmi_clock_off);
  373. vWriteHdmiSYSMsk(HDMI_PWR_CTRL, hdmi_iso_en, hdmi_iso_en);
  374. vWriteHdmiSYSMsk(HDMI_SYS_PWR_RST_B, hdmi_pwr_sys_sw_reset, hdmi_pwr_sys_sw_unreset);
  375. vWriteHdmiSYSMsk(HDMI_PWR_CTRL, hdmi_power_turnoff, hdmi_power_turnon);
  376. }
  377. void mt8193_register_callback(CABLE_INSERT_CALLBACK cb)
  378. {
  379. mt8193_hdmi_factory_callback = cb;
  380. }
  381. void mt8193_unregister_callback(CABLE_INSERT_CALLBACK cb)
  382. {
  383. mt8193_hdmi_factory_callback = NULL;
  384. }
  385. /*----------------------------------------------------------------------------*/
  386. void mt8193_dump(void)
  387. {
  388. MT8193_DRV_FUNC();
  389. /* mt8193_dump_reg(); */
  390. }
  391. /*----------------------------------------------------------------------------*/
  392. /*----------------------------------------------------------------------------*/
  393. enum HDMI_STATE mt8193_get_state(void)
  394. {
  395. MT8193_DRV_FUNC();
  396. if (mt8193_hotplugstate == HDMI_STATE_HOT_PLUGIN_AND_POWER_ON)
  397. return HDMI_STATE_ACTIVE;
  398. else
  399. return HDMI_STATE_NO_DEVICE;
  400. }
  401. /*----------------------------------------------------------------------------*/
  402. void mt8193_log_enable(unsigned short enable)
  403. {
  404. MT8193_DRV_FUNC();
  405. if (enable == 0) {
  406. hdmi_print("hdmi_pll_log = 0x1\n");
  407. hdmi_print("hdmi_dgi_log = 0x2\n");
  408. hdmi_print("hdmi_plug_log = 0x4\n");
  409. hdmi_print("hdmi_video_log = 0x8\n");
  410. hdmi_print("hdmi_audio_log = 0x10\n");
  411. hdmi_print("hdmi_hdcp_log = 0x20\n");
  412. hdmi_print("hdmi_cec_log = 0x40\n");
  413. hdmi_print("hdmi_ddc_log = 0x80\n");
  414. hdmi_print("hdmi_edid_log = 0x100\n");
  415. hdmi_print("hdmi_drv_log = 0x200\n");
  416. hdmi_print("hdmi_all_log = 0xffff\n");
  417. }
  418. mt8193_log_on = enable;
  419. }
  420. /*----------------------------------------------------------------------------*/
  421. void mt8193_enablehdcp(unsigned char u1hdcponoff)
  422. {
  423. MT8193_DRV_FUNC();
  424. _stAvdAVInfo.u1hdcponoff = u1hdcponoff;
  425. av_hdmiset(HDMI_SET_HDCP_OFF, &_stAvdAVInfo, 1);
  426. }
  427. void mt8193_setcecrxmode(unsigned char u1cecrxmode)
  428. {
  429. MT8193_DRV_FUNC();
  430. mt8193_rxcecmode = u1cecrxmode;
  431. }
  432. void mt8193_colordeep(unsigned char u1colorspace, unsigned char u1deepcolor)
  433. {
  434. MT8193_DRV_FUNC();
  435. if ((u1colorspace == 0xff) && (u1deepcolor == 0xff)) {
  436. hdmi_print("color_space:HDMI_YCBCR_444 = 2\n");
  437. hdmi_print("color_space:HDMI_YCBCR_422 = 3\n");
  438. hdmi_print("deep_color:HDMI_NO_DEEP_COLOR = 1\n");
  439. hdmi_print("deep_color:HDMI_DEEP_COLOR_10_BIT = 2\n");
  440. hdmi_print("deep_color:HDMI_DEEP_COLOR_12_BIT = 3\n");
  441. hdmi_print("deep_color:HDMI_DEEP_COLOR_16_BIT = 4\n");
  442. return;
  443. }
  444. /*
  445. if (dReadHdmiSYS(0x2cc) == 0x8193)
  446. _stAvdAVInfo.e_video_color_space = HDMI_YCBCR_444;
  447. else
  448. _stAvdAVInfo.e_video_color_space = HDMI_RGB;
  449. */
  450. _stAvdAVInfo.e_video_color_space = u1colorspace;
  451. _stAvdAVInfo.e_deep_color_bit = (HDMI_DEEP_COLOR_T) u1deepcolor;
  452. }
  453. void mt8193_read(unsigned short u2Reg, unsigned int *p4Data)
  454. {
  455. if (u2Reg & 0x8000) {
  456. /* if ((u2Reg & 0xf000) == 0x8000) */
  457. /* u2Reg -= 0x8000; */
  458. /* *p4Data = (*(unsigned int *)(0xf4000000 + u2Reg)); */
  459. } else
  460. mt8193_i2c_read(u2Reg, p4Data);
  461. hdmi_print("Reg read= 0x%04x, data = 0x%08x\n", u2Reg, *p4Data);
  462. }
  463. void mt8193_write(unsigned short u2Reg, unsigned int u4Data)
  464. {
  465. if (u2Reg & 0x8000) {
  466. /* if ((u2Reg & 0xf000) == 0x8000) */
  467. /* u2Reg -= 0x8000; */
  468. /* *(unsigned int *)(0xf4000000 + u2Reg) = u4Data; */
  469. } else {
  470. hdmi_print("Reg write= 0x%04x, data = 0x%08x\n", u2Reg, u4Data);
  471. mt8193_i2c_write(u2Reg, u4Data);
  472. }
  473. }
  474. #if defined(CONFIG_HAS_EARLYSUSPEND)
  475. static void mt8193_hdmi_early_suspend(struct early_suspend *h)
  476. {
  477. MT8193_PLUG_FUNC();
  478. mt8193_hdmiearlysuspend = 0;
  479. is_hdmi_plug_out_flag = 0;
  480. }
  481. static void mt8193_hdmi_late_resume(struct early_suspend *h)
  482. {
  483. MT8193_PLUG_FUNC();
  484. mt8193_hdmiearlysuspend = 1;
  485. }
  486. static struct early_suspend mt8193_hdmi_early_suspend_desc = {
  487. .level = 0xFE,
  488. .suspend = mt8193_hdmi_early_suspend,
  489. .resume = mt8193_hdmi_late_resume,
  490. };
  491. #endif
  492. /*********************************************************
  493. mt8193 debug
  494. *********************************************************/
  495. #define HDMI_ATTR_SPRINTF(fmt, arg...) \
  496. do { \
  497. temp_len = sprintf(buf, fmt, ##arg); \
  498. buf += temp_len; \
  499. len += temp_len; \
  500. buf[0] = 0;\
  501. } while (0)
  502. #define DPI0_BASE_ADDR dispsys_reg[DISP_REG_DPI0]
  503. static void process_dbg_opt(const char *opt)
  504. {
  505. unsigned int reg;
  506. unsigned int val;
  507. unsigned int vadr_regstart;
  508. unsigned int vadr_regend;
  509. char *buf;
  510. int temp_len = 0;
  511. int len = 0;
  512. int ret;
  513. long int p_temp;
  514. buf = (char *)opt;
  515. if (strncmp(buf, "dbgtype:", 8) == 0) {
  516. ret = sscanf(buf + 8, "%x", &val);
  517. mt8193_log_enable(val);
  518. pr_debug("hdmidrv_log_on = 0x%08x\n", mt8193_log_on);
  519. } else if (strncmp(buf, "w:", 2) == 0) {
  520. ret = sscanf(buf + 2, "%x=%x", &reg, &val);
  521. pr_debug("w:0x%08x=0x%08x\n", reg, val);
  522. mt8193_write(reg, val);
  523. } else if (strncmp(buf, "r:", 2) == 0) {
  524. ret = sscanf(buf + 2, "%x/%x", &vadr_regstart, &vadr_regend);
  525. vadr_regend &= 0x3ff;
  526. pr_debug("r:0x%08x/0x%08x\n", vadr_regstart, vadr_regend);
  527. vadr_regend = vadr_regstart + vadr_regend;
  528. while (vadr_regstart <= vadr_regend) {
  529. mt8193_read(vadr_regstart, &val);
  530. HDMI_ATTR_SPRINTF("0x%08x = 0x%08x\n", vadr_regstart, val);
  531. vadr_regstart += 4;
  532. }
  533. } else if (strncmp(buf, "dw:", 3) == 0) {
  534. ret = sscanf(buf + 3, "%x=%x", &reg, &val);
  535. pr_debug("dw:0x%08x=0x%08x\n", reg, val);
  536. iowrite32(val, (void __iomem *)DPI0_BASE_ADDR + reg);
  537. } else if (strncmp(buf, "dr:", 3) == 0) {
  538. ret = sscanf(buf + 3, "%x/%x", &vadr_regstart, &vadr_regend);
  539. vadr_regend &= 0x3ff;
  540. pr_debug("dr:0x%08x/0x%08x\n", vadr_regstart, vadr_regend);
  541. vadr_regend = vadr_regstart + vadr_regend;
  542. while (vadr_regstart <= vadr_regend) {
  543. HDMI_ATTR_SPRINTF("0x%08x = 0x%08x\n", vadr_regstart,
  544. ioread32((void __iomem *)DPI0_BASE_ADDR + vadr_regstart));
  545. vadr_regstart += 4;
  546. }
  547. } else if (strncmp(buf, "status", 6) == 0) {
  548. HDMI_ATTR_SPRINTF("[hdmi]mt8193_log_on=%x\n", mt8193_log_on);
  549. HDMI_ATTR_SPRINTF("[hdmi]hdmi_powerenable=%x\n", hdmi_powerenable);
  550. HDMI_ATTR_SPRINTF("[hdmi]mt8193_hdmiinit=%d\n", mt8193_hdmiinit);
  551. HDMI_ATTR_SPRINTF("[hdmi]mt8193_hotinit=%d\n", mt8193_hotinit);
  552. HDMI_ATTR_SPRINTF("[hdmi]mt8193_hdmipoweroninit=%d\n", mt8193_hdmipoweroninit);
  553. HDMI_ATTR_SPRINTF("[hdmi]is_user_mute_hdmi_audio=%x\n", is_user_mute_hdmi_audio);
  554. HDMI_ATTR_SPRINTF("[hdmi]port=%d\n", hdmi_port_status());
  555. if (mt8193_hotplugstate == HDMI_STATE_HOT_PLUGIN_AND_POWER_ON)
  556. HDMI_ATTR_SPRINTF("[hdmi]plug:HDMI_STATE_HOT_PLUGIN_AND_POWER_ON\n");
  557. else if (mt8193_hotplugstate == HDMI_STATE_HOT_PLUG_OUT)
  558. HDMI_ATTR_SPRINTF("[hdmi]plug:HDMI_STATE_HOT_PLUG_OUT\n");
  559. else if (mt8193_hotplugstate == HDMI_STATE_HOT_PLUG_IN_ONLY)
  560. HDMI_ATTR_SPRINTF("[hdmi]plug:HDMI_STATE_HOT_PLUG_IN_ONLY\n");
  561. HDMI_ATTR_SPRINTF("[hdmi]video resolution : %d\n", _stAvdAVInfo.e_resolution);
  562. HDMI_ATTR_SPRINTF("[hdmi]video color space : %d\n",
  563. _stAvdAVInfo.e_video_color_space);
  564. HDMI_ATTR_SPRINTF("[hdmi]video deep color : %d\n", _stAvdAVInfo.e_deep_color_bit);
  565. HDMI_ATTR_SPRINTF("[hdmi]audio fs : %d\n", _stAvdAVInfo.e_hdmi_fs);
  566. if (vIsDviMode())
  567. HDMI_ATTR_SPRINTF("[hdmi]dvi Mode\n");
  568. else
  569. HDMI_ATTR_SPRINTF("[hdmi]hdmi Mode\n");
  570. mt8193_hdmistatus();
  571. } else if (0 == strncmp(opt, "po", 2)) {
  572. mt8193_power_on();
  573. } else if (0 == strncmp(opt, "pd", 2)) {
  574. mt8193_power_off();
  575. } else if (0 == strncmp(opt, "cs:", 3)) {
  576. ret = sscanf(buf + 3, "%x", &val);
  577. mt8193_colordeep(val, 0);
  578. } else if (0 == strncmp(opt, "finit", 5)) {
  579. hdmi_factory_mode_test(STEP1_CHIP_INIT, NULL);
  580. } else if (0 == strncmp(opt, "fres:", 5)) {
  581. ret = sscanf(buf + 5, "%x", &val);
  582. p_temp = (long int)val;
  583. hdmi_factory_mode_test(STEP3_START_DPI_AND_CONFIG, (void *)p_temp);
  584. } else {
  585. HDMI_ATTR_SPRINTF("---hdmi debug help---\n");
  586. HDMI_ATTR_SPRINTF("please go in to sys/kernel/debug\n");
  587. HDMI_ATTR_SPRINTF("[debug type] echo dbgtype:VALUE>8193\n");
  588. HDMI_ATTR_SPRINTF("[8193 read reg] echo r:ADDR/LEN>8193;cat 8193\n");
  589. HDMI_ATTR_SPRINTF("[8193 write reg] echo w:ADDR=VALUE>8193\n");
  590. HDMI_ATTR_SPRINTF("[d2 dpi0 read reg] echo dr:ADDR/LEN>8193;cat 8193\n");
  591. HDMI_ATTR_SPRINTF("[d2 dpi0 write reg] echo dw:ADDR=VALUE>8193\n");
  592. HDMI_ATTR_SPRINTF("[hdmi status] echo status>8193;cat 8193\n");
  593. HDMI_ATTR_SPRINTF("[power on] echo po>8193\n");
  594. HDMI_ATTR_SPRINTF("[power off] echo dn>8193\n");
  595. HDMI_ATTR_SPRINTF("[color space] echo cs:VALUE>8193\n");
  596. HDMI_ATTR_SPRINTF("[factory mode init] echo finit>8193\n");
  597. HDMI_ATTR_SPRINTF("[factory res] echo fres:VALUE>8193\n");
  598. }
  599. }
  600. static void process_dbg_cmd(char *cmd)
  601. {
  602. char *tok;
  603. pr_debug("[hdmi] %s\n", cmd);
  604. while ((tok = strsep(&cmd, " ")) != NULL)
  605. process_dbg_opt(tok);
  606. }
  607. /* --------------------------------------------------------------------------- */
  608. /* Debug FileSystem Routines */
  609. /* --------------------------------------------------------------------------- */
  610. struct dentry *mt8193_hdmi_dbgfs = NULL;
  611. static int mt8193_hdmi_debug_open(struct inode *inode, struct file *file)
  612. {
  613. file->private_data = inode->i_private;
  614. return 0;
  615. }
  616. static char mt8193_hdmi_debug_buffer[2048];
  617. static ssize_t mt8193_hdmi_debug_read(struct file *file,
  618. char __user *ubuf, size_t count, loff_t *ppos)
  619. {
  620. int n = 0;
  621. n = strlen(mt8193_hdmi_debug_buffer);
  622. mt8193_hdmi_debug_buffer[n++] = 0;
  623. return simple_read_from_buffer(ubuf, count, ppos, mt8193_hdmi_debug_buffer, n);
  624. }
  625. static ssize_t mt8193_hdmi_debug_write(struct file *file,
  626. const char __user *ubuf, size_t count, loff_t *ppos)
  627. {
  628. const int debug_bufmax = sizeof(mt8193_hdmi_debug_buffer) - 1;
  629. size_t ret;
  630. ret = count;
  631. if (count > debug_bufmax)
  632. count = debug_bufmax;
  633. if (copy_from_user(&mt8193_hdmi_debug_buffer, ubuf, count))
  634. return -EFAULT;
  635. mt8193_hdmi_debug_buffer[count] = 0;
  636. process_dbg_cmd(mt8193_hdmi_debug_buffer);
  637. return ret;
  638. }
  639. static const struct file_operations mt8193_hdmi_debug_fops = {
  640. .read = mt8193_hdmi_debug_read,
  641. .write = mt8193_hdmi_debug_write,
  642. .open = mt8193_hdmi_debug_open,
  643. };
  644. void mt8193_hdmi_debug_init(void)
  645. {
  646. mt8193_hdmi_dbgfs = debugfs_create_file("8193",
  647. S_IFREG | S_IRUGO, NULL, (void *)0,
  648. &mt8193_hdmi_debug_fops);
  649. }
  650. void mt8193_hdmi_debug_deinit(void)
  651. {
  652. debugfs_remove(mt8193_hdmi_dbgfs);
  653. }
  654. static void vSetHDMICtrlState(HDMI_CTRL_STATE_T e_state)
  655. {
  656. MT8193_PLUG_FUNC();
  657. e_hdmi_ctrl_state = e_state;
  658. }
  659. static void vNotifyAppHdmiState(unsigned char u1hdmistate)
  660. {
  661. HDMI_EDID_T get_info;
  662. mt8193_AppGetEdidInfo(&get_info);
  663. #if 0
  664. if (mt8193_hdmi_factory_callback != NULL)
  665. mt8193_hdmi_factory_callback(HDMI_STATE_NO_DEVICE);
  666. #endif
  667. switch (u1hdmistate) {
  668. case HDMI_PLUG_OUT:
  669. HDMI_DEF_LOG("[hdmi]notify plug:HDMI_STATE_NO_DEVICE\n");
  670. is_hdmi_plug_out_flag = 1;
  671. hdmi_util.state_callback(HDMI_STATE_NO_DEVICE);
  672. mt8193_SetPhysicCECAddress(0xffff, 0x0);
  673. break;
  674. case HDMI_PLUG_IN_AND_SINK_POWER_ON:
  675. HDMI_DEF_LOG("[hdmi]notify plug:HDMI_STATE_ACTIVE\n");
  676. is_hdmi_plug_out_flag = 0;
  677. hdmi_util.state_callback(HDMI_STATE_ACTIVE);
  678. mt8193_SetPhysicCECAddress(get_info.ui2_sink_cec_address, 0x4);
  679. if ((mt8193_hdmi_factory_callback != NULL) && (mt8193_Check_EdidHeader() == TRUE))
  680. mt8193_hdmi_factory_callback(HDMI_STATE_ACTIVE);
  681. break;
  682. case HDMI_PLUG_IN_ONLY:
  683. HDMI_DEF_LOG("[hdmi]notify plug:HDMI_STATE_PLUGIN_ONLY\n");
  684. is_hdmi_plug_out_flag = 1;
  685. hdmi_util.state_callback(HDMI_STATE_PLUGIN_ONLY);
  686. mt8193_SetPhysicCECAddress(get_info.ui2_sink_cec_address, 0xf);
  687. break;
  688. case HDMI_PLUG_IN_CEC:
  689. hdmi_util.state_callback(HDMI_STATE_CEC_UPDATE);
  690. break;
  691. default:
  692. HDMI_DEF_LOG("[hdmi]notify plug:err\n");
  693. break;
  694. }
  695. }
  696. void vcheckhdmiplugstate(void)
  697. {
  698. unsigned int bMask;
  699. MT8193_PLUG_FUNC();
  700. bMask = bReadHdmiIntMask();
  701. vWriteHdmiIntMask((bMask & 0xfe));
  702. if (bCheckPordHotPlug(PORD_MODE | HOTPLUG_MODE) == FALSE) {
  703. {
  704. if ((i4SharedInfo(SI_HDMI_RECEIVER_STATUS) ==
  705. HDMI_PLUG_IN_AND_SINK_POWER_ON)
  706. || (i4SharedInfo(SI_HDMI_RECEIVER_STATUS) == HDMI_PLUG_IN_ONLY)) {
  707. bMask = bReadHdmiIntMask();
  708. vWriteHdmiIntMask((bMask | 0xfE));
  709. vHDCPReset();
  710. vTxSignalOnOff(0);
  711. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS, HDMI_PLUG_OUT);
  712. vSetHDMICtrlState(HDMI_STATE_HOT_PLUG_OUT);
  713. } else {
  714. MT8193_PLUG_LOG("plug out, no action\n");
  715. }
  716. }
  717. } else {
  718. if ((i4SharedInfo(SI_HDMI_RECEIVER_STATUS) == HDMI_PLUG_OUT)
  719. || (i4SharedInfo(SI_HDMI_RECEIVER_STATUS) == HDMI_PLUG_IN_ONLY)) {
  720. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS, HDMI_PLUG_IN_AND_SINK_POWER_ON);
  721. vSetHDMICtrlState(HDMI_STATE_HOT_PLUGIN_AND_POWER_ON);
  722. } else {
  723. MT8193_PLUG_LOG("plug in ok, no action\n");
  724. }
  725. }
  726. }
  727. static void vPlugDetectService(HDMI_CTRL_STATE_T e_state)
  728. {
  729. unsigned char bData = 0xff;
  730. MT8193_PLUG_FUNC();
  731. e_hdmi_ctrl_state = HDMI_STATE_IDLE;
  732. switch (e_state) {
  733. case HDMI_STATE_HOT_PLUG_OUT:
  734. vClearEdidInfo();
  735. vHDCPReset();
  736. bData = HDMI_PLUG_OUT;
  737. break;
  738. case HDMI_STATE_HOT_PLUGIN_AND_POWER_ON:
  739. mt8193_checkedid(0);
  740. bData = HDMI_PLUG_IN_AND_SINK_POWER_ON;
  741. break;
  742. case HDMI_STATE_HOT_PLUG_IN_ONLY:
  743. vClearEdidInfo();
  744. vHDCPReset();
  745. mt8193_checkedid(0);
  746. bData = HDMI_PLUG_IN_ONLY;
  747. break;
  748. case HDMI_STATE_IDLE:
  749. break;
  750. default:
  751. break;
  752. }
  753. if ((bData != 0xff) && (hdmi_powerenable == 1))
  754. vNotifyAppHdmiState(bData);
  755. }
  756. void hdmi_timer_impl(void)
  757. {
  758. msleep(500);/*Change by xmwuwh@20170120 for mantis 0058685 */
  759. if (mt8193_hdmiinit == 0) {
  760. mt8193_hdmiinit = 1;
  761. /* mt8193_power_off(); */
  762. vInitAvInfoVar();
  763. return;
  764. }
  765. if (mt8193_hotinit != 1)
  766. mt8193_hdmiinit++;
  767. #if defined(CONFIG_HAS_EARLYSUSPEND)
  768. if (mt8193_hdmiearlysuspend == 1) {
  769. #else
  770. {
  771. #endif
  772. if (((mt8193_hdmiinit > 5) || (mt8193_hotinit == 0)) && (mt8193_hotinit != 1)) {
  773. if (bCheckPordHotPlug(PORD_MODE | HOTPLUG_MODE) == FALSE) {
  774. if ((mt8193_hotplugstate == HDMI_STATE_HOT_PLUGIN_AND_POWER_ON)
  775. && (mt8193_hotinit == 2)) {
  776. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS, HDMI_PLUG_OUT);
  777. mt8193_hotplugstate = HDMI_STATE_HOT_PLUG_OUT;
  778. vPlugDetectService(HDMI_STATE_HOT_PLUG_OUT);
  779. MT8193_PLUG_LOG
  780. ("[detectcable1] mt8193_hotinit = %d,mt8193_hdmiinit=%d\n",
  781. mt8193_hotinit, mt8193_hdmiinit);
  782. }
  783. #if 1
  784. if ((mt8193_hotinit == 0)
  785. && (bCheckPordHotPlug(HOTPLUG_MODE) == TRUE)) {
  786. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS,
  787. HDMI_PLUG_IN_AND_SINK_POWER_ON);
  788. mt8193_hotinit = 2;
  789. mt8193_hotplugstate = HDMI_STATE_HOT_PLUGIN_AND_POWER_ON;
  790. vPlugDetectService(HDMI_STATE_HOT_PLUGIN_AND_POWER_ON);
  791. vWriteHdmiIntMask(0xff); /* INT mask MDI */
  792. MT8193_PLUG_LOG
  793. ("[detectcable2] mt8193_hotinit = %d,mt8193_hdmiinit=%d\n",
  794. mt8193_hotinit, mt8193_hdmiinit);
  795. }
  796. #endif
  797. if ((mt8193_hotinit == 0)
  798. && (bCheckPordHotPlug(HOTPLUG_MODE) == FALSE)) {
  799. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS, HDMI_PLUG_OUT);
  800. mt8193_hotinit = 2;
  801. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS, HDMI_PLUG_OUT);
  802. mt8193_hotplugstate = HDMI_STATE_HOT_PLUG_OUT;
  803. vPlugDetectService(HDMI_STATE_HOT_PLUG_OUT);
  804. MT8193_PLUG_LOG
  805. ("[detectcable1] mt8193_hotinit = %d,mt8193_hdmiinit=%d\n",
  806. mt8193_hotinit, mt8193_hdmiinit);
  807. }
  808. } else if ((mt8193_hotplugstate == HDMI_STATE_HOT_PLUG_OUT)
  809. && (bCheckPordHotPlug(PORD_MODE | HOTPLUG_MODE) == TRUE)) {
  810. vSetSharedInfo(SI_HDMI_RECEIVER_STATUS,
  811. HDMI_PLUG_IN_AND_SINK_POWER_ON);
  812. mt8193_hotplugstate = HDMI_STATE_HOT_PLUGIN_AND_POWER_ON;
  813. mt8193_hotinit = 2;
  814. vPlugDetectService(HDMI_STATE_HOT_PLUGIN_AND_POWER_ON);
  815. vWriteHdmiIntMask(0xff); /* INT mask MDI */
  816. MT8193_PLUG_LOG
  817. ("[detectcable3] mt8193_hotinit = %d,mt8193_hdmiinit=%d\n",
  818. mt8193_hotinit, mt8193_hdmiinit);
  819. } else if ((mt8193_hotplugstate == HDMI_STATE_HOT_PLUGIN_AND_POWER_ON)
  820. && ((e_hdcp_ctrl_state == HDCP_WAIT_RI)
  821. || (e_hdcp_ctrl_state == HDCP_CHECK_LINK_INTEGRITY))) {
  822. if (bCheckHDCPStatus(HDCP_STA_RI_RDY)) {
  823. vSetHDCPState(HDCP_CHECK_LINK_INTEGRITY);
  824. vSendHdmiCmd(HDMI_HDCP_PROTOCAL_CMD);
  825. }
  826. }
  827. mt8193_hdmiinit = 1;
  828. }
  829. }
  830. if (mt8193_hdmiCmd == HDMI_PLUG_DETECT_CMD) {
  831. vClearHdmiCmd();
  832. /* vcheckhdmiplugstate(); */
  833. /* vPlugDetectService(e_hdmi_ctrl_state); */
  834. } else if (mt8193_hdmiCmd == HDMI_HDCP_PROTOCAL_CMD) {
  835. vClearHdmiCmd();
  836. HdcpService(e_hdcp_ctrl_state);
  837. }
  838. }
  839. void cec_timer_impl(void)
  840. {
  841. if (mt8193_cecinit == 0) {
  842. mt8193_cecinit = 1;
  843. mt8193_cec_init();
  844. return;
  845. }
  846. if (mt8193_cec_on == 1)
  847. mt8193_cec_mainloop(mt8193_rxcecmode);
  848. }
  849. void mt8193_nlh_impl(void)
  850. {
  851. unsigned int u4Data;
  852. unsigned char bData;
  853. unsigned char bMask;
  854. /*read register and then assert which interrupt occurred*/
  855. mt8193_i2c_read(0x1508, &u4Data);
  856. mt8193_i2c_write(0x1504, 0xffffffff);
  857. MT8193_DRV_LOG("0x1508 = 0x%08x\n", u4Data);
  858. if (u4Data & 0x20) {
  859. MT8193_CEC_LOG("cec interrupt\n");
  860. if (mt8193_cec_on == 1) {
  861. if (mt8193_cec_isrprocess(mt8193_rxcecmode))
  862. vNotifyAppHdmiState(HDMI_PLUG_IN_CEC);
  863. }
  864. }
  865. if (u4Data & 0x4) {
  866. bCheckHDCPStatus(0xfb);
  867. bData = bReadGRLInt();
  868. if (bData & INT_HDCP) {
  869. MT8193_HDCP_LOG("hdcp interrupt\n");
  870. bClearGRLInt(INT_HDCP);
  871. } else if (bData & INT_MDI) {
  872. MT8193_PLUG_LOG("hdmi interrupt\n");
  873. bClearGRLInt(INT_MDI);
  874. bMask = bReadHdmiIntMask();
  875. /* vWriteHdmiIntMask((0xfd));//INT mask MDI */
  876. }
  877. }
  878. #ifdef CUST_EINT_EINT_HDMI_HPD_NUM
  879. mt65xx_eint_unmask(CUST_EINT_EINT_HDMI_HPD_NUM);
  880. #endif
  881. }
  882. static int hdmi_timer_kthread(void *data)
  883. {
  884. struct sched_param param = {.sched_priority = RTPM_PRIO_CAMERA_PREVIEW };
  885. sched_setscheduler(current, SCHED_RR, &param);
  886. for (;;) {
  887. wait_event_interruptible(hdmi_timer_wq, atomic_read(&hdmi_timer_event));
  888. atomic_set(&hdmi_timer_event, 0);
  889. hdmi_timer_impl();
  890. if (kthread_should_stop())
  891. break;
  892. }
  893. return 0;
  894. }
  895. static int cec_timer_kthread(void *data)
  896. {
  897. struct sched_param param = {.sched_priority = RTPM_PRIO_CAMERA_PREVIEW };
  898. sched_setscheduler(current, SCHED_RR, &param);
  899. for (;;) {
  900. wait_event_interruptible(cec_timer_wq, atomic_read(&cec_timer_event));
  901. atomic_set(&cec_timer_event, 0);
  902. cec_timer_impl();
  903. if (kthread_should_stop())
  904. break;
  905. }
  906. return 0;
  907. }
  908. static int mt8193_nlh_kthread(void *data)
  909. {
  910. struct sched_param param = {.sched_priority = RTPM_PRIO_SCRN_UPDATE };
  911. sched_setscheduler(current, SCHED_RR, &param);
  912. for (;;) {
  913. wait_event_interruptible(mt8193_nlh_wq, atomic_read(&mt8193_nlh_event));
  914. atomic_set(&mt8193_nlh_event, 0);
  915. mt8193_nlh_impl();
  916. if (kthread_should_stop())
  917. break;
  918. }
  919. return 0;
  920. }
  921. void hdmi_poll_isr(unsigned long n)
  922. {
  923. unsigned int i;
  924. if (hdmi_powerenable != 1)
  925. return;
  926. for (i = 0; i < MAX_HDMI_TMR_NUMBER; i++) {
  927. if (mt8193_TmrValue[i] >= AVD_TMR_ISR_TICKS) {
  928. mt8193_TmrValue[i] -= AVD_TMR_ISR_TICKS;
  929. if ((i == HDMI_PLUG_DETECT_CMD)
  930. && (mt8193_TmrValue[HDMI_PLUG_DETECT_CMD] == 0))
  931. vSendHdmiCmd(HDMI_PLUG_DETECT_CMD);
  932. else if ((i == HDMI_HDCP_PROTOCAL_CMD)
  933. && (mt8193_TmrValue[HDMI_HDCP_PROTOCAL_CMD] == 0))
  934. vSendHdmiCmd(HDMI_HDCP_PROTOCAL_CMD);
  935. } else if (mt8193_TmrValue[i] > 0) {
  936. mt8193_TmrValue[i] = 0;
  937. if ((i == HDMI_PLUG_DETECT_CMD)
  938. && (mt8193_TmrValue[HDMI_PLUG_DETECT_CMD] == 0))
  939. vSendHdmiCmd(HDMI_PLUG_DETECT_CMD);
  940. else if ((i == HDMI_HDCP_PROTOCAL_CMD)
  941. && (mt8193_TmrValue[HDMI_HDCP_PROTOCAL_CMD] == 0))
  942. vSendHdmiCmd(HDMI_HDCP_PROTOCAL_CMD);
  943. }
  944. }
  945. atomic_set(&hdmi_timer_event, 1);
  946. wake_up_interruptible(&hdmi_timer_wq);
  947. mod_timer(&r_hdmi_timer, jiffies + gHDMI_CHK_INTERVAL / (1000 / HZ));
  948. }
  949. void cec_poll_isr(unsigned long n)
  950. {
  951. if (hdmi_powerenable != 1)
  952. return;
  953. atomic_set(&cec_timer_event, 1);
  954. wake_up_interruptible(&cec_timer_wq);
  955. mod_timer(&r_cec_timer, jiffies + gCEC_CHK_INTERVAL / (1000 / HZ));
  956. }
  957. /*********************************************************
  958. mt8193 end
  959. *********************************************************/
  960. static int mt8193_init(void)
  961. {
  962. HDMI_DEF_LOG("[hdmi]mt8193_init\n");
  963. init_waitqueue_head(&hdmi_timer_wq);
  964. hdmi_timer_task = kthread_create(hdmi_timer_kthread, NULL, "hdmi_timer_kthread");
  965. wake_up_process(hdmi_timer_task);
  966. init_waitqueue_head(&cec_timer_wq);
  967. cec_timer_task = kthread_create(cec_timer_kthread, NULL, "cec_timer_kthread");
  968. wake_up_process(cec_timer_task);
  969. init_waitqueue_head(&mt8193_nlh_wq);
  970. mt8193_nlh_task = kthread_create(mt8193_nlh_kthread, NULL, "mt8193_nlh_kthread");
  971. wake_up_process(mt8193_nlh_task);
  972. #if defined(CONFIG_HAS_EARLYSUSPEND)
  973. register_early_suspend(&mt8193_hdmi_early_suspend_desc);
  974. #endif
  975. memset((void *)&r_hdmi_timer, 0, sizeof(r_hdmi_timer));
  976. r_hdmi_timer.expires = jiffies + 1000 / (1000 / HZ); /* wait 1s to stable */
  977. r_hdmi_timer.function = hdmi_poll_isr;
  978. r_hdmi_timer.data = 0;
  979. init_timer(&r_hdmi_timer);
  980. add_timer(&r_hdmi_timer);
  981. memset((void *)&r_cec_timer, 0, sizeof(r_cec_timer));
  982. r_cec_timer.expires = jiffies + 1000 / (1000 / HZ); /* wait 1s to stable */
  983. r_cec_timer.function = cec_poll_isr;
  984. r_cec_timer.data = 0;
  985. init_timer(&r_cec_timer);
  986. add_timer(&r_cec_timer);
  987. mt8193_hdmi_debug_init();
  988. mt8193_hdmi_factory_callback = NULL;
  989. return 0;
  990. }
  991. const struct HDMI_DRIVER *HDMI_GetDriver(void)
  992. {
  993. static const struct HDMI_DRIVER HDMI_DRV = {
  994. .set_util_funcs = mt8193_set_util_funcs,
  995. .get_params = mt8193_get_params,
  996. .init = mt8193_init,
  997. .enter = mt8193_enter,
  998. .exit = mt8193_exit,
  999. .suspend = mt8193_suspend,
  1000. .resume = mt8193_resume,
  1001. .video_config = mt8193_video_config,
  1002. .audio_config = mt8193_audio_config,
  1003. .video_enable = mt8193_video_enable,
  1004. .audio_enable = mt8193_audio_enable,
  1005. .power_on = mt8193_power_on,
  1006. .power_off = mt8193_power_off,
  1007. .set_mode = mt8193_set_mode,
  1008. .dump = mt8193_dump,
  1009. .read = mt8193_read,
  1010. .write = mt8193_write,
  1011. .get_state = mt8193_get_state,
  1012. .log_enable = mt8193_log_enable,
  1013. .InfoframeSetting = mt8193_InfoframeSetting,
  1014. .checkedid = mt8193_checkedid,
  1015. .colordeep = mt8193_colordeep,
  1016. .enablehdcp = mt8193_enablehdcp,
  1017. .setcecrxmode = mt8193_setcecrxmode,
  1018. .hdmistatus = mt8193_hdmistatus,
  1019. .hdcpkey = mt8193_hdcpkey,
  1020. .getedid = mt8193_AppGetEdidInfo,
  1021. .setcecla = mt8193_CECMWSetLA,
  1022. .sendsltdata = mt8193_u4CecSendSLTData,
  1023. .getceccmd = mt8193_CECMWGet,
  1024. .getsltdata = mt8193_GetSLTData,
  1025. .setceccmd = mt8193_CECMWSend,
  1026. .cecenable = mt8193_CECMWSetEnableCEC,
  1027. .getcecaddr = mt8193_NotifyApiCECAddress,
  1028. .mutehdmi = mt8193_mutehdmi,
  1029. .checkedidheader = mt8193_Check_EdidHeader,
  1030. .register_callback = mt8193_register_callback,
  1031. .unregister_callback = mt8193_unregister_callback,
  1032. };
  1033. return &HDMI_DRV;
  1034. }
  1035. EXPORT_SYMBOL(HDMI_GetDriver);
  1036. #endif