mlt8783_ftb_m.dts 23 KB

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  1. /dts-v1/;
  2. #include "mt6753.dtsi"
  3. #include <dt-bindings/lcm/r63417_fhd_dsi_cmd_truly_nt50358.dtsi>
  4. #include "mlt8783_ftb_m_bat_setting.dtsi"
  5. / {
  6. memory@00000000 {
  7. device_type = "memory";
  8. reg = <0 0x40000000 0 0x3F000000>;
  9. };
  10. bus {
  11. compatible = "simple-bus";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. ranges = <0 0 0 0xffffffff>;
  15. MTKFB@5e200000 {
  16. compatible = "mediatek,MTKFB";
  17. reg = <0x7F000000 0x1000000>;
  18. };
  19. };
  20. led0:led@0 {
  21. compatible = "mediatek,red";
  22. led_mode = <0>;
  23. data = <1>;
  24. pwm_config = <0 0 0 0 0>;
  25. };
  26. led1:led@1 {
  27. compatible = "mediatek,green";
  28. led_mode = <0>;
  29. data = <1>;
  30. pwm_config = <0 0 0 0 0>;
  31. };
  32. led2:led@2 {
  33. compatible = "mediatek,blue";
  34. led_mode = <0>;
  35. data = <1>;
  36. pwm_config = <0 0 0 0 0>;
  37. };
  38. led3:led@3 {
  39. compatible = "mediatek,jogball-backlight";
  40. led_mode = <0>;
  41. data = <1>;
  42. pwm_config = <0 0 0 0 0>;
  43. };
  44. led4:led@4 {
  45. compatible = "mediatek,keyboard-backlight";
  46. led_mode = <0>;
  47. data = <1>;
  48. pwm_config = <0 0 0 0 0>;
  49. };
  50. led5:led@5 {
  51. compatible = "mediatek,button-backlight";
  52. led_mode = <0>;
  53. data = <1>;
  54. pwm_config = <0 0 0 0 0>;
  55. };
  56. led6:led@6 {
  57. compatible = "mediatek,lcd-backlight";
  58. led_mode = <5>;
  59. data = <1>;
  60. pwm_config = <0 0 0 0 0>;
  61. };
  62. vibrator0:vibrator@0 {
  63. compatible = "mediatek,vibrator";
  64. vib_timer = <25>;
  65. vib_limit = <9>;
  66. vib_vol= <5>;
  67. };
  68. /* sensor standardization */
  69. cust_accel@0 {
  70. compatible = "mediatek,mpu6050g";
  71. i2c_num = <2>;
  72. i2c_addr = <0x68 0 0 0>;
  73. direction = <4>;
  74. power_id = <0xffff>;
  75. power_vol = <0>;
  76. firlen = <0>;
  77. is_batch_supported = <0>;
  78. };
  79. cust_alsps@0 {
  80. compatible = "mediatek,apds9930";
  81. i2c_num = <2>;
  82. i2c_addr = <0x72 0x48 0x78 0x00>;
  83. polling_mode_ps = <0>;
  84. polling_mode_als = <1>;
  85. power_id = <0xffff>;
  86. power_vol = <0>;
  87. als_level = <1 2 5 10 20 30 40 80 200 300 400 600 1000 1600 2000>;
  88. als_value = <80 400 800 1200 1800 2000 2300 2300 12000 12000 12000 48000 48000 72000 81920 81920>;
  89. ps_threshold_high = <90>;
  90. ps_threshold_low = <70>;
  91. is_batch_supported_ps = <0>;
  92. is_batch_supported_als = <0>;
  93. };
  94. cust_mag@0 {
  95. compatible = "mediatek,akm09911";
  96. i2c_num = <2>;
  97. i2c_addr = <0x0D 0 0 0>;
  98. direction = <1>;
  99. power_id = <0xffff>;
  100. power_vol = <0>;
  101. is_batch_supported = <0>;
  102. };
  103. cust_gyro@0 {
  104. compatible = "mediatek,mpu6050gy";
  105. i2c_num = <2>;
  106. i2c_addr = <0x69 0 0 0>;
  107. direction = <4>;
  108. power_id = <0xffff>;
  109. power_vol = <0>;
  110. firlen = <0>;
  111. is_batch_supported = <0>;
  112. };
  113. /* Connectivity */
  114. mediatek,connectivity-combo {
  115. compatible = "mediatek,connectivity-combo";
  116. /*gpio_combo_ldo_en_pin = <&pio 0xffff 0>; /*0) GPIO_COMBO_LDO_EN_PIN */
  117. /*gpio_combo_pmuv28_en_pin = <&pio 0xffff 0>; /* 1) GPIO_COMBO_PMUV28_EN_PIN */
  118. gpio_combo_pmu_en_pin = <&pio 21 0>; /* 2) GPIO_COMBO_PMU_EN_PIN */
  119. gpio_combo_rst_pin = <&pio 186 0>; /* 3) GPIO_COMBO_RST_PIN pin */
  120. /*gpio_combo_bgf_eint_pin = <&pio 0xffff 0>; /* 4) GPIO_COMBO_BGF_EINT_PIN */
  121. gpio_wifi_eint_pin = <&pio 20 0>; /* 5) GPIO_WIFI_EINT_PIN */
  122. /*gpio_all_eint_pin = <&pio 0xffff 0>; /* 6) GPIO_ALL_EINT_PIN */
  123. gpio_combo_urxd_pin = <&pio 74 0>; /* 7) GPIO_COMBO_URXD_PIN */
  124. gpio_combo_utxd_pin = <&pio 75 0>; /* 8) GPIO_COMBO_UTXD_PIN */
  125. gpio_pcm_daiclk_pin = <&pio 184 0>; /* 9) GPIO_PCM_DAICLK_PIN */
  126. gpio_pcm_daipcmin_pin = <&pio 185 0>; /* 10) GPIO_PCM_DAIPCMIN_PIN */
  127. gpio_pcm_daipcmout_pin = <&pio 187 0>; /* 11) GPIO_PCM_DAIPCMOUT_PIN */
  128. gpio_pcm_daisync_pin = <&pio 188 0>; /* 12) GPIO_PCM_DAISYNC_PIN */
  129. /*gpio_combo_i2s_ck_pin = <&pio 0xffff 0>; /* 13) GPIO_COMBO_I2S_CK_PIN */
  130. /*gpio_combo_i2s_ws_pin = <&pio 0xffff 0>; /* 14) GPIO_COMBO_I2S_WS_PIN */
  131. /*gpio_combo_i2s_dat_pin = <&pio 0xffff 0>; /* 15) GPIO_COMBO_I2S_DAT_PIN */
  132. gpio_gps_sync_pin = <&pio 19 0>; /* 16) GPIO_GPS_SYNC_PIN */
  133. gpio_gps_lna_pin = <&pio 77 0>; /* 17) GPIO_GPS_LNA_PIN */
  134. pinctrl-names = "gpio_pmu_en_pull_dis",
  135. "gpio_pmu_en_in_pulldown",
  136. "gpio_rst_pull_dis",
  137. "gpio_wifi_eint_in_pull_dis",
  138. "gpio_wifi_eint_in_pullup",
  139. "gpio_urxd_uart_pull_dis",
  140. "gpio_urxd_gpio_in_pullup",
  141. "gpio_urxd_gpio_in_pull_dis",
  142. "gpio_utxd_uart_pull_dis",
  143. "gpio_pcm_daiclk_pull_dis",
  144. "gpio_pcm_daipcmin_pull_dis",
  145. "gpio_pcm_daipcmout_pull_dis",
  146. "gpio_pcm_daisync_pull_dis",
  147. "gpio_gps_sync_pull_dis",
  148. "gpio_gps_lna_pull_dis";
  149. pinctrl-0 = <&pcfg_combo_pmu_en_pull_dis_cfgs>;
  150. pinctrl-1 = <&pcfg_combo_pmu_en_in_pulldown_cfgs>;
  151. pinctrl-2 = <&pcfg_combo_rst_pull_dis_cfgs>;
  152. pinctrl-3 = <&pcfg_combo_wifi_eint_in_pull_dis_cfgs>;
  153. pinctrl-4 = <&pcfg_combo_wifi_eint_in_pullup_cfgs>;
  154. pinctrl-5 = <&pcfg_combo_urxd_uart_pull_dis_cfgs>;
  155. pinctrl-6 = <&pcfg_combo_urxd_gpio_in_pullup_cfgs>;
  156. pinctrl-7 = <&pcfg_combo_urxd_gpio_in_pull_dis_cfgs>;
  157. pinctrl-8 = <&pcfg_combo_utxd_uart_pull_dis_cfgs>;
  158. pinctrl-9 = <&pcfg_combo_pcm_daiclk_pull_dis_cfgs>;
  159. pinctrl-10 = <&pcfg_combo_pcm_daipcmin_pull_dis_cfgs>;
  160. pinctrl-11 = <&pcfg_combo_pcm_daipcmout_pull_dis_cfgs>;
  161. pinctrl-12 = <&pcfg_combo_pcm_daisync_pull_dis_cfgs>;
  162. pinctrl-13 = <&pcfg_combo_gps_sync_pull_dis_cfgs>;
  163. pinctrl-14 = <&pcfg_combo_gps_lna_pull_dis_cfgs>;
  164. interrupt-parent = <&eintc>;
  165. interrupts = < 20 IRQ_TYPE_LEVEL_LOW >; /* WIFI EINT num is 1 active low level-sensitive */
  166. debounce = <20 0>;
  167. status = "okay";
  168. };
  169. };
  170. /* sensor gpio standization */
  171. &pio {
  172. alsps_intpin_cfg: alspspincfg {
  173. pins_cmd_dat {
  174. pins = <PINMUX_GPIO65__FUNC_GPIO65>;
  175. slew-rate = <0>;
  176. bias-pull-up = <00>;
  177. };
  178. };
  179. alsps_intpin_default: alspsdefaultcfg {
  180. };
  181. gyro_intpin_cfg: gyropincfg {
  182. pins_cmd_dat {
  183. pins = <PINMUX_GPIO67__FUNC_GPIO67>;
  184. slew-rate = <0>;
  185. bias-pull-down = <00>;
  186. };
  187. };
  188. gyro_intpin_default: gyrodefaultcfg {
  189. };
  190. };
  191. &alsps {
  192. pinctrl-names = "pin_default", "pin_cfg";
  193. pinctrl-0 = <&alsps_intpin_default>;
  194. pinctrl-1 = <&alsps_intpin_cfg>;
  195. status = "okay";
  196. };
  197. &gyro {
  198. pinctrl-names = "pin_default", "pin_cfg";
  199. pinctrl-0 = <&gyro_intpin_default>;
  200. pinctrl-1 = <&gyro_intpin_cfg>;
  201. status = "okay";
  202. };
  203. /* sensor end */
  204. &accdet {
  205. interrupt-parent = <&eintc>;
  206. interrupts = <86 IRQ_TYPE_LEVEL_HIGH>;
  207. eint-debounce = <256>;
  208. accdet-gpio = <&pio 86 0>;
  209. accdet-mic-vol = <7>;
  210. headset-mode-setting = <0x500 0x200 1 0x1f0 0x800 0x800 0x20>;
  211. accdet-plugout-debounce = <20>;
  212. /*1:ACC mode, 2:low cost without in bias, 6:low cost with in bias*/
  213. accdet-mic-mode = <1>;
  214. /*0--MD_MAX--UP_MAX--DW_MAX*/
  215. headset-three-key-threshold = <0 80 220 500>;
  216. /*0--MD_MAX--VOICE_MAX--UP_MAX--DW_MAX*/
  217. headset-four-key-threshold = <0 58 121 192 450>;
  218. pinctrl-names = "default", "state_eint_as_int";
  219. pinctrl-0 = <&accdet_pins_default>;
  220. pinctrl-1 = <&accdet_pins_eint_as_int>;
  221. status = "okay";
  222. };
  223. &touch {
  224. tpd-resolution = <1080 1920>;
  225. use-tpd-button = <0>;
  226. tpd-key-num = <3>;
  227. tpd-key-local= <139 172 158 0>;
  228. tpd-key-dim-local = <90 883 100 40 230 883 100 40 370 883 100 40 0 0 0 0>;
  229. tpd-max-touch-num = <5>;
  230. tpd-filter-enable = <1>;
  231. tpd-filter-pixel-density = <186>;
  232. tpd-filter-custom-prameters = <0 0 0 0 0 0 0 0 0 0 0 0>;
  233. tpd-filter-custom-speed = <0 0 0>;
  234. pinctrl-names = "default", "state_eint_as_int", "state_eint_output0", "state_eint_output1",
  235. "state_rst_output0", "state_rst_output1";
  236. pinctrl-0 = <&CTP_pins_default>;
  237. pinctrl-1 = <&CTP_pins_eint_as_int>;
  238. pinctrl-2 = <&CTP_pins_eint_output0>;
  239. pinctrl-3 = <&CTP_pins_eint_output1>;
  240. pinctrl-4 = <&CTP_pins_rst_output0>;
  241. pinctrl-5 = <&CTP_pins_rst_output1>;
  242. status = "okay";
  243. };
  244. &pio {
  245. CTP_pins_default: eint0default {
  246. };
  247. accdet_pins_default: eint86default {
  248. };
  249. accdet_pins_eint_as_int: eint86 {
  250. pins_cmd_dat {
  251. pins = <PINMUX_GPIO86__FUNC_GPIO86>;
  252. bias-disable;
  253. };
  254. };
  255. CTP_pins_eint_as_int: eint@0 {
  256. pins_cmd_dat {
  257. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  258. slew-rate = <0>;
  259. bias-disable;
  260. };
  261. };
  262. CTP_pins_eint_output0: eintoutput0 {
  263. pins_cmd_dat {
  264. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  265. slew-rate = <1>;
  266. output-low;
  267. };
  268. };
  269. CTP_pins_eint_output1: eintoutput1 {
  270. pins_cmd_dat {
  271. pins = <PINMUX_GPIO10__FUNC_GPIO10>;
  272. slew-rate = <1>;
  273. output-high;
  274. };
  275. };
  276. CTP_pins_rst_output0: rstoutput0 {
  277. pins_cmd_dat {
  278. pins = <PINMUX_GPIO62__FUNC_GPIO62>;
  279. slew-rate = <1>;
  280. output-low;
  281. };
  282. };
  283. CTP_pins_rst_output1: rstoutput1 {
  284. pins_cmd_dat {
  285. pins = <PINMUX_GPIO62__FUNC_GPIO62>;
  286. slew-rate = <1>;
  287. output-high;
  288. };
  289. };
  290. };
  291. /* TOUCH end */
  292. /* CAMERA GPIO standardization */
  293. &pio {
  294. camera_pins_cam0_rst0: cam0@0 {
  295. pins_cmd_dat {
  296. pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST_PIN*/
  297. slew-rate = <1>; /*direction 0:in, 1:out*/
  298. output-low;/*direction out used only. output_low or high*/
  299. };
  300. };
  301. camera_pins_cam0_rst1: cam0@1 {
  302. pins_cmd_dat {
  303. pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST_PIN*/
  304. slew-rate = <1>;
  305. output-high;
  306. };
  307. };
  308. camera_pins_cam0_pnd0: cam0@2 {
  309. pins_cmd_dat {
  310. pins = <PINMUX_GPIO82__FUNC_GPIO82>;/*GPIO_CAMERA_CMPDN_PIN*/
  311. slew-rate = <1>;
  312. output-low;
  313. };
  314. };
  315. camera_pins_cam0_pnd1: cam0@3 {
  316. pins_cmd_dat {
  317. pins = <PINMUX_GPIO82__FUNC_GPIO82>;/*GPIO_CAMERA_CMPDN_PIN*/
  318. slew-rate = <1>;
  319. output-high;
  320. };
  321. };
  322. camera_pins_cam1_rst0: cam1@0 {
  323. pins_cmd_dat {
  324. pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST1_PIN*/
  325. slew-rate = <1>; /*direction 0:in, 1:out*/
  326. output-low;/*direction out used only. output_low or high*/
  327. };
  328. };
  329. camera_pins_cam1_rst1: cam1@1 {
  330. pins_cmd_dat {
  331. pins = <PINMUX_GPIO44__FUNC_GPIO44>;/*GPIO_CAMERA_CMRST1_PIN*/
  332. slew-rate = <1>;
  333. output-high;
  334. };
  335. };
  336. camera_pins_cam1_pnd0: cam1@2 {
  337. pins_cmd_dat {
  338. pins = <PINMUX_GPIO12__FUNC_GPIO12>;/*GPIO_CAMERA_CMPDN1_PIN*/
  339. slew-rate = <1>;
  340. output-low;
  341. };
  342. };
  343. camera_pins_cam1_pnd1: cam1@3 {
  344. pins_cmd_dat {
  345. pins = <PINMUX_GPIO12__FUNC_GPIO12>;/*GPIO_CAMERA_CMPDN1_PIN*/
  346. slew-rate = <1>;
  347. output-high;
  348. };
  349. };
  350. camera_pins_cam_ldo0_0: cam@0 {
  351. pins_cmd_dat {
  352. pins = <PINMUX_GPIO11__FUNC_GPIO11>;
  353. slew-rate = <1>;
  354. output-low;
  355. };
  356. };
  357. camera_pins_cam_ldo0_1: cam@1 {
  358. pins_cmd_dat {
  359. pins = <PINMUX_GPIO11__FUNC_GPIO11>;
  360. slew-rate = <1>;
  361. output-high;
  362. };
  363. };
  364. camera_pins_default: camdefault {
  365. };
  366. };
  367. &kd_camera_hw1 {
  368. pinctrl-names = "default", "cam0_rst0", "cam0_rst1", "cam0_pnd0", "cam0_pnd1",
  369. "cam1_rst0", "cam1_rst1", "cam1_pnd0", "cam1_pnd1",
  370. "cam_ldo0_0", "cam_ldo0_1";
  371. pinctrl-0 = <&camera_pins_default>;
  372. pinctrl-1 = <&camera_pins_cam0_rst0>;
  373. pinctrl-2 = <&camera_pins_cam0_rst1>;
  374. pinctrl-3 = <&camera_pins_cam0_pnd0>;
  375. pinctrl-4 = <&camera_pins_cam0_pnd1>;
  376. pinctrl-5 = <&camera_pins_cam1_rst0>;
  377. pinctrl-6 = <&camera_pins_cam1_rst1>;
  378. pinctrl-7 = <&camera_pins_cam1_pnd0>;
  379. pinctrl-8 = <&camera_pins_cam1_pnd1>;
  380. pinctrl-9 = <&camera_pins_cam_ldo0_0>;
  381. pinctrl-10 = <&camera_pins_cam_ldo0_1>;
  382. status = "okay";
  383. };
  384. /* CAMERA GPIO end */
  385. /* CONSYS GPIO standardization */
  386. &pio {
  387. consys_pins_default: default {
  388. };
  389. gpslna_pins_init: gpslna@0 {
  390. pins_cmd_dat {
  391. pins = <PINMUX_GPIO79__FUNC_GPIO79>;
  392. slew-rate = <0>;
  393. bias-disable;
  394. output-low;
  395. };
  396. };
  397. gpslna_pins_oh: gpslna@1 {
  398. pins_cmd_dat {
  399. pins = <PINMUX_GPIO79__FUNC_GPIO79>;
  400. slew-rate = <1>;
  401. output-high;
  402. };
  403. };
  404. gpslna_pins_ol: gpslna@2 {
  405. pins_cmd_dat {
  406. pins = <PINMUX_GPIO79__FUNC_GPIO79>;
  407. slew-rate = <1>;
  408. output-low;
  409. };
  410. };
  411. };
  412. &consys {
  413. pinctrl-names = "default", "gps_lna_state_init", "gps_lna_state_oh", "gps_lna_state_ol";
  414. pinctrl-0 = <&consys_pins_default>;
  415. pinctrl-1 = <&gpslna_pins_init>;
  416. pinctrl-2 = <&gpslna_pins_oh>;
  417. pinctrl-3 = <&gpslna_pins_ol>;
  418. status = "okay";
  419. };
  420. /* CONSYS end */
  421. /* mmc start */
  422. &mmc0 {
  423. clk_src = /bits/ 8 <MSDC50_CLKSRC_400MHZ>;
  424. bus-width = <8>;
  425. max-frequency = <200000000>;
  426. cap-mmc-highspeed;
  427. msdc-sys-suspend;
  428. mmc-ddr-1_8v;
  429. mmc-hs200-1_8v;
  430. mmc-hs400-1_8v;
  431. non-removable;
  432. pinctl = <&mmc0_pins_default>;
  433. register_setting = <&mmc0_register_setting_default>;
  434. host_function = /bits/ 8 <MSDC_EMMC>;
  435. bootable;
  436. status = "okay";
  437. };
  438. &mmc1 {
  439. clk_src = /bits/ 8 <MSDC30_CLKSRC_200MHZ>;
  440. bus-width = <4>;
  441. max-frequency = <200000000>;
  442. msdc-sys-suspend;
  443. sd_need_power;
  444. cap-sd-highspeed;
  445. sd-uhs-sdr12;
  446. sd-uhs-sdr25;
  447. sd-uhs-sdr50;
  448. sd-uhs-sdr104;
  449. sd-uhs-ddr50;
  450. pinctl = <&mmc1_pins_default>;
  451. pinctl_sdr104 = <&mmc1_pins_sdr104>;
  452. pinctl_sdr50 = <&mmc1_pins_sdr50>;
  453. pinctl_ddr50 = <&mmc1_pins_ddr50>;
  454. register_setting = <&mmc1_register_setting_default>;
  455. host_function = /bits/ 8 <MSDC_SD>;
  456. cd_level = /bits/ 8 <MSDC_CD_HIGH>;
  457. cd-gpios = <&pio 76 0>;
  458. status = "okay";
  459. };
  460. &mmc2 {
  461. clk_src = /bits/ 8 <MSDC30_CLKSRC_200MHZ>;
  462. bus-width = <4>;
  463. max-frequency = <200000000>;
  464. cap-sd-highspeed;
  465. sd-uhs-sdr12;
  466. sd-uhs-sdr25;
  467. sd-uhs-sdr50;
  468. sd-uhs-sdr104;
  469. sd-uhs-ddr50;
  470. non-removable;
  471. host_function = /bits/ 8 <MSDC_SDIO>;
  472. status = "okay";
  473. };
  474. &pio {
  475. mmc0_pins_default: mmc0@default {
  476. pins_cmd {
  477. drive-strength = /bits/ 8 <2>;
  478. };
  479. pins_dat {
  480. drive-strength = /bits/ 8 <2>;
  481. };
  482. pins_clk {
  483. drive-strength = /bits/ 8 <2>;
  484. };
  485. pins_rst {
  486. drive-strength = /bits/ 8 <2>;
  487. };
  488. pins_ds {
  489. drive-strength = /bits/ 8 <2>;
  490. };
  491. };
  492. mmc0_register_setting_default: mmc0@register_default {
  493. dat0rddly = /bits/ 8 <0>;
  494. dat1rddly = /bits/ 8 <0>;
  495. dat2rddly = /bits/ 8 <0>;
  496. dat3rddly = /bits/ 8 <0>;
  497. dat4rddly = /bits/ 8 <0>;
  498. dat5rddly = /bits/ 8 <0>;
  499. dat6rddly = /bits/ 8 <0>;
  500. dat7rddly = /bits/ 8 <0>;
  501. datwrddly = /bits/ 8 <0>;
  502. cmdrrddly = /bits/ 8 <0>;
  503. cmdrddly = /bits/ 8 <0>;
  504. cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  505. rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  506. wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  507. ett-hs200-cells = <12>;
  508. ett-hs200-default = <OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_INT_DAT_LATCH_CK_SEL 0x0
  509. OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_CKGEN_MSDC_DLY_SEL 0x0
  510. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_CMD_RSP_TA_CNTR 0x1
  511. OFFSET_MSDC_IOCON MSDC_IOCON_RSPL 0x1
  512. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRDLY 0xf
  513. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRRDLY 0x0
  514. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_WRDAT_CRCS_TA_CNTR 0x1
  515. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_DATWRDLY 0xf
  516. OFFSET_MSDC_IOCON MSDC_IOCON_W_D0SPL 0x1
  517. OFFSET_MSDC_DAT_RDDLY0 MSDC_DAT_RDDLY0_D0 0xf
  518. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_DATRRDLY 0x16
  519. OFFSET_MSDC_IOCON MSDC_IOCON_R_D_SMPL 0x0>;
  520. ett-hs400-cells = <8>;
  521. ett-hs400-default = <OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_INT_DAT_LATCH_CK_SEL 0x0
  522. OFFSET_MSDC_PATCH_BIT0 MSDC_PB0_CKGEN_MSDC_DLY_SEL 0x0
  523. OFFSET_EMMC50_PAD_DS_TUNE MSDC_EMMC50_PAD_DS_TUNE_DLY1 0x2
  524. OFFSET_EMMC50_PAD_DS_TUNE MSDC_EMMC50_PAD_DS_TUNE_DLY3 0xe
  525. OFFSET_MSDC_PATCH_BIT1 MSDC_PB1_CMD_RSP_TA_CNTR 0x1
  526. OFFSET_MSDC_IOCON MSDC_IOCON_RSPL 0x0
  527. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRDLY 0xf
  528. OFFSET_MSDC_PAD_TUNE0 MSDC_PAD_TUNE0_CMDRRDLY 0xd>;
  529. };
  530. mmc1_pins_default: mmc1@default {
  531. pins_cmd {
  532. drive-strength = /bits/ 8 <3>;
  533. };
  534. pins_dat {
  535. drive-strength = /bits/ 8 <3>;
  536. };
  537. pins_clk {
  538. drive-strength = /bits/ 8 <3>;
  539. };
  540. };
  541. mmc1_pins_sdr104: mmc1@sdr104 {
  542. pins_cmd {
  543. drive-strength = /bits/ 8 <2>;
  544. };
  545. pins_dat {
  546. drive-strength = /bits/ 8 <2>;
  547. };
  548. pins_clk {
  549. drive-strength = /bits/ 8 <3>;
  550. };
  551. };
  552. mmc1_pins_sdr50: mmc1@sdr50 {
  553. pins_cmd {
  554. drive-strength = /bits/ 8 <2>;
  555. };
  556. pins_dat {
  557. drive-strength = /bits/ 8 <2>;
  558. };
  559. pins_clk {
  560. drive-strength = /bits/ 8 <3>;
  561. };
  562. };
  563. mmc1_pins_ddr50: mmc1@ddr50 {
  564. pins_cmd {
  565. drive-strength = /bits/ 8 <2>;
  566. };
  567. pins_dat {
  568. drive-strength = /bits/ 8 <2>;
  569. };
  570. pins_clk {
  571. drive-strength = /bits/ 8 <3>;
  572. };
  573. };
  574. mmc1_register_setting_default: mmc1@register_default {
  575. dat0rddly = /bits/ 8 <0>;
  576. dat1rddly = /bits/ 8 <0>;
  577. dat2rddly = /bits/ 8 <0>;
  578. dat3rddly = /bits/ 8 <0>;
  579. datwrddly = /bits/ 8 <0>;
  580. cmdrrddly = /bits/ 8 <0>;
  581. cmdrddly = /bits/ 8 <0>;
  582. cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  583. rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  584. wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
  585. };
  586. };
  587. /* mmc end */
  588. /* ++++++ Connectivity GPIO configs ++++++ */
  589. &pio {
  590. pinctrl-names = "default";
  591. pinctrl-0 = <&state_default>;
  592. pcfg_combo_pmu_en_pull_dis_cfgs:cfg_mode1_pull_dis {
  593. combo_pins {
  594. pinmux = <PINMUX_GPIO21__FUNC_GPIO21>;
  595. bias-disable;
  596. };
  597. };
  598. pcfg_combo_pmu_en_in_pulldown_cfgs:cfg_mode1_in_pulldown {
  599. combo_pins {
  600. pinmux = <PINMUX_GPIO21__FUNC_GPIO21>;
  601. bias-pull-down;
  602. };
  603. };
  604. pcfg_combo_rst_pull_dis_cfgs:cfg_mode1_pull_dis {
  605. combo_pins {
  606. pinmux = <PINMUX_GPIO186__FUNC_GPIO186>;
  607. bias-disable;
  608. };
  609. };
  610. pcfg_combo_wifi_eint_in_pull_dis_cfgs:cfg_mode1_in_pull_dis {
  611. combo_pins {
  612. pinmux = <PINMUX_GPIO20__FUNC_GPIO20>;
  613. input-enable;
  614. bias-disable;
  615. };
  616. };
  617. pcfg_combo_wifi_eint_in_pullup_cfgs:cfg_mode1_in_pullup {
  618. combo_pins {
  619. pinmux = <PINMUX_GPIO20__FUNC_GPIO20>;
  620. input-enable;
  621. bias-pull-up;
  622. };
  623. };
  624. pcfg_combo_urxd_uart_pull_dis_cfgs:cfg_mode2_pull_dis {
  625. combo_pins {
  626. pinmux = <PINMUX_GPIO74__FUNC_URXD0>;
  627. bias-disable;
  628. };
  629. };
  630. pcfg_combo_urxd_gpio_in_pullup_cfgs:cfg_mode1_in_pullup {
  631. combo_pins {
  632. pinmux = <PINMUX_GPIO74__FUNC_URXD0>;
  633. input-enable;
  634. bias-pull-up;
  635. };
  636. };
  637. pcfg_combo_urxd_gpio_in_pull_dis_cfgs:cfg_mode1_in_pull_dis {
  638. combo_pins {
  639. pinmux = <PINMUX_GPIO74__FUNC_URXD0>;
  640. input-enable;
  641. bias-disable;
  642. };
  643. };
  644. pcfg_combo_utxd_uart_pull_dis_cfgs:cfg_mode2_pull_dis {
  645. combo_pins {
  646. pinmux = <PINMUX_GPIO75__FUNC_UTXD0>;
  647. bias-disable;
  648. };
  649. };
  650. pcfg_combo_pcm_daiclk_pull_dis_cfgs:cfg_mode3_pull_dis {
  651. combo_pins {
  652. pinmux = <PINMUX_GPIO184__FUNC_PCM0_CLK>;
  653. bias-disable;
  654. };
  655. };
  656. pcfg_combo_pcm_daipcmin_pull_dis_cfgs:cfg_mode3_pull_dis {
  657. combo_pins {
  658. pinmux = <PINMUX_GPIO185__FUNC_PCM0_DI>;
  659. bias-disable;
  660. };
  661. };
  662. pcfg_combo_pcm_daipcmout_pull_dis_cfgs:cfg_mode3_pull_dis {
  663. combo_pins {
  664. pinmux = <PINMUX_GPIO187__FUNC_PCM0_DO>;
  665. bias-disable;
  666. };
  667. };
  668. pcfg_combo_pcm_daisync_pull_dis_cfgs:cfg_mode3_pull_dis {
  669. combo_pins {
  670. pinmux = <PINMUX_GPIO188__FUNC_PCM0_SYNC>;
  671. bias-disable;
  672. };
  673. };
  674. pcfg_combo_gps_sync_pull_dis_cfgs:cfg_mode1_pull_dis {
  675. combo_pins {
  676. pinmux = <PINMUX_GPIO19__FUNC_GPS_FRAME_SYNC>;
  677. bias-disable;
  678. };
  679. };
  680. pcfg_combo_gps_lna_pull_dis_cfgs:cfg_mode1_pull_dis {
  681. combo_pins {
  682. pinmux = <PINMUX_GPIO77__FUNC_GPIO77>;
  683. bias-disable;
  684. };
  685. };
  686. state_default:pinctrl {
  687. /* ++++++ Connectivity GPIO configs ++++++ */
  688. combo_wifi_eint_pins {
  689. pinmux = <PINMUX_GPIO20__FUNC_GPIO20>;
  690. bias-pull-up;
  691. };
  692. combo_pcm_pins {
  693. pinmux = <PINMUX_GPIO184__FUNC_MRG_CLK>,
  694. <PINMUX_GPIO185__FUNC_MRG_DI>,
  695. <PINMUX_GPIO187__FUNC_MRG_DO>,
  696. <PINMUX_GPIO188__FUNC_MRG_SYNC>;
  697. bias-disable;
  698. };
  699. /* ----- Connectivity GPIO configs ----- */
  700. };
  701. /* ------ Connectivity GPIO configs ------ */
  702. };
  703. /* NFC GPIO standardization */
  704. &pio {
  705. nfc_default: default {
  706. };
  707. nfc_ven_high: state_ven_high {
  708. pins_cmd_dat {
  709. pins = <PINMUX_GPIO4__FUNC_GPIO4>;
  710. slew-rate = <1>;
  711. output-high;
  712. };
  713. };
  714. nfc_ven_low: state_ven_low {
  715. pins_cmd_dat {
  716. pins = <PINMUX_GPIO4__FUNC_GPIO4>;
  717. slew-rate = <1>;
  718. output-low;
  719. };
  720. };
  721. nfc_rst_high: state_rst_high {
  722. pins_cmd_dat {
  723. pins = <PINMUX_GPIO3__FUNC_GPIO3>;
  724. slew-rate = <1>;
  725. output-high;
  726. };
  727. };
  728. nfc_rst_low: state_rst_low {
  729. pins_cmd_dat {
  730. pins = <PINMUX_GPIO3__FUNC_GPIO3>;
  731. slew-rate = <1>;
  732. output-low;
  733. };
  734. };
  735. nfc_eint_high: state_eint_high {
  736. pins_cmd_dat {
  737. pins = <PINMUX_GPIO1__FUNC_GPIO1>;
  738. slew-rate = <1>;
  739. output-high;
  740. };
  741. };
  742. nfc_eint_low: state_eint_low {
  743. pins_cmd_dat {
  744. pins = <PINMUX_GPIO1__FUNC_GPIO1>;
  745. slew-rate = <1>;
  746. output-low;
  747. };
  748. };
  749. nfc_irq_init: state_irq_init {
  750. pins_cmd_dat {
  751. pins = <PINMUX_GPIO2__FUNC_GPIO2>;
  752. slew-rate = <0>;
  753. bias-pull-down = <00>;
  754. };
  755. };
  756. };
  757. &nfc {
  758. pinctrl-names = "default", "ven_high", "ven_low", "rst_high", "rst_low", "eint_high", "eint_low", "irq_init";
  759. pinctrl-0 = <&nfc_default>;
  760. pinctrl-1 = <&nfc_ven_high>;
  761. pinctrl-2 = <&nfc_ven_low>;
  762. pinctrl-3 = <&nfc_rst_high>;
  763. pinctrl-4 = <&nfc_rst_low>;
  764. pinctrl-5 = <&nfc_eint_high>;
  765. pinctrl-6 = <&nfc_eint_low>;
  766. pinctrl-7 = <&nfc_irq_init>;
  767. status = "okay";
  768. };
  769. /* NFC end */
  770. /* USB GPIO Kernal Standardization start */
  771. &pio {
  772. usb_default: usb_default {
  773. };
  774. gpio67_mode5_iddig: iddig_irq_init {
  775. pins_cmd_dat {
  776. pins = <PINMUX_GPIO67__FUNC_IDDIG>;
  777. slew-rate = <0>;
  778. bias-pull-up = <00>;
  779. };
  780. };
  781. gpio83_mode0_drvvbus: drvvbus_init {
  782. pins_cmd_dat {
  783. pins = <PINMUX_GPIO83__FUNC_GPIO83>;
  784. slew-rate = <1>;
  785. bias-pull-up = <00>;
  786. };
  787. };
  788. gpio83_mode0_drvvbus_low: drvvbus_low {
  789. pins_cmd_dat {
  790. pins = <PINMUX_GPIO83__FUNC_GPIO83>;
  791. slew-rate = <1>;
  792. output-low;
  793. };
  794. };
  795. gpio83_mode0_drvvbus_high: drvvbus_high {
  796. pins_cmd_dat {
  797. pins = <PINMUX_GPIO83__FUNC_GPIO83>;
  798. slew-rate = <1>;
  799. output-high;
  800. };
  801. };
  802. };
  803. &usb0 {
  804. iddig_gpio = <67 5>;
  805. pinctrl-names = "usb_default", "iddig_irq_init", "drvvbus_init", "drvvbus_low", "drvvbus_high";
  806. pinctrl-0 = <&usb_default>;
  807. pinctrl-1 = <&gpio67_mode5_iddig>;
  808. pinctrl-2 = <&gpio83_mode0_drvvbus>;
  809. pinctrl-3 = <&gpio83_mode0_drvvbus_low>;
  810. pinctrl-4 = <&gpio83_mode0_drvvbus_high>;
  811. status = "okay";
  812. };
  813. /* USB GPIO Kernal Standardization end */
  814. /* LCM GPIO Kernal Standardization start */
  815. &pio {
  816. lcm_mode_default: lcm_mode_default {
  817. pins_cmd_dat {
  818. pins = <PINMUX_GPIO80__FUNC_GPIO80>;
  819. };
  820. };
  821. lcm_mode_00: lcm_mode@0 {
  822. pins_cmd_dat {
  823. pins = <PINMUX_GPIO80__FUNC_GPIO80>;
  824. };
  825. };
  826. lcm_mode_01: lcm_mode@1 {
  827. pins_cmd_dat {
  828. pins = <PINMUX_GPIO80__FUNC_I2S0_BCK>;
  829. };
  830. };
  831. lcm_mode_02: lcm_mode@2 {
  832. pins_cmd_dat {
  833. pins = <PINMUX_GPIO80__FUNC_PCM1_CLK_1>;
  834. };
  835. };
  836. lcm_mode_03: lcm_mode@3 {
  837. pins_cmd_dat {
  838. pins = <PINMUX_GPIO80__FUNC_I2S3_BCK>;
  839. };
  840. };
  841. lcm_mode_04: lcm_mode@4 {
  842. pins_cmd_dat {
  843. pins = <PINMUX_GPIO80__FUNC_I2S1_BCK>;
  844. };
  845. };
  846. lcm_mode_05: lcm_mode@5 {
  847. pins_cmd_dat {
  848. pins = <PINMUX_GPIO80__FUNC_PWM4>;
  849. };
  850. };
  851. lcm_mode_06: lcm_mode@6 {
  852. pins_cmd_dat {
  853. pins = <PINMUX_GPIO80__FUNC_I2S2_BCK>;
  854. };
  855. };
  856. lcm_mode_07: lcm_mode@7 {
  857. pins_cmd_dat {
  858. pins = <PINMUX_GPIO80__FUNC_DBG_MON_A28>;
  859. };
  860. };
  861. };
  862. &lcm {
  863. gpio_lcm_pwr_en = <&pio 64 0>;
  864. gpio_lcm_rst_en = <&pio 146 0>;
  865. };
  866. &lcm_mode {
  867. pinctrl-names = "default", "lcm_mode_00", "lcm_mode_01", "lcm_mode_02", "lcm_mode_03", "lcm_mode_04",
  868. "lcm_mode_05", "lcm_mode_06", "lcm_mode_07";
  869. pinctrl-0 = <&lcm_mode_default>;
  870. pinctrl-1 = <&lcm_mode_00>;
  871. pinctrl-2 = <&lcm_mode_01>;
  872. pinctrl-3 = <&lcm_mode_02>;
  873. pinctrl-4 = <&lcm_mode_03>;
  874. pinctrl-5 = <&lcm_mode_04>;
  875. pinctrl-6 = <&lcm_mode_05>;
  876. pinctrl-7 = <&lcm_mode_06>;
  877. pinctrl-8 = <&lcm_mode_07>;
  878. lcm_power_gpio = <&pio 80 0>;
  879. lcm_bl_gpio = <&pio 129 0>;
  880. status = "okay";
  881. };
  882. /* LCM GPIO Kernal Standardization end */
  883. /* i2c start */
  884. &i2c3 {
  885. ncp1854@36 {
  886. status = "okay";
  887. compatible = "ncp1854";
  888. reg = <0x36>;
  889. disable_ncp1854_fctry_mod = <1>;
  890. pinctrl-names = "drvvbus_init", "drvvbus_low";
  891. pinctrl-0 = <&gpio83_mode0_drvvbus>;
  892. pinctrl-1 = <&gpio83_mode0_drvvbus_low>;
  893. };
  894. };
  895. /* i2c end */