| 12345678910111213141516171819202122232425262728293031323334353637383940414243444546 |
- Qualcomm adreno/snapdragon hdmi output
- Required properties:
- - compatible: one of the following
- * "qcom,hdmi-tx-8660"
- * "qcom,hdmi-tx-8960"
- - reg: Physical base address and length of the controller's registers
- - reg-names: "core_physical"
- - interrupts: The interrupt signal from the hdmi block.
- - clocks: device clocks
- See ../clocks/clock-bindings.txt for details.
- - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
- - qcom,hdmi-tx-ddc-data-gpio: ddc data pin
- - qcom,hdmi-tx-hpd-gpio: hpd pin
- - core-vdda-supply: phandle to supply regulator
- - hdmi-mux-supply: phandle to mux regulator
- Optional properties:
- - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
- - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
- Example:
- / {
- ...
- hdmi: qcom,hdmi-tx-8960@4a00000 {
- compatible = "qcom,hdmi-tx-8960";
- reg-names = "core_physical";
- reg = <0x04a00000 0x1000>;
- interrupts = <GIC_SPI 79 0>;
- clock-names =
- "core_clk",
- "master_iface_clk",
- "slave_iface_clk";
- clocks =
- <&mmcc HDMI_APP_CLK>,
- <&mmcc HDMI_M_AHB_CLK>,
- <&mmcc HDMI_S_AHB_CLK>;
- qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
- qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
- qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
- core-vdda-supply = <&pm8921_hdmi_mvs>;
- hdmi-mux-supply = <&ext_3p3v>;
- };
- };
|