hdmi.txt 1.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546
  1. Qualcomm adreno/snapdragon hdmi output
  2. Required properties:
  3. - compatible: one of the following
  4. * "qcom,hdmi-tx-8660"
  5. * "qcom,hdmi-tx-8960"
  6. - reg: Physical base address and length of the controller's registers
  7. - reg-names: "core_physical"
  8. - interrupts: The interrupt signal from the hdmi block.
  9. - clocks: device clocks
  10. See ../clocks/clock-bindings.txt for details.
  11. - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
  12. - qcom,hdmi-tx-ddc-data-gpio: ddc data pin
  13. - qcom,hdmi-tx-hpd-gpio: hpd pin
  14. - core-vdda-supply: phandle to supply regulator
  15. - hdmi-mux-supply: phandle to mux regulator
  16. Optional properties:
  17. - qcom,hdmi-tx-mux-en-gpio: hdmi mux enable pin
  18. - qcom,hdmi-tx-mux-sel-gpio: hdmi mux select pin
  19. Example:
  20. / {
  21. ...
  22. hdmi: qcom,hdmi-tx-8960@4a00000 {
  23. compatible = "qcom,hdmi-tx-8960";
  24. reg-names = "core_physical";
  25. reg = <0x04a00000 0x1000>;
  26. interrupts = <GIC_SPI 79 0>;
  27. clock-names =
  28. "core_clk",
  29. "master_iface_clk",
  30. "slave_iface_clk";
  31. clocks =
  32. <&mmcc HDMI_APP_CLK>,
  33. <&mmcc HDMI_M_AHB_CLK>,
  34. <&mmcc HDMI_S_AHB_CLK>;
  35. qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
  36. qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
  37. qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
  38. core-vdda-supply = <&pm8921_hdmi_mvs>;
  39. hdmi-mux-supply = <&ext_3p3v>;
  40. };
  41. };